This is the Arm specific changes required to reduce the
amount of translation for address space randomization.

Changes for v8:
  * Add a comment to both gen_goto_tb concerning the ordering
    of the pc update vs the goto_tb opcode.

r~

Richard Henderson (9):
  target/arm: Introduce curr_insn_len
  target/arm: Change gen_goto_tb to work on displacements
  target/arm: Change gen_*set_pc_im to gen_*update_pc
  target/arm: Change gen_exception_insn* to work on displacements
  target/arm: Remove gen_exception_internal_insn pc argument
  target/arm: Change gen_jmp* to work on displacements
  target/arm: Introduce gen_pc_plus_diff for aarch64
  target/arm: Introduce gen_pc_plus_diff for aarch32
  target/arm: Enable TARGET_TB_PCREL

 target/arm/cpu-param.h        |   1 +
 target/arm/translate-a32.h    |   2 +-
 target/arm/translate.h        |  66 +++++++-
 target/arm/cpu.c              |  23 +--
 target/arm/translate-a64.c    | 199 ++++++++++++++----------
 target/arm/translate-m-nocp.c |   8 +-
 target/arm/translate-mve.c    |   2 +-
 target/arm/translate-vfp.c    |  10 +-
 target/arm/translate.c        | 284 ++++++++++++++++++++--------------
 9 files changed, 367 insertions(+), 228 deletions(-)

-- 
2.34.1

On Thu, 20 Oct 2022 at 04:14, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This is the Arm specific changes required to reduce the
> amount of translation for address space randomization.
>
> Changes for v8:
>   * Add a comment to both gen_goto_tb concerning the ordering
>     of the pc update vs the goto_tb opcode.

Applied to target-arm.next, thanks.

-- PMM