The following changes since commit 5c2439a92ce4a1c5a53070bd803d6f7647e702ca:

Merge tag 'pull-riscv-to-apply-20221014' of https://github.com/alistair23/qemu into staging (2022-10-16 15:53:13 -0400)

https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20221017

for you to fetch changes up to 5ef4a4af8b41fb175374726f379a2aea79929023:

hw/intc: Fix LoongArch ipi device emulation (2022-10-17 10:28:35 +0800)

pull-loongarch-20221017

Song Gao (3):

target/loongarch: bstrins.w src register need EXT_NONE

target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flags

softfloat: logB(0) should raise divideByZero exception

WANG Xuerui (1):

linux-user: Fix struct statfs ABI on loongarch64

Xiaojuan Yang (1):

hw/intc: Fix LoongArch ipi device emulation

fpu/softfloat-parts.c.inc | 1 +

hw/intc/loongarch_ipi.c | 1 -

linux-user/syscall_defs.h | 3 ++-

target/loongarch/insn_trans/trans_bit.c.inc | 36 ++++++++++++++++----------

target/loongarch/insn_trans/trans_farith.c.inc | 12 ++++-----

5 files changed, 31 insertions(+), 22 deletions(-)

From: WANG Xuerui <xen0n@gentoo.org>

Previously the 32-bit version was incorrectly chosen, leading to funny

but incorrect output from e.g. df(1). Simply select the version

corresponding to the 64-bit asm-generic definition.

For reference, this program should produce the same output no matter

natively compiled or not, for loongarch64 or not:

```c

#include <stdio.h>

#include <sys/statfs.h>

int main(int argc, const char *argv[])

{

struct statfs b;

if (statfs(argv[0], &b))

return 1;

printf("f_type = 0x%lx\n", b.f_type);

printf("f_bsize = %ld\n", b.f_bsize);

printf("f_blocks = %ld\n", b.f_blocks);

printf("f_bfree = %ld\n", b.f_bfree);

printf("f_bavail = %ld\n", b.f_bavail);

return 0;

}

// Example output on my amd64 box, with the test binary residing on a

// btrfs partition.

// Native and emulated output after the fix:

//

// f_type = 0x9123683e

// f_bsize = 4096

// f_blocks = 268435456

// f_bfree = 168406890

// f_bavail = 168355058

// Output before the fix, note the messed layout:

//

// f_type = 0x10009123683e

// f_bsize = 723302085239504896

// f_blocks = 168355058

// f_bfree = 2250817541779750912

// f_bavail = 1099229433104

```

Fixes: 1f63019632 ("linux-user: Add LoongArch syscall support")

Signed-off-by: WANG Xuerui <xen0n@gentoo.org>

Cc: Song Gao <gaosong@loongson.cn>

Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Cc: Andreas K. Hüttel <dilfridge@gentoo.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Tested-by: Andreas K. Huettel <dilfridge@gentoo.org>

Message-Id: <20221006100710.427252-1-xen0n@gentoo.org>

Signed-off-by: Song Gao <gaosong@loongson.cn>

---

linux-user/syscall_defs.h | 3 ++-

1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h

--- a/linux-user/syscall_defs.h

+++ b/linux-user/syscall_defs.h

@@ -XXX,XX +XXX,XX @@ struct target_statfs64 {

};

#elif (defined(TARGET_PPC64) || defined(TARGET_X86_64) || \

defined(TARGET_SPARC64) || defined(TARGET_AARCH64) || \

- defined(TARGET_RISCV)) && !defined(TARGET_ABI32)

+ defined(TARGET_RISCV) || defined(TARGET_LOONGARCH64)) && \

+ !defined(TARGET_ABI32)

struct target_statfs {

    abi_long f_type;

    abi_long f_bsize;

2.31.1

logB(0) should raise divideByZero exception from IEEE 754-2008 spec 7.3

Suggested-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Song Gao <gaosong@loongson.cn>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-Id: <20220930024510.800005-4-gaosong@loongson.cn>

fpu/softfloat-parts.c.inc | 1 +

1 file changed, 1 insertion(+)

diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc

--- a/fpu/softfloat-parts.c.inc

+++ b/fpu/softfloat-parts.c.inc

@@ -XXX,XX +XXX,XX @@ static void partsN(log2)(FloatPartsN *a, float_status *s, const FloatFmt *fmt)

parts_return_nan(a, s);

return;

case float_class_zero:

+ float_raise(float_flag_divbyzero, s);

/* log2(0) = -inf */

a->cls = float_class_inf;

a->sign = 1;

2.31.1

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

In ipi_send function, it should not to set irq before

writing data to dest cpu iocsr space, as the irq will

trigger after data writing.

When call this function 'address_space_stl()', it will

trigger loongarch_ipi_writel(), the addr arg is 0x1008

('CORE_SET_OFF'), and qemu_irq_raise will be called in

this case.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-Id: <20220930095139.867115-3-yangxiaojuan@loongson.cn>

Signed-off-by: Song Gao <gaosong@loongson.cn>

---

hw/intc/loongarch_ipi.c | 1 -

1 file changed, 1 deletion(-)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c

--- a/hw/intc/loongarch_ipi.c

+++ b/hw/intc/loongarch_ipi.c

@@ -XXX,XX +XXX,XX @@ static void ipi_send(uint64_t val)

cs = qemu_get_cpu(cpuid);

cpu = LOONGARCH_CPU(cs);

env = &cpu->env;

- loongarch_cpu_set_irq(cpu, IRQ_IPI, 1);

address_space_stl(&env->address_space_iocsr, 0x1008,

data, MEMTXATTRS_UNSPECIFIED, NULL);

2.31.1

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Song Gao <gaosong@loongson.cn>

Message-Id: <20220930024510.800005-3-gaosong@loongson.cn>

target/loongarch/insn_trans/trans_farith.c.inc | 12 ++++++------

1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loongarch/insn_trans/trans_farith.c.inc

--- a/target/loongarch/insn_trans/trans_farith.c.inc

+++ b/target/loongarch/insn_trans/trans_farith.c.inc

@@ -XXX,XX +XXX,XX @@ TRANS(fmadd_s, gen_muladd, gen_helper_fmuladd_s, 0)

TRANS(fmadd_d, gen_muladd, gen_helper_fmuladd_d, 0)

TRANS(fmsub_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c)

TRANS(fmsub_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c)

-TRANS(fnmadd_s, gen_muladd, gen_helper_fmuladd_s,

- float_muladd_negate_product | float_muladd_negate_c)

-TRANS(fnmadd_d, gen_muladd, gen_helper_fmuladd_d,

- float_muladd_negate_product | float_muladd_negate_c)

-TRANS(fnmsub_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_product)

-TRANS(fnmsub_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_product)

+TRANS(fnmadd_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result)

+TRANS(fnmadd_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result)

+TRANS(fnmsub_s, gen_muladd, gen_helper_fmuladd_s,

+ float_muladd_negate_c | float_muladd_negate_result)

+TRANS(fnmsub_d, gen_muladd, gen_helper_fmuladd_d,

+ float_muladd_negate_c | float_muladd_negate_result)

2.31.1

use gen_bstrins/gen_bstrpic to replace gen_rr_ms_ls.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Song Gao <gaosong@loongson.cn>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-Id: <20220930024510.800005-2-gaosong@loongson.cn>

target/loongarch/insn_trans/trans_bit.c.inc | 36 +++++++++++++--------

1 file changed, 22 insertions(+), 14 deletions(-)

diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc

--- a/target/loongarch/insn_trans/trans_bit.c.inc

+++ b/target/loongarch/insn_trans/trans_bit.c.inc

@@ -XXX,XX +XXX,XX @@ static void gen_bytepick_d(TCGv dest, TCGv src1, TCGv src2, target_long sa)

tcg_gen_extract2_i64(dest, src1, src2, (64 - sa * 8));

}

-static void gen_bstrins(TCGv dest, TCGv src1,

- unsigned int ls, unsigned int len)

+static bool gen_bstrins(DisasContext *ctx, arg_rr_ms_ls *a,

+ DisasExtend dst_ext)

{

- tcg_gen_deposit_tl(dest, dest, src1, ls, len);

+ TCGv src1 = gpr_src(ctx, a->rd, EXT_NONE);

+ TCGv src2 = gpr_src(ctx, a->rj, EXT_NONE);

+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);

+

+ if (a->ls > a->ms) {

+ return false;

+ tcg_gen_deposit_tl(dest, src1, src2, a->ls, a->ms - a->ls + 1);

+ gen_set_gpr(a->rd, dest, dst_ext);

+ return true;

-static bool gen_rr_ms_ls(DisasContext *ctx, arg_rr_ms_ls *a,

- DisasExtend src_ext, DisasExtend dst_ext,

- void (*func)(TCGv, TCGv, unsigned int, unsigned int))

+static bool gen_bstrpick(DisasContext *ctx, arg_rr_ms_ls *a,

+ DisasExtend dst_ext)

- TCGv dest = gpr_dst(ctx, a->rd, dst_ext);

- TCGv src1 = gpr_src(ctx, a->rj, src_ext);

+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);

+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);

if (a->ls > a->ms) {

- func(dest, src1, a->ls, a->ms - a->ls + 1);

+ tcg_gen_extract_tl(dest, src1, a->ls, a->ms - a->ls + 1);

gen_set_gpr(a->rd, dest, dst_ext);

-

return true;

}

@@ -XXX,XX +XXX,XX @@ TRANS(maskeqz, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)

TRANS(masknez, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)

TRANS(bytepick_w, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)

TRANS(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)

-TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)

-TRANS(bstrins_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)

-TRANS(bstrpick_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, tcg_gen_extract_tl)

-TRANS(bstrpick_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, tcg_gen_extract_tl)

+TRANS(bstrins_w, gen_bstrins, EXT_SIGN)

+TRANS(bstrins_d, gen_bstrins, EXT_NONE)

+TRANS(bstrpick_w, gen_bstrpick, EXT_SIGN)

+TRANS(bstrpick_d, gen_bstrpick, EXT_NONE)

2.31.1