[PULL 0/5] loongarch-to-apply queue
[PULL 0/1] loongarch-to-apply queue
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The following changes since commit 5c2439a92ce4a1c5a53070bd803d6f7647e702ca:
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The following changes since commit 848a6caa88b9f082c89c9b41afa975761262981d:
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Merge tag 'pull-riscv-to-apply-20221014' of https://github.com/alistair23/qemu into staging (2022-10-16 15:53:13 -0400)
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Merge tag 'migration-20230602-pull-request' of https://gitlab.com/juan.quintela/qemu into staging (2023-06-02 17:33:29 -0700)
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are available in the Git repository at:
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are available in the Git repository at:
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https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20221017
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https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230605
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for you to fetch changes up to 5ef4a4af8b41fb175374726f379a2aea79929023:
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for you to fetch changes up to 8555ddc671203969b0e6eb651e538d02a9a79b3a:
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hw/intc: Fix LoongArch ipi device emulation (2022-10-17 10:28:35 +0800)
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hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes (2023-06-05 11:08:55 +0800)
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----------------------------------------------------------------
13
----------------------------------------------------------------
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pull-loongarch-20221017
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Fixes Coverity CID: 1512452, 1512453
15
Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
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----------------------------------------------------------------
17
----------------------------------------------------------------
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Song Gao (3):
18
Jiaxun Yang (1):
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target/loongarch: bstrins.w src register need EXT_NONE
19
hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes
19
target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flags
20
softfloat: logB(0) should raise divideByZero exception
21
20
22
WANG Xuerui (1):
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hw/intc/loongarch_ipi.c | 6 +++---
23
linux-user: Fix struct statfs ABI on loongarch64
22
include/hw/intc/loongarch_ipi.h | 4 +++-
24
23
2 files changed, 6 insertions(+), 4 deletions(-)
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Xiaojuan Yang (1):
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hw/intc: Fix LoongArch ipi device emulation
27
28
fpu/softfloat-parts.c.inc | 1 +
29
hw/intc/loongarch_ipi.c | 1 -
30
linux-user/syscall_defs.h | 3 ++-
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target/loongarch/insn_trans/trans_bit.c.inc | 36 ++++++++++++++++----------
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target/loongarch/insn_trans/trans_farith.c.inc | 12 ++++-----
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5 files changed, 31 insertions(+), 22 deletions(-)
diff view generated by jsdifflib
[PULL 1/5] target/loongarch: bstrins.w src register need EXT_NONE
Deleted patch
1
use gen_bstrins/gen_bstrpic to replace gen_rr_ms_ls.
2
1
3
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Song Gao <gaosong@loongson.cn>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-Id: <20220930024510.800005-2-gaosong@loongson.cn>
7
---
8
target/loongarch/insn_trans/trans_bit.c.inc | 36 +++++++++++++--------
9
1 file changed, 22 insertions(+), 14 deletions(-)
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11
diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/loongarch/insn_trans/trans_bit.c.inc
14
+++ b/target/loongarch/insn_trans/trans_bit.c.inc
15
@@ -XXX,XX +XXX,XX @@ static void gen_bytepick_d(TCGv dest, TCGv src1, TCGv src2, target_long sa)
16
tcg_gen_extract2_i64(dest, src1, src2, (64 - sa * 8));
17
}
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19
-static void gen_bstrins(TCGv dest, TCGv src1,
20
- unsigned int ls, unsigned int len)
21
+static bool gen_bstrins(DisasContext *ctx, arg_rr_ms_ls *a,
22
+ DisasExtend dst_ext)
23
{
24
- tcg_gen_deposit_tl(dest, dest, src1, ls, len);
25
+ TCGv src1 = gpr_src(ctx, a->rd, EXT_NONE);
26
+ TCGv src2 = gpr_src(ctx, a->rj, EXT_NONE);
27
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
28
+
29
+ if (a->ls > a->ms) {
30
+ return false;
31
+ }
32
+
33
+ tcg_gen_deposit_tl(dest, src1, src2, a->ls, a->ms - a->ls + 1);
34
+ gen_set_gpr(a->rd, dest, dst_ext);
35
+ return true;
36
}
37
38
-static bool gen_rr_ms_ls(DisasContext *ctx, arg_rr_ms_ls *a,
39
- DisasExtend src_ext, DisasExtend dst_ext,
40
- void (*func)(TCGv, TCGv, unsigned int, unsigned int))
41
+static bool gen_bstrpick(DisasContext *ctx, arg_rr_ms_ls *a,
42
+ DisasExtend dst_ext)
43
{
44
- TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
45
- TCGv src1 = gpr_src(ctx, a->rj, src_ext);
46
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
47
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
48
49
if (a->ls > a->ms) {
50
return false;
51
}
52
53
- func(dest, src1, a->ls, a->ms - a->ls + 1);
54
+ tcg_gen_extract_tl(dest, src1, a->ls, a->ms - a->ls + 1);
55
gen_set_gpr(a->rd, dest, dst_ext);
56
-
57
return true;
58
}
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60
@@ -XXX,XX +XXX,XX @@ TRANS(maskeqz, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
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TRANS(masknez, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
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TRANS(bytepick_w, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
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TRANS(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
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-TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
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-TRANS(bstrins_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
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-TRANS(bstrpick_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, tcg_gen_extract_tl)
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-TRANS(bstrpick_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, tcg_gen_extract_tl)
68
+TRANS(bstrins_w, gen_bstrins, EXT_SIGN)
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+TRANS(bstrins_d, gen_bstrins, EXT_NONE)
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+TRANS(bstrpick_w, gen_bstrpick, EXT_SIGN)
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+TRANS(bstrpick_d, gen_bstrpick, EXT_NONE)
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--
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2.31.1
diff view generated by jsdifflib
[PULL 2/5] target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flags
Deleted patch
1
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2
Signed-off-by: Song Gao <gaosong@loongson.cn>
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Message-Id: <20220930024510.800005-3-gaosong@loongson.cn>
4
---
5
target/loongarch/insn_trans/trans_farith.c.inc | 12 ++++++------
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1 file changed, 6 insertions(+), 6 deletions(-)
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1
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diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loongarch/insn_trans/trans_farith.c.inc
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index XXXXXXX..XXXXXXX 100644
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--- a/target/loongarch/insn_trans/trans_farith.c.inc
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+++ b/target/loongarch/insn_trans/trans_farith.c.inc
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@@ -XXX,XX +XXX,XX @@ TRANS(fmadd_s, gen_muladd, gen_helper_fmuladd_s, 0)
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TRANS(fmadd_d, gen_muladd, gen_helper_fmuladd_d, 0)
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TRANS(fmsub_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c)
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TRANS(fmsub_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c)
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-TRANS(fnmadd_s, gen_muladd, gen_helper_fmuladd_s,
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- float_muladd_negate_product | float_muladd_negate_c)
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-TRANS(fnmadd_d, gen_muladd, gen_helper_fmuladd_d,
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- float_muladd_negate_product | float_muladd_negate_c)
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-TRANS(fnmsub_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_product)
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-TRANS(fnmsub_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_product)
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+TRANS(fnmadd_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result)
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+TRANS(fnmadd_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result)
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+TRANS(fnmsub_s, gen_muladd, gen_helper_fmuladd_s,
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+ float_muladd_negate_c | float_muladd_negate_result)
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+TRANS(fnmsub_d, gen_muladd, gen_helper_fmuladd_d,
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+ float_muladd_negate_c | float_muladd_negate_result)
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--
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2.31.1
diff view generated by jsdifflib
[PULL 3/5] softfloat: logB(0) should raise divideByZero exception
Deleted patch
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logB(0) should raise divideByZero exception from IEEE 754-2008 spec 7.3
2
1
3
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Song Gao <gaosong@loongson.cn>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-Id: <20220930024510.800005-4-gaosong@loongson.cn>
7
---
8
fpu/softfloat-parts.c.inc | 1 +
9
1 file changed, 1 insertion(+)
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diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
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index XXXXXXX..XXXXXXX 100644
13
--- a/fpu/softfloat-parts.c.inc
14
+++ b/fpu/softfloat-parts.c.inc
15
@@ -XXX,XX +XXX,XX @@ static void partsN(log2)(FloatPartsN *a, float_status *s, const FloatFmt *fmt)
16
parts_return_nan(a, s);
17
return;
18
case float_class_zero:
19
+ float_raise(float_flag_divbyzero, s);
20
/* log2(0) = -inf */
21
a->cls = float_class_inf;
22
a->sign = 1;
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--
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2.31.1
diff view generated by jsdifflib
[PULL 4/5] linux-user: Fix struct statfs ABI on loongarch64
Deleted patch
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From: WANG Xuerui <xen0n@gentoo.org>
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1
3
Previously the 32-bit version was incorrectly chosen, leading to funny
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but incorrect output from e.g. df(1). Simply select the version
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corresponding to the 64-bit asm-generic definition.
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For reference, this program should produce the same output no matter
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natively compiled or not, for loongarch64 or not:
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10
```c
11
#include <stdio.h>
12
#include <sys/statfs.h>
13
14
int main(int argc, const char *argv[])
15
{
16
struct statfs b;
17
if (statfs(argv[0], &b))
18
return 1;
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20
printf("f_type = 0x%lx\n", b.f_type);
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printf("f_bsize = %ld\n", b.f_bsize);
22
printf("f_blocks = %ld\n", b.f_blocks);
23
printf("f_bfree = %ld\n", b.f_bfree);
24
printf("f_bavail = %ld\n", b.f_bavail);
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26
return 0;
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}
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// Example output on my amd64 box, with the test binary residing on a
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// btrfs partition.
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// Native and emulated output after the fix:
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//
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// f_type = 0x9123683e
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// f_bsize = 4096
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// f_blocks = 268435456
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// f_bfree = 168406890
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// f_bavail = 168355058
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// Output before the fix, note the messed layout:
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//
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// f_type = 0x10009123683e
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// f_bsize = 723302085239504896
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// f_blocks = 168355058
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// f_bfree = 2250817541779750912
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// f_bavail = 1099229433104
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```
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Fixes: 1f63019632 ("linux-user: Add LoongArch syscall support")
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Signed-off-by: WANG Xuerui <xen0n@gentoo.org>
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Cc: Song Gao <gaosong@loongson.cn>
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Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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Cc: Andreas K. Hüttel <dilfridge@gentoo.org>
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Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
55
Tested-by: Andreas K. Huettel <dilfridge@gentoo.org>
56
Message-Id: <20221006100710.427252-1-xen0n@gentoo.org>
57
Signed-off-by: Song Gao <gaosong@loongson.cn>
58
---
59
linux-user/syscall_defs.h | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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62
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/linux-user/syscall_defs.h
65
+++ b/linux-user/syscall_defs.h
66
@@ -XXX,XX +XXX,XX @@ struct target_statfs64 {
67
};
68
#elif (defined(TARGET_PPC64) || defined(TARGET_X86_64) || \
69
defined(TARGET_SPARC64) || defined(TARGET_AARCH64) || \
70
- defined(TARGET_RISCV)) && !defined(TARGET_ABI32)
71
+ defined(TARGET_RISCV) || defined(TARGET_LOONGARCH64)) && \
72
+ !defined(TARGET_ABI32)
73
struct target_statfs {
74
    abi_long f_type;
75
    abi_long f_bsize;
76
--
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2.31.1
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79
diff view generated by jsdifflib
[PULL 5/5] hw/intc: Fix LoongArch ipi device emulation
[PULL 1/1] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
1
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
2
2
3
In ipi_send function, it should not to set irq before
3
As per "Loongson 3A5000/3B5000 Processor Reference Manual",
4
writing data to dest cpu iocsr space, as the irq will
4
Loongson 3A5000's IPI implementation have 4 mailboxes per
5
trigger after data writing.
5
core.
6
When call this function 'address_space_stl()', it will
7
trigger loongarch_ipi_writel(), the addr arg is 0x1008
8
('CORE_SET_OFF'), and qemu_irq_raise will be called in
9
this case.
10
6
11
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
7
However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
percpu device"), the number of IPI mailboxes was reduced to
13
Message-Id: <20220930095139.867115-3-yangxiaojuan@loongson.cn>
9
one, which mismatches actual hardware.
10
11
It won't affect LoongArch based system as LoongArch boot code
12
only uses the first mailbox, however MIPS based Loongson boot
13
code uses all 4 mailboxes.
14
15
Fixes Coverity CID: 1512452, 1512453
16
Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
17
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
18
Reviewed-by: Song Gao <gaosong@loongson.cn>
19
Message-Id: <20230521102307.87081-2-jiaxun.yang@flygoat.com>
14
Signed-off-by: Song Gao <gaosong@loongson.cn>
20
Signed-off-by: Song Gao <gaosong@loongson.cn>
15
---
21
---
16
hw/intc/loongarch_ipi.c | 1 -
22
hw/intc/loongarch_ipi.c | 6 +++---
17
1 file changed, 1 deletion(-)
23
include/hw/intc/loongarch_ipi.h | 4 +++-
24
2 files changed, 6 insertions(+), 4 deletions(-)
18
25
19
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
26
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
20
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/intc/loongarch_ipi.c
28
--- a/hw/intc/loongarch_ipi.c
22
+++ b/hw/intc/loongarch_ipi.c
29
+++ b/hw/intc/loongarch_ipi.c
23
@@ -XXX,XX +XXX,XX @@ static void ipi_send(uint64_t val)
30
@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_init(Object *obj)
24
cs = qemu_get_cpu(cpuid);
31
25
cpu = LOONGARCH_CPU(cs);
32
static const VMStateDescription vmstate_ipi_core = {
26
env = &cpu->env;
33
.name = "ipi-single",
27
- loongarch_cpu_set_irq(cpu, IRQ_IPI, 1);
34
- .version_id = 1,
28
address_space_stl(&env->address_space_iocsr, 0x1008,
35
- .minimum_version_id = 1,
29
data, MEMTXATTRS_UNSPECIFIED, NULL);
36
+ .version_id = 2,
37
+ .minimum_version_id = 2,
38
.fields = (VMStateField[]) {
39
VMSTATE_UINT32(status, IPICore),
40
VMSTATE_UINT32(en, IPICore),
41
VMSTATE_UINT32(set, IPICore),
42
VMSTATE_UINT32(clear, IPICore),
43
- VMSTATE_UINT32_ARRAY(buf, IPICore, 2),
44
+ VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
45
VMSTATE_END_OF_LIST()
46
}
47
};
48
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/intc/loongarch_ipi.h
51
+++ b/include/hw/intc/loongarch_ipi.h
52
@@ -XXX,XX +XXX,XX @@
53
#define MAIL_SEND_OFFSET 0
54
#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
55
56
+#define IPI_MBX_NUM 4
57
+
58
#define TYPE_LOONGARCH_IPI "loongarch_ipi"
59
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
60
61
@@ -XXX,XX +XXX,XX @@ typedef struct IPICore {
62
uint32_t set;
63
uint32_t clear;
64
/* 64bit buf divide into 2 32bit buf */
65
- uint32_t buf[2];
66
+ uint32_t buf[IPI_MBX_NUM * 2];
67
qemu_irq irq;
68
} IPICore;
30
69
31
--
70
--
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2.31.1
71
2.39.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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