If smstateen is implemented and sstateen0.fcsr is clear then the floating point
operations must return illegal instruction exception or virtual instruction
trap, if relevant.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
---
target/riscv/csr.c | 23 ++++++++++++
target/riscv/insn_trans/trans_rvf.c.inc | 43 +++++++++++++++++++++--
target/riscv/insn_trans/trans_rvzfh.c.inc | 12 +++++++
3 files changed, 75 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 71236f2b5d..8b25f885ec 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -84,6 +84,10 @@ static RISCVException fs(CPURISCVState *env, int csrno)
!RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
return RISCV_EXCP_ILLEGAL_INST;
}
+
+ if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+ return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR);
+ }
#endif
return RISCV_EXCP_NONE;
}
@@ -2023,6 +2027,9 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
target_ulong new_val)
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
+ if (!riscv_has_ext(env, RVF)) {
+ wr_mask |= SMSTATEEN0_FCSR;
+ }
return write_mstateen(env, csrno, wr_mask, new_val);
}
@@ -2059,6 +2066,10 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
+ if (!riscv_has_ext(env, RVF)) {
+ wr_mask |= SMSTATEEN0_FCSR;
+ }
+
return write_mstateenh(env, csrno, wr_mask, new_val);
}
@@ -2096,6 +2107,10 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
+ if (!riscv_has_ext(env, RVF)) {
+ wr_mask |= SMSTATEEN0_FCSR;
+ }
+
return write_hstateen(env, csrno, wr_mask, new_val);
}
@@ -2135,6 +2150,10 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
+ if (!riscv_has_ext(env, RVF)) {
+ wr_mask |= SMSTATEEN0_FCSR;
+ }
+
return write_hstateenh(env, csrno, wr_mask, new_val);
}
@@ -2182,6 +2201,10 @@ static RISCVException write_sstateen0(CPURISCVState *env, int csrno,
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
+ if (!riscv_has_ext(env, RVF)) {
+ wr_mask |= SMSTATEEN0_FCSR;
+ }
+
return write_sstateen(env, csrno, wr_mask, new_val);
}
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index a1d3eb52ad..93657680c6 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -24,9 +24,46 @@
return false; \
} while (0)
-#define REQUIRE_ZFINX_OR_F(ctx) do {\
- if (!ctx->cfg_ptr->ext_zfinx) { \
- REQUIRE_EXT(ctx, RVF); \
+#ifndef CONFIG_USER_ONLY
+static inline bool smstateen_fcsr_check(DisasContext *ctx, int index)
+{
+ CPUState *cpu = ctx->cs;
+ CPURISCVState *env = cpu->env_ptr;
+ uint64_t stateen = env->mstateen[index];
+
+ if (!ctx->cfg_ptr->ext_smstateen || env->priv == PRV_M) {
+ return true;
+ }
+
+ if (ctx->virt_enabled) {
+ stateen &= env->hstateen[index];
+ }
+
+ if (env->priv == PRV_U && has_ext(ctx, RVS)) {
+ stateen &= env->sstateen[index];
+ }
+
+ if (!(stateen & SMSTATEEN0_FCSR)) {
+ if (ctx->virt_enabled) {
+ ctx->virt_inst_excp = true;
+ }
+ return false;
+ }
+
+ return true;
+}
+#else
+#define smstateen_fcsr_check(ctx, index) (true)
+#endif
+
+#define REQUIRE_ZFINX_OR_F(ctx) do { \
+ if (!has_ext(ctx, RVF)) { \
+ if (!ctx->cfg_ptr->ext_zfinx) { \
+ return false; \
+ } \
+ if (!smstateen_fcsr_check(ctx, 0)) { \
+ return false; \
+ } \
} \
} while (0)
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
index 5d07150cd0..6c2e338c0a 100644
--- a/target/riscv/insn_trans/trans_rvzfh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -20,18 +20,27 @@
if (!ctx->cfg_ptr->ext_zfh) { \
return false; \
} \
+ if (!smstateen_fcsr_check(ctx, 0)) { \
+ return false; \
+ } \
} while (0)
#define REQUIRE_ZHINX_OR_ZFH(ctx) do { \
if (!ctx->cfg_ptr->ext_zhinx && !ctx->cfg_ptr->ext_zfh) { \
return false; \
} \
+ if (!smstateen_fcsr_check(ctx, 0)) { \
+ return false; \
+ } \
} while (0)
#define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \
if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \
return false; \
} \
+ if (!smstateen_fcsr_check(ctx, 0)) { \
+ return false; \
+ } \
} while (0)
#define REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx) do { \
@@ -39,6 +48,9 @@
ctx->cfg_ptr->ext_zhinx || ctx->cfg_ptr->ext_zhinxmin)) { \
return false; \
} \
+ if (!smstateen_fcsr_check(ctx, 0)) { \
+ return false; \
+ } \
} while (0)
static bool trans_flh(DisasContext *ctx, arg_flh *a)
--
2.25.1On Sun, Oct 16, 2022 at 11:09 PM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> If smstateen is implemented and sstateen0.fcsr is clear then the floating point
> operations must return illegal instruction exception or virtual instruction
> trap, if relevant.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> ---
> target/riscv/csr.c | 23 ++++++++++++
> target/riscv/insn_trans/trans_rvf.c.inc | 43 +++++++++++++++++++++--
> target/riscv/insn_trans/trans_rvzfh.c.inc | 12 +++++++
> 3 files changed, 75 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 71236f2b5d..8b25f885ec 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -84,6 +84,10 @@ static RISCVException fs(CPURISCVState *env, int csrno)
> !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
> +
> + if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> + return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR);
> + }
> #endif
> return RISCV_EXCP_NONE;
> }
> @@ -2023,6 +2027,9 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
> target_ulong new_val)
> {
> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
> + if (!riscv_has_ext(env, RVF)) {
> + wr_mask |= SMSTATEEN0_FCSR;
> + }
>
> return write_mstateen(env, csrno, wr_mask, new_val);
> }
> @@ -2059,6 +2066,10 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
> {
> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>
> + if (!riscv_has_ext(env, RVF)) {
> + wr_mask |= SMSTATEEN0_FCSR;
> + }
> +
> return write_mstateenh(env, csrno, wr_mask, new_val);
> }
>
> @@ -2096,6 +2107,10 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
> {
> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>
> + if (!riscv_has_ext(env, RVF)) {
> + wr_mask |= SMSTATEEN0_FCSR;
> + }
> +
> return write_hstateen(env, csrno, wr_mask, new_val);
> }
>
> @@ -2135,6 +2150,10 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
> {
> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>
> + if (!riscv_has_ext(env, RVF)) {
> + wr_mask |= SMSTATEEN0_FCSR;
> + }
> +
> return write_hstateenh(env, csrno, wr_mask, new_val);
> }
>
> @@ -2182,6 +2201,10 @@ static RISCVException write_sstateen0(CPURISCVState *env, int csrno,
> {
> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>
> + if (!riscv_has_ext(env, RVF)) {
> + wr_mask |= SMSTATEEN0_FCSR;
> + }
> +
> return write_sstateen(env, csrno, wr_mask, new_val);
> }
>
> diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
> index a1d3eb52ad..93657680c6 100644
> --- a/target/riscv/insn_trans/trans_rvf.c.inc
> +++ b/target/riscv/insn_trans/trans_rvf.c.inc
> @@ -24,9 +24,46 @@
> return false; \
> } while (0)
>
> -#define REQUIRE_ZFINX_OR_F(ctx) do {\
> - if (!ctx->cfg_ptr->ext_zfinx) { \
> - REQUIRE_EXT(ctx, RVF); \
> +#ifndef CONFIG_USER_ONLY
> +static inline bool smstateen_fcsr_check(DisasContext *ctx, int index)
> +{
> + CPUState *cpu = ctx->cs;
> + CPURISCVState *env = cpu->env_ptr;
> + uint64_t stateen = env->mstateen[index];
Sorry I missed this the first time around. You can't access env here
Richard pointed it out here:
https://patchwork.kernel.org/project/qemu-devel/patch/20221117070316.58447-8-liweiwei@iscas.ac.cn/#25095773
I'm going to drop this patch and patch v5
Alistair
On 2022/11/21 07:35, Alistair Francis wrote:
> On Sun, Oct 16, 2022 at 11:09 PM Mayuresh Chitale
> <mchitale@ventanamicro.com> wrote:
>> If smstateen is implemented and sstateen0.fcsr is clear then the floating point
>> operations must return illegal instruction exception or virtual instruction
>> trap, if relevant.
>>
>> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
>> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> ---
>> target/riscv/csr.c | 23 ++++++++++++
>> target/riscv/insn_trans/trans_rvf.c.inc | 43 +++++++++++++++++++++--
>> target/riscv/insn_trans/trans_rvzfh.c.inc | 12 +++++++
>> 3 files changed, 75 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index 71236f2b5d..8b25f885ec 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -84,6 +84,10 @@ static RISCVException fs(CPURISCVState *env, int csrno)
>> !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
>> return RISCV_EXCP_ILLEGAL_INST;
>> }
>> +
>> + if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
>> + return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR);
>> + }
>> #endif
>> return RISCV_EXCP_NONE;
>> }
>> @@ -2023,6 +2027,9 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
>> target_ulong new_val)
>> {
>> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>> + if (!riscv_has_ext(env, RVF)) {
>> + wr_mask |= SMSTATEEN0_FCSR;
>> + }
>>
>> return write_mstateen(env, csrno, wr_mask, new_val);
>> }
>> @@ -2059,6 +2066,10 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
>> {
>> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>>
>> + if (!riscv_has_ext(env, RVF)) {
>> + wr_mask |= SMSTATEEN0_FCSR;
>> + }
>> +
>> return write_mstateenh(env, csrno, wr_mask, new_val);
>> }
>>
>> @@ -2096,6 +2107,10 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
>> {
>> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>>
>> + if (!riscv_has_ext(env, RVF)) {
>> + wr_mask |= SMSTATEEN0_FCSR;
>> + }
>> +
>> return write_hstateen(env, csrno, wr_mask, new_val);
>> }
>>
>> @@ -2135,6 +2150,10 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
>> {
>> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>>
>> + if (!riscv_has_ext(env, RVF)) {
>> + wr_mask |= SMSTATEEN0_FCSR;
>> + }
>> +
>> return write_hstateenh(env, csrno, wr_mask, new_val);
>> }
>>
>> @@ -2182,6 +2201,10 @@ static RISCVException write_sstateen0(CPURISCVState *env, int csrno,
>> {
>> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>>
>> + if (!riscv_has_ext(env, RVF)) {
>> + wr_mask |= SMSTATEEN0_FCSR;
>> + }
>> +
>> return write_sstateen(env, csrno, wr_mask, new_val);
>> }
>>
>> diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
>> index a1d3eb52ad..93657680c6 100644
>> --- a/target/riscv/insn_trans/trans_rvf.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvf.c.inc
>> @@ -24,9 +24,46 @@
>> return false; \
>> } while (0)
>>
>> -#define REQUIRE_ZFINX_OR_F(ctx) do {\
>> - if (!ctx->cfg_ptr->ext_zfinx) { \
>> - REQUIRE_EXT(ctx, RVF); \
>> +#ifndef CONFIG_USER_ONLY
>> +static inline bool smstateen_fcsr_check(DisasContext *ctx, int index)
>> +{
>> + CPUState *cpu = ctx->cs;
>> + CPURISCVState *env = cpu->env_ptr;
>> + uint64_t stateen = env->mstateen[index];
> Sorry I missed this the first time around. You can't access env here
>
> Richard pointed it out here:
> https://patchwork.kernel.org/project/qemu-devel/patch/20221117070316.58447-8-liweiwei@iscas.ac.cn/#25095773
>
> I'm going to drop this patch and patch v5
>
> Alistair
Hi, Any new updates for the last two patches after they were dropped?
Regards,
Weiwei Li
On Fri, Mar 24, 2023 at 7:01 PM liweiwei <liweiwei@iscas.ac.cn> wrote:
>
>
> On 2022/11/21 07:35, Alistair Francis wrote:
> > On Sun, Oct 16, 2022 at 11:09 PM Mayuresh Chitale
> > <mchitale@ventanamicro.com> wrote:
> >> If smstateen is implemented and sstateen0.fcsr is clear then the floating point
> >> operations must return illegal instruction exception or virtual instruction
> >> trap, if relevant.
> >>
> >> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> >> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> >> ---
> >> target/riscv/csr.c | 23 ++++++++++++
> >> target/riscv/insn_trans/trans_rvf.c.inc | 43 +++++++++++++++++++++--
> >> target/riscv/insn_trans/trans_rvzfh.c.inc | 12 +++++++
> >> 3 files changed, 75 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> >> index 71236f2b5d..8b25f885ec 100644
> >> --- a/target/riscv/csr.c
> >> +++ b/target/riscv/csr.c
> >> @@ -84,6 +84,10 @@ static RISCVException fs(CPURISCVState *env, int csrno)
> >> !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
> >> return RISCV_EXCP_ILLEGAL_INST;
> >> }
> >> +
> >> + if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> >> + return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR);
> >> + }
> >> #endif
> >> return RISCV_EXCP_NONE;
> >> }
> >> @@ -2023,6 +2027,9 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
> >> target_ulong new_val)
> >> {
> >> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
> >> + if (!riscv_has_ext(env, RVF)) {
> >> + wr_mask |= SMSTATEEN0_FCSR;
> >> + }
> >>
> >> return write_mstateen(env, csrno, wr_mask, new_val);
> >> }
> >> @@ -2059,6 +2066,10 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
> >> {
> >> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
> >>
> >> + if (!riscv_has_ext(env, RVF)) {
> >> + wr_mask |= SMSTATEEN0_FCSR;
> >> + }
> >> +
> >> return write_mstateenh(env, csrno, wr_mask, new_val);
> >> }
> >>
> >> @@ -2096,6 +2107,10 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
> >> {
> >> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
> >>
> >> + if (!riscv_has_ext(env, RVF)) {
> >> + wr_mask |= SMSTATEEN0_FCSR;
> >> + }
> >> +
> >> return write_hstateen(env, csrno, wr_mask, new_val);
> >> }
> >>
> >> @@ -2135,6 +2150,10 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
> >> {
> >> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
> >>
> >> + if (!riscv_has_ext(env, RVF)) {
> >> + wr_mask |= SMSTATEEN0_FCSR;
> >> + }
> >> +
> >> return write_hstateenh(env, csrno, wr_mask, new_val);
> >> }
> >>
> >> @@ -2182,6 +2201,10 @@ static RISCVException write_sstateen0(CPURISCVState *env, int csrno,
> >> {
> >> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
> >>
> >> + if (!riscv_has_ext(env, RVF)) {
> >> + wr_mask |= SMSTATEEN0_FCSR;
> >> + }
> >> +
> >> return write_sstateen(env, csrno, wr_mask, new_val);
> >> }
> >>
> >> diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
> >> index a1d3eb52ad..93657680c6 100644
> >> --- a/target/riscv/insn_trans/trans_rvf.c.inc
> >> +++ b/target/riscv/insn_trans/trans_rvf.c.inc
> >> @@ -24,9 +24,46 @@
> >> return false; \
> >> } while (0)
> >>
> >> -#define REQUIRE_ZFINX_OR_F(ctx) do {\
> >> - if (!ctx->cfg_ptr->ext_zfinx) { \
> >> - REQUIRE_EXT(ctx, RVF); \
> >> +#ifndef CONFIG_USER_ONLY
> >> +static inline bool smstateen_fcsr_check(DisasContext *ctx, int index)
> >> +{
> >> + CPUState *cpu = ctx->cs;
> >> + CPURISCVState *env = cpu->env_ptr;
> >> + uint64_t stateen = env->mstateen[index];
> > Sorry I missed this the first time around. You can't access env here
> >
> > Richard pointed it out here:
> > https://patchwork.kernel.org/project/qemu-devel/patch/20221117070316.58447-8-liweiwei@iscas.ac.cn/#25095773
> >
> > I'm going to drop this patch and patch v5
> >
> > Alistair
>
> Hi, Any new updates for the last two patches after they were dropped?
>
> Regards,
>
> Weiwei Li
>
Looks like I missed the original comments from Richard and Alistair. I
am not yet clear how to implement it but I am looking into it.
On Sun, Oct 16, 2022 at 11:09 PM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> If smstateen is implemented and sstateen0.fcsr is clear then the floating point
> operations must return illegal instruction exception or virtual instruction
> trap, if relevant.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 23 ++++++++++++
> target/riscv/insn_trans/trans_rvf.c.inc | 43 +++++++++++++++++++++--
> target/riscv/insn_trans/trans_rvzfh.c.inc | 12 +++++++
> 3 files changed, 75 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 71236f2b5d..8b25f885ec 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -84,6 +84,10 @@ static RISCVException fs(CPURISCVState *env, int csrno)
> !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
> +
> + if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> + return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR);
> + }
> #endif
> return RISCV_EXCP_NONE;
> }
> @@ -2023,6 +2027,9 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
> target_ulong new_val)
> {
> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
> + if (!riscv_has_ext(env, RVF)) {
> + wr_mask |= SMSTATEEN0_FCSR;
> + }
>
> return write_mstateen(env, csrno, wr_mask, new_val);
> }
> @@ -2059,6 +2066,10 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
> {
> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>
> + if (!riscv_has_ext(env, RVF)) {
> + wr_mask |= SMSTATEEN0_FCSR;
> + }
> +
> return write_mstateenh(env, csrno, wr_mask, new_val);
> }
>
> @@ -2096,6 +2107,10 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
> {
> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>
> + if (!riscv_has_ext(env, RVF)) {
> + wr_mask |= SMSTATEEN0_FCSR;
> + }
> +
> return write_hstateen(env, csrno, wr_mask, new_val);
> }
>
> @@ -2135,6 +2150,10 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
> {
> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>
> + if (!riscv_has_ext(env, RVF)) {
> + wr_mask |= SMSTATEEN0_FCSR;
> + }
> +
> return write_hstateenh(env, csrno, wr_mask, new_val);
> }
>
> @@ -2182,6 +2201,10 @@ static RISCVException write_sstateen0(CPURISCVState *env, int csrno,
> {
> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>
> + if (!riscv_has_ext(env, RVF)) {
> + wr_mask |= SMSTATEEN0_FCSR;
> + }
> +
> return write_sstateen(env, csrno, wr_mask, new_val);
> }
>
> diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
> index a1d3eb52ad..93657680c6 100644
> --- a/target/riscv/insn_trans/trans_rvf.c.inc
> +++ b/target/riscv/insn_trans/trans_rvf.c.inc
> @@ -24,9 +24,46 @@
> return false; \
> } while (0)
>
> -#define REQUIRE_ZFINX_OR_F(ctx) do {\
> - if (!ctx->cfg_ptr->ext_zfinx) { \
> - REQUIRE_EXT(ctx, RVF); \
> +#ifndef CONFIG_USER_ONLY
> +static inline bool smstateen_fcsr_check(DisasContext *ctx, int index)
> +{
> + CPUState *cpu = ctx->cs;
> + CPURISCVState *env = cpu->env_ptr;
> + uint64_t stateen = env->mstateen[index];
> +
> + if (!ctx->cfg_ptr->ext_smstateen || env->priv == PRV_M) {
> + return true;
> + }
> +
> + if (ctx->virt_enabled) {
> + stateen &= env->hstateen[index];
> + }
> +
> + if (env->priv == PRV_U && has_ext(ctx, RVS)) {
> + stateen &= env->sstateen[index];
> + }
> +
> + if (!(stateen & SMSTATEEN0_FCSR)) {
> + if (ctx->virt_enabled) {
> + ctx->virt_inst_excp = true;
> + }
> + return false;
> + }
> +
> + return true;
> +}
> +#else
> +#define smstateen_fcsr_check(ctx, index) (true)
> +#endif
> +
> +#define REQUIRE_ZFINX_OR_F(ctx) do { \
> + if (!has_ext(ctx, RVF)) { \
> + if (!ctx->cfg_ptr->ext_zfinx) { \
> + return false; \
> + } \
> + if (!smstateen_fcsr_check(ctx, 0)) { \
> + return false; \
> + } \
> } \
> } while (0)
>
> diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
> index 5d07150cd0..6c2e338c0a 100644
> --- a/target/riscv/insn_trans/trans_rvzfh.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
> @@ -20,18 +20,27 @@
> if (!ctx->cfg_ptr->ext_zfh) { \
> return false; \
> } \
> + if (!smstateen_fcsr_check(ctx, 0)) { \
> + return false; \
> + } \
> } while (0)
>
> #define REQUIRE_ZHINX_OR_ZFH(ctx) do { \
> if (!ctx->cfg_ptr->ext_zhinx && !ctx->cfg_ptr->ext_zfh) { \
> return false; \
> } \
> + if (!smstateen_fcsr_check(ctx, 0)) { \
> + return false; \
> + } \
> } while (0)
>
> #define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \
> if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \
> return false; \
> } \
> + if (!smstateen_fcsr_check(ctx, 0)) { \
> + return false; \
> + } \
> } while (0)
>
> #define REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx) do { \
> @@ -39,6 +48,9 @@
> ctx->cfg_ptr->ext_zhinx || ctx->cfg_ptr->ext_zhinxmin)) { \
> return false; \
> } \
> + if (!smstateen_fcsr_check(ctx, 0)) { \
> + return false; \
> + } \
> } while (0)
>
> static bool trans_flh(DisasContext *ctx, arg_flh *a)
> --
> 2.25.1
>
>
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