hw/net/e1000_regs.h | 1 + tests/qtest/libqos/e1000e.c | 119 +++++++++++++----------------------- 2 files changed, 45 insertions(+), 75 deletions(-)
The register definitions in tests/qtest/libqos/e1000e.c had names
different from hw/net/e1000_regs.h, which made it hard to understand
what test codes corresponds to the implementation. Use
hw/net/e1000_regs.h from tests/qtest/libqos/e1000e.c to remove
these duplications.
E1000E_CTRL_EXT_TXLSFLOW is removed from E1000E_CTRL_EXT settings
because hw/net/e1000_regs.h does not have the definition and it is for
TCP segmentation offload, which does not matter for the implemented
tests.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
---
hw/net/e1000_regs.h | 1 +
tests/qtest/libqos/e1000e.c | 119 +++++++++++++-----------------------
2 files changed, 45 insertions(+), 75 deletions(-)
diff --git a/hw/net/e1000_regs.h b/hw/net/e1000_regs.h
index e274c4fcd2..170452e0af 100644
--- a/hw/net/e1000_regs.h
+++ b/hw/net/e1000_regs.h
@@ -793,6 +793,7 @@
#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* auto speed detection check */
#define E1000_CTRL_EXT_EE_RST 0x00002000 /* EEPROM reset */
#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
+#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
#define E1000_CTRL_EXT_EIAME 0x01000000
#define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
diff --git a/tests/qtest/libqos/e1000e.c b/tests/qtest/libqos/e1000e.c
index f87e0e84b2..9b6bb17565 100644
--- a/tests/qtest/libqos/e1000e.c
+++ b/tests/qtest/libqos/e1000e.c
@@ -17,6 +17,7 @@
*/
#include "qemu/osdep.h"
+#include "hw/net/e1000_regs.h"
#include "../libqtest.h"
#include "pci-pc.h"
#include "qemu/sockets.h"
@@ -27,49 +28,13 @@
#include "qgraph.h"
#include "e1000e.h"
-#define E1000E_IMS (0x00d0)
+#define E1000E_IVAR_TEST_CFG \
+ (E1000E_RX0_MSG_ID | E1000_IVAR_INT_ALLOC_VALID | \
+ ((E1000E_TX0_MSG_ID | E1000_IVAR_INT_ALLOC_VALID) << 8) | \
+ ((E1000E_OTHER_MSG_ID | E1000_IVAR_INT_ALLOC_VALID) << 16) | \
+ E1000_IVAR_TX_INT_EVERY_WB)
-#define E1000E_STATUS (0x0008)
-#define E1000E_STATUS_LU BIT(1)
-#define E1000E_STATUS_ASDV1000 BIT(9)
-
-#define E1000E_CTRL (0x0000)
-#define E1000E_CTRL_RESET BIT(26)
-
-#define E1000E_RCTL (0x0100)
-#define E1000E_RCTL_EN BIT(1)
-#define E1000E_RCTL_UPE BIT(3)
-#define E1000E_RCTL_MPE BIT(4)
-
-#define E1000E_RFCTL (0x5008)
-#define E1000E_RFCTL_EXTEN BIT(15)
-
-#define E1000E_TCTL (0x0400)
-#define E1000E_TCTL_EN BIT(1)
-
-#define E1000E_CTRL_EXT (0x0018)
-#define E1000E_CTRL_EXT_DRV_LOAD BIT(28)
-#define E1000E_CTRL_EXT_TXLSFLOW BIT(22)
-
-#define E1000E_IVAR (0x00E4)
-#define E1000E_IVAR_TEST_CFG ((E1000E_RX0_MSG_ID << 0) | BIT(3) | \
- (E1000E_TX0_MSG_ID << 8) | BIT(11) | \
- (E1000E_OTHER_MSG_ID << 16) | BIT(19) | \
- BIT(31))
-
-#define E1000E_RING_LEN (0x1000)
-
-#define E1000E_TDBAL (0x3800)
-
-#define E1000E_TDBAH (0x3804)
-#define E1000E_TDH (0x3810)
-
-#define E1000E_RDBAL (0x2800)
-#define E1000E_RDBAH (0x2804)
-#define E1000E_RDH (0x2810)
-
-#define E1000E_TXD_LEN (16)
-#define E1000E_RXD_LEN (16)
+#define E1000E_RING_LEN (0x1000)
static void e1000e_macreg_write(QE1000E *d, uint32_t reg, uint32_t val)
{
@@ -87,30 +52,34 @@ void e1000e_tx_ring_push(QE1000E *d, void *descr)
{
QE1000E_PCI *d_pci = container_of(d, QE1000E_PCI, e1000e);
uint32_t tail = e1000e_macreg_read(d, E1000E_TDT);
- uint32_t len = e1000e_macreg_read(d, E1000E_TDLEN) / E1000E_TXD_LEN;
+ uint32_t len = e1000e_macreg_read(d, E1000E_TDLEN) / E1000_RING_DESC_LEN;
- qtest_memwrite(d_pci->pci_dev.bus->qts, d->tx_ring + tail * E1000E_TXD_LEN,
- descr, E1000E_TXD_LEN);
+ qtest_memwrite(d_pci->pci_dev.bus->qts,
+ d->tx_ring + tail * E1000_RING_DESC_LEN,
+ descr, E1000_RING_DESC_LEN);
e1000e_macreg_write(d, E1000E_TDT, (tail + 1) % len);
/* Read WB data for the packet transmitted */
- qtest_memread(d_pci->pci_dev.bus->qts, d->tx_ring + tail * E1000E_TXD_LEN,
- descr, E1000E_TXD_LEN);
+ qtest_memread(d_pci->pci_dev.bus->qts,
+ d->tx_ring + tail * E1000_RING_DESC_LEN,
+ descr, E1000_RING_DESC_LEN);
}
void e1000e_rx_ring_push(QE1000E *d, void *descr)
{
QE1000E_PCI *d_pci = container_of(d, QE1000E_PCI, e1000e);
uint32_t tail = e1000e_macreg_read(d, E1000E_RDT);
- uint32_t len = e1000e_macreg_read(d, E1000E_RDLEN) / E1000E_RXD_LEN;
+ uint32_t len = e1000e_macreg_read(d, E1000E_RDLEN) / E1000_RING_DESC_LEN;
- qtest_memwrite(d_pci->pci_dev.bus->qts, d->rx_ring + tail * E1000E_RXD_LEN,
- descr, E1000E_RXD_LEN);
+ qtest_memwrite(d_pci->pci_dev.bus->qts,
+ d->rx_ring + tail * E1000_RING_DESC_LEN,
+ descr, E1000_RING_DESC_LEN);
e1000e_macreg_write(d, E1000E_RDT, (tail + 1) % len);
/* Read WB data for the packet received */
- qtest_memread(d_pci->pci_dev.bus->qts, d->rx_ring + tail * E1000E_RXD_LEN,
- descr, E1000E_RXD_LEN);
+ qtest_memread(d_pci->pci_dev.bus->qts,
+ d->rx_ring + tail * E1000_RING_DESC_LEN,
+ descr, E1000_RING_DESC_LEN);
}
static void e1000e_foreach_callback(QPCIDevice *dev, int devfn, void *data)
@@ -151,53 +120,53 @@ static void e1000e_pci_start_hw(QOSGraphObject *obj)
qpci_device_enable(&d->pci_dev);
/* Reset the device */
- val = e1000e_macreg_read(&d->e1000e, E1000E_CTRL);
- e1000e_macreg_write(&d->e1000e, E1000E_CTRL, val | E1000E_CTRL_RESET);
+ val = e1000e_macreg_read(&d->e1000e, E1000_CTRL);
+ e1000e_macreg_write(&d->e1000e, E1000_CTRL, val | E1000_CTRL_RST);
/* Enable and configure MSI-X */
qpci_msix_enable(&d->pci_dev);
- e1000e_macreg_write(&d->e1000e, E1000E_IVAR, E1000E_IVAR_TEST_CFG);
+ e1000e_macreg_write(&d->e1000e, E1000_IVAR, E1000E_IVAR_TEST_CFG);
/* Check the device status - link and speed */
- val = e1000e_macreg_read(&d->e1000e, E1000E_STATUS);
- g_assert_cmphex(val & (E1000E_STATUS_LU | E1000E_STATUS_ASDV1000),
- ==, E1000E_STATUS_LU | E1000E_STATUS_ASDV1000);
+ val = e1000e_macreg_read(&d->e1000e, E1000_STATUS);
+ g_assert_cmphex(val & (E1000_STATUS_LU | E1000_STATUS_LAN_INIT_DONE),
+ ==, E1000_STATUS_LU | E1000_STATUS_LAN_INIT_DONE);
/* Initialize TX/RX logic */
- e1000e_macreg_write(&d->e1000e, E1000E_RCTL, 0);
- e1000e_macreg_write(&d->e1000e, E1000E_TCTL, 0);
+ e1000e_macreg_write(&d->e1000e, E1000_RCTL, 0);
+ e1000e_macreg_write(&d->e1000e, E1000_TCTL, 0);
/* Notify the device that the driver is ready */
- val = e1000e_macreg_read(&d->e1000e, E1000E_CTRL_EXT);
- e1000e_macreg_write(&d->e1000e, E1000E_CTRL_EXT,
- val | E1000E_CTRL_EXT_DRV_LOAD | E1000E_CTRL_EXT_TXLSFLOW);
+ val = e1000e_macreg_read(&d->e1000e, E1000_CTRL_EXT);
+ e1000e_macreg_write(&d->e1000e, E1000_CTRL_EXT,
+ val | E1000_CTRL_EXT_DRV_LOAD);
- e1000e_macreg_write(&d->e1000e, E1000E_TDBAL,
+ e1000e_macreg_write(&d->e1000e, E1000_TDBAL,
(uint32_t) d->e1000e.tx_ring);
- e1000e_macreg_write(&d->e1000e, E1000E_TDBAH,
+ e1000e_macreg_write(&d->e1000e, E1000_TDBAH,
(uint32_t) (d->e1000e.tx_ring >> 32));
e1000e_macreg_write(&d->e1000e, E1000E_TDLEN, E1000E_RING_LEN);
e1000e_macreg_write(&d->e1000e, E1000E_TDT, 0);
- e1000e_macreg_write(&d->e1000e, E1000E_TDH, 0);
+ e1000e_macreg_write(&d->e1000e, E1000_TDH, 0);
/* Enable transmit */
- e1000e_macreg_write(&d->e1000e, E1000E_TCTL, E1000E_TCTL_EN);
- e1000e_macreg_write(&d->e1000e, E1000E_RDBAL,
+ e1000e_macreg_write(&d->e1000e, E1000_TCTL, E1000_TCTL_EN);
+ e1000e_macreg_write(&d->e1000e, E1000_RDBAL,
(uint32_t)d->e1000e.rx_ring);
- e1000e_macreg_write(&d->e1000e, E1000E_RDBAH,
+ e1000e_macreg_write(&d->e1000e, E1000_RDBAH,
(uint32_t)(d->e1000e.rx_ring >> 32));
e1000e_macreg_write(&d->e1000e, E1000E_RDLEN, E1000E_RING_LEN);
e1000e_macreg_write(&d->e1000e, E1000E_RDT, 0);
- e1000e_macreg_write(&d->e1000e, E1000E_RDH, 0);
+ e1000e_macreg_write(&d->e1000e, E1000_RDH, 0);
/* Enable receive */
- e1000e_macreg_write(&d->e1000e, E1000E_RFCTL, E1000E_RFCTL_EXTEN);
- e1000e_macreg_write(&d->e1000e, E1000E_RCTL, E1000E_RCTL_EN |
- E1000E_RCTL_UPE |
- E1000E_RCTL_MPE);
+ e1000e_macreg_write(&d->e1000e, E1000_RFCTL, E1000_RFCTL_EXTEN);
+ e1000e_macreg_write(&d->e1000e, E1000_RCTL, E1000_RCTL_EN |
+ E1000_RCTL_UPE |
+ E1000_RCTL_MPE);
/* Enable all interrupts */
- e1000e_macreg_write(&d->e1000e, E1000E_IMS, 0xFFFFFFFF);
+ e1000e_macreg_write(&d->e1000e, E1000_IMS, 0xFFFFFFFF);
}
--
2.37.3On 13/10/2022 07.52, Akihiko Odaki wrote: > The register definitions in tests/qtest/libqos/e1000e.c had names > different from hw/net/e1000_regs.h, which made it hard to understand > what test codes corresponds to the implementation. Use > hw/net/e1000_regs.h from tests/qtest/libqos/e1000e.c to remove > these duplications. > > E1000E_CTRL_EXT_TXLSFLOW is removed from E1000E_CTRL_EXT settings > because hw/net/e1000_regs.h does not have the definition and it is for > TCP segmentation offload, which does not matter for the implemented > tests. > > Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> > --- > hw/net/e1000_regs.h | 1 + > tests/qtest/libqos/e1000e.c | 119 +++++++++++++----------------------- > 2 files changed, 45 insertions(+), 75 deletions(-) Acked-by: Thomas Huth <thuth@redhat.com> I can take it through my testing-next tree: https://gitlab.com/thuth/qemu/-/commits/testing-next Thomas
On Tue, Oct 25, 2022 at 10:54 PM Thomas Huth <thuth@redhat.com> wrote: > > On 13/10/2022 07.52, Akihiko Odaki wrote: > > The register definitions in tests/qtest/libqos/e1000e.c had names > > different from hw/net/e1000_regs.h, which made it hard to understand > > what test codes corresponds to the implementation. Use > > hw/net/e1000_regs.h from tests/qtest/libqos/e1000e.c to remove > > these duplications. > > > > E1000E_CTRL_EXT_TXLSFLOW is removed from E1000E_CTRL_EXT settings > > because hw/net/e1000_regs.h does not have the definition and it is for > > TCP segmentation offload, which does not matter for the implemented > > tests. > > > > Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> > > --- > > hw/net/e1000_regs.h | 1 + > > tests/qtest/libqos/e1000e.c | 119 +++++++++++++----------------------- > > 2 files changed, 45 insertions(+), 75 deletions(-) > > Acked-by: Thomas Huth <thuth@redhat.com> > > I can take it through my testing-next tree: Acked-by: Jason Wang <jasowang@redhat.com> > > https://gitlab.com/thuth/qemu/-/commits/testing-next > > Thomas >
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