Series comparison

-[PULL 00/28] target-arm queue
+[PULL 00/21] target-arm queue
-Hi; this is the latest target-arm queue; most of this is a refactoring
+Hi; here's the first target-arm pullreq for the 8.1 cycle.
-patchset from RTH for the arm page-table-walk emulation.
+Nothing particularly huge in here, just the various things
 that had accumulated during the freeze.
 thanks
 -- PMM
-The following changes since commit f1d33f55c47dfdaf8daacd618588ad3ae4c452d1:
+The following changes since commit 2d82c32b2ceaca3dc3da5e36e10976f34bfcb598:
-  Merge tag 'pull-testing-gdbstub-plugins-gitdm-061022-3' of https://github.com/stsquad/qemu into staging (2022-10-06 07:11:56 -0400)
+  Open 8.1 development tree (2023-04-20 10:05:25 +0100)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221010
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230420
-for you to fetch changes up to 915f62844cf62e428c7c178149b5ff1cbe129b07:
+for you to fetch changes up to 1ed1f338520cda0574b7e04f5e8e85e049740548:
-  docs/system/arm/emulation.rst: Report FEAT_GTG support (2022-10-10 14:52:25 +0100)
+  arm/mcimx7d-sabre: Set fec2-phy-connected property to false (2023-04-20 10:46:43 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * Retry KVM_CREATE_VM call if it fails EINTR
+ * hw/arm: Fix some typos in comments (most found by codespell)
- * allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented
+ * exynos: Fix out-of-bounds access in exynos4210_gcomp_find debug printf
- * docs/nuvoton: Update URL for images
+ * Orangepi-PC, Cubieboard: add Allwinner WDT watchdog emulation
- * refactoring of page table walk code
+ * tests/avocado: Add reboot tests to Cubieboard
- * hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3
+ * hw/timer/imx_epit: Fix bugs in timer limit checking
- * Don't allow guest to use unimplemented granule sizes
+ * target/arm: Remove KVM AArch32 CPU definitions
- * Report FEAT_GTG support
+ * hw/arm/virt: Restrict Cortex-A7 check to TCG
  * target/arm: Initialize debug capabilities only once
  * target/arm: Implement FEAT_PAN3
  * docs/devel/kconfig.rst: Fix incorrect markup
  * target/arm: Report pauth information to gdb as 'pauth_v2'
  * mcimxd7-sabre, mcimx6ul-evk: Correctly model the way the PHY
    on the second ethernet device must be configured via the
    first one
 ----------------------------------------------------------------
-Jerome Forissier (2):
+Akihiko Odaki (1):
-      target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented
+      target/arm: Initialize debug capabilities only once
       hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3
-Joel Stanley (1):
+Axel Heider (2):
-      docs/nuvoton: Update URL for images
+      hw/timer/imx_epit: don't shadow variable
       hw/timer/imx_epit: fix limit check
-Peter Maydell (4):
+Feng Jiang (1):
-      target/arm/kvm: Retry KVM_CREATE_VM call if it fails EINTR
+      exynos: Fix out-of-bounds access in exynos4210_gcomp_find debug printf
       target/arm: Don't allow guest to use unimplemented granule sizes
       target/arm: Use ARMGranuleSize in ARMVAParameters
       docs/system/arm/emulation.rst: Report FEAT_GTG support
-Richard Henderson (21):
+Guenter Roeck (5):
-      target/arm: Split s2walk_secure from ipa_secure in get_phys_addr
+      hw/net/imx_fec: Support two Ethernet interfaces connected to single MDIO bus
-      target/arm: Make the final stage1+2 write to secure be unconditional
+      fsl-imx6ul: Add fec[12]-phy-connected properties
-      target/arm: Add is_secure parameter to get_phys_addr_lpae
+      arm/mcimx6ul-evk: Set fec1-phy-connected property to false
-      target/arm: Fix S2 disabled check in S1_ptw_translate
+      fsl-imx7: Add fec[12]-phy-connected properties
-      target/arm: Add is_secure parameter to regime_translation_disabled
+      arm/mcimx7d-sabre: Set fec2-phy-connected property to false
       target/arm: Split out get_phys_addr_with_secure
       target/arm: Add is_secure parameter to v7m_read_half_insn
       target/arm: Add TBFLAG_M32.SECURE
       target/arm: Merge regime_is_secure into get_phys_addr
       target/arm: Add is_secure parameter to do_ats_write
       target/arm: Fold secure and non-secure a-profile mmu indexes
       target/arm: Reorg regime_translation_disabled
       target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M
       target/arm: Introduce arm_hcr_el2_eff_secstate
       target/arm: Hoist read of *is_secure in S1_ptw_translate
       target/arm: Remove env argument from combined_attrs_fwb
       target/arm: Pass HCR to attribute subroutines.
       target/arm: Fix ATS12NSO* from S PL1
       target/arm: Split out get_phys_addr_disabled
       target/arm: Fix cacheattr in get_phys_addr_disabled
       target/arm: Use tlb_set_page_full
- docs/system/arm/emulation.rst |   1 +
+Peter Maydell (5):
- docs/system/arm/nuvoton.rst   |   4 +-
+      target/arm: Pass ARMMMUFaultInfo to merge_syn_data_abort()
- target/arm/cpu-param.h        |   2 +-
+      target/arm: Don't set ISV when reporting stage 1 faults in ESR_EL2
- target/arm/cpu.h              | 181 ++++++++------
+      target/arm: Implement FEAT_PAN3
- target/arm/internals.h        | 150 ++++++-----
+      docs/devel/kconfig.rst: Fix incorrect markup
- hw/arm/boot.c                 |   4 +
+      target/arm: Report pauth information to gdb as 'pauth_v2'
- target/arm/helper.c           | 332 ++++++++++++++----------
- target/arm/kvm.c              |   4 +-
+Philippe Mathieu-Daudé (2):
- target/arm/m_helper.c         |  29 ++-
+      target/arm: Remove KVM AArch32 CPU definitions
- target/arm/ptw.c              | 570 ++++++++++++++++++++++--------------------
+      hw/arm/virt: Restrict Cortex-A7 check to TCG
- target/arm/tlb_helper.c       |   9 +-
- target/arm/translate-a64.c    |   8 -
+Stefan Weil (1):
- target/arm/translate.c        |   9 +-
+      hw/arm: Fix some typos in comments (most found by codespell)
-files changed, 717 insertions(+), 586 deletions(-)
 Strahinja Jankovic (4):
       hw/watchdog: Allwinner WDT emulation for system reset
       hw/arm: Add WDT to Allwinner-A10 and Cubieboard
       hw/arm: Add WDT to Allwinner-H3 and Orangepi-PC
       tests/avocado: Add reboot tests to Cubieboard
  docs/devel/kconfig.rst              |   2 +-
  docs/system/arm/cubieboard.rst      |   1 +
  docs/system/arm/emulation.rst       |   1 +
  docs/system/arm/orangepi.rst        |   1 +
  include/hw/arm/allwinner-a10.h      |   2 +
  include/hw/arm/allwinner-h3.h       |   5 +-
  include/hw/arm/fsl-imx6ul.h         |   1 +
  include/hw/arm/fsl-imx7.h           |   1 +
  include/hw/net/imx_fec.h            |   2 +
  include/hw/watchdog/allwinner-wdt.h | 123 +++++++++++
  target/arm/cpu.h                    |   5 +
  target/arm/kvm-consts.h             |   9 +-
  target/arm/kvm_arm.h                |   8 +
  hw/arm/allwinner-a10.c              |   7 +
  hw/arm/allwinner-h3.c               |   8 +
  hw/arm/exynos4210.c                 |   4 +-
  hw/arm/fsl-imx6ul.c                 |  20 ++
  hw/arm/fsl-imx7.c                   |  20 ++
  hw/arm/mcimx6ul-evk.c               |   2 +
  hw/arm/mcimx7d-sabre.c              |   2 +
  hw/arm/musicpal.c                   |   2 +-
  hw/arm/omap1.c                      |   2 +-
  hw/arm/omap2.c                      |   2 +-
  hw/arm/virt-acpi-build.c            |   2 +-
  hw/arm/virt.c                       |   4 +-
  hw/arm/xlnx-versal-virt.c           |   2 +-
  hw/net/imx_fec.c                    |  27 ++-
  hw/timer/exynos4210_mct.c           |  13 +-
  hw/timer/imx_epit.c                 |   2 +-
  hw/watchdog/allwinner-wdt.c         | 416 ++++++++++++++++++++++++++++++++++++
  target/arm/cpu64.c                  |   2 +-
  target/arm/cpu_tcg.c                |   2 -
  target/arm/gdbstub.c                |   9 +-
  target/arm/kvm.c                    |   2 +
  target/arm/kvm64.c                  |  18 +-
  target/arm/ptw.c                    |  14 +-
  target/arm/tcg/tlb_helper.c         |  26 ++-
  gdb-xml/aarch64-pauth.xml           |   2 +-
  hw/arm/Kconfig                      |   4 +-
  hw/watchdog/Kconfig                 |   4 +
  hw/watchdog/meson.build             |   1 +
  hw/watchdog/trace-events            |   7 +
  tests/avocado/boot_linux_console.py |  15 +-
 files changed, 738 insertions(+), 64 deletions(-)
  create mode 100644 include/hw/watchdog/allwinner-wdt.h
  create mode 100644 hw/watchdog/allwinner-wdt.c

-[PULL 01/28] target/arm/kvm: Retry KVM_CREATE_VM call if it fails EINTR
+Deleted patch
-Occasionally the KVM_CREATE_VM ioctl can return EINTR, even though
-there is no pending signal to be taken. In commit 94ccff13382055
-we added a retry-on-EINTR loop to the KVM_CREATE_VM call in the
-generic KVM code. Adopt the same approach for the use of the
-ioctl in the Arm-specific KVM code (where we use it to create a
-scratch VM for probing for various things).
-For more information, see the mailing list thread:
-https://lore.kernel.org/qemu-devel/8735e0s1zw.wl-maz@kernel.org/
-Reported-by: Vitaly Chikunov <vt@altlinux.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Vitaly Chikunov <vt@altlinux.org>
-Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Acked-by: Marc Zyngier <maz@kernel.org>
-Message-id: 20220930113824.1933293-1-peter.maydell@linaro.org
----
- target/arm/kvm.c | 4 +++-
-file changed, 3 insertions(+), 1 deletion(-)
-diff --git a/target/arm/kvm.c b/target/arm/kvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm.c
-+++ b/target/arm/kvm.c
-@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
-     if (max_vm_pa_size < 0) {
-         max_vm_pa_size = 0;
-     }
--    vmfd = ioctl(kvmfd, KVM_CREATE_VM, max_vm_pa_size);
-+    do {
-+        vmfd = ioctl(kvmfd, KVM_CREATE_VM, max_vm_pa_size);
-+    } while (vmfd == -1 && errno == EINTR);
-     if (vmfd < 0) {
-         goto err;
-     }
---
-.25.1

-[PULL 02/28] target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented
+Deleted patch
-From: Jerome Forissier <jerome.forissier@linaro.org>
-Updates write_scr() to allow setting SCR_EL3.EnTP2 when FEAT_SME is
-implemented. SCR_EL3 being a 64-bit register, valid_mask is changed
-to uint64_t and the SCR_* constants in target/arm/cpu.h are extended
-to 64-bit so that masking and bitwise not (~) behave as expected.
-This enables booting Linux with Trusted Firmware-A at EL3 with
-"-M virt,secure=on -cpu max".
-Cc: qemu-stable@nongnu.org
-Fixes: 78cb9776662a ("target/arm: Enable SME for -cpu max")
-Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
-Reviewed-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20221004072354.27037-1-jerome.forissier@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu.h    | 54 ++++++++++++++++++++++-----------------------
- target/arm/helper.c |  5 ++++-
-files changed, 31 insertions(+), 28 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
- #define HPFAR_NS      (1ULL << 63)
--#define SCR_NS                (1U << 0)
--#define SCR_IRQ               (1U << 1)
--#define SCR_FIQ               (1U << 2)
--#define SCR_EA                (1U << 3)
--#define SCR_FW                (1U << 4)
--#define SCR_AW                (1U << 5)
--#define SCR_NET               (1U << 6)
--#define SCR_SMD               (1U << 7)
--#define SCR_HCE               (1U << 8)
--#define SCR_SIF               (1U << 9)
--#define SCR_RW                (1U << 10)
--#define SCR_ST                (1U << 11)
--#define SCR_TWI               (1U << 12)
--#define SCR_TWE               (1U << 13)
--#define SCR_TLOR              (1U << 14)
--#define SCR_TERR              (1U << 15)
--#define SCR_APK               (1U << 16)
--#define SCR_API               (1U << 17)
--#define SCR_EEL2              (1U << 18)
--#define SCR_EASE              (1U << 19)
--#define SCR_NMEA              (1U << 20)
--#define SCR_FIEN              (1U << 21)
--#define SCR_ENSCXT            (1U << 25)
--#define SCR_ATA               (1U << 26)
--#define SCR_FGTEN             (1U << 27)
--#define SCR_ECVEN             (1U << 28)
--#define SCR_TWEDEN            (1U << 29)
-+#define SCR_NS                (1ULL << 0)
-+#define SCR_IRQ               (1ULL << 1)
-+#define SCR_FIQ               (1ULL << 2)
-+#define SCR_EA                (1ULL << 3)
-+#define SCR_FW                (1ULL << 4)
-+#define SCR_AW                (1ULL << 5)
-+#define SCR_NET               (1ULL << 6)
-+#define SCR_SMD               (1ULL << 7)
-+#define SCR_HCE               (1ULL << 8)
-+#define SCR_SIF               (1ULL << 9)
-+#define SCR_RW                (1ULL << 10)
-+#define SCR_ST                (1ULL << 11)
-+#define SCR_TWI               (1ULL << 12)
-+#define SCR_TWE               (1ULL << 13)
-+#define SCR_TLOR              (1ULL << 14)
-+#define SCR_TERR              (1ULL << 15)
-+#define SCR_APK               (1ULL << 16)
-+#define SCR_API               (1ULL << 17)
-+#define SCR_EEL2              (1ULL << 18)
-+#define SCR_EASE              (1ULL << 19)
-+#define SCR_NMEA              (1ULL << 20)
-+#define SCR_FIEN              (1ULL << 21)
-+#define SCR_ENSCXT            (1ULL << 25)
-+#define SCR_ATA               (1ULL << 26)
-+#define SCR_FGTEN             (1ULL << 27)
-+#define SCR_ECVEN             (1ULL << 28)
-+#define SCR_TWEDEN            (1ULL << 29)
- #define SCR_TWEDEL            MAKE_64BIT_MASK(30, 4)
- #define SCR_TME               (1ULL << 34)
- #define SCR_AMVOFFEN          (1ULL << 35)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
- static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
- {
-     /* Begin with base v8.0 state.  */
--    uint32_t valid_mask = 0x3fff;
-+    uint64_t valid_mask = 0x3fff;
-     ARMCPU *cpu = env_archcpu(env);
-     /*
-@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
-         if (cpu_isar_feature(aa64_doublefault, cpu)) {
-             valid_mask |= SCR_EASE | SCR_NMEA;
-         }
-+        if (cpu_isar_feature(aa64_sme, cpu)) {
-+            valid_mask |= SCR_ENTP2;
-+        }
-     } else {
-         valid_mask &= ~(SCR_RW | SCR_ST);
-         if (cpu_isar_feature(aa32_ras, cpu)) {
---
-.25.1

-[PULL 03/28] docs/nuvoton: Update URL for images
+[PULL 01/21] hw/arm: Fix some typos in comments (most found by codespell)
-From: Joel Stanley <joel@jms.id.au>
+From: Stefan Weil <sw@weilnetz.de>
-openpower.xyz was retired some time ago. The OpenBMC Jenkins is where
+Signed-off-by: Stefan Weil <sw@weilnetz.de>
-images can be found these days.
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230409200526.1156456-1-sw@weilnetz.de
 Signed-off-by: Joel Stanley <joel@jms.id.au>
 Reviewed-by: Hao Wu <wuhaotsh@google.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20221004050042.22681-1-joel@jms.id.au
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/nuvoton.rst | 4 ++--
+ hw/arm/exynos4210.c       | 4 ++--
-file changed, 2 insertions(+), 2 deletions(-)
+ hw/arm/musicpal.c         | 2 +-
  hw/arm/omap1.c            | 2 +-
  hw/arm/omap2.c            | 2 +-
  hw/arm/virt-acpi-build.c  | 2 +-
  hw/arm/virt.c             | 2 +-
  hw/arm/xlnx-versal-virt.c | 2 +-
  hw/arm/Kconfig            | 2 +-
 files changed, 9 insertions(+), 9 deletions(-)
-diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/nuvoton.rst
+--- a/hw/arm/exynos4210.c
-+++ b/docs/system/arm/nuvoton.rst
++++ b/hw/arm/exynos4210.c
-@@ -XXX,XX +XXX,XX @@ Boot options
+@@ -XXX,XX +XXX,XX @@ static int mapline_size(const int *mapline)
- The Nuvoton machines can boot from an OpenBMC firmware image, or directly into
+ /*
- a kernel using the ``-kernel`` option. OpenBMC images for ``quanta-gsj`` and
+  * Initialize board IRQs.
--possibly others can be downloaded from the OpenPOWER jenkins :
+- * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
-+possibly others can be downloaded from the OpenBMC jenkins :
++ * These IRQs contain split Int/External Combiner and External Gic IRQs.
+  */
--   https://openpower.xyz/
+ static void exynos4210_init_board_irqs(Exynos4210State *s)
-+   https://jenkins.openbmc.org/
+ {
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
- The firmware image should be attached as an MTD drive. Example :
+          * - SDMA
+          * - ADMA2
           *
 -         * As this part of the Exynos4210 is not publically available,
 +         * As this part of the Exynos4210 is not publicly available,
           * we used the "HS-MMC Controller S3C2416X RISC Microprocessor"
           * public datasheet which is very similar (implementing
           * MMC Specification Version 4.0 being the only difference noted)
 diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/musicpal.c
 +++ b/hw/arm/musicpal.c
@@ -XXX,XX +XXX,XX @@
  #define MP_LCD_SPI_CMD          0x00104011
  #define MP_LCD_SPI_INVALID      0x00000000
 -/* Commmands */
 +/* Commands */
  #define MP_LCD_INST_SETPAGE0    0xB0
  /* ... */
  #define MP_LCD_INST_SETPAGE7    0xB7
 diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/omap1.c
 +++ b/hw/arm/omap1.c
@@ -XXX,XX +XXX,XX @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
      s->led[1] = omap_lpg_init(system_memory,
 xfffbd800, omap_findclk(s, "clk32-kHz"));
 -    /* Register mappings not currenlty implemented:
 +    /* Register mappings not currently implemented:
       * MCSI2 Comm    fffb2000 - fffb27ff (not mapped on OMAP310)
       * MCSI1 Bluetooth    fffb2800 - fffb2fff (not mapped on OMAP310)
       * USB W2FC        fffb4000 - fffb47ff
 diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/omap2.c
 +++ b/hw/arm/omap2.c
@@ -XXX,XX +XXX,XX @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
                      omap_findclk(s, "func_96m_clk"),
                      omap_findclk(s, "core_l4_iclk"));
 -    /* All register mappings (includin those not currenlty implemented):
 +    /* All register mappings (including those not currently implemented):
       * SystemControlMod    48000000 - 48000fff
       * SystemControlL4    48001000 - 48001fff
       * 32kHz Timer Mod    48004000 - 48004fff
 diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt-acpi-build.c
 +++ b/hw/arm/virt-acpi-build.c
@@ -XXX,XX +XXX,XX @@ static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size)
      build_append_int_noprefix(table_data, 0xE, 1);  /* Type */
      build_append_int_noprefix(table_data, 16, 1);   /* Length */
      build_append_int_noprefix(table_data, 0, 2);    /* Reserved */
 -    /* Discovery Range Base Addres */
 +    /* Discovery Range Base Address */
      build_append_int_noprefix(table_data, base, 8);
      build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */
  }
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
          int pa_bits;
          /*
 -         * Instanciate a temporary CPU object to find out about what
 +         * Instantiate a temporary CPU object to find out about what
           * we are about to deal with. Once this is done, get rid of
           * the object.
           */
 diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/xlnx-versal-virt.c
 +++ b/hw/arm/xlnx-versal-virt.c
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
      fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
      /* Make the APU cpu address space visible to virtio and other
 -     * modules unaware of muliple address-spaces.  */
 +     * modules unaware of multiple address-spaces.  */
      memory_region_add_subregion_overlap(get_system_memory(),
 , &s->soc.fpd.apu.mr, 0);
 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/Kconfig
 +++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config OLIMEX_STM32_H405
  config NSERIES
      bool
      select OMAP
 -    select TMP105   # tempature sensor
 +    select TMP105   # temperature sensor
      select BLIZZARD # LCD/TV controller
      select ONENAND
      select TSC210X  # touchscreen/sensors/audio
 --
-.25.1
+.34.1

-[PULL 04/28] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-The starting security state comes with the translation regime,
-not the current state of arm_is_secure_below_el3().
-Create a new local variable, s2walk_secure, which does not need
-to be written back to result->attrs.secure -- we compute that
-value later, after the S2 walk is complete.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20221001162318.153420-2-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/ptw.c | 18 +++++++++---------
-file changed, 9 insertions(+), 9 deletions(-)
-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
-+++ b/target/arm/ptw.c
-@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
-             hwaddr ipa;
-             int s1_prot;
-             int ret;
--            bool ipa_secure;
-+            bool ipa_secure, s2walk_secure;
-             ARMCacheAttrs cacheattrs1;
-             ARMMMUIdx s2_mmu_idx;
-             bool is_el0;
-@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
-             ipa = result->phys;
-             ipa_secure = result->attrs.secure;
--            if (arm_is_secure_below_el3(env)) {
--                if (ipa_secure) {
--                    result->attrs.secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
--                } else {
--                    result->attrs.secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
--                }
-+            if (is_secure) {
-+                /* Select TCR based on the NS bit from the S1 walk. */
-+                s2walk_secure = !(ipa_secure
-+                                  ? env->cp15.vstcr_el2 & VSTCR_SW
-+                                  : env->cp15.vtcr_el2 & VTCR_NSW);
-             } else {
-                 assert(!ipa_secure);
-+                s2walk_secure = false;
-             }
--            s2_mmu_idx = (result->attrs.secure
-+            s2_mmu_idx = (s2walk_secure
-                           ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2);
-             is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0;
-@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
-                                                     result->cacheattrs);
-             /* Check if IPA translates to secure or non-secure PA space. */
--            if (arm_is_secure_below_el3(env)) {
-+            if (is_secure) {
-                 if (ipa_secure) {
-                     result->attrs.secure =
-                         !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW));
---
-.25.1

-[PULL 23/28] target/arm: Fix cacheattr in get_phys_addr_disabled
+[PULL 02/21] exynos: Fix out-of-bounds access in exynos4210_gcomp_find debug printf
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Feng Jiang <jiangfeng@kylinos.cn>
-Do not apply memattr or shareability for Stage2 translations.
+One of the debug printfs in exynos4210_gcomp_find() will
-Make sure to apply HCR_{DC,DCT} only to Regime_EL10, per the
+access outside the 's->g_timer.reg.comp[]' array if there
-pseudocode in AArch64.S1DisabledOutput.
+was no active comparator and 'res' is -1. Add a conditional
 to avoid this.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+This doesn't happen in normal use because the debug printfs
 are by default not compiled in.
 Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
 Message-id: 20230404074506.112615-1-jiangfeng@kylinos.cn
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20221001162318.153420-20-richard.henderson@linaro.org
+[PMM: Adjusted commit message to clarify that the overrun
 only happens if you've enabled debug printfs]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/ptw.c | 48 +++++++++++++++++++++++++-----------------------
+ hw/timer/exynos4210_mct.c | 13 ++++++++-----
-file changed, 25 insertions(+), 23 deletions(-)
+file changed, 8 insertions(+), 5 deletions(-)
-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
+diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
+--- a/hw/timer/exynos4210_mct.c
-+++ b/target/arm/ptw.c
++++ b/hw/timer/exynos4210_mct.c
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
+@@ -XXX,XX +XXX,XX @@ static int32_t exynos4210_gcomp_find(Exynos4210MCTState *s)
-                                    GetPhysAddrResult *result,
+         res = min_comp_i;
                                     ARMMMUFaultInfo *fi)
  {
 -    uint64_t hcr;
 -    uint8_t memattr;
 +    uint8_t memattr = 0x00;    /* Device nGnRnE */
 +    uint8_t shareability = 0;  /* non-sharable */
      if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) {
          int r_el = regime_el(env, mmu_idx);
 +
          if (arm_el_is_aa64(env, r_el)) {
              int pamax = arm_pamax(env_archcpu(env));
              uint64_t tcr = env->cp15.tcr_el[r_el];
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
               */
              address = extract64(address, 0, 52);
          }
 +
 +        /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
 +        if (r_el == 1) {
 +            uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure);
 +            if (hcr & HCR_DC) {
 +                if (hcr & HCR_DCT) {
 +                    memattr = 0xf0;  /* Tagged, Normal, WB, RWA */
 +                } else {
 +                    memattr = 0xff;  /* Normal, WB, RWA */
 +                }
 +            }
 +        }
 +        if (memattr == 0 && access_type == MMU_INST_FETCH) {
 +            if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
 +                memattr = 0xee;  /* Normal, WT, RA, NT */
 +            } else {
 +                memattr = 0x44;  /* Normal, NC, No */
 +            }
 +            shareability = 2; /* outer sharable */
 +        }
 +        result->cacheattrs.is_s2_format = false;
      }
-     result->phys = address;
+-    DPRINTF("found comparator %d: comp 0x%llx distance 0x%llx, gfrc 0x%llx\n",
-     result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+-            res,
-     result->page_size = TARGET_PAGE_SIZE;
+-            s->g_timer.reg.comp[res],
--
+-            distance_min,
--    /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
+-            gfrc);
--    hcr = arm_hcr_el2_eff_secstate(env, is_secure);
++    if (res >= 0) {
--    result->cacheattrs.shareability = 0;
++        DPRINTF("found comparator %d: "
--    result->cacheattrs.is_s2_format = false;
++                "comp 0x%llx distance 0x%llx, gfrc 0x%llx\n",
--    if (hcr & HCR_DC) {
++                res,
--        if (hcr & HCR_DCT) {
++                s->g_timer.reg.comp[res],
--            memattr = 0xf0;  /* Tagged, Normal, WB, RWA */
++                distance_min,
--        } else {
++                gfrc);
--            memattr = 0xff;  /* Normal, WB, RWA */
++    }
--        }
--    } else if (access_type == MMU_INST_FETCH) {
+     return res;
 -        if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
 -            memattr = 0xee;  /* Normal, WT, RA, NT */
 -        } else {
 -            memattr = 0x44;  /* Normal, NC, No */
 -        }
 -        result->cacheattrs.shareability = 2; /* outer sharable */
 -    } else {
 -        memattr = 0x00;      /* Device, nGnRnE */
 -    }
 +    result->cacheattrs.shareability = shareability;
      result->cacheattrs.attrs = memattr;
      return 0;
  }
 --
-.25.1
+.34.1

-[PULL 12/28] target/arm: Merge regime_is_secure into get_phys_addr
+[PULL 03/21] hw/watchdog: Allwinner WDT emulation for system reset
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
-This is the last use of regime_is_secure; remove it
+This patch adds basic support for Allwinner WDT.
-entirely before changing the layout of ARMMMUIdx.
+Both sun4i and sun6i variants are supported.
 However, interrupt generation is not supported, so WDT can be used only to trigger system reset.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
-Message-id: 20221001162318.153420-9-richard.henderson@linaro.org
+Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
 Message-id: 20230326202256.22980-2-strahinja.p.jankovic@gmail.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/internals.h | 42 ----------------------------------------
+ include/hw/watchdog/allwinner-wdt.h | 123 ++++++++
- target/arm/ptw.c       | 44 ++++++++++++++++++++++++++++++++++++++++--
+ hw/watchdog/allwinner-wdt.c         | 416 ++++++++++++++++++++++++++++
-files changed, 42 insertions(+), 44 deletions(-)
+ hw/watchdog/Kconfig                 |   4 +
  hw/watchdog/meson.build             |   1 +
  hw/watchdog/trace-events            |   7 +
 files changed, 551 insertions(+)
  create mode 100644 include/hw/watchdog/allwinner-wdt.h
  create mode 100644 hw/watchdog/allwinner-wdt.c
-diff --git a/target/arm/internals.h b/target/arm/internals.h
+diff --git a/include/hw/watchdog/allwinner-wdt.h b/include/hw/watchdog/allwinner-wdt.h
-index XXXXXXX..XXXXXXX 100644
+new file mode 100644
---- a/target/arm/internals.h
+index XXXXXXX..XXXXXXX
-+++ b/target/arm/internals.h
+--- /dev/null
-@@ -XXX,XX +XXX,XX @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx)
++++ b/include/hw/watchdog/allwinner-wdt.h
-     }
+@@ -XXX,XX +XXX,XX @@
- }
++/*
++ * Allwinner Watchdog emulation
--/* Return true if this address translation regime is secure */
++ *
--static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
++ * Copyright (C) 2023 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
--{
++ *
--    switch (mmu_idx) {
++ *  This file is derived from Allwinner RTC,
--    case ARMMMUIdx_E10_0:
++ *  by Niek Linnenbank.
--    case ARMMMUIdx_E10_1:
++ *
--    case ARMMMUIdx_E10_1_PAN:
++ * This program is free software: you can redistribute it and/or modify
--    case ARMMMUIdx_E20_0:
++ * it under the terms of the GNU General Public License as published by
--    case ARMMMUIdx_E20_2:
++ * the Free Software Foundation, either version 2 of the License, or
--    case ARMMMUIdx_E20_2_PAN:
++ * (at your option) any later version.
--    case ARMMMUIdx_Stage1_E0:
++ *
--    case ARMMMUIdx_Stage1_E1:
++ * This program is distributed in the hope that it will be useful,
--    case ARMMMUIdx_Stage1_E1_PAN:
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
--    case ARMMMUIdx_E2:
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--    case ARMMMUIdx_Stage2:
++ * GNU General Public License for more details.
--    case ARMMMUIdx_MPrivNegPri:
++ *
--    case ARMMMUIdx_MUserNegPri:
++ * You should have received a copy of the GNU General Public License
--    case ARMMMUIdx_MPriv:
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
--    case ARMMMUIdx_MUser:
++ */
--        return false;
++
--    case ARMMMUIdx_SE3:
++#ifndef HW_WATCHDOG_ALLWINNER_WDT_H
--    case ARMMMUIdx_SE10_0:
++#define HW_WATCHDOG_ALLWINNER_WDT_H
--    case ARMMMUIdx_SE10_1:
++
--    case ARMMMUIdx_SE10_1_PAN:
++#include "qom/object.h"
--    case ARMMMUIdx_SE20_0:
++#include "hw/ptimer.h"
--    case ARMMMUIdx_SE20_2:
++#include "hw/sysbus.h"
--    case ARMMMUIdx_SE20_2_PAN:
++
--    case ARMMMUIdx_Stage1_SE0:
++/*
--    case ARMMMUIdx_Stage1_SE1:
++ * This is a model of the Allwinner watchdog.
--    case ARMMMUIdx_Stage1_SE1_PAN:
++ * Since watchdog registers belong to the timer module (and are shared with the
--    case ARMMMUIdx_SE2:
++ * RTC module), the interrupt line from watchdog is not handled right now.
--    case ARMMMUIdx_Stage2_S:
++ * In QEMU, we just wire up the watchdog reset to watchdog_perform_action(),
--    case ARMMMUIdx_MSPrivNegPri:
++ * at least for the moment.
--    case ARMMMUIdx_MSUserNegPri:
++ */
--    case ARMMMUIdx_MSPriv:
++
--    case ARMMMUIdx_MSUser:
++#define TYPE_AW_WDT    "allwinner-wdt"
--        return true;
++
--    default:
++/** Allwinner WDT sun4i family (A10, A12), also sun7i (A20) */
--        g_assert_not_reached();
++#define TYPE_AW_WDT_SUN4I    TYPE_AW_WDT "-sun4i"
--    }
++
--}
++/** Allwinner WDT sun6i family and newer (A31, H2+, H3, etc) */
--
++#define TYPE_AW_WDT_SUN6I    TYPE_AW_WDT "-sun6i"
- static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx)
++
- {
++/** Number of WDT registers */
-     switch (mmu_idx) {
++#define AW_WDT_REGS_NUM      (5)
-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
++
-index XXXXXXX..XXXXXXX 100644
++OBJECT_DECLARE_TYPE(AwWdtState, AwWdtClass, AW_WDT)
---- a/target/arm/ptw.c
++
-+++ b/target/arm/ptw.c
++/**
-@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
++ * Allwinner WDT object instance state.
-                    MMUAccessType access_type, ARMMMUIdx mmu_idx,
++ */
-                    GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
++struct AwWdtState {
- {
++    /*< private >*/
-+    bool is_secure;
++    SysBusDevice parent_obj;
 +
-+    switch (mmu_idx) {
++    /*< public >*/
-+    case ARMMMUIdx_E10_0:
++    MemoryRegion iomem;
-+    case ARMMMUIdx_E10_1:
++    struct ptimer_state *timer;
-+    case ARMMMUIdx_E10_1_PAN:
++
-+    case ARMMMUIdx_E20_0:
++    uint32_t regs[AW_WDT_REGS_NUM];
-+    case ARMMMUIdx_E20_2:
++};
-+    case ARMMMUIdx_E20_2_PAN:
++
-+    case ARMMMUIdx_Stage1_E0:
++/**
-+    case ARMMMUIdx_Stage1_E1:
++ * Allwinner WDT class-level struct.
-+    case ARMMMUIdx_Stage1_E1_PAN:
++ *
-+    case ARMMMUIdx_E2:
++ * This struct is filled by each sunxi device specific code
-+    case ARMMMUIdx_Stage2:
++ * such that the generic code can use this struct to support
-+    case ARMMMUIdx_MPrivNegPri:
++ * all devices.
-+    case ARMMMUIdx_MUserNegPri:
++ */
-+    case ARMMMUIdx_MPriv:
++struct AwWdtClass {
-+    case ARMMMUIdx_MUser:
++    /*< private >*/
-+        is_secure = false;
++    SysBusDeviceClass parent_class;
 +    /*< public >*/
 +
 +    /** Defines device specific register map */
 +    const uint8_t *regmap;
 +
 +    /** Size of the regmap in bytes */
 +    size_t regmap_size;
 +
 +    /**
 +     * Read device specific register
 +     *
 +     * @offset: register offset to read
 +     * @return true if register read successful, false otherwise
 +     */
 +    bool (*read)(AwWdtState *s, uint32_t offset);
 +
 +    /**
 +     * Write device specific register
 +     *
 +     * @offset: register offset to write
 +     * @data: value to set in register
 +     * @return true if register write successful, false otherwise
 +     */
 +    bool (*write)(AwWdtState *s, uint32_t offset, uint32_t data);
 +
 +    /**
 +     * Check if watchdog can generate system reset
 +     *
 +     * @return true if watchdog can generate system reset
 +     */
 +    bool (*can_reset_system)(AwWdtState *s);
 +
 +    /**
 +     * Check if provided key is valid
 +     *
 +     * @value: value written to register
 +     * @return true if key is valid, false otherwise
 +     */
 +    bool (*is_key_valid)(AwWdtState *s, uint32_t val);
 +
 +    /**
 +     * Get current INTV_VALUE setting
 +     *
 +     * @return current INTV_VALUE (0-15)
 +     */
 +    uint8_t (*get_intv_value)(AwWdtState *s);
 +};
 +
 +#endif /* HW_WATCHDOG_ALLWINNER_WDT_H */
 diff --git a/hw/watchdog/allwinner-wdt.c b/hw/watchdog/allwinner-wdt.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/watchdog/allwinner-wdt.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Allwinner Watchdog emulation
 + *
 + * Copyright (C) 2023 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
 + *
 + *  This file is derived from Allwinner RTC,
 + *  by Niek Linnenbank.
 + *
 + * This program is free software: you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License as published by
 + * the Free Software Foundation, either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/log.h"
 +#include "qemu/units.h"
 +#include "qemu/module.h"
 +#include "trace.h"
 +#include "hw/sysbus.h"
 +#include "hw/registerfields.h"
 +#include "hw/watchdog/allwinner-wdt.h"
 +#include "sysemu/watchdog.h"
 +#include "migration/vmstate.h"
 +
 +/* WDT registers */
 +enum {
 +    REG_IRQ_EN = 0,     /* Watchdog interrupt enable */
 +    REG_IRQ_STA,        /* Watchdog interrupt status */
 +    REG_CTRL,           /* Watchdog control register */
 +    REG_CFG,            /* Watchdog configuration register */
 +    REG_MODE,           /* Watchdog mode register */
 +};
 +
 +/* Universal WDT register flags */
 +#define WDT_RESTART_MASK    (1 << 0)
 +#define WDT_EN_MASK         (1 << 0)
 +
 +/* sun4i specific WDT register flags */
 +#define RST_EN_SUN4I_MASK       (1 << 1)
 +#define INTV_VALUE_SUN4I_SHIFT  (3)
 +#define INTV_VALUE_SUN4I_MASK   (0xfu << INTV_VALUE_SUN4I_SHIFT)
 +
 +/* sun6i specific WDT register flags */
 +#define RST_EN_SUN6I_MASK       (1 << 0)
 +#define KEY_FIELD_SUN6I_SHIFT   (1)
 +#define KEY_FIELD_SUN6I_MASK    (0xfffu << KEY_FIELD_SUN6I_SHIFT)
 +#define KEY_FIELD_SUN6I         (0xA57u)
 +#define INTV_VALUE_SUN6I_SHIFT  (4)
 +#define INTV_VALUE_SUN6I_MASK   (0xfu << INTV_VALUE_SUN6I_SHIFT)
 +
 +/* Map of INTV_VALUE to 0.5s units. */
 +static const uint8_t allwinner_wdt_count_map[] = {
 +    1,
 +    2,
 +    4,
 +    6,
 +    8,
 +    10,
 +    12,
 +    16,
 +    20,
 +    24,
 +    28,
 +    32
 +};
 +
 +/* WDT sun4i register map (offset to name) */
 +const uint8_t allwinner_wdt_sun4i_regmap[] = {
 +    [0x0000] = REG_CTRL,
 +    [0x0004] = REG_MODE,
 +};
 +
 +/* WDT sun6i register map (offset to name) */
 +const uint8_t allwinner_wdt_sun6i_regmap[] = {
 +    [0x0000] = REG_IRQ_EN,
 +    [0x0004] = REG_IRQ_STA,
 +    [0x0010] = REG_CTRL,
 +    [0x0014] = REG_CFG,
 +    [0x0018] = REG_MODE,
 +};
 +
 +static bool allwinner_wdt_sun4i_read(AwWdtState *s, uint32_t offset)
 +{
 +    /* no sun4i specific registers currently implemented */
 +    return false;
 +}
 +
 +static bool allwinner_wdt_sun4i_write(AwWdtState *s, uint32_t offset,
 +                                      uint32_t data)
 +{
 +    /* no sun4i specific registers currently implemented */
 +    return false;
 +}
 +
 +static bool allwinner_wdt_sun4i_can_reset_system(AwWdtState *s)
 +{
 +    if (s->regs[REG_MODE] & RST_EN_SUN4I_MASK) {
 +        return true;
 +    } else {
 +        return false;
 +    }
 +}
 +
 +static bool allwinner_wdt_sun4i_is_key_valid(AwWdtState *s, uint32_t val)
 +{
 +    /* sun4i has no key */
 +    return true;
 +}
 +
 +static uint8_t allwinner_wdt_sun4i_get_intv_value(AwWdtState *s)
 +{
 +    return ((s->regs[REG_MODE] & INTV_VALUE_SUN4I_MASK) >>
 +            INTV_VALUE_SUN4I_SHIFT);
 +}
 +
 +static bool allwinner_wdt_sun6i_read(AwWdtState *s, uint32_t offset)
 +{
 +    const AwWdtClass *c = AW_WDT_GET_CLASS(s);
 +
 +    switch (c->regmap[offset]) {
 +    case REG_IRQ_EN:
 +    case REG_IRQ_STA:
 +    case REG_CFG:
 +        return true;
 +    default:
 +        break;
-+    case ARMMMUIdx_SE3:
++    }
-+    case ARMMMUIdx_SE10_0:
++    return false;
-+    case ARMMMUIdx_SE10_1:
++}
-+    case ARMMMUIdx_SE10_1_PAN:
++
-+    case ARMMMUIdx_SE20_0:
++static bool allwinner_wdt_sun6i_write(AwWdtState *s, uint32_t offset,
-+    case ARMMMUIdx_SE20_2:
++                                      uint32_t data)
-+    case ARMMMUIdx_SE20_2_PAN:
++{
-+    case ARMMMUIdx_Stage1_SE0:
++    const AwWdtClass *c = AW_WDT_GET_CLASS(s);
-+    case ARMMMUIdx_Stage1_SE1:
++
-+    case ARMMMUIdx_Stage1_SE1_PAN:
++    switch (c->regmap[offset]) {
-+    case ARMMMUIdx_SE2:
++    case REG_IRQ_EN:
-+    case ARMMMUIdx_Stage2_S:
++    case REG_IRQ_STA:
-+    case ARMMMUIdx_MSPrivNegPri:
++    case REG_CFG:
-+    case ARMMMUIdx_MSUserNegPri:
++        return true;
-+    case ARMMMUIdx_MSPriv:
++    default:
-+    case ARMMMUIdx_MSUser:
++        break;
-+        is_secure = true;
++    }
 +    return false;
 +}
 +
 +static bool allwinner_wdt_sun6i_can_reset_system(AwWdtState *s)
 +{
 +    if (s->regs[REG_CFG] & RST_EN_SUN6I_MASK) {
 +        return true;
 +    } else {
 +        return false;
 +    }
 +}
 +
 +static bool allwinner_wdt_sun6i_is_key_valid(AwWdtState *s, uint32_t val)
 +{
 +    uint16_t key = (val & KEY_FIELD_SUN6I_MASK) >> KEY_FIELD_SUN6I_SHIFT;
 +    return (key == KEY_FIELD_SUN6I);
 +}
 +
 +static uint8_t allwinner_wdt_sun6i_get_intv_value(AwWdtState *s)
 +{
 +    return ((s->regs[REG_MODE] & INTV_VALUE_SUN6I_MASK) >>
 +            INTV_VALUE_SUN6I_SHIFT);
 +}
 +
 +static void allwinner_wdt_update_timer(AwWdtState *s)
 +{
 +    const AwWdtClass *c = AW_WDT_GET_CLASS(s);
 +    uint8_t count = c->get_intv_value(s);
 +
 +    ptimer_transaction_begin(s->timer);
 +    ptimer_stop(s->timer);
 +
 +    /* Use map to convert. */
 +    if (count < sizeof(allwinner_wdt_count_map)) {
 +        ptimer_set_count(s->timer, allwinner_wdt_count_map[count]);
 +    } else {
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: incorrect INTV_VALUE 0x%02x\n",
 +                __func__, count);
 +    }
 +
 +    ptimer_run(s->timer, 1);
 +    ptimer_transaction_commit(s->timer);
 +
 +    trace_allwinner_wdt_update_timer(count);
 +}
 +
 +static uint64_t allwinner_wdt_read(void *opaque, hwaddr offset,
 +                                       unsigned size)
 +{
 +    AwWdtState *s = AW_WDT(opaque);
 +    const AwWdtClass *c = AW_WDT_GET_CLASS(s);
 +    uint64_t r;
 +
 +    if (offset >= c->regmap_size) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
 +                      __func__, (uint32_t)offset);
 +        return 0;
 +    }
 +
 +    switch (c->regmap[offset]) {
 +    case REG_CTRL:
 +    case REG_MODE:
 +        r = s->regs[c->regmap[offset]];
 +        break;
 +    default:
-+        g_assert_not_reached();
++        if (!c->read(s, offset)) {
-+    }
++            qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
-     return get_phys_addr_with_secure(env, address, access_type, mmu_idx,
++                            __func__, (uint32_t)offset);
--                                     regime_is_secure(env, mmu_idx),
++            return 0;
--                                     result, fi);
++        }
-+                                     is_secure, result, fi);
++        r = s->regs[c->regmap[offset]];
- }
++        break;
++    }
- hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
++
 +    trace_allwinner_wdt_read(offset, r, size);
 +
 +    return r;
 +}
 +
 +static void allwinner_wdt_write(void *opaque, hwaddr offset,
 +                                   uint64_t val, unsigned size)
 +{
 +    AwWdtState *s = AW_WDT(opaque);
 +    const AwWdtClass *c = AW_WDT_GET_CLASS(s);
 +    uint32_t old_val;
 +
 +    if (offset >= c->regmap_size) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
 +                      __func__, (uint32_t)offset);
 +        return;
 +    }
 +
 +   trace_allwinner_wdt_write(offset, val, size);
 +
 +    switch (c->regmap[offset]) {
 +    case REG_CTRL:
 +        if (c->is_key_valid(s, val)) {
 +            if (val & WDT_RESTART_MASK) {
 +                /* Kick timer */
 +                allwinner_wdt_update_timer(s);
 +            }
 +        }
 +        break;
 +    case REG_MODE:
 +        old_val = s->regs[REG_MODE];
 +        s->regs[REG_MODE] = (uint32_t)val;
 +
 +        /* Check for rising edge on WDOG_MODE_EN */
 +        if ((s->regs[REG_MODE] & ~old_val) & WDT_EN_MASK) {
 +            allwinner_wdt_update_timer(s);
 +        }
 +        break;
 +    default:
 +        if (!c->write(s, offset, val)) {
 +            qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
 +                          __func__, (uint32_t)offset);
 +        }
 +        s->regs[c->regmap[offset]] = (uint32_t)val;
 +        break;
 +    }
 +}
 +
 +static const MemoryRegionOps allwinner_wdt_ops = {
 +    .read = allwinner_wdt_read,
 +    .write = allwinner_wdt_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .valid = {
 +        .min_access_size = 4,
 +        .max_access_size = 4,
 +    },
 +    .impl.min_access_size = 4,
 +};
 +
 +static void allwinner_wdt_expired(void *opaque)
 +{
 +    AwWdtState *s = AW_WDT(opaque);
 +    const AwWdtClass *c = AW_WDT_GET_CLASS(s);
 +
 +    bool enabled = s->regs[REG_MODE] & WDT_EN_MASK;
 +    bool reset_enabled = c->can_reset_system(s);
 +
 +    trace_allwinner_wdt_expired(enabled, reset_enabled);
 +
 +    /* Perform watchdog action if watchdog is enabled and can trigger reset */
 +    if (enabled && reset_enabled) {
 +        watchdog_perform_action();
 +    }
 +}
 +
 +static void allwinner_wdt_reset_enter(Object *obj, ResetType type)
 +{
 +    AwWdtState *s = AW_WDT(obj);
 +
 +    trace_allwinner_wdt_reset_enter();
 +
 +    /* Clear registers */
 +    memset(s->regs, 0, sizeof(s->regs));
 +}
 +
 +static const VMStateDescription allwinner_wdt_vmstate = {
 +    .name = "allwinner-wdt",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_PTIMER(timer, AwWdtState),
 +        VMSTATE_UINT32_ARRAY(regs, AwWdtState, AW_WDT_REGS_NUM),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static void allwinner_wdt_init(Object *obj)
 +{
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    AwWdtState *s = AW_WDT(obj);
 +    const AwWdtClass *c = AW_WDT_GET_CLASS(s);
 +
 +    /* Memory mapping */
 +    memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_wdt_ops, s,
 +                          TYPE_AW_WDT, c->regmap_size * 4);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +}
 +
 +static void allwinner_wdt_realize(DeviceState *dev, Error **errp)
 +{
 +    AwWdtState *s = AW_WDT(dev);
 +
 +    s->timer = ptimer_init(allwinner_wdt_expired, s,
 +                           PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
 +                           PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
 +                           PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
 +
 +    ptimer_transaction_begin(s->timer);
 +    /* Set to 2Hz (0.5s period); other periods are multiples of 0.5s. */
 +    ptimer_set_freq(s->timer, 2);
 +    ptimer_set_limit(s->timer, 0xff, 1);
 +    ptimer_transaction_commit(s->timer);
 +}
 +
 +static void allwinner_wdt_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +
 +    rc->phases.enter = allwinner_wdt_reset_enter;
 +    dc->realize = allwinner_wdt_realize;
 +    dc->vmsd = &allwinner_wdt_vmstate;
 +}
 +
 +static void allwinner_wdt_sun4i_class_init(ObjectClass *klass, void *data)
 +{
 +    AwWdtClass *awc = AW_WDT_CLASS(klass);
 +
 +    awc->regmap = allwinner_wdt_sun4i_regmap;
 +    awc->regmap_size = sizeof(allwinner_wdt_sun4i_regmap);
 +    awc->read = allwinner_wdt_sun4i_read;
 +    awc->write = allwinner_wdt_sun4i_write;
 +    awc->can_reset_system = allwinner_wdt_sun4i_can_reset_system;
 +    awc->is_key_valid = allwinner_wdt_sun4i_is_key_valid;
 +    awc->get_intv_value = allwinner_wdt_sun4i_get_intv_value;
 +}
 +
 +static void allwinner_wdt_sun6i_class_init(ObjectClass *klass, void *data)
 +{
 +    AwWdtClass *awc = AW_WDT_CLASS(klass);
 +
 +    awc->regmap = allwinner_wdt_sun6i_regmap;
 +    awc->regmap_size = sizeof(allwinner_wdt_sun6i_regmap);
 +    awc->read = allwinner_wdt_sun6i_read;
 +    awc->write = allwinner_wdt_sun6i_write;
 +    awc->can_reset_system = allwinner_wdt_sun6i_can_reset_system;
 +    awc->is_key_valid = allwinner_wdt_sun6i_is_key_valid;
 +    awc->get_intv_value = allwinner_wdt_sun6i_get_intv_value;
 +}
 +
 +static const TypeInfo allwinner_wdt_info = {
 +    .name          = TYPE_AW_WDT,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_init = allwinner_wdt_init,
 +    .instance_size = sizeof(AwWdtState),
 +    .class_init    = allwinner_wdt_class_init,
 +    .class_size    = sizeof(AwWdtClass),
 +    .abstract      = true,
 +};
 +
 +static const TypeInfo allwinner_wdt_sun4i_info = {
 +    .name          = TYPE_AW_WDT_SUN4I,
 +    .parent        = TYPE_AW_WDT,
 +    .class_init    = allwinner_wdt_sun4i_class_init,
 +};
 +
 +static const TypeInfo allwinner_wdt_sun6i_info = {
 +    .name          = TYPE_AW_WDT_SUN6I,
 +    .parent        = TYPE_AW_WDT,
 +    .class_init    = allwinner_wdt_sun6i_class_init,
 +};
 +
 +static void allwinner_wdt_register(void)
 +{
 +    type_register_static(&allwinner_wdt_info);
 +    type_register_static(&allwinner_wdt_sun4i_info);
 +    type_register_static(&allwinner_wdt_sun6i_info);
 +}
 +
 +type_init(allwinner_wdt_register)
 diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/watchdog/Kconfig
 +++ b/hw/watchdog/Kconfig
@@ -XXX,XX +XXX,XX @@ config WDT_IMX2
  config WDT_SBSA
      bool
 +
 +config ALLWINNER_WDT
 +    bool
 +    select PTIMER
 diff --git a/hw/watchdog/meson.build b/hw/watchdog/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/watchdog/meson.build
 +++ b/hw/watchdog/meson.build
@@ -XXX,XX +XXX,XX @@
  softmmu_ss.add(files('watchdog.c'))
 +softmmu_ss.add(when: 'CONFIG_ALLWINNER_WDT', if_true: files('allwinner-wdt.c'))
  softmmu_ss.add(when: 'CONFIG_CMSDK_APB_WATCHDOG', if_true: files('cmsdk-apb-watchdog.c'))
  softmmu_ss.add(when: 'CONFIG_WDT_IB6300ESB', if_true: files('wdt_i6300esb.c'))
  softmmu_ss.add(when: 'CONFIG_WDT_IB700', if_true: files('wdt_ib700.c'))
 diff --git a/hw/watchdog/trace-events b/hw/watchdog/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/watchdog/trace-events
 +++ b/hw/watchdog/trace-events
@@ -XXX,XX +XXX,XX @@
  # See docs/devel/tracing.rst for syntax documentation.
 +# allwinner-wdt.c
 +allwinner_wdt_read(uint64_t offset, uint64_t data, unsigned size) "Allwinner watchdog read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 +allwinner_wdt_write(uint64_t offset, uint64_t data, unsigned size) "Allwinner watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 +allwinner_wdt_reset_enter(void) "Allwinner watchdog: reset"
 +allwinner_wdt_update_timer(uint8_t count) "Allwinner watchdog: count %" PRIu8
 +allwinner_wdt_expired(bool enabled, bool reset_enabled) "Allwinner watchdog: enabled %u reset_enabled %u"
 +
  # cmsdk-apb-watchdog.c
  cmsdk_apb_watchdog_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
  cmsdk_apb_watchdog_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 --
-.25.1
+.34.1

-[PULL 17/28] target/arm: Introduce arm_hcr_el2_eff_secstate
+[PULL 04/21] hw/arm: Add WDT to Allwinner-A10 and Cubieboard
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
-For page walking, we may require HCR for a security state
+This patch adds WDT to Allwinner-A10 and Cubieboard.
-that is not "current".
+WDT is added as an overlay to the Timer module memory map.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
-Message-id: 20221001162318.153420-14-richard.henderson@linaro.org
+Message-id: 20230326202256.22980-3-strahinja.p.jankovic@gmail.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h    | 20 +++++++++++++-------
+ docs/system/arm/cubieboard.rst | 1 +
- target/arm/helper.c | 11 ++++++++---
+ include/hw/arm/allwinner-a10.h | 2 ++
-files changed, 21 insertions(+), 10 deletions(-)
+ hw/arm/allwinner-a10.c         | 7 +++++++
  hw/arm/Kconfig                 | 1 +
 files changed, 11 insertions(+)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/docs/system/arm/cubieboard.rst b/docs/system/arm/cubieboard.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/docs/system/arm/cubieboard.rst
-+++ b/target/arm/cpu.h
++++ b/docs/system/arm/cubieboard.rst
-@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure(CPUARMState *env)
+@@ -XXX,XX +XXX,XX @@ Emulated devices:
-  * Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
+ - USB controller
-  * This corresponds to the pseudocode EL2Enabled()
+ - SATA controller
-  */
+ - TWI (I2C) controller
-+static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
++- Watchdog timer
-+{
+diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
-+    return arm_feature(env, ARM_FEATURE_EL2)
+index XXXXXXX..XXXXXXX 100644
-+           && (!secure || (env->cp15.scr_el3 & SCR_EEL2));
+--- a/include/hw/arm/allwinner-a10.h
-+}
++++ b/include/hw/arm/allwinner-a10.h
@@ -XXX,XX +XXX,XX @@
  #include "hw/misc/allwinner-a10-ccm.h"
  #include "hw/misc/allwinner-a10-dramc.h"
  #include "hw/i2c/allwinner-i2c.h"
 +#include "hw/watchdog/allwinner-wdt.h"
  #include "sysemu/block-backend.h"
  #include "target/arm/cpu.h"
@@ -XXX,XX +XXX,XX @@ struct AwA10State {
      AwSdHostState mmc0;
      AWI2CState i2c0;
      AwRtcState rtc;
 +    AwWdtState wdt;
      MemoryRegion sram_a;
      EHCISysBusState ehci[AW_A10_NUM_USB];
      OHCISysBusState ohci[AW_A10_NUM_USB];
 diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/allwinner-a10.c
 +++ b/hw/arm/allwinner-a10.c
@@ -XXX,XX +XXX,XX @@
  #define AW_A10_EHCI_BASE        0x01c14000
  #define AW_A10_OHCI_BASE        0x01c14400
  #define AW_A10_SATA_BASE        0x01c18000
 +#define AW_A10_WDT_BASE         0x01c20c90
  #define AW_A10_RTC_BASE         0x01c20d00
  #define AW_A10_I2C0_BASE        0x01c2ac00
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
      object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I);
      object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I);
 +
- static inline bool arm_is_el2_enabled(CPUARMState *env)
++    object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I);
  {
 -    if (arm_feature(env, ARM_FEATURE_EL2)) {
 -        if (arm_is_secure_below_el3(env)) {
 -            return (env->cp15.scr_el3 & SCR_EEL2) != 0;
 -        }
 -        return true;
 -    }
 -    return false;
 +    return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env));
  }
- #else
+ static void aw_a10_realize(DeviceState *dev, Error **errp)
-@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure(CPUARMState *env)
+@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
-     return false;
+     sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE);
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7));
 +
 +    /* WDT */
 +    sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);
 +    sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0, AW_A10_WDT_BASE, 1);
  }
-+static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
+ static void aw_a10_class_init(ObjectClass *oc, void *data)
-+{
+diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
 +    return false;
 +}
 +
  static inline bool arm_is_el2_enabled(CPUARMState *env)
  {
      return false;
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_el2_enabled(CPUARMState *env)
   * "for all purposes other than a direct read or write access of HCR_EL2."
   * Not included here is HCR_RW.
   */
 +uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure);
  uint64_t arm_hcr_el2_eff(CPUARMState *env);
  uint64_t arm_hcrx_el2_eff(CPUARMState *env);
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/arm/Kconfig
-+++ b/target/arm/helper.c
++++ b/hw/arm/Kconfig
-@@ -XXX,XX +XXX,XX @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
- }
+     select ALLWINNER_A10_PIC
+     select ALLWINNER_A10_CCM
- /*
+     select ALLWINNER_A10_DRAMC
-- * Return the effective value of HCR_EL2.
++    select ALLWINNER_WDT
-+ * Return the effective value of HCR_EL2, at the given security state.
+     select ALLWINNER_EMAC
-  * Bits that are not included here:
+     select ALLWINNER_I2C
-  * RW       (read from SCR_EL3.RW as needed)
+     select AXP209_PMU
   */
 -uint64_t arm_hcr_el2_eff(CPUARMState *env)
 +uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure)
  {
      uint64_t ret = env->cp15.hcr_el2;
 -    if (!arm_is_el2_enabled(env)) {
 +    if (!arm_is_el2_enabled_secstate(env, secure)) {
          /*
           * "This register has no effect if EL2 is not enabled in the
           * current Security state".  This is ARMv8.4-SecEL2 speak for
@@ -XXX,XX +XXX,XX @@ uint64_t arm_hcr_el2_eff(CPUARMState *env)
      return ret;
  }
 +uint64_t arm_hcr_el2_eff(CPUARMState *env)
 +{
 +    return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env));
 +}
 +
  /*
   * Corresponds to ARM pseudocode function ELIsInHost().
   */
 --
-.25.1
+.34.1

-[PULL 20/28] target/arm: Pass HCR to attribute subroutines.
+[PULL 05/21] hw/arm: Add WDT to Allwinner-H3 and Orangepi-PC
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
-These subroutines did not need ENV for anything except
+This patch adds WDT to Allwinner-H3 and Orangepi-PC.
-retrieving the effective value of HCR anyway.
+WDT is added as an overlay to the Timer module memory area.
-We have computed the effective value of HCR in the callers,
+Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
-and this will be especially important for interpreting HCR
+Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
-in a non-current security state.
+Message-id: 20230326202256.22980-4-strahinja.p.jankovic@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20221001162318.153420-17-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/ptw.c | 30 +++++++++++++++++-------------
+ docs/system/arm/orangepi.rst  | 1 +
-file changed, 17 insertions(+), 13 deletions(-)
+ include/hw/arm/allwinner-h3.h | 5 ++++-
  hw/arm/allwinner-h3.c         | 8 ++++++++
  hw/arm/Kconfig                | 1 +
 files changed, 14 insertions(+), 1 deletion(-)
-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
+diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
+--- a/docs/system/arm/orangepi.rst
-+++ b/target/arm/ptw.c
++++ b/docs/system/arm/orangepi.rst
-@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
+@@ -XXX,XX +XXX,XX @@ The Orange Pi PC machine supports the following devices:
-     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
+  * System Control module
   * Security Identifier device
   * TWI (I2C)
 + * Watchdog timer
  Limitations
  """""""""""
 diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/allwinner-h3.h
 +++ b/include/hw/arm/allwinner-h3.h
@@ -XXX,XX +XXX,XX @@
  #include "hw/net/allwinner-sun8i-emac.h"
  #include "hw/rtc/allwinner-rtc.h"
  #include "hw/i2c/allwinner-i2c.h"
 +#include "hw/watchdog/allwinner-wdt.h"
  #include "target/arm/cpu.h"
  #include "sysemu/block-backend.h"
@@ -XXX,XX +XXX,XX @@ enum {
      AW_H3_DEV_RTC,
      AW_H3_DEV_CPUCFG,
      AW_H3_DEV_R_TWI,
 -    AW_H3_DEV_SDRAM
 +    AW_H3_DEV_SDRAM,
 +    AW_H3_DEV_WDT
  };
  /** Total number of CPU cores in the H3 SoC */
@@ -XXX,XX +XXX,XX @@ struct AwH3State {
      AWI2CState r_twi;
      AwSun8iEmacState emac;
      AwRtcState rtc;
 +    AwWdtState wdt;
      GICState gic;
      MemoryRegion sram_a1;
      MemoryRegion sram_a2;
 diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/allwinner-h3.c
 +++ b/hw/arm/allwinner-h3.c
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
      [AW_H3_DEV_OHCI3]      = 0x01c1d400,
      [AW_H3_DEV_CCU]        = 0x01c20000,
      [AW_H3_DEV_PIT]        = 0x01c20c00,
 +    [AW_H3_DEV_WDT]        = 0x01c20ca0,
      [AW_H3_DEV_UART0]      = 0x01c28000,
      [AW_H3_DEV_UART1]      = 0x01c28400,
      [AW_H3_DEV_UART2]      = 0x01c28800,
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
      object_initialize_child(obj, "twi1",  &s->i2c1,  TYPE_AW_I2C_SUN6I);
      object_initialize_child(obj, "twi2",  &s->i2c2,  TYPE_AW_I2C_SUN6I);
      object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I);
 +
 +    object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN6I);
  }
--static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs)
+ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
-+static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs)
+@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
- {
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0,
-     /*
+                        qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI));
-      * For an S1 page table walk, the stage 1 attributes are always
-@@ -XXX,XX +XXX,XX @@ static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs)
++    /* WDT */
-      * when cacheattrs.attrs bit [2] is 0.
++    sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);
-      */
++    sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0,
-     assert(cacheattrs.is_s2_format);
++                            s->memmap[AW_H3_DEV_WDT], 1);
 -    if (arm_hcr_el2_eff(env) & HCR_FWB) {
 +    if (hcr & HCR_FWB) {
          return (cacheattrs.attrs & 0x4) == 0;
      } else {
          return (cacheattrs.attrs & 0xc) == 0;
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
      if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
          !regime_translation_disabled(env, s2_mmu_idx, is_secure)) {
          GetPhysAddrResult s2 = {};
 +        uint64_t hcr;
          int ret;
          ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx,
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
              fi->s1ns = !is_secure;
              return ~0;
          }
 -        if ((arm_hcr_el2_eff(env) & HCR_PTW) &&
 -            ptw_attrs_are_device(env, s2.cacheattrs)) {
 +
-+        hcr = arm_hcr_el2_eff(env);
+     /* Unimplemented devices */
-+        if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) {
+     for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
-             /*
+         create_unimplemented_device(unimplemented[i].device_name,
-              * PTW set and S1 walk touched S2 Device memory:
+diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
-              * generate Permission fault.
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
+--- a/hw/arm/Kconfig
-  * ref: shared/translation/attrs/S2AttrDecode()
++++ b/hw/arm/Kconfig
-  *      .../S2ConvertAttrsHints()
+@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
-  */
+     select ALLWINNER_A10_PIT
--static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
+     select ALLWINNER_SUN8I_EMAC
-+static uint8_t convert_stage2_attrs(uint64_t hcr, uint8_t s2attrs)
+     select ALLWINNER_I2C
- {
++    select ALLWINNER_WDT
-     uint8_t hiattr = extract32(s2attrs, 2, 2);
+     select SERIAL
-     uint8_t loattr = extract32(s2attrs, 0, 2);
+     select ARM_TIMER
-     uint8_t hihint = 0, lohint = 0;
+     select ARM_GIC
      if (hiattr != 0) { /* normal memory */
 -        if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */
 +        if (hcr & HCR_CD) { /* cache disabled */
              hiattr = loattr = 1; /* non-cacheable */
          } else {
              if (hiattr != 1) { /* Write-through or write-back */
@@ -XXX,XX +XXX,XX @@ static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2)
   * s1 and s2 for the HCR_EL2.FWB == 0 case, returning the
   * combined attributes in MAIR_EL1 format.
   */
 -static uint8_t combined_attrs_nofwb(CPUARMState *env,
 +static uint8_t combined_attrs_nofwb(uint64_t hcr,
                                      ARMCacheAttrs s1, ARMCacheAttrs s2)
  {
      uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs;
 -    s2_mair_attrs = convert_stage2_attrs(env, s2.attrs);
 +    s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs);
      s1lo = extract32(s1.attrs, 0, 4);
      s2lo = extract32(s2_mair_attrs, 0, 4);
@@ -XXX,XX +XXX,XX @@ static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2)
   * @s1:      Attributes from stage 1 walk
   * @s2:      Attributes from stage 2 walk
   */
 -static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
 +static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
                                          ARMCacheAttrs s1, ARMCacheAttrs s2)
  {
      ARMCacheAttrs ret;
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
      }
      /* Combine memory type and cacheability attributes */
 -    if (arm_hcr_el2_eff(env) & HCR_FWB) {
 +    if (hcr & HCR_FWB) {
          ret.attrs = combined_attrs_fwb(s1, s2);
      } else {
 -        ret.attrs = combined_attrs_nofwb(env, s1, s2);
 +        ret.attrs = combined_attrs_nofwb(hcr, s1, s2);
      }
      /*
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
              ARMCacheAttrs cacheattrs1;
              ARMMMUIdx s2_mmu_idx;
              bool is_el0;
 +            uint64_t hcr;
              ret = get_phys_addr_with_secure(env, address, access_type,
                                              s1_mmu_idx, is_secure, result, fi);
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
              }
              /* Combine the S1 and S2 cache attributes. */
 -            if (arm_hcr_el2_eff(env) & HCR_DC) {
 +            hcr = arm_hcr_el2_eff(env);
 +            if (hcr & HCR_DC) {
                  /*
                   * HCR.DC forces the first stage attributes to
                   *  Normal Non-Shareable,
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
                  }
                  cacheattrs1.shareability = 0;
              }
 -            result->cacheattrs = combine_cacheattrs(env, cacheattrs1,
 +            result->cacheattrs = combine_cacheattrs(hcr, cacheattrs1,
                                                      result->cacheattrs);
              /*
 --
-.25.1
+.34.1

-[PULL 24/28] target/arm: Use tlb_set_page_full
+[PULL 06/21] tests/avocado: Add reboot tests to Cubieboard
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
-Adjust GetPhysAddrResult to fill in CPUTLBEntryFull,
+Cubieboard tests end with comment "reboot not functioning; omit test".
-so that it may be passed directly to tlb_set_page_full.
+Fix this so reboot is done at the end of each test.
-The change is large, but mostly mechanical.  The major
+Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
-non-mechanical change is page_size -> lg_page_size.
+Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
-Most of the time this is obvious, and is related to
+Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
-TARGET_PAGE_BITS.
+Message-id: 20230326202256.22980-5-strahinja.p.jankovic@gmail.com
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20221001162318.153420-21-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/internals.h  |   5 +-
+ tests/avocado/boot_linux_console.py | 15 ++++++++++++---
- target/arm/helper.c     |  12 +--
+file changed, 12 insertions(+), 3 deletions(-)
  target/arm/m_helper.c   |  20 ++---
  target/arm/ptw.c        | 179 ++++++++++++++++++++--------------------
  target/arm/tlb_helper.c |   9 +-
 files changed, 111 insertions(+), 114 deletions(-)
-diff --git a/target/arm/internals.h b/target/arm/internals.h
+diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
+--- a/tests/avocado/boot_linux_console.py
-+++ b/target/arm/internals.h
++++ b/tests/avocado/boot_linux_console.py
-@@ -XXX,XX +XXX,XX @@ typedef struct ARMCacheAttrs {
+@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self):
+                                                 'Allwinner sun4i/sun5i')
- /* Fields that are valid upon success. */
+         exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
- typedef struct GetPhysAddrResult {
+                                                 'system-control@1c00000')
--    hwaddr phys;
+-        # cubieboard's reboot is not functioning; omit reboot test.
--    target_ulong page_size;
++        exec_command_and_wait_for_pattern(self, 'reboot',
--    int prot;
++                                                'reboot: Restarting system')
--    MemTxAttrs attrs;
++        # Wait for VM to shut down gracefully
-+    CPUTLBEntryFull f;
++        self.vm.wait()
-     ARMCacheAttrs cacheattrs;
- } GetPhysAddrResult;
+     def test_arm_cubieboard_sata(self):
+         """
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_sata(self):
-index XXXXXXX..XXXXXXX 100644
+                                                 'Allwinner sun4i/sun5i')
---- a/target/arm/helper.c
+         exec_command_and_wait_for_pattern(self, 'cat /proc/partitions',
-+++ b/target/arm/helper.c
+                                                 'sda')
-@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
+-        # cubieboard's reboot is not functioning; omit reboot test.
-         /* Create a 64-bit PAR */
++        exec_command_and_wait_for_pattern(self, 'reboot',
-         par64 = (1 << 11); /* LPAE bit always set */
++                                                'reboot: Restarting system')
-         if (!ret) {
++        # Wait for VM to shut down gracefully
--            par64 |= res.phys & ~0xfffULL;
++        self.vm.wait()
--            if (!res.attrs.secure) {
-+            par64 |= res.f.phys_addr & ~0xfffULL;
+     @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
-+            if (!res.f.attrs.secure) {
+     def test_arm_cubieboard_openwrt_22_03_2(self):
-                 par64 |= (1 << 9); /* NS */
+@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_openwrt_22_03_2(self):
-             }
-             par64 |= (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */
+         exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
-@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
+                                                 'Allwinner sun4i/sun5i')
-          */
+-        # cubieboard's reboot is not functioning; omit reboot test.
-         if (!ret) {
++        exec_command_and_wait_for_pattern(self, 'reboot',
-             /* We do not set any attribute bits in the PAR */
++                                                'reboot: Restarting system')
--            if (res.page_size == (1 << 24)
++        # Wait for VM to shut down gracefully
-+            if (res.f.lg_page_size == 24
++        self.vm.wait()
-                 && arm_feature(env, ARM_FEATURE_V7)) {
--                par64 = (res.phys & 0xff000000) | (1 << 1);
+     @skipUnless(os.getenv('AVOCADO_TIMEOUT_EXPECTED'), 'Test might timeout')
-+                par64 = (res.f.phys_addr & 0xff000000) | (1 << 1);
+     def test_arm_quanta_gsj(self):
              } else {
 -                par64 = res.phys & 0xfffff000;
 +                par64 = res.f.phys_addr & 0xfffff000;
              }
 -            if (!res.attrs.secure) {
 +            if (!res.f.attrs.secure) {
                  par64 |= (1 << 9); /* NS */
              }
          } else {
 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/m_helper.c
 +++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
          }
          goto pend_fault;
      }
 -    address_space_stl_le(arm_addressspace(cs, res.attrs), res.phys, value,
 -                         res.attrs, &txres);
 +    address_space_stl_le(arm_addressspace(cs, res.f.attrs), res.f.phys_addr,
 +                         value, res.f.attrs, &txres);
      if (txres != MEMTX_OK) {
          /* BusFault trying to write the data */
          if (mode == STACK_LAZYFP) {
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
          goto pend_fault;
      }
 -    value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys,
 -                              res.attrs, &txres);
 +    value = address_space_ldl(arm_addressspace(cs, res.f.attrs),
 +                              res.f.phys_addr, res.f.attrs, &txres);
      if (txres != MEMTX_OK) {
          /* BusFault trying to read the data */
          qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n");
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure,
          qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL\n");
          return false;
      }
 -    *insn = address_space_lduw_le(arm_addressspace(cs, res.attrs), res.phys,
 -                                  res.attrs, &txres);
 +    *insn = address_space_lduw_le(arm_addressspace(cs, res.f.attrs),
 +                                  res.f.phys_addr, res.f.attrs, &txres);
      if (txres != MEMTX_OK) {
          env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK;
          armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
          }
          return false;
      }
 -    value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys,
 -                              res.attrs, &txres);
 +    value = address_space_ldl(arm_addressspace(cs, res.f.attrs),
 +                              res.f.phys_addr, res.f.attrs, &txres);
      if (txres != MEMTX_OK) {
          /* BusFault trying to read the data */
          qemu_log_mask(CPU_LOG_INT,
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
          } else {
              mrvalid = true;
          }
 -        r = res.prot & PAGE_READ;
 -        rw = res.prot & PAGE_WRITE;
 +        r = res.f.prot & PAGE_READ;
 +        rw = res.f.prot & PAGE_WRITE;
      } else {
          r = false;
          rw = false;
 diff --git a/target/arm/ptw.c b/target/arm/ptw.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/ptw.c
 +++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
              assert(!is_secure);
          }
 -        addr = s2.phys;
 +        addr = s2.f.phys_addr;
      }
      return addr;
  }
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
          /* 1Mb section.  */
          phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
          ap = (desc >> 10) & 3;
 -        result->page_size = 1024 * 1024;
 +        result->f.lg_page_size = 20; /* 1MB */
      } else {
          /* Lookup l2 entry.  */
          if (type == 1) {
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
          case 1: /* 64k page.  */
              phys_addr = (desc & 0xffff0000) | (address & 0xffff);
              ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
 -            result->page_size = 0x10000;
 +            result->f.lg_page_size = 16;
              break;
          case 2: /* 4k page.  */
              phys_addr = (desc & 0xfffff000) | (address & 0xfff);
              ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
 -            result->page_size = 0x1000;
 +            result->f.lg_page_size = 12;
              break;
          case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
              if (type == 1) {
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
                  if (arm_feature(env, ARM_FEATURE_XSCALE)
                      || arm_feature(env, ARM_FEATURE_V6)) {
                      phys_addr = (desc & 0xfffff000) | (address & 0xfff);
 -                    result->page_size = 0x1000;
 +                    result->f.lg_page_size = 12;
                  } else {
                      /*
                       * UNPREDICTABLE in ARMv5; we choose to take a
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
                  }
              } else {
                  phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
 -                result->page_size = 0x400;
 +                result->f.lg_page_size = 10;
              }
              ap = (desc >> 4) & 3;
              break;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
              g_assert_not_reached();
          }
      }
 -    result->prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
 -    result->prot |= result->prot ? PAGE_EXEC : 0;
 -    if (!(result->prot & (1 << access_type))) {
 +    result->f.prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
 +    result->f.prot |= result->f.prot ? PAGE_EXEC : 0;
 +    if (!(result->f.prot & (1 << access_type))) {
          /* Access permission fault.  */
          fi->type = ARMFault_Permission;
          goto do_fault;
      }
 -    result->phys = phys_addr;
 +    result->f.phys_addr = phys_addr;
      return false;
  do_fault:
      fi->domain = domain;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
              phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
              phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
              phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
 -            result->page_size = 0x1000000;
 +            result->f.lg_page_size = 24;  /* 16MB */
          } else {
              /* Section.  */
              phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
 -            result->page_size = 0x100000;
 +            result->f.lg_page_size = 20;  /* 1MB */
          }
          ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
          xn = desc & (1 << 4);
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
          case 1: /* 64k page.  */
              phys_addr = (desc & 0xffff0000) | (address & 0xffff);
              xn = desc & (1 << 15);
 -            result->page_size = 0x10000;
 +            result->f.lg_page_size = 16;
              break;
          case 2: case 3: /* 4k page.  */
              phys_addr = (desc & 0xfffff000) | (address & 0xfff);
              xn = desc & 1;
 -            result->page_size = 0x1000;
 +            result->f.lg_page_size = 12;
              break;
          default:
              /* Never happens, but compiler isn't smart enough to tell.  */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
          }
      }
      if (domain_prot == 3) {
 -        result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 +        result->f.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
      } else {
          if (pxn && !regime_is_user(env, mmu_idx)) {
              xn = 1;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
                  fi->type = ARMFault_AccessFlag;
                  goto do_fault;
              }
 -            result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
 +            result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
          } else {
 -            result->prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
 +            result->f.prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
          }
 -        if (result->prot && !xn) {
 -            result->prot |= PAGE_EXEC;
 +        if (result->f.prot && !xn) {
 +            result->f.prot |= PAGE_EXEC;
          }
 -        if (!(result->prot & (1 << access_type))) {
 +        if (!(result->f.prot & (1 << access_type))) {
              /* Access permission fault.  */
              fi->type = ARMFault_Permission;
              goto do_fault;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
           * the CPU doesn't support TZ or this is a non-secure translation
           * regime, because the attribute will already be non-secure.
           */
 -        result->attrs.secure = false;
 +        result->f.attrs.secure = false;
      }
 -    result->phys = phys_addr;
 +    result->f.phys_addr = phys_addr;
      return false;
  do_fault:
      fi->domain = domain;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
      if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
          ns = mmu_idx == ARMMMUIdx_Stage2;
          xn = extract32(attrs, 11, 2);
 -        result->prot = get_S2prot(env, ap, xn, s1_is_el0);
 +        result->f.prot = get_S2prot(env, ap, xn, s1_is_el0);
      } else {
          ns = extract32(attrs, 3, 1);
          xn = extract32(attrs, 12, 1);
          pxn = extract32(attrs, 11, 1);
 -        result->prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
 +        result->f.prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
      }
      fault_type = ARMFault_Permission;
 -    if (!(result->prot & (1 << access_type))) {
 +    if (!(result->f.prot & (1 << access_type))) {
          goto do_fault;
      }
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
           * the CPU doesn't support TZ or this is a non-secure translation
           * regime, because the attribute will already be non-secure.
           */
 -        result->attrs.secure = false;
 +        result->f.attrs.secure = false;
      }
      /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.  */
      if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
 -        arm_tlb_bti_gp(&result->attrs) = true;
 +        arm_tlb_bti_gp(&result->f.attrs) = true;
      }
      if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
          result->cacheattrs.shareability = extract32(attrs, 6, 2);
      }
 -    result->phys = descaddr;
 -    result->page_size = page_size;
 +    result->f.phys_addr = descaddr;
 +    result->f.lg_page_size = ctz64(page_size);
      return false;
  do_fault:
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
      if (regime_translation_disabled(env, mmu_idx, is_secure)) {
          /* MPU disabled.  */
 -        result->phys = address;
 -        result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 +        result->f.phys_addr = address;
 +        result->f.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
          return false;
      }
 -    result->phys = address;
 +    result->f.phys_addr = address;
      for (n = 7; n >= 0; n--) {
          base = env->cp15.c6_region[n];
          if ((base & 1) == 0) {
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
              fi->level = 1;
              return true;
          }
 -        result->prot = PAGE_READ | PAGE_WRITE;
 +        result->f.prot = PAGE_READ | PAGE_WRITE;
          break;
      case 2:
 -        result->prot = PAGE_READ;
 +        result->f.prot = PAGE_READ;
          if (!is_user) {
 -            result->prot |= PAGE_WRITE;
 +            result->f.prot |= PAGE_WRITE;
          }
          break;
      case 3:
 -        result->prot = PAGE_READ | PAGE_WRITE;
 +        result->f.prot = PAGE_READ | PAGE_WRITE;
          break;
      case 5:
          if (is_user) {
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
              fi->level = 1;
              return true;
          }
 -        result->prot = PAGE_READ;
 +        result->f.prot = PAGE_READ;
          break;
      case 6:
 -        result->prot = PAGE_READ;
 +        result->f.prot = PAGE_READ;
          break;
      default:
          /* Bad permission.  */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
          fi->level = 1;
          return true;
      }
 -    result->prot |= PAGE_EXEC;
 +    result->f.prot |= PAGE_EXEC;
      return false;
  }
  static void get_phys_addr_pmsav7_default(CPUARMState *env, ARMMMUIdx mmu_idx,
 -                                         int32_t address, int *prot)
 +                                         int32_t address, uint8_t *prot)
  {
      if (!arm_feature(env, ARM_FEATURE_M)) {
          *prot = PAGE_READ | PAGE_WRITE;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
      int n;
      bool is_user = regime_is_user(env, mmu_idx);
 -    result->phys = address;
 -    result->page_size = TARGET_PAGE_SIZE;
 -    result->prot = 0;
 +    result->f.phys_addr = address;
 +    result->f.lg_page_size = TARGET_PAGE_BITS;
 +    result->f.prot = 0;
      if (regime_translation_disabled(env, mmu_idx, secure) ||
          m_is_ppb_region(env, address)) {
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
           * which always does a direct read using address_space_ldl(), rather
           * than going via this function, so we don't need to check that here.
           */
 -        get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
 +        get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.prot);
      } else { /* MPU enabled */
          for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
              /* region search */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
                  if (ranges_overlap(base, rmask,
                                     address & TARGET_PAGE_MASK,
                                     TARGET_PAGE_SIZE)) {
 -                    result->page_size = 1;
 +                    result->f.lg_page_size = 0;
                  }
                  continue;
              }
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
                  continue;
              }
              if (rsize < TARGET_PAGE_BITS) {
 -                result->page_size = 1 << rsize;
 +                result->f.lg_page_size = rsize;
              }
              break;
          }
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
                  fi->type = ARMFault_Background;
                  return true;
              }
 -            get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
 +            get_phys_addr_pmsav7_default(env, mmu_idx, address,
 +                                         &result->f.prot);
          } else { /* a MPU hit! */
              uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
              uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1);
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
                  case 5:
                      break; /* no access */
                  case 3:
 -                    result->prot |= PAGE_WRITE;
 +                    result->f.prot |= PAGE_WRITE;
                      /* fall through */
                  case 2:
                  case 6:
 -                    result->prot |= PAGE_READ | PAGE_EXEC;
 +                    result->f.prot |= PAGE_READ | PAGE_EXEC;
                      break;
                  case 7:
                      /* for v7M, same as 6; for R profile a reserved value */
                      if (arm_feature(env, ARM_FEATURE_M)) {
 -                        result->prot |= PAGE_READ | PAGE_EXEC;
 +                        result->f.prot |= PAGE_READ | PAGE_EXEC;
                          break;
                      }
                      /* fall through */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
                  case 1:
                  case 2:
                  case 3:
 -                    result->prot |= PAGE_WRITE;
 +                    result->f.prot |= PAGE_WRITE;
                      /* fall through */
                  case 5:
                  case 6:
 -                    result->prot |= PAGE_READ | PAGE_EXEC;
 +                    result->f.prot |= PAGE_READ | PAGE_EXEC;
                      break;
                  case 7:
                      /* for v7M, same as 6; for R profile a reserved value */
                      if (arm_feature(env, ARM_FEATURE_M)) {
 -                        result->prot |= PAGE_READ | PAGE_EXEC;
 +                        result->f.prot |= PAGE_READ | PAGE_EXEC;
                          break;
                      }
                      /* fall through */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
              /* execute never */
              if (xn) {
 -                result->prot &= ~PAGE_EXEC;
 +                result->f.prot &= ~PAGE_EXEC;
              }
          }
      }
      fi->type = ARMFault_Permission;
      fi->level = 1;
 -    return !(result->prot & (1 << access_type));
 +    return !(result->f.prot & (1 << access_type));
  }
  bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
      uint32_t addr_page_base = address & TARGET_PAGE_MASK;
      uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
 -    result->page_size = TARGET_PAGE_SIZE;
 -    result->phys = address;
 -    result->prot = 0;
 +    result->f.lg_page_size = TARGET_PAGE_BITS;
 +    result->f.phys_addr = address;
 +    result->f.prot = 0;
      if (mregion) {
          *mregion = -1;
      }
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
                      ranges_overlap(base, limit - base + 1,
                                     addr_page_base,
                                     TARGET_PAGE_SIZE)) {
 -                    result->page_size = 1;
 +                    result->f.lg_page_size = 0;
                  }
                  continue;
              }
              if (base > addr_page_base || limit < addr_page_limit) {
 -                result->page_size = 1;
 +                result->f.lg_page_size = 0;
              }
              if (matchregion != -1) {
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
      if (matchregion == -1) {
          /* hit using the background region */
 -        get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
 +        get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.prot);
      } else {
          uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
          uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
              xn = 1;
          }
 -        result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
 -        if (result->prot && !xn && !(pxn && !is_user)) {
 -            result->prot |= PAGE_EXEC;
 +        result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
 +        if (result->f.prot && !xn && !(pxn && !is_user)) {
 +            result->f.prot |= PAGE_EXEC;
          }
          /*
           * We don't need to look the attribute up in the MAIR0/MAIR1
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
      fi->type = ARMFault_Permission;
      fi->level = 1;
 -    return !(result->prot & (1 << access_type));
 +    return !(result->f.prot & (1 << access_type));
  }
  static bool v8m_is_sau_exempt(CPUARMState *env,
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
                  } else {
                      fi->type = ARMFault_QEMU_SFault;
                  }
 -                result->page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
 -                result->phys = address;
 -                result->prot = 0;
 +                result->f.lg_page_size = sattrs.subpage ? 0 : TARGET_PAGE_BITS;
 +                result->f.phys_addr = address;
 +                result->f.prot = 0;
                  return true;
              }
          } else {
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
               * might downgrade a secure access to nonsecure.
               */
              if (sattrs.ns) {
 -                result->attrs.secure = false;
 +                result->f.attrs.secure = false;
              } else if (!secure) {
                  /*
                   * NS access to S memory must fault.
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
                   * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
                   */
                  fi->type = ARMFault_QEMU_SFault;
 -                result->page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
 -                result->phys = address;
 -                result->prot = 0;
 +                result->f.lg_page_size = sattrs.subpage ? 0 : TARGET_PAGE_BITS;
 +                result->f.phys_addr = address;
 +                result->f.prot = 0;
                  return true;
              }
          }
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
      ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, secure,
                              result, fi, NULL);
      if (sattrs.subpage) {
 -        result->page_size = 1;
 +        result->f.lg_page_size = 0;
      }
      return ret;
  }
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
          result->cacheattrs.is_s2_format = false;
      }
 -    result->phys = address;
 -    result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 -    result->page_size = TARGET_PAGE_SIZE;
 +    result->f.phys_addr = address;
 +    result->f.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 +    result->f.lg_page_size = TARGET_PAGE_BITS;
      result->cacheattrs.shareability = shareability;
      result->cacheattrs.attrs = memattr;
      return 0;
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
                  return ret;
              }
 -            ipa = result->phys;
 -            ipa_secure = result->attrs.secure;
 +            ipa = result->f.phys_addr;
 +            ipa_secure = result->f.attrs.secure;
              if (is_secure) {
                  /* Select TCR based on the NS bit from the S1 walk. */
                  s2walk_secure = !(ipa_secure
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
               * Save the stage1 results so that we may merge
               * prot and cacheattrs later.
               */
 -            s1_prot = result->prot;
 +            s1_prot = result->f.prot;
              cacheattrs1 = result->cacheattrs;
              memset(result, 0, sizeof(*result));
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
              fi->s2addr = ipa;
              /* Combine the S1 and S2 perms.  */
 -            result->prot &= s1_prot;
 +            result->f.prot &= s1_prot;
              /* If S2 fails, return early.  */
              if (ret) {
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
               * Check if IPA translates to secure or non-secure PA space.
               * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
               */
 -            result->attrs.secure =
 +            result->f.attrs.secure =
                  (is_secure
                   && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
                   && (ipa_secure
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
       * cannot upgrade an non-secure translation regime's attributes
       * to secure.
       */
 -    result->attrs.secure = is_secure;
 -    result->attrs.user = regime_is_user(env, mmu_idx);
 +    result->f.attrs.secure = is_secure;
 +    result->f.attrs.user = regime_is_user(env, mmu_idx);
      /*
       * Fast Context Switch Extension. This doesn't exist at all in v8.
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
      if (arm_feature(env, ARM_FEATURE_PMSA)) {
          bool ret;
 -        result->page_size = TARGET_PAGE_SIZE;
 +        result->f.lg_page_size = TARGET_PAGE_BITS;
          if (arm_feature(env, ARM_FEATURE_V8)) {
              /* PMSAv8 */
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
                        (access_type == MMU_DATA_STORE ? "writing" : "execute"),
                        (uint32_t)address, mmu_idx,
                        ret ? "Miss" : "Hit",
 -                      result->prot & PAGE_READ ? 'r' : '-',
 -                      result->prot & PAGE_WRITE ? 'w' : '-',
 -                      result->prot & PAGE_EXEC ? 'x' : '-');
 +                      result->f.prot & PAGE_READ ? 'r' : '-',
 +                      result->f.prot & PAGE_WRITE ? 'w' : '-',
 +                      result->f.prot & PAGE_EXEC ? 'x' : '-');
          return ret;
      }
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
      bool ret;
      ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi);
 -    *attrs = res.attrs;
 +    *attrs = res.f.attrs;
      if (ret) {
          return -1;
      }
 -    return res.phys;
 +    return res.f.phys_addr;
  }
 diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tlb_helper.c
 +++ b/target/arm/tlb_helper.c
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
           * target page size are handled specially, so for those we
           * pass in the exact addresses.
           */
 -        if (res.page_size >= TARGET_PAGE_SIZE) {
 -            res.phys &= TARGET_PAGE_MASK;
 +        if (res.f.lg_page_size >= TARGET_PAGE_BITS) {
 +            res.f.phys_addr &= TARGET_PAGE_MASK;
              address &= TARGET_PAGE_MASK;
          }
          /* Notice and record tagged memory. */
          if (cpu_isar_feature(aa64_mte, cpu) && res.cacheattrs.attrs == 0xf0) {
 -            arm_tlb_mte_tagged(&res.attrs) = true;
 +            arm_tlb_mte_tagged(&res.f.attrs) = true;
          }
 -        tlb_set_page_with_attrs(cs, address, res.phys, res.attrs,
 -                                res.prot, mmu_idx, res.page_size);
 +        tlb_set_page_full(cs, mmu_idx, address, &res.f);
          return true;
      } else if (probe) {
          return false;
 --
-.25.1
+.34.1

-[PULL 21/28] target/arm: Fix ATS12NSO* from S PL1
+[PULL 07/21] hw/timer/imx_epit: don't shadow variable
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Axel Heider <axel.heider@hensoldt.net>
-Use arm_hcr_el2_eff_secstate instead of arm_hcr_el2_eff, so
+Fix issue reported by Coverity.
 that we use is_secure instead of the current security state.
 These AT* operations have been broken since arm_hcr_el2_eff
 gained a check for "el2 enabled" for Secure EL2.
+Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
+Message-id: 168070611775.20412.2883242077302841473-1@git.sr.ht
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20221001162318.153420-18-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/ptw.c | 8 ++++----
+ hw/timer/imx_epit.c | 2 +-
-file changed, 4 insertions(+), 4 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
+diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
+--- a/hw/timer/imx_epit.c
-+++ b/target/arm/ptw.c
++++ b/hw/timer/imx_epit.c
-@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
+@@ -XXX,XX +XXX,XX @@ static void imx_epit_update_compare_timer(IMXEPITState *s)
-         }
+          * the compare value. Otherwise it may fire at most once in the
-     }
+          * current round.
+          */
--    hcr_el2 = arm_hcr_el2_eff(env);
+-        bool is_oneshot = (limit >= s->cmp);
-+    hcr_el2 = arm_hcr_el2_eff_secstate(env, is_secure);
++        is_oneshot = (limit >= s->cmp);
+         if (counter >= s->cmp) {
-     switch (mmu_idx) {
+             /* The compare timer fires in the current round. */
-     case ARMMMUIdx_Stage2:
+             counter -= s->cmp;
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
              return ~0;
          }
 -        hcr = arm_hcr_el2_eff(env);
 +        hcr = arm_hcr_el2_eff_secstate(env, is_secure);
          if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) {
              /*
               * PTW set and S1 walk touched S2 Device memory:
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
              }
              /* Combine the S1 and S2 cache attributes. */
 -            hcr = arm_hcr_el2_eff(env);
 +            hcr = arm_hcr_el2_eff_secstate(env, is_secure);
              if (hcr & HCR_DC) {
                  /*
                   * HCR.DC forces the first stage attributes to
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
          result->page_size = TARGET_PAGE_SIZE;
          /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
 -        hcr = arm_hcr_el2_eff(env);
 +        hcr = arm_hcr_el2_eff_secstate(env, is_secure);
          result->cacheattrs.shareability = 0;
          result->cacheattrs.is_s2_format = false;
          if (hcr & HCR_DC) {
 --
-.25.1
+.34.1

-[PULL 19/28] target/arm: Remove env argument from combined_attrs_fwb
+[PULL 08/21] hw/timer/imx_epit: fix limit check
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Axel Heider <axel.heider@hensoldt.net>
-This value is unused.
+Fix the limit check. If the limit is less than the compare value,
 the timer can never reach this value, thus it will never fire.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1491
 Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
 Message-id: 168070611775.20412.2883242077302841473-2@git.sr.ht
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20221001162318.153420-16-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/ptw.c | 5 ++---
+ hw/timer/imx_epit.c | 2 +-
-file changed, 2 insertions(+), 3 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
+diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
+--- a/hw/timer/imx_epit.c
-+++ b/target/arm/ptw.c
++++ b/hw/timer/imx_epit.c
-@@ -XXX,XX +XXX,XX @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr)
+@@ -XXX,XX +XXX,XX @@ static void imx_epit_update_compare_timer(IMXEPITState *s)
-  * s1 and s2 for the HCR_EL2.FWB == 1 case, returning the
+          * the compare value. Otherwise it may fire at most once in the
-  * combined attributes in MAIR_EL1 format.
+          * current round.
-  */
+          */
--static uint8_t combined_attrs_fwb(CPUARMState *env,
+-        is_oneshot = (limit >= s->cmp);
--                                  ARMCacheAttrs s1, ARMCacheAttrs s2)
++        is_oneshot = (limit < s->cmp);
-+static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2)
+         if (counter >= s->cmp) {
- {
+             /* The compare timer fires in the current round. */
-     switch (s2.attrs) {
+             counter -= s->cmp;
      case 7:
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
      /* Combine memory type and cacheability attributes */
      if (arm_hcr_el2_eff(env) & HCR_FWB) {
 -        ret.attrs = combined_attrs_fwb(env, s1, s2);
 +        ret.attrs = combined_attrs_fwb(s1, s2);
      } else {
          ret.attrs = combined_attrs_nofwb(env, s1, s2);
      }
 --
-.25.1
+.34.1

-[PULL 06/28] target/arm: Add is_secure parameter to get_phys_addr_lpae
+[PULL 09/21] target/arm: Remove KVM AArch32 CPU definitions
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Remove the use of regime_is_secure from get_phys_addr_lpae,
+Missed in commit 80485d88f9 ("target/arm: Restrict
-using the new parameter instead.
+v7A TCG cpus to TCG accel").
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20221001162318.153420-3-richard.henderson@linaro.org
+Message-id: 20230405100848.76145-2-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/ptw.c | 20 ++++++++++----------
+ target/arm/kvm-consts.h | 9 +++------
-file changed, 10 insertions(+), 10 deletions(-)
+ target/arm/cpu_tcg.c    | 2 --
 files changed, 3 insertions(+), 8 deletions(-)
-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
+diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
+--- a/target/arm/kvm-consts.h
-+++ b/target/arm/ptw.c
++++ b/target/arm/kvm-consts.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_RET_INTERNAL_FAILURE, PSCI_RET_INTERNAL_FAILURE);
+ MISMATCH_CHECK(QEMU_PSCI_RET_NOT_PRESENT, PSCI_RET_NOT_PRESENT);
- static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
+ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED);
-                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
--                               bool s1_is_el0, GetPhysAddrResult *result,
+-/* Note that KVM uses overlapping values for AArch32 and AArch64
--                               ARMMMUFaultInfo *fi)
+- * target CPU numbers. AArch32 targets:
-+                               bool is_secure, bool s1_is_el0,
++/*
-+                               GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
++ * Note that KVM uses overlapping values for AArch32 and AArch64
-     __attribute__((nonnull));
++ * target CPU numbers. AArch64 targets:
  /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
          GetPhysAddrResult s2 = {};
          int ret;
 -        ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false,
 -                                 &s2, fi);
 +        ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx,
 +                                 *is_secure, false, &s2, fi);
          if (ret) {
              assert(fi->type != ARMFault_None);
              fi->s2addr = addr;
@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
   */
- static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
+-#define QEMU_KVM_ARM_TARGET_CORTEX_A15 0
-                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
+-#define QEMU_KVM_ARM_TARGET_CORTEX_A7 1
--                               bool s1_is_el0, GetPhysAddrResult *result,
+-
--                               ARMMMUFaultInfo *fi)
+-/* AArch64 targets: */
-+                               bool is_secure, bool s1_is_el0,
+ #define QEMU_KVM_ARM_TARGET_AEM_V8 0
-+                               GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
+ #define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1
- {
+ #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2
-     ARMCPU *cpu = env_archcpu(env);
+diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-     /* Read an LPAE long-descriptor translation table. */
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
+--- a/target/arm/cpu_tcg.c
-      * remain non-secure. We implement this by just ORing in the NSTable/NS
++++ b/target/arm/cpu_tcg.c
-      * bits at each step.
+@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
-      */
+     set_feature(&cpu->env, ARM_FEATURE_EL2);
--    tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
+     set_feature(&cpu->env, ARM_FEATURE_EL3);
-+    tableattrs = is_secure ? 0 : (1 << 4);
+     set_feature(&cpu->env, ARM_FEATURE_PMU);
-     for (;;) {
+-    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
-         uint64_t descriptor;
+     cpu->midr = 0x410fc075;
-         bool nstable;
+     cpu->reset_fpsid = 0x41023075;
-@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
+     cpu->isar.mvfr0 = 0x10110222;
-             memset(result, 0, sizeof(*result));
+@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
+     set_feature(&cpu->env, ARM_FEATURE_EL2);
-             ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx,
+     set_feature(&cpu->env, ARM_FEATURE_EL3);
--                                     is_el0, result, fi);
+     set_feature(&cpu->env, ARM_FEATURE_PMU);
-+                                     s2walk_secure, is_el0, result, fi);
+-    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
-             fi->s2addr = ipa;
+     /* r4p0 cpu, not requiring expensive tlb flush errata */
+     cpu->midr = 0x414fc0f0;
-             /* Combine the S1 and S2 perms.  */
+     cpu->revidr = 0x0;
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
      }
      if (regime_using_lpae_format(env, mmu_idx)) {
 -        return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
 -                                  result, fi);
 +        return get_phys_addr_lpae(env, address, access_type, mmu_idx,
 +                                  is_secure, false, result, fi);
      } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
          return get_phys_addr_v6(env, address, access_type, mmu_idx,
                                  is_secure, result, fi);
 --
-.25.1
+.34.1

-[PULL 10/28] target/arm: Add is_secure parameter to v7m_read_half_insn
+[PULL 10/21] hw/arm/virt: Restrict Cortex-A7 check to TCG
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Remove the use of regime_is_secure from v7m_read_half_insn, using
+The Cortex-A7 core is only available when TCG is enabled (see
-the new parameter instead.
+commit 80485d88f9 "target/arm: Restrict v7A TCG cpus to TCG accel").
-As it happens, both callers pass true, propagated from the argument
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-to arm_v7m_mmu_idx_for_secstate which created the mmu_idx argument,
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-but that is a detail of v7m_handle_execute_nsc we need not expose
+Message-id: 20230405100848.76145-3-philmd@linaro.org
 to the callee.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20221001162318.153420-7-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/m_helper.c | 9 ++++-----
+ hw/arm/virt.c | 2 ++
-file changed, 4 insertions(+), 5 deletions(-)
+file changed, 2 insertions(+)
-diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/m_helper.c
+--- a/hw/arm/virt.c
-+++ b/target/arm/m_helper.c
++++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
+@@ -XXX,XX +XXX,XX @@ static const int a15irqmap[] = {
-     return true;
+ };
- }
+ static const char *valid_cpus[] = {
--static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
++#ifdef CONFIG_TCG
-+static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure,
+     ARM_CPU_TYPE_NAME("cortex-a7"),
-                                uint32_t addr, uint16_t *insn)
++#endif
- {
+     ARM_CPU_TYPE_NAME("cortex-a15"),
-     /*
+     ARM_CPU_TYPE_NAME("cortex-a35"),
-@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
+     ARM_CPU_TYPE_NAME("cortex-a53"),
      ARMMMUFaultInfo fi = {};
      MemTxResult txres;
 -    v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx,
 -                        regime_is_secure(env, mmu_idx), &sattrs);
 +    v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, secure, &sattrs);
      if (!sattrs.nsc || sattrs.ns) {
          /*
           * This must be the second half of the insn, and it straddles a
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
      /* We want to do the MPU lookup as secure; work out what mmu_idx that is */
      mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
 -    if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) {
 +    if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15], &insn)) {
          return false;
      }
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
          goto gen_invep;
      }
 -    if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) {
 +    if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15] + 2, &insn)) {
          return false;
      }
 --
-.25.1
+.34.1

-[PULL 09/28] target/arm: Split out get_phys_addr_with_secure
+[PULL 11/21] target/arm: Initialize debug capabilities only once
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Akihiko Odaki <akihiko.odaki@daynix.com>
-Retain the existing get_phys_addr interface using the security
+kvm_arm_init_debug() used to be called several times on a SMP system as
-state derived from mmu_idx.  Move the kerneldoc comments to the
+kvm_arch_init_vcpu() calls it. Move the call to kvm_arch_init() to make
-header file where they belong.
+sure it will be called only once; otherwise it will overwrite pointers
 to memory allocated with the previous call and leak it.
+Fixes: e4482ab7e3 ("target-arm: kvm - add support for HW assisted debug")
+Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
+Message-id: 20230405153644.25300-1-akihiko.odaki@daynix.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20221001162318.153420-6-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/internals.h | 40 ++++++++++++++++++++++++++++++++++++++
+ target/arm/kvm_arm.h |  8 ++++++++
- target/arm/ptw.c       | 44 ++++++++++++++----------------------------
+ target/arm/kvm.c     |  2 ++
-files changed, 55 insertions(+), 29 deletions(-)
+ target/arm/kvm64.c   | 18 ++++--------------
 files changed, 14 insertions(+), 14 deletions(-)
-diff --git a/target/arm/internals.h b/target/arm/internals.h
+diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
+--- a/target/arm/kvm_arm.h
-+++ b/target/arm/internals.h
++++ b/target/arm/kvm_arm.h
-@@ -XXX,XX +XXX,XX @@ typedef struct GetPhysAddrResult {
+@@ -XXX,XX +XXX,XX @@
-     ARMCacheAttrs cacheattrs;
+ #define KVM_ARM_VGIC_V2   (1 << 0)
- } GetPhysAddrResult;
+ #define KVM_ARM_VGIC_V3   (1 << 1)
 +/**
-+ * get_phys_addr_with_secure: get the physical address for a virtual address
++ * kvm_arm_init_debug() - initialize guest debug capabilities
-+ * @env: CPUARMState
++ * @s: KVMState
 + * @address: virtual address to get physical address for
 + * @access_type: 0 for read, 1 for write, 2 for execute
 + * @mmu_idx: MMU index indicating required translation regime
 + * @is_secure: security state for the access
 + * @result: set on translation success.
 + * @fi: set to fault info if the translation fails
 + *
-+ * Find the physical address corresponding to the given virtual address,
++ * Should be called only once before using guest debug capabilities.
 + * by doing a translation table walk on MMU based systems or using the
 + * MPU state on MPU based systems.
 + *
 + * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
 + * prot and page_size may not be filled in, and the populated fsr value provides
 + * information on why the translation aborted, in the format of a
 + * DFSR/IFSR fault register, with the following caveats:
 + *  * we honour the short vs long DFSR format differences.
 + *  * the WnR bit is never set (the caller must do this).
 + *  * for PSMAv5 based systems we don't bother to return a full FSR format
 + *    value.
 + */
-+bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
++void kvm_arm_init_debug(KVMState *s);
 +                               MMUAccessType access_type,
 +                               ARMMMUIdx mmu_idx, bool is_secure,
 +                               GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
 +    __attribute__((nonnull));
 +
-+/**
+ /**
-+ * get_phys_addr: get the physical address for a virtual address
+  * kvm_arm_vcpu_init:
-+ * @env: CPUARMState
+  * @cs: CPUState
-+ * @address: virtual address to get physical address for
+diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 + * @access_type: 0 for read, 1 for write, 2 for execute
 + * @mmu_idx: MMU index indicating required translation regime
 + * @result: set on translation success.
 + * @fi: set to fault info if the translation fails
 + *
 + * Similarly, but use the security regime of @mmu_idx.
 + */
  bool get_phys_addr(CPUARMState *env, target_ulong address,
                     MMUAccessType access_type, ARMMMUIdx mmu_idx,
                     GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
 diff --git a/target/arm/ptw.c b/target/arm/ptw.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
+--- a/target/arm/kvm.c
-+++ b/target/arm/ptw.c
++++ b/target/arm/kvm.c
-@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s)
          }
      }
 +    kvm_arm_init_debug(s);
 +
      return ret;
  }
+diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/kvm64.c
++++ b/target/arm/kvm64.c
+@@ -XXX,XX +XXX,XX @@ GArray *hw_breakpoints, *hw_watchpoints;
+ #define get_hw_bp(i)    (&g_array_index(hw_breakpoints, HWBreakpoint, i))
+ #define get_hw_wp(i)    (&g_array_index(hw_watchpoints, HWWatchpoint, i))
 -/**
-- * get_phys_addr - get the physical address for this virtual address
+- * kvm_arm_init_debug() - check for guest debug capabilities
 - * @cs: CPUState
 - *
-- * Find the physical address corresponding to the given virtual address,
+- * kvm_check_extension returns the number of debug registers we have
-- * by doing a translation table walk on MMU based systems or using the
+- * or 0 if we have none.
 - * MPU state on MPU based systems.
 - *
-- * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
-- * prot and page_size may not be filled in, and the populated fsr value provides
-- * information on why the translation aborted, in the format of a
-- * DFSR/IFSR fault register, with the following caveats:
-- *  * we honour the short vs long DFSR format differences.
-- *  * the WnR bit is never set (the caller must do this).
-- *  * for PSMAv5 based systems we don't bother to return a full FSR format
-- *    value.
-- *
-- * @env: CPUARMState
-- * @address: virtual address to get physical address for
-- * @access_type: 0 for read, 1 for write, 2 for execute
-- * @mmu_idx: MMU index indicating required translation regime
-- * @result: set on translation success.
-- * @fi: set to fault info if the translation fails
 - */
--bool get_phys_addr(CPUARMState *env, target_ulong address,
+-static void kvm_arm_init_debug(CPUState *cs)
--                   MMUAccessType access_type, ARMMMUIdx mmu_idx,
++void kvm_arm_init_debug(KVMState *s)
 -                   GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
 +bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
 +                               MMUAccessType access_type, ARMMMUIdx mmu_idx,
 +                               bool is_secure, GetPhysAddrResult *result,
 +                               ARMMMUFaultInfo *fi)
  {
-     ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
+-    have_guest_debug = kvm_check_extension(cs->kvm_state,
--    bool is_secure = regime_is_secure(env, mmu_idx);
++    have_guest_debug = kvm_check_extension(s,
+                                            KVM_CAP_SET_GUEST_DEBUG);
-     if (mmu_idx != s1_mmu_idx) {
-         /*
+-    max_hw_wps = kvm_check_extension(cs->kvm_state, KVM_CAP_GUEST_DEBUG_HW_WPS);
-@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
++    max_hw_wps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS);
-             ARMMMUIdx s2_mmu_idx;
+     hw_watchpoints = g_array_sized_new(true, true,
-             bool is_el0;
+                                        sizeof(HWWatchpoint), max_hw_wps);
--            ret = get_phys_addr(env, address, access_type, s1_mmu_idx,
+-    max_hw_bps = kvm_check_extension(cs->kvm_state, KVM_CAP_GUEST_DEBUG_HW_BPS);
--                                result, fi);
++    max_hw_bps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_BPS);
-+            ret = get_phys_addr_with_secure(env, address, access_type,
+     hw_breakpoints = g_array_sized_new(true, true,
-+                                            s1_mmu_idx, is_secure, result, fi);
+                                        sizeof(HWBreakpoint), max_hw_bps);
+     return;
-             /* If S1 fails or S2 is disabled, return early.  */
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
              if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2,
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
      }
- }
+     cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK;
-+bool get_phys_addr(CPUARMState *env, target_ulong address,
+-    kvm_arm_init_debug(cs);
-+                   MMUAccessType access_type, ARMMMUIdx mmu_idx,
+-
-+                   GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
+     /* Check whether user space can specify guest syndrome value */
-+{
+     kvm_arm_init_serror_injection(cs);
-+    return get_phys_addr_with_secure(env, address, access_type, mmu_idx,
 +                                     regime_is_secure(env, mmu_idx),
 +                                     result, fi);
 +}
 +
  hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
                                           MemTxAttrs *attrs)
  {
 --
-.25.1
+.34.1

-[PULL 08/28] target/arm: Add is_secure parameter to regime_translation_disabled
+[PULL 12/21] target/arm: Pass ARMMMUFaultInfo to merge_syn_data_abort()
-From: Richard Henderson <richard.henderson@linaro.org>
+We already pass merge_syn_data_abort() two fields from the
 ARMMMUFaultInfo struct, and we're about to want to use a third field.
 Refactor to just pass a pointer to the fault info.
-Remove the use of regime_is_secure from regime_translation_disabled,
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-using the new parameter instead.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20230331145045.2584941-2-peter.maydell@linaro.org
 ---
  target/arm/tcg/tlb_helper.c | 15 +++++++--------
 file changed, 7 insertions(+), 8 deletions(-)
-This fixes a bug in S1_ptw_translate and get_phys_addr where we had
+diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
 passed ARMMMUIdx_Stage2 and not ARMMMUIdx_Stage2_S to determine if
 Stage2 is disabled, affecting FEAT_SEL2.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20221001162318.153420-5-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/ptw.c | 20 +++++++++++---------
 file changed, 11 insertions(+), 9 deletions(-)
 diff --git a/target/arm/ptw.c b/target/arm/ptw.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
+--- a/target/arm/tcg/tlb_helper.c
-+++ b/target/arm/ptw.c
++++ b/target/arm/tcg/tlb_helper.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn)
+@@ -XXX,XX +XXX,XX @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
  }
- /* Return true if the specified stage of address translation is disabled */
+ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
--static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx)
++                                            ARMMMUFaultInfo *fi,
-+static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
+                                             unsigned int target_el,
-+                                        bool is_secure)
+-                                            bool same_el, bool ea,
 -                                            bool s1ptw, bool is_write,
 +                                            bool same_el, bool is_write,
                                              int fsc)
  {
-     uint64_t hcr_el2;
+     uint32_t syn;
+@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
-     if (arm_feature(env, ARM_FEATURE_M)) {
+      * ISS encoding for an exception from a Data Abort, the
--        switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] &
+      * ISV field.
-+        switch (env->v7m.mpu_ctrl[is_secure] &
+      */
-                 (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
+-    if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) {
-         case R_V7M_MPU_CTRL_ENABLE_MASK:
++    if (!(template_syn & ARM_EL_ISV) || target_el != 2 || fi->s1ptw) {
-             /* Enabled, but not for HardFault and NMI */
+         syn = syn_data_abort_no_iss(same_el, 0,
-@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx)
+-                                    ea, 0, s1ptw, is_write, fsc);
++                                    fi->ea, 0, fi->s1ptw, is_write, fsc);
-     if (hcr_el2 & HCR_TGE) {
+     } else {
          /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
 -        if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) {
 +        if (!is_secure && regime_el(env, mmu_idx) == 1) {
              return true;
          }
      }
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
      ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
      if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
 -        !regime_translation_disabled(env, s2_mmu_idx)) {
 +        !regime_translation_disabled(env, s2_mmu_idx, *is_secure)) {
          GetPhysAddrResult s2 = {};
          int ret;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
      uint32_t base;
      bool is_user = regime_is_user(env, mmu_idx);
 -    if (regime_translation_disabled(env, mmu_idx)) {
 +    if (regime_translation_disabled(env, mmu_idx, is_secure)) {
          /* MPU disabled.  */
          result->phys = address;
          result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
      result->page_size = TARGET_PAGE_SIZE;
      result->prot = 0;
 -    if (regime_translation_disabled(env, mmu_idx) ||
 +    if (regime_translation_disabled(env, mmu_idx, secure) ||
          m_is_ppb_region(env, address)) {
          /*
-          * MPU disabled or M profile PPB access: use default memory map.
+          * Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
-@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
+@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
-      * are done in arm_v7m_load_vector(), which always does a direct
+          */
-      * read using address_space_ldl(), rather than going via this function.
+         syn = syn_data_abort_with_iss(same_el,
-      */
+, 0, 0, 0, 0,
--    if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
+-                                      ea, 0, s1ptw, is_write, fsc,
-+    if (regime_translation_disabled(env, mmu_idx, secure)) { /* MPU disabled */
++                                      fi->ea, 0, fi->s1ptw, is_write, fsc,
-         hit = true;
+                                       true);
-     } else if (m_is_ppb_region(env, address)) {
+         /* Merge the runtime syndrome with the template syndrome.  */
-         hit = true;
+         syn |= template_syn;
-@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
+@@ -XXX,XX +XXX,XX @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr,
-                                 result, fi);
+         syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);
+         exc = EXCP_PREFETCH_ABORT;
-             /* If S1 fails or S2 is disabled, return early.  */
+     } else {
--            if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
+-        syn = merge_syn_data_abort(env->exception.syndrome, target_el,
-+            if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2,
+-                                   same_el, fi->ea, fi->s1ptw,
-+                                                   is_secure)) {
+-                                   access_type == MMU_DATA_STORE,
-                 return ret;
++        syn = merge_syn_data_abort(env->exception.syndrome, fi, target_el,
-             }
++                                   same_el, access_type == MMU_DATA_STORE,
+                                    fsc);
-@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
+         if (access_type == MMU_DATA_STORE
+             && arm_feature(env, ARM_FEATURE_V6)) {
      /* Definitely a real MMU, not an MPU */
 -    if (regime_translation_disabled(env, mmu_idx)) {
 +    if (regime_translation_disabled(env, mmu_idx, is_secure)) {
          uint64_t hcr;
          uint8_t memattr;
 --
-.25.1
+.34.1

-[PULL 26/28] target/arm: Don't allow guest to use unimplemented granule sizes
+[PULL 13/21] target/arm: Don't set ISV when reporting stage 1 faults in ESR_EL2
-Arm CPUs support some subset of the granule (page) sizes 4K, 16K and
+The syndrome value reported to ESR_EL2 should only contain the
-K.  The guest selects the one it wants using bits in the TCR_ELx
+detailed instruction syndrome information when the fault has been
-registers.  If it tries to program these registers with a value that
+caused by a stage 2 abort, not when the fault was a stage 1 abort
-is either reserved or which requests a size that the CPU does not
+(i.e.  caused by execution at EL2).  We were getting this wrong and
-implement, the architecture requires that the CPU behaves as if the
+reporting the detailed ISV information all the time.
 field was programmed to some size that has been implemented.
 Currently we don't implement this, and instead let the guest use any
 granule size, even if the CPU ID register fields say it isn't
 present.
-Make aa64_va_parameters() check against the supported granule size
+Fix the bug by checking fi->stage2.  Add a TODO comment noting the
-and force use of a different one if it is not implemented.
+cases where we'll have to come back and revisit this when we
 implement FEAT_LS64 and friends.
-(A subsequent commit will make ARMVAParameters use the new enum
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rather than the current pair of using16k/using64k bools.)
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230331145045.2584941-3-peter.maydell@linaro.org
 ---
  target/arm/tcg/tlb_helper.c | 13 ++++++++++---
 file changed, 10 insertions(+), 3 deletions(-)
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20221003162315.2833797-2-peter.maydell@linaro.org
 ---
  target/arm/cpu.h       |  33 +++++++++++++
  target/arm/internals.h |   9 ++++
  target/arm/helper.c    | 102 +++++++++++++++++++++++++++++++++++++----
 files changed, 136 insertions(+), 8 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/target/arm/tcg/tlb_helper.c
-+++ b/target/arm/cpu.h
++++ b/target/arm/tcg/tlb_helper.c
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
-     return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
+     uint32_t syn;
- }
+     /*
-+static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id)
+-     * ISV is only set for data aborts routed to EL2 and
-+{
+-     * never for stage-1 page table walks faulting on stage 2.
-+    return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0;
++     * ISV is only set for stage-2 data aborts routed to EL2 and
-+}
++     * never for stage-1 page table walks faulting on stage 2
-+
++     * or for stage-1 faults.
-+static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id)
+      *
-+{
+      * Furthermore, ISV is only set for certain kinds of load/stores.
-+    return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1;
+      * If the template syndrome does not have ISV set, we should leave
-+}
+@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
-+
+      * See ARMv8 specs, D7-1974:
-+static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id)
+      * ISS encoding for an exception from a Data Abort, the
-+{
+      * ISV field.
-+    return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0;
++     *
-+}
++     * TODO: FEAT_LS64/FEAT_LS64_V/FEAT_SL64_ACCDATA: Translation,
-+
++     * Access Flag, and Permission faults caused by LD64B, ST64B,
-+static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id)
++     * ST64BV, or ST64BV0 insns report syndrome info even for stage-1
-+{
++     * faults and regardless of the target EL.
-+    unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
+      */
-+    return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id));
+-    if (!(template_syn & ARM_EL_ISV) || target_el != 2 || fi->s1ptw) {
-+}
++    if (!(template_syn & ARM_EL_ISV) || target_el != 2
-+
++        || fi->s1ptw || !fi->stage2) {
-+static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id)
+         syn = syn_data_abort_no_iss(same_el, 0,
-+{
+                                     fi->ea, 0, fi->s1ptw, is_write, fsc);
 +    unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
 +    return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id));
 +}
 +
 +static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
 +{
 +    unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2);
 +    return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
 +}
 +
  static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
  {
      return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
      return valid;
  }
 +/* Granule size (i.e. page size) */
 +typedef enum ARMGranuleSize {
 +    /* Same order as TG0 encoding */
 +    Gran4K,
 +    Gran64K,
 +    Gran16K,
 +    GranInvalid,
 +} ARMGranuleSize;
 +
  /*
   * Parameters of a given virtual address, as extracted from the
   * translation control register (TCR) for a given regime.
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx)
      }
  }
 +static ARMGranuleSize tg0_to_gran_size(int tg)
 +{
 +    switch (tg) {
 +    case 0:
 +        return Gran4K;
 +    case 1:
 +        return Gran64K;
 +    case 2:
 +        return Gran16K;
 +    default:
 +        return GranInvalid;
 +    }
 +}
 +
 +static ARMGranuleSize tg1_to_gran_size(int tg)
 +{
 +    switch (tg) {
 +    case 1:
 +        return Gran16K;
 +    case 2:
 +        return Gran4K;
 +    case 3:
 +        return Gran64K;
 +    default:
 +        return GranInvalid;
 +    }
 +}
 +
 +static inline bool have4k(ARMCPU *cpu, bool stage2)
 +{
 +    return stage2 ? cpu_isar_feature(aa64_tgran4_2, cpu)
 +        : cpu_isar_feature(aa64_tgran4, cpu);
 +}
 +
 +static inline bool have16k(ARMCPU *cpu, bool stage2)
 +{
 +    return stage2 ? cpu_isar_feature(aa64_tgran16_2, cpu)
 +        : cpu_isar_feature(aa64_tgran16, cpu);
 +}
 +
 +static inline bool have64k(ARMCPU *cpu, bool stage2)
 +{
 +    return stage2 ? cpu_isar_feature(aa64_tgran64_2, cpu)
 +        : cpu_isar_feature(aa64_tgran64, cpu);
 +}
 +
 +static ARMGranuleSize sanitize_gran_size(ARMCPU *cpu, ARMGranuleSize gran,
 +                                         bool stage2)
 +{
 +    switch (gran) {
 +    case Gran4K:
 +        if (have4k(cpu, stage2)) {
 +            return gran;
 +        }
 +        break;
 +    case Gran16K:
 +        if (have16k(cpu, stage2)) {
 +            return gran;
 +        }
 +        break;
 +    case Gran64K:
 +        if (have64k(cpu, stage2)) {
 +            return gran;
 +        }
 +        break;
 +    case GranInvalid:
 +        break;
 +    }
 +    /*
 +     * If the guest selects a granule size that isn't implemented,
 +     * the architecture requires that we behave as if it selected one
 +     * that is (with an IMPDEF choice of which one to pick). We choose
 +     * to implement the smallest supported granule size.
 +     */
 +    if (have4k(cpu, stage2)) {
 +        return Gran4K;
 +    }
 +    if (have16k(cpu, stage2)) {
 +        return Gran16K;
 +    }
 +    assert(have64k(cpu, stage2));
 +    return Gran64K;
 +}
 +
  ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
                                     ARMMMUIdx mmu_idx, bool data)
  {
      uint64_t tcr = regime_tcr(env, mmu_idx);
      bool epd, hpd, using16k, using64k, tsz_oob, ds;
      int select, tsz, tbi, max_tsz, min_tsz, ps, sh;
 +    ARMGranuleSize gran;
      ARMCPU *cpu = env_archcpu(env);
 +    bool stage2 = mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S;
      if (!regime_has_2_ranges(mmu_idx)) {
          select = 0;
          tsz = extract32(tcr, 0, 6);
 -        using64k = extract32(tcr, 14, 1);
 -        using16k = extract32(tcr, 15, 1);
 -        if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
 +        gran = tg0_to_gran_size(extract32(tcr, 14, 2));
 +        if (stage2) {
              /* VTCR_EL2 */
              hpd = false;
          } else {
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
          select = extract64(va, 55, 1);
          if (!select) {
              tsz = extract32(tcr, 0, 6);
 +            gran = tg0_to_gran_size(extract32(tcr, 14, 2));
              epd = extract32(tcr, 7, 1);
              sh = extract32(tcr, 12, 2);
 -            using64k = extract32(tcr, 14, 1);
 -            using16k = extract32(tcr, 15, 1);
              hpd = extract64(tcr, 41, 1);
          } else {
 -            int tg = extract32(tcr, 30, 2);
 -            using16k = tg == 1;
 -            using64k = tg == 3;
              tsz = extract32(tcr, 16, 6);
 +            gran = tg1_to_gran_size(extract32(tcr, 30, 2));
              epd = extract32(tcr, 23, 1);
              sh = extract32(tcr, 28, 2);
              hpd = extract64(tcr, 42, 1);
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
          ds = extract64(tcr, 59, 1);
      }
 +    gran = sanitize_gran_size(cpu, gran, stage2);
 +    using64k = gran == Gran64K;
 +    using16k = gran == Gran16K;
 +
      if (cpu_isar_feature(aa64_st, cpu)) {
          max_tsz = 48 - using64k;
      } else {
 --
-.25.1
+.34.1

-[PULL 14/28] target/arm: Fold secure and non-secure a-profile mmu indexes
+[PULL 14/21] target/arm: Implement FEAT_PAN3
-From: Richard Henderson <richard.henderson@linaro.org>
+FEAT_PAN3 adds an EPAN bit to SCTLR_EL1 and SCTLR_EL2, which allows
 the PAN bit to make memory non-privileged-read/write if it is
 user-executable as well as if it is user-read/write.
-For a-profile aarch64, which does not bank system registers, it takes
+Implement this feature and enable it in the AArch64 'max' CPU.
 quite a lot of code to switch between security states.  In the process,
 registers such as TCR_EL{1,2} must be swapped, which in itself requires
 the flushing of softmmu tlbs.  Therefore it doesn't buy us anything to
 separate tlbs by security state.
-Retain the distinction between Stage2 and Stage2_S.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230331145045.2584941-4-peter.maydell@linaro.org
 ---
  docs/system/arm/emulation.rst |  1 +
  target/arm/cpu.h              |  5 +++++
  target/arm/cpu64.c            |  2 +-
  target/arm/ptw.c              | 14 +++++++++++++-
 files changed, 20 insertions(+), 2 deletions(-)
-This will be important as we implement FEAT_RME, and do not wish to
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 add a third set of mmu indexes for Realm state.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20221001162318.153420-11-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu-param.h     |   2 +-
  target/arm/cpu.h           |  72 +++++++------------
  target/arm/internals.h     |  31 +-------
  target/arm/helper.c        | 144 +++++++++++++------------------------
  target/arm/ptw.c           |  25 ++-----
  target/arm/translate-a64.c |   8 ---
  target/arm/translate.c     |   6 +-
 files changed, 85 insertions(+), 203 deletions(-)
 diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu-param.h
+--- a/docs/system/arm/emulation.rst
-+++ b/target/arm/cpu-param.h
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- # define TARGET_PAGE_BITS_MIN  10
+ - FEAT_MTE3 (MTE Asymmetric Fault Handling)
- #endif
+ - FEAT_PAN (Privileged access never)
+ - FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN)
--#define NB_MMU_MODES 15
++- FEAT_PAN3 (Support for SCTLR_ELx.EPAN)
-+#define NB_MMU_MODES 8
+ - FEAT_PAuth (Pointer authentication)
+ - FEAT_PMULL (PMULL, PMULL2 instructions)
- #endif
+ - FEAT_PMUv3p1 (PMU Extensions v3.1)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
+@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
-  *     table over and over.
+     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
-  *  6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
+ }
-  *     Never (PAN) bit within PSTATE.
-+ *  7. we fold together the secure and non-secure regimes for A-profile,
++static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id)
-+ *     because there are no banked system registers for aarch64, so the
++{
-+ *     process of switching between secure and non-secure is
++    return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 3;
-+ *     already heavyweight.
++}
-  *
++
-  * This gives us the following list of cases:
+ static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
-  *
+ {
-- * NS EL0 EL1&0 stage 1+2 (aka NS PL0)
+     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0;
-- * NS EL1 EL1&0 stage 1+2 (aka NS PL1)
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 - * NS EL1 EL1&0 stage 1+2 +PAN
 - * NS EL0 EL2&0
 - * NS EL2 EL2&0
 - * NS EL2 EL2&0 +PAN
 - * NS EL2 (aka NS PL2)
 - * S EL0 EL1&0 (aka S PL0)
 - * S EL1 EL1&0 (not used if EL3 is 32 bit)
 - * S EL1 EL1&0 +PAN
 - * S EL3 (aka S PL1)
 + * EL0 EL1&0 stage 1+2 (aka NS PL0)
 + * EL1 EL1&0 stage 1+2 (aka NS PL1)
 + * EL1 EL1&0 stage 1+2 +PAN
 + * EL0 EL2&0
 + * EL2 EL2&0
 + * EL2 EL2&0 +PAN
 + * EL2 (aka NS PL2)
 + * EL3 (aka S PL1)
   *
 - * for a total of 11 different mmu_idx.
 + * for a total of 8 different mmu_idx.
   *
   * R profile CPUs have an MPU, but can use the same set of MMU indexes
 - * as A profile. They only need to distinguish NS EL0 and NS EL1 (and
 - * NS EL2 if we ever model a Cortex-R52).
 + * as A profile. They only need to distinguish EL0 and EL1 (and
 + * EL2 if we ever model a Cortex-R52).
   *
   * M profile CPUs are rather different as they do not have a true MMU.
   * They have the following different MMU indexes:
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
  #define ARM_MMU_IDX_NOTLB 0x20  /* does not have a TLB */
  #define ARM_MMU_IDX_M     0x40  /* M profile */
 -/* Meanings of the bits for A profile mmu idx values */
 -#define ARM_MMU_IDX_A_NS     0x8
 -
  /* Meanings of the bits for M profile mmu idx values */
  #define ARM_MMU_IDX_M_PRIV   0x1
  #define ARM_MMU_IDX_M_NEGPRI 0x2
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
      /*
       * A-profile.
       */
 -    ARMMMUIdx_SE10_0     =  0 | ARM_MMU_IDX_A,
 -    ARMMMUIdx_SE20_0     =  1 | ARM_MMU_IDX_A,
 -    ARMMMUIdx_SE10_1     =  2 | ARM_MMU_IDX_A,
 -    ARMMMUIdx_SE20_2     =  3 | ARM_MMU_IDX_A,
 -    ARMMMUIdx_SE10_1_PAN =  4 | ARM_MMU_IDX_A,
 -    ARMMMUIdx_SE20_2_PAN =  5 | ARM_MMU_IDX_A,
 -    ARMMMUIdx_SE2        =  6 | ARM_MMU_IDX_A,
 -    ARMMMUIdx_SE3        =  7 | ARM_MMU_IDX_A,
 -
 -    ARMMMUIdx_E10_0     = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS,
 -    ARMMMUIdx_E20_0     = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS,
 -    ARMMMUIdx_E10_1     = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS,
 -    ARMMMUIdx_E20_2     = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS,
 -    ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS,
 -    ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS,
 -    ARMMMUIdx_E2        = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS,
 +    ARMMMUIdx_E10_0     = 0 | ARM_MMU_IDX_A,
 +    ARMMMUIdx_E20_0     = 1 | ARM_MMU_IDX_A,
 +    ARMMMUIdx_E10_1     = 2 | ARM_MMU_IDX_A,
 +    ARMMMUIdx_E20_2     = 3 | ARM_MMU_IDX_A,
 +    ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A,
 +    ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A,
 +    ARMMMUIdx_E2        = 6 | ARM_MMU_IDX_A,
 +    ARMMMUIdx_E3        = 7 | ARM_MMU_IDX_A,
      /*
       * These are not allocated TLBs and are used only for AT system
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
      ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
      ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
      ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
 -    ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB,
 -    ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB,
 -    ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB,
      /*
       * Not allocated a TLB: used only for second stage of an S12 page
       * table walk, or for descriptor loads during first stage of an S1
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
       * then various TLB flush insns which currently are no-ops or flush
       * only stage 1 MMU indexes will need to change to flush stage 2.
       */
 -    ARMMMUIdx_Stage2     = 6 | ARM_MMU_IDX_NOTLB,
 -    ARMMMUIdx_Stage2_S   = 7 | ARM_MMU_IDX_NOTLB,
 +    ARMMMUIdx_Stage2     = 3 | ARM_MMU_IDX_NOTLB,
 +    ARMMMUIdx_Stage2_S   = 4 | ARM_MMU_IDX_NOTLB,
      /*
       * M-profile.
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit {
      TO_CORE_BIT(E2),
      TO_CORE_BIT(E20_2),
      TO_CORE_BIT(E20_2_PAN),
 -    TO_CORE_BIT(SE10_0),
 -    TO_CORE_BIT(SE20_0),
 -    TO_CORE_BIT(SE10_1),
 -    TO_CORE_BIT(SE20_2),
 -    TO_CORE_BIT(SE10_1_PAN),
 -    TO_CORE_BIT(SE20_2_PAN),
 -    TO_CORE_BIT(SE2),
 -    TO_CORE_BIT(SE3),
 +    TO_CORE_BIT(E3),
      TO_CORE_BIT(MUser),
      TO_CORE_BIT(MPriv),
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
+--- a/target/arm/cpu64.c
-+++ b/target/arm/internals.h
++++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx)
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-     case ARMMMUIdx_Stage1_E0:
+     t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
-     case ARMMMUIdx_Stage1_E1:
+     t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
-     case ARMMMUIdx_Stage1_E1_PAN:
+     t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
--    case ARMMMUIdx_Stage1_SE0:
+-    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2);      /* FEAT_PAN2 */
--    case ARMMMUIdx_Stage1_SE1:
++    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3);      /* FEAT_PAN3 */
--    case ARMMMUIdx_Stage1_SE1_PAN:
+     t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
-     case ARMMMUIdx_E10_0:
+     t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1);      /* FEAT_ETS */
-     case ARMMMUIdx_E10_1:
+     t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1);      /* FEAT_HCX */
      case ARMMMUIdx_E10_1_PAN:
      case ARMMMUIdx_E20_0:
      case ARMMMUIdx_E20_2:
      case ARMMMUIdx_E20_2_PAN:
 -    case ARMMMUIdx_SE10_0:
 -    case ARMMMUIdx_SE10_1:
 -    case ARMMMUIdx_SE10_1_PAN:
 -    case ARMMMUIdx_SE20_0:
 -    case ARMMMUIdx_SE20_2:
 -    case ARMMMUIdx_SE20_2_PAN:
          return true;
      default:
          return false;
@@ -XXX,XX +XXX,XX @@ static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx)
  {
      switch (mmu_idx) {
      case ARMMMUIdx_Stage1_E1_PAN:
 -    case ARMMMUIdx_Stage1_SE1_PAN:
      case ARMMMUIdx_E10_1_PAN:
      case ARMMMUIdx_E20_2_PAN:
 -    case ARMMMUIdx_SE10_1_PAN:
 -    case ARMMMUIdx_SE20_2_PAN:
          return true;
      default:
          return false;
@@ -XXX,XX +XXX,XX @@ static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx)
  static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
  {
      switch (mmu_idx) {
 -    case ARMMMUIdx_SE20_0:
 -    case ARMMMUIdx_SE20_2:
 -    case ARMMMUIdx_SE20_2_PAN:
      case ARMMMUIdx_E20_0:
      case ARMMMUIdx_E20_2:
      case ARMMMUIdx_E20_2_PAN:
      case ARMMMUIdx_Stage2:
      case ARMMMUIdx_Stage2_S:
 -    case ARMMMUIdx_SE2:
      case ARMMMUIdx_E2:
          return 2;
 -    case ARMMMUIdx_SE3:
 +    case ARMMMUIdx_E3:
          return 3;
 -    case ARMMMUIdx_SE10_0:
 -    case ARMMMUIdx_Stage1_SE0:
 -        return arm_el_is_aa64(env, 3) ? 1 : 3;
 -    case ARMMMUIdx_SE10_1:
 -    case ARMMMUIdx_SE10_1_PAN:
 +    case ARMMMUIdx_E10_0:
      case ARMMMUIdx_Stage1_E0:
 +        return arm_el_is_aa64(env, 3) || !arm_is_secure_below_el3(env) ? 1 : 3;
      case ARMMMUIdx_Stage1_E1:
      case ARMMMUIdx_Stage1_E1_PAN:
 -    case ARMMMUIdx_Stage1_SE1:
 -    case ARMMMUIdx_Stage1_SE1_PAN:
 -    case ARMMMUIdx_E10_0:
      case ARMMMUIdx_E10_1:
      case ARMMMUIdx_E10_1_PAN:
      case ARMMMUIdx_MPrivNegPri:
@@ -XXX,XX +XXX,XX @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx)
      case ARMMMUIdx_Stage1_E0:
      case ARMMMUIdx_Stage1_E1:
      case ARMMMUIdx_Stage1_E1_PAN:
 -    case ARMMMUIdx_Stage1_SE0:
 -    case ARMMMUIdx_Stage1_SE1:
 -    case ARMMMUIdx_Stage1_SE1_PAN:
          return true;
      default:
          return false;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
      /* Begin with base v8.0 state.  */
      uint64_t valid_mask = 0x3fff;
      ARMCPU *cpu = env_archcpu(env);
 +    uint64_t changed;
      /*
       * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
      /* Clear all-context RES0 bits.  */
      value &= valid_mask;
 -    raw_write(env, ri, value);
 +    changed = env->cp15.scr_el3 ^ value;
 +    env->cp15.scr_el3 = value;
 +
 +    /*
 +     * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then
 +     * we must invalidate all TLBs below EL3.
 +     */
 +    if (changed & SCR_NS) {
 +        tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 |
 +                                           ARMMMUIdxBit_E20_0 |
 +                                           ARMMMUIdxBit_E10_1 |
 +                                           ARMMMUIdxBit_E20_2 |
 +                                           ARMMMUIdxBit_E10_1_PAN |
 +                                           ARMMMUIdxBit_E20_2_PAN |
 +                                           ARMMMUIdxBit_E2));
 +    }
  }
  static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static int gt_phys_redir_timeridx(CPUARMState *env)
      case ARMMMUIdx_E20_0:
      case ARMMMUIdx_E20_2:
      case ARMMMUIdx_E20_2_PAN:
 -    case ARMMMUIdx_SE20_0:
 -    case ARMMMUIdx_SE20_2:
 -    case ARMMMUIdx_SE20_2_PAN:
          return GTIMER_HYP;
      default:
          return GTIMER_PHYS;
@@ -XXX,XX +XXX,XX @@ static int gt_virt_redir_timeridx(CPUARMState *env)
      case ARMMMUIdx_E20_0:
      case ARMMMUIdx_E20_2:
      case ARMMMUIdx_E20_2_PAN:
 -    case ARMMMUIdx_SE20_0:
 -    case ARMMMUIdx_SE20_2:
 -    case ARMMMUIdx_SE20_2_PAN:
          return GTIMER_HYPVIRT;
      default:
          return GTIMER_VIRT;
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
          /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
          switch (el) {
          case 3:
 -            mmu_idx = ARMMMUIdx_SE3;
 +            mmu_idx = ARMMMUIdx_E3;
              secure = true;
              break;
          case 2:
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
              /* fall through */
          case 1:
              if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) {
 -                mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN
 -                           : ARMMMUIdx_Stage1_E1_PAN);
 +                mmu_idx = ARMMMUIdx_Stage1_E1_PAN;
              } else {
 -                mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1;
 +                mmu_idx = ARMMMUIdx_Stage1_E1;
              }
              break;
          default:
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
          /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
          switch (el) {
          case 3:
 -            mmu_idx = ARMMMUIdx_SE10_0;
 +            mmu_idx = ARMMMUIdx_E10_0;
              secure = true;
              break;
          case 2:
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
              mmu_idx = ARMMMUIdx_Stage1_E0;
              break;
          case 1:
 -            mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0;
 +            mmu_idx = ARMMMUIdx_Stage1_E0;
              break;
          default:
              g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
          switch (ri->opc1) {
          case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
              if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) {
 -                mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN
 -                           : ARMMMUIdx_Stage1_E1_PAN);
 +                mmu_idx = ARMMMUIdx_Stage1_E1_PAN;
              } else {
 -                mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1;
 +                mmu_idx = ARMMMUIdx_Stage1_E1;
              }
              break;
          case 4: /* AT S1E2R, AT S1E2W */
 -            mmu_idx = secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2;
 +            mmu_idx = ARMMMUIdx_E2;
              break;
          case 6: /* AT S1E3R, AT S1E3W */
 -            mmu_idx = ARMMMUIdx_SE3;
 +            mmu_idx = ARMMMUIdx_E3;
              secure = true;
              break;
          default:
@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
          }
          break;
      case 2: /* AT S1E0R, AT S1E0W */
 -        mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0;
 +        mmu_idx = ARMMMUIdx_Stage1_E0;
          break;
      case 4: /* AT S12E1R, AT S12E1W */
 -        mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1;
 +        mmu_idx = ARMMMUIdx_E10_1;
          break;
      case 6: /* AT S12E0R, AT S12E0W */
 -        mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0;
 +        mmu_idx = ARMMMUIdx_E10_0;
          break;
      default:
          g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
          uint16_t mask = ARMMMUIdxBit_E20_2 |
                          ARMMMUIdxBit_E20_2_PAN |
                          ARMMMUIdxBit_E20_0;
 -
 -        if (arm_is_secure_below_el3(env)) {
 -            mask >>= ARM_MMU_IDX_A_NS;
 -        }
 -
          tlb_flush_by_mmuidx(env_cpu(env), mask);
      }
      raw_write(env, ri, value);
@@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
          uint16_t mask = ARMMMUIdxBit_E10_1 |
                          ARMMMUIdxBit_E10_1_PAN |
                          ARMMMUIdxBit_E10_0;
 -
 -        if (arm_is_secure_below_el3(env)) {
 -            mask >>= ARM_MMU_IDX_A_NS;
 -        }
 -
          tlb_flush_by_mmuidx(cs, mask);
          raw_write(env, ri, value);
      }
@@ -XXX,XX +XXX,XX @@ static int vae1_tlbmask(CPUARMState *env)
                 ARMMMUIdxBit_E10_1_PAN |
                 ARMMMUIdxBit_E10_0;
      }
 -
 -    if (arm_is_secure_below_el3(env)) {
 -        mask >>= ARM_MMU_IDX_A_NS;
 -    }
 -
      return mask;
  }
@@ -XXX,XX +XXX,XX @@ static int vae1_tlbbits(CPUARMState *env, uint64_t addr)
          mmu_idx = ARMMMUIdx_E10_0;
      }
 -    if (arm_is_secure_below_el3(env)) {
 -        mmu_idx &= ~ARM_MMU_IDX_A_NS;
 -    }
 -
      return tlbbits_for_regime(env, mmu_idx, addr);
  }
@@ -XXX,XX +XXX,XX @@ static int alle1_tlbmask(CPUARMState *env)
       * stage 2 translations, whereas most other scopes only invalidate
       * stage 1 translations.
       */
 -    if (arm_is_secure_below_el3(env)) {
 -        return ARMMMUIdxBit_SE10_1 |
 -               ARMMMUIdxBit_SE10_1_PAN |
 -               ARMMMUIdxBit_SE10_0;
 -    } else {
 -        return ARMMMUIdxBit_E10_1 |
 -               ARMMMUIdxBit_E10_1_PAN |
 -               ARMMMUIdxBit_E10_0;
 -    }
 +    return (ARMMMUIdxBit_E10_1 |
 +            ARMMMUIdxBit_E10_1_PAN |
 +            ARMMMUIdxBit_E10_0);
  }
  static int e2_tlbmask(CPUARMState *env)
  {
 -    if (arm_is_secure_below_el3(env)) {
 -        return ARMMMUIdxBit_SE20_0 |
 -               ARMMMUIdxBit_SE20_2 |
 -               ARMMMUIdxBit_SE20_2_PAN |
 -               ARMMMUIdxBit_SE2;
 -    } else {
 -        return ARMMMUIdxBit_E20_0 |
 -               ARMMMUIdxBit_E20_2 |
 -               ARMMMUIdxBit_E20_2_PAN |
 -               ARMMMUIdxBit_E2;
 -    }
 +    return (ARMMMUIdxBit_E20_0 |
 +            ARMMMUIdxBit_E20_2 |
 +            ARMMMUIdxBit_E20_2_PAN |
 +            ARMMMUIdxBit_E2);
  }
  static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
      ARMCPU *cpu = env_archcpu(env);
      CPUState *cs = CPU(cpu);
 -    tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3);
 +    tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E3);
  }
  static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
  {
      CPUState *cs = env_cpu(env);
 -    tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3);
 +    tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3);
  }
  static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
      CPUState *cs = CPU(cpu);
      uint64_t pageaddr = sextract64(value << 12, 0, 56);
 -    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3);
 +    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E3);
  }
  static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
  {
      CPUState *cs = env_cpu(env);
      uint64_t pageaddr = sextract64(value << 12, 0, 56);
 -    bool secure = arm_is_secure_below_el3(env);
 -    int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2;
 -    int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2,
 -                                  pageaddr);
 +    int bits = tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr);
 -    tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
 +    tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
 +                                                  ARMMMUIdxBit_E2, bits);
  }
  static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
  {
      CPUState *cs = env_cpu(env);
      uint64_t pageaddr = sextract64(value << 12, 0, 56);
 -    int bits = tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr);
 +    int bits = tlbbits_for_regime(env, ARMMMUIdx_E3, pageaddr);
      tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
 -                                                  ARMMMUIdxBit_SE3, bits);
 +                                                  ARMMMUIdxBit_E3, bits);
  }
  #ifdef TARGET_AARCH64
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_rvae1is_write(CPUARMState *env,
  static int vae2_tlbmask(CPUARMState *env)
  {
 -    return (arm_is_secure_below_el3(env)
 -            ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2);
 +    return ARMMMUIdxBit_E2;
  }
  static void tlbi_aa64_rvae2_write(CPUARMState *env,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_rvae3_write(CPUARMState *env,
       * flush-last-level-only.
       */
 -    do_rvae_write(env, value, ARMMMUIdxBit_SE3,
 -                  tlb_force_broadcast(env));
 +    do_rvae_write(env, value, ARMMMUIdxBit_E3, tlb_force_broadcast(env));
  }
  static void tlbi_aa64_rvae3is_write(CPUARMState *env,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_rvae3is_write(CPUARMState *env,
       * flush-last-level-only or inner/outer specific flushes.
       */
 -    do_rvae_write(env, value, ARMMMUIdxBit_SE3, true);
 +    do_rvae_write(env, value, ARMMMUIdxBit_E3, true);
  }
  #endif
@@ -XXX,XX +XXX,XX @@ uint64_t arm_sctlr(CPUARMState *env, int el)
      /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
      if (el == 0) {
          ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0);
 -        el = (mmu_idx == ARMMMUIdx_E20_0 || mmu_idx == ARMMMUIdx_SE20_0)
 -             ? 2 : 1;
 +        el = mmu_idx == ARMMMUIdx_E20_0 ? 2 : 1;
      }
      return env->cp15.sctlr_el[el];
  }
@@ -XXX,XX +XXX,XX @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
      switch (mmu_idx) {
      case ARMMMUIdx_E10_0:
      case ARMMMUIdx_E20_0:
 -    case ARMMMUIdx_SE10_0:
 -    case ARMMMUIdx_SE20_0:
          return 0;
      case ARMMMUIdx_E10_1:
      case ARMMMUIdx_E10_1_PAN:
 -    case ARMMMUIdx_SE10_1:
 -    case ARMMMUIdx_SE10_1_PAN:
          return 1;
      case ARMMMUIdx_E2:
      case ARMMMUIdx_E20_2:
      case ARMMMUIdx_E20_2_PAN:
 -    case ARMMMUIdx_SE2:
 -    case ARMMMUIdx_SE20_2:
 -    case ARMMMUIdx_SE20_2_PAN:
          return 2;
 -    case ARMMMUIdx_SE3:
 +    case ARMMMUIdx_E3:
          return 3;
      default:
          g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
          }
          break;
      case 3:
 -        return ARMMMUIdx_SE3;
 +        return ARMMMUIdx_E3;
      default:
          g_assert_not_reached();
      }
 -    if (arm_is_secure_below_el3(env)) {
 -        idx &= ~ARM_MMU_IDX_A_NS;
 -    }
 -
      return idx;
  }
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
          switch (mmu_idx) {
          case ARMMMUIdx_E10_1:
          case ARMMMUIdx_E10_1_PAN:
 -        case ARMMMUIdx_SE10_1:
 -        case ARMMMUIdx_SE10_1_PAN:
              /* TODO: ARMv8.3-NV */
              DP_TBFLAG_A64(flags, UNPRIV, 1);
              break;
          case ARMMMUIdx_E20_2:
          case ARMMMUIdx_E20_2_PAN:
 -        case ARMMMUIdx_SE20_2:
 -        case ARMMMUIdx_SE20_2_PAN:
              /*
               * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
               * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
 diff --git a/target/arm/ptw.c b/target/arm/ptw.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/ptw.c
 +++ b/target/arm/ptw.c
-@@ -XXX,XX +XXX,XX @@ unsigned int arm_pamax(ARMCPU *cpu)
+@@ -XXX,XX +XXX,XX @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)
- ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
+ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
                        int ap, int ns, int xn, int pxn)
  {
-     switch (mmu_idx) {
++    ARMCPU *cpu = env_archcpu(env);
--    case ARMMMUIdx_SE10_0:
+     bool is_user = regime_is_user(env, mmu_idx);
--        return ARMMMUIdx_Stage1_SE0;
+     int prot_rw, user_rw;
--    case ARMMMUIdx_SE10_1:
+     bool have_wxn;
--        return ARMMMUIdx_Stage1_SE1;
+@@ -XXX,XX +XXX,XX @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
--    case ARMMMUIdx_SE10_1_PAN:
+     if (is_user) {
--        return ARMMMUIdx_Stage1_SE1_PAN;
+         prot_rw = user_rw;
-     case ARMMMUIdx_E10_0:
+     } else {
-         return ARMMMUIdx_Stage1_E0;
++        /*
-     case ARMMMUIdx_E10_1:
++         * PAN controls can forbid data accesses but don't affect insn fetch.
-@@ -XXX,XX +XXX,XX @@ static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx)
++         * Plain PAN forbids data accesses if EL0 has data permissions;
- static bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
++         * PAN3 forbids data accesses if EL0 has either data or exec perms.
- {
++         * Note that for AArch64 the 'user can exec' case is exactly !xn.
-     switch (mmu_idx) {
++         * We make the IMPDEF choices that SCR_EL3.SIF and Realm EL2&0
--    case ARMMMUIdx_SE10_0:
++         * do not affect EPAN.
-     case ARMMMUIdx_E20_0:
++         */
--    case ARMMMUIdx_SE20_0:
+         if (user_rw && regime_is_pan(env, mmu_idx)) {
-     case ARMMMUIdx_Stage1_E0:
+-            /* PAN forbids data accesses but doesn't affect insn fetch */
--    case ARMMMUIdx_Stage1_SE0:
++            prot_rw = 0;
-     case ARMMMUIdx_MUser:
++        } else if (cpu_isar_feature(aa64_pan3, cpu) && is_aa64 &&
-     case ARMMMUIdx_MSUser:
++                   regime_is_pan(env, mmu_idx) &&
-     case ARMMMUIdx_MUserNegPri:
++                   (regime_sctlr(env, mmu_idx) & SCTLR_EPAN) && !xn) {
-@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
+             prot_rw = 0;
+         } else {
-             s2_mmu_idx = (s2walk_secure
+             prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
                            ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2);
 -            is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0;
 +            is_el0 = mmu_idx == ARMMMUIdx_E10_0;
              /*
               * S1 is done, now do S2 translation.
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
      case ARMMMUIdx_Stage1_E1:
      case ARMMMUIdx_Stage1_E1_PAN:
      case ARMMMUIdx_E2:
 +        is_secure = arm_is_secure_below_el3(env);
 +        break;
      case ARMMMUIdx_Stage2:
      case ARMMMUIdx_MPrivNegPri:
      case ARMMMUIdx_MUserNegPri:
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
      case ARMMMUIdx_MUser:
          is_secure = false;
          break;
 -    case ARMMMUIdx_SE3:
 -    case ARMMMUIdx_SE10_0:
 -    case ARMMMUIdx_SE10_1:
 -    case ARMMMUIdx_SE10_1_PAN:
 -    case ARMMMUIdx_SE20_0:
 -    case ARMMMUIdx_SE20_2:
 -    case ARMMMUIdx_SE20_2_PAN:
 -    case ARMMMUIdx_Stage1_SE0:
 -    case ARMMMUIdx_Stage1_SE1:
 -    case ARMMMUIdx_Stage1_SE1_PAN:
 -    case ARMMMUIdx_SE2:
 +    case ARMMMUIdx_E3:
      case ARMMMUIdx_Stage2_S:
      case ARMMMUIdx_MSPrivNegPri:
      case ARMMMUIdx_MSUserNegPri:
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static int get_a64_user_mem_index(DisasContext *s)
          case ARMMMUIdx_E20_2_PAN:
              useridx = ARMMMUIdx_E20_0;
              break;
 -        case ARMMMUIdx_SE10_1:
 -        case ARMMMUIdx_SE10_1_PAN:
 -            useridx = ARMMMUIdx_SE10_0;
 -            break;
 -        case ARMMMUIdx_SE20_2:
 -        case ARMMMUIdx_SE20_2_PAN:
 -            useridx = ARMMMUIdx_SE20_0;
 -            break;
          default:
              g_assert_not_reached();
          }
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline int get_a32_user_mem_index(DisasContext *s)
       *  otherwise, access as if at PL0.
       */
      switch (s->mmu_idx) {
 +    case ARMMMUIdx_E3:
      case ARMMMUIdx_E2:        /* this one is UNPREDICTABLE */
      case ARMMMUIdx_E10_0:
      case ARMMMUIdx_E10_1:
      case ARMMMUIdx_E10_1_PAN:
          return arm_to_core_mmu_idx(ARMMMUIdx_E10_0);
 -    case ARMMMUIdx_SE3:
 -    case ARMMMUIdx_SE10_0:
 -    case ARMMMUIdx_SE10_1:
 -    case ARMMMUIdx_SE10_1_PAN:
 -        return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0);
      case ARMMMUIdx_MUser:
      case ARMMMUIdx_MPriv:
          return arm_to_core_mmu_idx(ARMMMUIdx_MUser);
 --
-.25.1
+.34.1

-[PULL 28/28] docs/system/arm/emulation.rst: Report FEAT_GTG support
+[PULL 15/21] docs/devel/kconfig.rst: Fix incorrect markup
-FEAT_GTG is a change tho the ID register ID_AA64MMFR0_EL1 so that it
+In rST markup syntax, the inline markup (*italics*, **bold** and
-can report a different set of supported granule (page) sizes for
+``monospaced``) must be separated from the surrending text by
-stage 1 and stage 2 translation tables.  As of commit c20281b2a5048
+non-word characters, otherwise it is not interpreted as markup.
-we already report the granule sizes that way for '-cpu max', and now
+To force interpretation as markup in the middle of a word,
-we also correctly make attempts to use unimplemented granule sizes
+you need to use a backslash-escaped space (which will not
-fail, so we can report the support of the feature in the
+appear as a space in the output).
 documentation.
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Fix a missing backslash-space in this file, which meant that the ``
 after "select" was output literally and the monospacing was
 incorrectly extended all the way to the end of the next monospaced
 word.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20221003162315.2833797-4-peter.maydell@linaro.org
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20230411105424.3994585-1-peter.maydell@linaro.org
 ---
- docs/system/arm/emulation.rst | 1 +
+ docs/devel/kconfig.rst | 2 +-
-file changed, 1 insertion(+)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
+diff --git a/docs/devel/kconfig.rst b/docs/devel/kconfig.rst
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
+--- a/docs/devel/kconfig.rst
-+++ b/docs/system/arm/emulation.rst
++++ b/docs/devel/kconfig.rst
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+@@ -XXX,XX +XXX,XX @@ or commenting out lines in the second group.
- - FEAT_FRINTTS (Floating-point to integer instructions)
- - FEAT_FlagM (Flag manipulation instructions v2)
+ It is also possible to run QEMU's configure script with the
- - FEAT_FlagM2 (Enhancements to flag manipulation instructions)
+ ``--without-default-devices`` option.  When this is done, everything defaults
-+- FEAT_GTG (Guest translation granule size)
+-to ``n`` unless it is ``select``ed or explicitly switched on in the
- - FEAT_HCX (Support for the HCRX_EL2 register)
++to ``n`` unless it is ``select``\ ed or explicitly switched on in the
- - FEAT_HPDS (Hierarchical permission disables)
+ ``.mak`` files.  In other words, ``default`` and ``imply`` directives
- - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
+ are disabled.  When QEMU is built with this option, the user will probably
  want to change some lines in the first group, for example like this::
 --
-.25.1
+.34.1

-[PULL 27/28] target/arm: Use ARMGranuleSize in ARMVAParameters
+[PULL 16/21] target/arm: Report pauth information to gdb as 'pauth_v2'
-Now we have an enum for the granule size, use it in the
+So that we can avoid the "older gdb crashes" problem described in
-ARMVAParameters struct instead of the using16k/using64k bools.
+commit 5787d17a42f7af4 and which caused us to disable reporting pauth
 information via the gdbstub, newer gdb is going to implement support
 for recognizing the pauth information via a new feature name:
  org.gnu.gdb.aarch64.pauth_v2
 Older gdb won't recognize this feature name, so we can re-enable the
 pauth support under the new name without risking them crashing.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20221003162315.2833797-3-peter.maydell@linaro.org
+Message-id: 20230406150827.3322670-1-peter.maydell@linaro.org
 ---
- target/arm/internals.h | 23 +++++++++++++++++++++--
+ target/arm/gdbstub.c      | 9 ++++-----
- target/arm/helper.c    | 39 ++++++++++++++++++++++++++++-----------
+ gdb-xml/aarch64-pauth.xml | 2 +-
- target/arm/ptw.c       |  8 +-------
+files changed, 5 insertions(+), 6 deletions(-)
 files changed, 50 insertions(+), 20 deletions(-)
-diff --git a/target/arm/internals.h b/target/arm/internals.h
+diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
+--- a/target/arm/gdbstub.c
-+++ b/target/arm/internals.h
++++ b/target/arm/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ typedef enum ARMGranuleSize {
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
-     GranInvalid,
+                                      aarch64_gdb_set_fpu_reg,
- } ARMGranuleSize;
+, "aarch64-fpu.xml", 0);
+         }
-+/**
+-#if 0
-+ * arm_granule_bits: Return address size of the granule in bits
+         /*
-+ *
+-         * GDB versions 9 through 12 have a bug which means they will
-+ * Return the address size of the granule in bits. This corresponds
+-         * crash if they see this XML from QEMU; disable it for the 8.0
-+ * to the pseudocode TGxGranuleBits().
+-         * release, pending a better solution.
-+ */
++         * Note that we report pauth information via the feature name
-+static inline int arm_granule_bits(ARMGranuleSize gran)
++         * org.gnu.gdb.aarch64.pauth_v2, not org.gnu.gdb.aarch64.pauth.
-+{
++         * GDB versions 9 through 12 have a bug where they will crash
-+    switch (gran) {
++         * if they see the latter XML from QEMU.
-+    case Gran64K:
+          */
-+        return 16;
+         if (isar_feature_aa64_pauth(&cpu->isar)) {
-+    case Gran16K:
+             gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg,
-+        return 14;
+                                      aarch64_gdb_set_pauth_reg,
-+    case Gran4K:
+, "aarch64-pauth.xml", 0);
-+        return 12;
+         }
-+    default:
+-#endif
-+        g_assert_not_reached();
+ #endif
-+    }
+     } else {
-+}
+         if (arm_feature(env, ARM_FEATURE_NEON)) {
-+
+diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml
  /*
   * Parameters of a given virtual address, as extracted from the
   * translation control register (TCR) for a given regime.
@@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters {
      bool tbi        : 1;
      bool epd        : 1;
      bool hpd        : 1;
 -    bool using16k   : 1;
 -    bool using64k   : 1;
      bool tsz_oob    : 1;  /* tsz has been clamped to legal range */
      bool ds         : 1;
 +    ARMGranuleSize gran : 2;
  } ARMVAParameters;
  ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/gdb-xml/aarch64-pauth.xml
-+++ b/target/arm/helper.c
++++ b/gdb-xml/aarch64-pauth.xml
-@@ -XXX,XX +XXX,XX @@ typedef struct {
+@@ -XXX,XX +XXX,XX @@
-     uint64_t length;
+      notice and this notice are preserved.  -->
- } TLBIRange;
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
-+static ARMGranuleSize tlbi_range_tg_to_gran_size(int tg)
+-<feature name="org.gnu.gdb.aarch64.pauth">
-+{
++<feature name="org.gnu.gdb.aarch64.pauth_v2">
-+    /*
+   <reg name="pauth_dmask" bitsize="64"/>
-+     * Note that the TLBI range TG field encoding differs from both
+   <reg name="pauth_cmask" bitsize="64"/>
-+     * TG0 and TG1 encodings.
+   <reg name="pauth_dmask_high" bitsize="64"/>
 +     */
 +    switch (tg) {
 +    case 1:
 +        return Gran4K;
 +    case 2:
 +        return Gran16K;
 +    case 3:
 +        return Gran64K;
 +    default:
 +        return GranInvalid;
 +    }
 +}
 +
  static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
                                       uint64_t value)
  {
@@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
      uint64_t select = sextract64(value, 36, 1);
      ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true);
      TLBIRange ret = { };
 +    ARMGranuleSize gran;
      page_size_granule = extract64(value, 46, 2);
 +    gran = tlbi_range_tg_to_gran_size(page_size_granule);
      /* The granule encoded in value must match the granule in use. */
 -    if (page_size_granule != (param.using64k ? 3 : param.using16k ? 2 : 1)) {
 +    if (gran != param.gran) {
          qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\n",
                        page_size_granule);
          return ret;
      }
 -    page_shift = (page_size_granule - 1) * 2 + 12;
 +    page_shift = arm_granule_bits(gran);
      num = extract64(value, 39, 5);
      scale = extract64(value, 44, 2);
      exponent = (5 * scale) + 1;
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
                                     ARMMMUIdx mmu_idx, bool data)
  {
      uint64_t tcr = regime_tcr(env, mmu_idx);
 -    bool epd, hpd, using16k, using64k, tsz_oob, ds;
 +    bool epd, hpd, tsz_oob, ds;
      int select, tsz, tbi, max_tsz, min_tsz, ps, sh;
      ARMGranuleSize gran;
      ARMCPU *cpu = env_archcpu(env);
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
      }
      gran = sanitize_gran_size(cpu, gran, stage2);
 -    using64k = gran == Gran64K;
 -    using16k = gran == Gran16K;
      if (cpu_isar_feature(aa64_st, cpu)) {
 -        max_tsz = 48 - using64k;
 +        max_tsz = 48 - (gran == Gran64K);
      } else {
          max_tsz = 39;
      }
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
       * adjust the effective value of DS, as documented.
       */
      min_tsz = 16;
 -    if (using64k) {
 +    if (gran == Gran64K) {
          if (cpu_isar_feature(aa64_lva, cpu)) {
              min_tsz = 12;
          }
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
          switch (mmu_idx) {
          case ARMMMUIdx_Stage2:
          case ARMMMUIdx_Stage2_S:
 -            if (using16k) {
 +            if (gran == Gran16K) {
                  ds = cpu_isar_feature(aa64_tgran16_2_lpa2, cpu);
              } else {
                  ds = cpu_isar_feature(aa64_tgran4_2_lpa2, cpu);
              }
              break;
          default:
 -            if (using16k) {
 +            if (gran == Gran16K) {
                  ds = cpu_isar_feature(aa64_tgran16_lpa2, cpu);
              } else {
                  ds = cpu_isar_feature(aa64_tgran4_lpa2, cpu);
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
          .tbi = tbi,
          .epd = epd,
          .hpd = hpd,
 -        .using16k = using16k,
 -        .using64k = using64k,
          .tsz_oob = tsz_oob,
          .ds = ds,
 +        .gran = gran,
      };
  }
 diff --git a/target/arm/ptw.c b/target/arm/ptw.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/ptw.c
 +++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
          }
      }
 -    if (param.using64k) {
 -        stride = 13;
 -    } else if (param.using16k) {
 -        stride = 11;
 -    } else {
 -        stride = 9;
 -    }
 +    stride = arm_granule_bits(param.gran) - 3;
      /*
       * Note that QEMU ignores shareability and cacheability attributes,
 --
-.25.1
+.34.1

-[PULL 11/28] target/arm: Add TBFLAG_M32.SECURE
+[PULL 17/21] hw/net/imx_fec: Support two Ethernet interfaces connected to single MDIO bus
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Guenter Roeck <linux@roeck-us.net>
-Remove the use of regime_is_secure from arm_tr_init_disas_context.
+The SOC on i.MX6UL and i.MX7 has 2 Ethernet interfaces. The PHY on each may
-Instead, provide the value of v8m_secure directly from tb_flags.
+be connected to separate MDIO busses, or both may be connected on the same
-Rather than use regime_is_secure, use the env->v7m.secure directly,
+MDIO bus using different PHY addresses. Commit 461c51ad4275 ("Add a phy-num
-as per arm_mmu_idx_el.
+property to the i.MX FEC emulator") added support for specifying PHY
 addresses, but it did not provide support for linking the second PHY on
 a given MDIO bus to the other Ethernet interface.
+To be able to support two PHY instances on a single MDIO bus, two properties
+are needed: First, there needs to be a flag indicating if the MDIO bus on
+a given Ethernet interface is connected. If not, attempts to read from this
+bus must always return 0xffff. Implement this property as phy-connected.
+Second, if the MDIO bus on an interface is active, it needs a link to the
+consumer interface to be able to provide PHY access for it. Implement this
+property as phy-consumer.
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Message-id: 20230315145248.1639364-2-linux@roeck-us.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20221001162318.153420-8-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h       | 2 ++
+ include/hw/net/imx_fec.h |  2 ++
- target/arm/helper.c    | 4 ++++
+ hw/net/imx_fec.c         | 27 +++++++++++++++++++++++----
- target/arm/translate.c | 3 +--
+files changed, 25 insertions(+), 4 deletions(-)
 files changed, 7 insertions(+), 2 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/include/hw/net/imx_fec.h
-+++ b/target/arm/cpu.h
++++ b/include/hw/net/imx_fec.h
-@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1)     /* Not cached. */
+@@ -XXX,XX +XXX,XX @@ struct IMXFECState {
- FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1)          /* Not cached. */
+     uint32_t phy_int;
- /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */
+     uint32_t phy_int_mask;
- FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1)            /* Not cached. */
+     uint32_t phy_num;
-+/* Set if in secure mode */
++    bool phy_connected;
-+FIELD(TBFLAG_M32, SECURE, 6, 1)
++    struct IMXFECState *phy_consumer;
- /*
+     bool is_fec;
-  * Bit usage when in AArch64 state
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/net/imx_fec.c
-+++ b/target/arm/helper.c
++++ b/hw/net/imx_fec.c
-@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
+@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
-         DP_TBFLAG_M32(flags, STACKCHECK, 1);
+     uint32_t val;
      uint32_t phy = reg / 32;
 -    if (phy != s->phy_num) {
 -        trace_imx_phy_read_num(phy, s->phy_num);
 +    if (!s->phy_connected) {
          return 0xffff;
      }
-+    if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) {
++    if (phy != s->phy_num) {
-+        DP_TBFLAG_M32(flags, SECURE, 1);
++        if (s->phy_consumer && phy == s->phy_consumer->phy_num) {
 +            s = s->phy_consumer;
 +        } else {
 +            trace_imx_phy_read_num(phy, s->phy_num);
 +            return 0xffff;
 +        }
 +    }
 +
-     return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
+     reg %= 32;
- }
+     switch (reg) {
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
-index XXXXXXX..XXXXXXX 100644
+ {
---- a/target/arm/translate.c
+     uint32_t phy = reg / 32;
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+-    if (phy != s->phy_num) {
-         dc->vfp_enabled = 1;
+-        trace_imx_phy_write_num(phy, s->phy_num);
-         dc->be_data = MO_TE;
++    if (!s->phy_connected) {
-         dc->v7m_handler_mode = EX_TBFLAG_M32(tb_flags, HANDLER);
+         return;
--        dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) &&
+     }
--            regime_is_secure(env, dc->mmu_idx);
-+        dc->v8m_secure = EX_TBFLAG_M32(tb_flags, SECURE);
++    if (phy != s->phy_num) {
-         dc->v8m_stackcheck = EX_TBFLAG_M32(tb_flags, STACKCHECK);
++        if (s->phy_consumer && phy == s->phy_consumer->phy_num) {
-         dc->v8m_fpccr_s_wrong = EX_TBFLAG_M32(tb_flags, FPCCR_S_WRONG);
++            s = s->phy_consumer;
-         dc->v7m_new_fp_ctxt_needed =
++        } else {
 +            trace_imx_phy_write_num(phy, s->phy_num);
 +            return;
 +        }
 +    }
 +
      reg %= 32;
      trace_imx_phy_write(val, phy, reg);
@@ -XXX,XX +XXX,XX @@ static Property imx_eth_properties[] = {
      DEFINE_NIC_PROPERTIES(IMXFECState, conf),
      DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1),
      DEFINE_PROP_UINT32("phy-num", IMXFECState, phy_num, 0),
 +    DEFINE_PROP_BOOL("phy-connected", IMXFECState, phy_connected, true),
 +    DEFINE_PROP_LINK("phy-consumer", IMXFECState, phy_consumer, TYPE_IMX_FEC,
 +                     IMXFECState *),
      DEFINE_PROP_END_OF_LIST(),
  };
 --
-.25.1
+.34.1

-[PULL 13/28] target/arm: Add is_secure parameter to do_ats_write
+[PULL 18/21] fsl-imx6ul: Add fec[12]-phy-connected properties
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Guenter Roeck <linux@roeck-us.net>
-Use get_phys_addr_with_secure directly.  For a-profile, this is the
+Add fec[12]-phy-connected properties and use it to set phy-connected
-one place where the value of is_secure may not equal arm_is_secure(env).
+and phy-consumer properties for imx_fec.
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Message-id: 20230315145248.1639364-3-linux@roeck-us.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20221001162318.153420-10-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 19 ++++++++++++++-----
+ include/hw/arm/fsl-imx6ul.h |  1 +
-file changed, 14 insertions(+), 5 deletions(-)
+ hw/arm/fsl-imx6ul.c         | 20 ++++++++++++++++++++
 files changed, 21 insertions(+)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/include/hw/arm/fsl-imx6ul.h
-+++ b/target/arm/helper.c
++++ b/include/hw/arm/fsl-imx6ul.h
-@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
+     MemoryRegion       ocram_alias;
- #ifdef CONFIG_TCG
- static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
+     uint32_t           phy_num[FSL_IMX6UL_NUM_ETHS];
--                             MMUAccessType access_type, ARMMMUIdx mmu_idx)
++    bool               phy_connected[FSL_IMX6UL_NUM_ETHS];
-+                             MMUAccessType access_type, ARMMMUIdx mmu_idx,
+ };
-+                             bool is_secure)
- {
+ enum FslIMX6ULMemoryMap {
-     bool ret;
+diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
-     uint64_t par64;
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
+--- a/hw/arm/fsl-imx6ul.c
-     ARMMMUFaultInfo fi = {};
++++ b/hw/arm/fsl-imx6ul.c
-     GetPhysAddrResult res = {};
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
 -    ret = get_phys_addr(env, value, access_type, mmu_idx, &res, &fi);
 +    ret = get_phys_addr_with_secure(env, value, access_type, mmu_idx,
 +                                    is_secure, &res, &fi);
      /*
-      * ATS operations only do S1 or S1+S2 translations, so we never
+      * Ethernet
-@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
++     *
-         switch (el) {
++     * We must use two loops since phy_connected affects the other interface
-         case 3:
++     * and we have to set all properties before calling sysbus_realize().
-             mmu_idx = ARMMMUIdx_SE3;
+      */
-+            secure = true;
++    for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
-             break;
++        object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected",
-         case 2:
++                                 s->phy_connected[i], &error_abort);
-             g_assert(!secure);  /* ARMv8.4-SecEL2 is 64-bit only */
++        /*
-@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
++         * If the MDIO bus on this controller is not connected, assume the
-         switch (el) {
++         * other controller provides support for it.
-         case 3:
++         */
-             mmu_idx = ARMMMUIdx_SE10_0;
++        if (!s->phy_connected[i]) {
-+            secure = true;
++            object_property_set_link(OBJECT(&s->eth[1 - i]), "phy-consumer",
-             break;
++                                     OBJECT(&s->eth[i]), &error_abort);
-         case 2:
++        }
-             g_assert(!secure);  /* ARMv8.4-SecEL2 is 64-bit only */
++    }
-@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
++
-     case 4:
+     for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
-         /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
+         static const hwaddr FSL_IMX6UL_ENETn_ADDR[FSL_IMX6UL_NUM_ETHS] = {
-         mmu_idx = ARMMMUIdx_E10_1;
+             FSL_IMX6UL_ENET1_ADDR,
-+        secure = false;
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
-         break;
+ static Property fsl_imx6ul_properties[] = {
-     case 6:
+     DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0),
-         /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
+     DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1),
-         mmu_idx = ARMMMUIdx_E10_0;
++    DEFINE_PROP_BOOL("fec1-phy-connected", FslIMX6ULState, phy_connected[0],
-+        secure = false;
++                     true),
-         break;
++    DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX6ULState, phy_connected[1],
-     default:
++                     true),
-         g_assert_not_reached();
+     DEFINE_PROP_END_OF_LIST(),
-     }
+ };
 -    par64 = do_ats_write(env, value, access_type, mmu_idx);
 +    par64 = do_ats_write(env, value, access_type, mmu_idx, secure);
      A32_BANKED_CURRENT_REG_SET(env, par, par64);
  #else
@@ -XXX,XX +XXX,XX @@ static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
      MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
      uint64_t par64;
 -    par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2);
 +    /* There is no SecureEL2 for AArch32. */
 +    par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2, false);
      A32_BANKED_CURRENT_REG_SET(env, par, par64);
  #else
@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
              break;
          case 6: /* AT S1E3R, AT S1E3W */
              mmu_idx = ARMMMUIdx_SE3;
 +            secure = true;
              break;
          default:
              g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
          g_assert_not_reached();
      }
 -    env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
 +    env->cp15.par_el[1] = do_ats_write(env, value, access_type,
 +                                       mmu_idx, secure);
  #else
      /* Handled by hardware accelerator. */
      g_assert_not_reached();
 --
-.25.1
+.34.1

-[PULL 25/28] hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3
+[PULL 19/21] arm/mcimx6ul-evk: Set fec1-phy-connected property to false
-From: Jerome Forissier <jerome.forissier@linaro.org>
+From: Guenter Roeck <linux@roeck-us.net>
-According to the Linux kernel booting.rst [1], CPTR_EL3.ESM and
+On mcimx6ul-evk, the MDIO bus is connected to the second Ethernet
-SCR_EL3.EnTP2 must be initialized to 1 when EL3 is present and FEAT_SME
+interface. Set fec1-phy-connected to false to reflect this.
 is advertised. This has to be taken care of when QEMU boots directly
 into the kernel (i.e., "-M virt,secure=on -cpu max -kernel Image").
-Cc: qemu-stable@nongnu.org
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Fixes: 78cb9776662a ("target/arm: Enable SME for -cpu max")
+Message-id: 20230315145248.1639364-4-linux@roeck-us.net
 Link: [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/arm64/booting.rst?h=v6.0#n321
 Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
 Message-id: 20221003145641.1921467-1-jerome.forissier@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/boot.c | 4 ++++
+ hw/arm/mcimx6ul-evk.c | 2 ++
-file changed, 4 insertions(+)
+file changed, 2 insertions(+)
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
+--- a/hw/arm/mcimx6ul-evk.c
-+++ b/hw/arm/boot.c
++++ b/hw/arm/mcimx6ul-evk.c
-@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
+@@ -XXX,XX +XXX,XX @@ static void mcimx6ul_evk_init(MachineState *machine)
-                     if (cpu_isar_feature(aa64_sve, cpu)) {
+     object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
-                         env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
+     object_property_set_uint(OBJECT(s), "fec1-phy-num", 2, &error_fatal);
-                     }
+     object_property_set_uint(OBJECT(s), "fec2-phy-num", 1, &error_fatal);
-+                    if (cpu_isar_feature(aa64_sme, cpu)) {
++    object_property_set_bool(OBJECT(s), "fec1-phy-connected", false,
-+                        env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
++                             &error_fatal);
-+                        env->cp15.scr_el3 |= SCR_ENTP2;
+     qdev_realize(DEVICE(s), NULL, &error_fatal);
-+                    }
-                     /* AArch64 kernels never boot in secure mode */
+     memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR,
                      assert(!info->secure_boot);
                      /* This hook is only supported for AArch32 currently:
 --
-.25.1
+.34.1

-[PULL 22/28] target/arm: Split out get_phys_addr_disabled
+[PULL 20/21] fsl-imx7: Add fec[12]-phy-connected properties
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Guenter Roeck <linux@roeck-us.net>
+Add fec[12]-phy-connected properties and use it to set phy-connected
+and phy-consumer properties for imx_fec.
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Message-id: 20230315145248.1639364-5-linux@roeck-us.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20221001162318.153420-19-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/ptw.c | 138 +++++++++++++++++++++++++----------------------
+ include/hw/arm/fsl-imx7.h |  1 +
-file changed, 74 insertions(+), 64 deletions(-)
+ hw/arm/fsl-imx7.c         | 20 ++++++++++++++++++++
 files changed, 21 insertions(+)
-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
+diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
+--- a/include/hw/arm/fsl-imx7.h
-+++ b/target/arm/ptw.c
++++ b/include/hw/arm/fsl-imx7.h
-@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
+@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
-     return ret;
+     ChipideaState      usb[FSL_IMX7_NUM_USBS];
- }
+     DesignwarePCIEHost pcie;
+     uint32_t           phy_num[FSL_IMX7_NUM_ETHS];
-+/*
++    bool               phy_connected[FSL_IMX7_NUM_ETHS];
-+ * MMU disabled.  S1 addresses within aa64 translation regimes are
+ };
-+ * still checked for bounds -- see AArch64.S1DisabledOutput().
-+ */
+ enum FslIMX7MemoryMap {
-+static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
+diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
-+                                   MMUAccessType access_type,
+index XXXXXXX..XXXXXXX 100644
-+                                   ARMMMUIdx mmu_idx, bool is_secure,
+--- a/hw/arm/fsl-imx7.c
-+                                   GetPhysAddrResult *result,
++++ b/hw/arm/fsl-imx7.c
-+                                   ARMMMUFaultInfo *fi)
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
-+{
-+    uint64_t hcr;
+     /*
-+    uint8_t memattr;
+      * Ethernet
-+
++     *
-+    if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) {
++     * We must use two loops since phy_connected affects the other interface
-+        int r_el = regime_el(env, mmu_idx);
++     * and we have to set all properties before calling sysbus_realize().
-+        if (arm_el_is_aa64(env, r_el)) {
+      */
-+            int pamax = arm_pamax(env_archcpu(env));
++    for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
-+            uint64_t tcr = env->cp15.tcr_el[r_el];
++        object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected",
-+            int addrtop, tbi;
++                                 s->phy_connected[i], &error_abort);
-+
++        /*
-+            tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
++         * If the MDIO bus on this controller is not connected, assume the
-+            if (access_type == MMU_INST_FETCH) {
++         * other controller provides support for it.
-+                tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
++         */
-+            }
++        if (!s->phy_connected[i]) {
-+            tbi = (tbi >> extract64(address, 55, 1)) & 1;
++            object_property_set_link(OBJECT(&s->eth[1 - i]), "phy-consumer",
-+            addrtop = (tbi ? 55 : 63);
++                                     OBJECT(&s->eth[i]), &error_abort);
 +
 +            if (extract64(address, pamax, addrtop - pamax + 1) != 0) {
 +                fi->type = ARMFault_AddressSize;
 +                fi->level = 0;
 +                fi->stage2 = false;
 +                return 1;
 +            }
 +
 +            /*
 +             * When TBI is disabled, we've just validated that all of the
 +             * bits above PAMax are zero, so logically we only need to
 +             * clear the top byte for TBI.  But it's clearer to follow
 +             * the pseudocode set of addrdesc.paddress.
 +             */
 +            address = extract64(address, 0, 52);
 +        }
 +    }
 +
-+    result->phys = address;
+     for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
-+    result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+         static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] = {
-+    result->page_size = TARGET_PAGE_SIZE;
+             FSL_IMX7_ENET1_ADDR,
-+
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
-+    /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
+ static Property fsl_imx7_properties[] = {
-+    hcr = arm_hcr_el2_eff_secstate(env, is_secure);
+     DEFINE_PROP_UINT32("fec1-phy-num", FslIMX7State, phy_num[0], 0),
-+    result->cacheattrs.shareability = 0;
+     DEFINE_PROP_UINT32("fec2-phy-num", FslIMX7State, phy_num[1], 1),
-+    result->cacheattrs.is_s2_format = false;
++    DEFINE_PROP_BOOL("fec1-phy-connected", FslIMX7State, phy_connected[0],
-+    if (hcr & HCR_DC) {
++                     true),
-+        if (hcr & HCR_DCT) {
++    DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX7State, phy_connected[1],
-+            memattr = 0xf0;  /* Tagged, Normal, WB, RWA */
++                     true),
-+        } else {
+     DEFINE_PROP_END_OF_LIST(),
-+            memattr = 0xff;  /* Normal, WB, RWA */
+ };
-+        }
 +    } else if (access_type == MMU_INST_FETCH) {
 +        if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
 +            memattr = 0xee;  /* Normal, WT, RA, NT */
 +        } else {
 +            memattr = 0x44;  /* Normal, NC, No */
 +        }
 +        result->cacheattrs.shareability = 2; /* outer sharable */
 +    } else {
 +        memattr = 0x00;      /* Device, nGnRnE */
 +    }
 +    result->cacheattrs.attrs = memattr;
 +    return 0;
 +}
 +
  bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
                                 MMUAccessType access_type, ARMMMUIdx mmu_idx,
                                 bool is_secure, GetPhysAddrResult *result,
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
      /* Definitely a real MMU, not an MPU */
      if (regime_translation_disabled(env, mmu_idx, is_secure)) {
 -        uint64_t hcr;
 -        uint8_t memattr;
 -
 -        /*
 -         * MMU disabled.  S1 addresses within aa64 translation regimes are
 -         * still checked for bounds -- see AArch64.TranslateAddressS1Off.
 -         */
 -        if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) {
 -            int r_el = regime_el(env, mmu_idx);
 -            if (arm_el_is_aa64(env, r_el)) {
 -                int pamax = arm_pamax(env_archcpu(env));
 -                uint64_t tcr = env->cp15.tcr_el[r_el];
 -                int addrtop, tbi;
 -
 -                tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
 -                if (access_type == MMU_INST_FETCH) {
 -                    tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
 -                }
 -                tbi = (tbi >> extract64(address, 55, 1)) & 1;
 -                addrtop = (tbi ? 55 : 63);
 -
 -                if (extract64(address, pamax, addrtop - pamax + 1) != 0) {
 -                    fi->type = ARMFault_AddressSize;
 -                    fi->level = 0;
 -                    fi->stage2 = false;
 -                    return 1;
 -                }
 -
 -                /*
 -                 * When TBI is disabled, we've just validated that all of the
 -                 * bits above PAMax are zero, so logically we only need to
 -                 * clear the top byte for TBI.  But it's clearer to follow
 -                 * the pseudocode set of addrdesc.paddress.
 -                 */
 -                address = extract64(address, 0, 52);
 -            }
 -        }
 -        result->phys = address;
 -        result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 -        result->page_size = TARGET_PAGE_SIZE;
 -
 -        /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
 -        hcr = arm_hcr_el2_eff_secstate(env, is_secure);
 -        result->cacheattrs.shareability = 0;
 -        result->cacheattrs.is_s2_format = false;
 -        if (hcr & HCR_DC) {
 -            if (hcr & HCR_DCT) {
 -                memattr = 0xf0;  /* Tagged, Normal, WB, RWA */
 -            } else {
 -                memattr = 0xff;  /* Normal, WB, RWA */
 -            }
 -        } else if (access_type == MMU_INST_FETCH) {
 -            if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
 -                memattr = 0xee;  /* Normal, WT, RA, NT */
 -            } else {
 -                memattr = 0x44;  /* Normal, NC, No */
 -            }
 -            result->cacheattrs.shareability = 2; /* outer sharable */
 -        } else {
 -            memattr = 0x00;      /* Device, nGnRnE */
 -        }
 -        result->cacheattrs.attrs = memattr;
 -        return 0;
 +        return get_phys_addr_disabled(env, address, access_type, mmu_idx,
 +                                      is_secure, result, fi);
      }
 -
      if (regime_using_lpae_format(env, mmu_idx)) {
          return get_phys_addr_lpae(env, address, access_type, mmu_idx,
                                    is_secure, false, result, fi);
 --
-.25.1
+.34.1

-[PULL 05/28] target/arm: Make the final stage1+2 write to secure be unconditional
+[PULL 21/21] arm/mcimx7d-sabre: Set fec2-phy-connected property to false
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Guenter Roeck <linux@roeck-us.net>
-While the stage2 call to get_phys_addr_lpae should never set
+On mcimx7d-sabre, the MDIO bus is connected to the first Ethernet
-attrs.secure when given a non-secure input, it's just as easy
+interface. Set fec2-phy-connected to false to reflect this.
 to make the final update to attrs.secure be unconditional and
 false in the case of non-secure input.
-Suggested-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230315145248.1639364-6-linux@roeck-us.net
 Message-id: 20221007152159.1414065-1-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/ptw.c | 21 ++++++++++-----------
+ hw/arm/mcimx7d-sabre.c | 2 ++
-file changed, 10 insertions(+), 11 deletions(-)
+file changed, 2 insertions(+)
-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
+diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
+--- a/hw/arm/mcimx7d-sabre.c
-+++ b/target/arm/ptw.c
++++ b/hw/arm/mcimx7d-sabre.c
-@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
+@@ -XXX,XX +XXX,XX @@ static void mcimx7d_sabre_init(MachineState *machine)
-             result->cacheattrs = combine_cacheattrs(env, cacheattrs1,
-                                                     result->cacheattrs);
+     s = FSL_IMX7(object_new(TYPE_FSL_IMX7));
+     object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
--            /* Check if IPA translates to secure or non-secure PA space. */
++    object_property_set_bool(OBJECT(s), "fec2-phy-connected", false,
--            if (is_secure) {
++                             &error_fatal);
--                if (ipa_secure) {
+     qdev_realize(DEVICE(s), NULL, &error_fatal);
--                    result->attrs.secure =
--                        !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW));
+     memory_region_add_subregion(get_system_memory(), FSL_IMX7_MMDC_ADDR,
 -                } else {
 -                    result->attrs.secure =
 -                        !((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))
 -                        || (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)));
 -                }
 -            }
 +            /*
 +             * Check if IPA translates to secure or non-secure PA space.
 +             * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
 +             */
 +            result->attrs.secure =
 +                (is_secure
 +                 && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
 +                 && (ipa_secure
 +                     || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))));
 +
              return 0;
          } else {
              /*
 --
-.25.1
+.34.1

-[PULL 07/28] target/arm: Fix S2 disabled check in S1_ptw_translate
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Pass the correct stage2 mmu_idx to regime_translation_disabled,
-which we computed afterward.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20221001162318.153420-4-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/ptw.c | 6 +++---
-file changed, 3 insertions(+), 3 deletions(-)
-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
-+++ b/target/arm/ptw.c
-@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
-                                hwaddr addr, bool *is_secure,
-                                ARMMMUFaultInfo *fi)
- {
-+    ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
-+
-     if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
--        !regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
--        ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S
--                                          : ARMMMUIdx_Stage2;
-+        !regime_translation_disabled(env, s2_mmu_idx)) {
-         GetPhysAddrResult s2 = {};
-         int ret;
---
-.25.1

-[PULL 15/28] target/arm: Reorg regime_translation_disabled
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Use a switch on mmu_idx for the a-profile indexes, instead of
-three different if's vs regime_el and arm_mmu_idx_is_stage1_of_2.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20221001162318.153420-12-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/ptw.c | 32 +++++++++++++++++++++++++-------
-file changed, 25 insertions(+), 7 deletions(-)
-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
-+++ b/target/arm/ptw.c
-@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
-     hcr_el2 = arm_hcr_el2_eff(env);
--    if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
-+    switch (mmu_idx) {
-+    case ARMMMUIdx_Stage2:
-+    case ARMMMUIdx_Stage2_S:
-         /* HCR.DC means HCR.VM behaves as 1 */
-         return (hcr_el2 & (HCR_DC | HCR_VM)) == 0;
--    }
--    if (hcr_el2 & HCR_TGE) {
-+    case ARMMMUIdx_E10_0:
-+    case ARMMMUIdx_E10_1:
-+    case ARMMMUIdx_E10_1_PAN:
-         /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
--        if (!is_secure && regime_el(env, mmu_idx) == 1) {
-+        if (!is_secure && (hcr_el2 & HCR_TGE)) {
-             return true;
-         }
--    }
-+        break;
--    if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) {
-+    case ARMMMUIdx_Stage1_E0:
-+    case ARMMMUIdx_Stage1_E1:
-+    case ARMMMUIdx_Stage1_E1_PAN:
-         /* HCR.DC means SCTLR_EL1.M behaves as 0 */
--        return true;
-+        if (hcr_el2 & HCR_DC) {
-+            return true;
-+        }
-+        break;
-+
-+    case ARMMMUIdx_E20_0:
-+    case ARMMMUIdx_E20_2:
-+    case ARMMMUIdx_E20_2_PAN:
-+    case ARMMMUIdx_E2:
-+    case ARMMMUIdx_E3:
-+        break;
-+
-+    default:
-+        g_assert_not_reached();
-     }
-     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
---
-.25.1

-[PULL 16/28] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-The effect of TGE does not only apply to non-secure state,
-now that Secure EL2 exists.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20221001162318.153420-13-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/ptw.c | 4 ++--
-file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
-+++ b/target/arm/ptw.c
-@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
-     case ARMMMUIdx_E10_0:
-     case ARMMMUIdx_E10_1:
-     case ARMMMUIdx_E10_1_PAN:
--        /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
--        if (!is_secure && (hcr_el2 & HCR_TGE)) {
-+        /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */
-+        if (hcr_el2 & HCR_TGE) {
-             return true;
-         }
-         break;
---
-.25.1

-[PULL 18/28] target/arm: Hoist read of *is_secure in S1_ptw_translate
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Rename the argument to is_secure_ptr, and introduce a
-local variable is_secure with the value.  We only write
-back to the pointer toward the end of the function.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20221001162318.153420-15-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/ptw.c | 22 ++++++++++++----------
-file changed, 12 insertions(+), 10 deletions(-)
-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
-+++ b/target/arm/ptw.c
-@@ -XXX,XX +XXX,XX @@ static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs)
- /* Translate a S1 pagetable walk through S2 if needed.  */
- static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
--                               hwaddr addr, bool *is_secure,
-+                               hwaddr addr, bool *is_secure_ptr,
-                                ARMMMUFaultInfo *fi)
- {
--    ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
-+    bool is_secure = *is_secure_ptr;
-+    ARMMMUIdx s2_mmu_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
-     if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
--        !regime_translation_disabled(env, s2_mmu_idx, *is_secure)) {
-+        !regime_translation_disabled(env, s2_mmu_idx, is_secure)) {
-         GetPhysAddrResult s2 = {};
-         int ret;
-         ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx,
--                                 *is_secure, false, &s2, fi);
-+                                 is_secure, false, &s2, fi);
-         if (ret) {
-             assert(fi->type != ARMFault_None);
-             fi->s2addr = addr;
-             fi->stage2 = true;
-             fi->s1ptw = true;
--            fi->s1ns = !*is_secure;
-+            fi->s1ns = !is_secure;
-             return ~0;
-         }
-         if ((arm_hcr_el2_eff(env) & HCR_PTW) &&
-@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
-             fi->s2addr = addr;
-             fi->stage2 = true;
-             fi->s1ptw = true;
--            fi->s1ns = !*is_secure;
-+            fi->s1ns = !is_secure;
-             return ~0;
-         }
-         if (arm_is_secure_below_el3(env)) {
-             /* Check if page table walk is to secure or non-secure PA space. */
--            if (*is_secure) {
--                *is_secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
-+            if (is_secure) {
-+                is_secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
-             } else {
--                *is_secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
-+                is_secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
-             }
-+            *is_secure_ptr = is_secure;
-         } else {
--            assert(!*is_secure);
-+            assert(!is_secure);
-         }
-         addr = s2.phys;
---
-.25.1

Hi; this is the latest target-arm queue; most of this is a refactoring
patchset from RTH for the arm page-table-walk emulation.

thanks
-- PMM

The following changes since commit f1d33f55c47dfdaf8daacd618588ad3ae4c452d1:

Merge tag 'pull-testing-gdbstub-plugins-gitdm-061022-3' of https://github.com/stsquad/qemu into staging (2022-10-06 07:11:56 -0400)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221010

for you to fetch changes up to 915f62844cf62e428c7c178149b5ff1cbe129b07:

docs/system/arm/emulation.rst: Report FEAT_GTG support (2022-10-10 14:52:25 +0100)

----------------------------------------------------------------
target-arm queue:
 * Retry KVM_CREATE_VM call if it fails EINTR
 * allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented
 * docs/nuvoton: Update URL for images
 * refactoring of page table walk code
 * hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3
 * Don't allow guest to use unimplemented granule sizes
 * Report FEAT_GTG support

----------------------------------------------------------------
Jerome Forissier (2):
      target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented
      hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3

Joel Stanley (1):
      docs/nuvoton: Update URL for images

Peter Maydell (4):
      target/arm/kvm: Retry KVM_CREATE_VM call if it fails EINTR
      target/arm: Don't allow guest to use unimplemented granule sizes
      target/arm: Use ARMGranuleSize in ARMVAParameters
      docs/system/arm/emulation.rst: Report FEAT_GTG support

Richard Henderson (21):
      target/arm: Split s2walk_secure from ipa_secure in get_phys_addr
      target/arm: Make the final stage1+2 write to secure be unconditional
      target/arm: Add is_secure parameter to get_phys_addr_lpae
      target/arm: Fix S2 disabled check in S1_ptw_translate
      target/arm: Add is_secure parameter to regime_translation_disabled
      target/arm: Split out get_phys_addr_with_secure
      target/arm: Add is_secure parameter to v7m_read_half_insn
      target/arm: Add TBFLAG_M32.SECURE
      target/arm: Merge regime_is_secure into get_phys_addr
      target/arm: Add is_secure parameter to do_ats_write
      target/arm: Fold secure and non-secure a-profile mmu indexes
      target/arm: Reorg regime_translation_disabled
      target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M
      target/arm: Introduce arm_hcr_el2_eff_secstate
      target/arm: Hoist read of *is_secure in S1_ptw_translate
      target/arm: Remove env argument from combined_attrs_fwb
      target/arm: Pass HCR to attribute subroutines.
      target/arm: Fix ATS12NSO* from S PL1
      target/arm: Split out get_phys_addr_disabled
      target/arm: Fix cacheattr in get_phys_addr_disabled
      target/arm: Use tlb_set_page_full

Occasionally the KVM_CREATE_VM ioctl can return EINTR, even though
there is no pending signal to be taken. In commit 94ccff13382055
we added a retry-on-EINTR loop to the KVM_CREATE_VM call in the
generic KVM code. Adopt the same approach for the use of the
ioctl in the Arm-specific KVM code (where we use it to create a
scratch VM for probing for various things).

For more information, see the mailing list thread:
https://lore.kernel.org/qemu-devel/8735e0s1zw.wl-maz@kernel.org/

Reported-by: Vitaly Chikunov <vt@altlinux.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Vitaly Chikunov <vt@altlinux.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Message-id: 20220930113824.1933293-1-peter.maydell@linaro.org
---
 target/arm/kvm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
     if (max_vm_pa_size < 0) {
         max_vm_pa_size = 0;
     }
-    vmfd = ioctl(kvmfd, KVM_CREATE_VM, max_vm_pa_size);
+    do {
+        vmfd = ioctl(kvmfd, KVM_CREATE_VM, max_vm_pa_size);
+    } while (vmfd == -1 && errno == EINTR);
     if (vmfd < 0) {
         goto err;
     }
-- 
2.25.1

From: Jerome Forissier <jerome.forissier@linaro.org>

Updates write_scr() to allow setting SCR_EL3.EnTP2 when FEAT_SME is
implemented. SCR_EL3 being a 64-bit register, valid_mask is changed
to uint64_t and the SCR_* constants in target/arm/cpu.h are extended
to 64-bit so that masking and bitwise not (~) behave as expected.

This enables booting Linux with Trusted Firmware-A at EL3 with
"-M virt,secure=on -cpu max".

Cc: qemu-stable@nongnu.org
Fixes: 78cb9776662a ("target/arm: Enable SME for -cpu max")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221004072354.27037-1-jerome.forissier@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h    | 54 ++++++++++++++++++++++-----------------------
 target/arm/helper.c |  5 ++++-
 2 files changed, 31 insertions(+), 28 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 
 #define HPFAR_NS      (1ULL << 63)
 
-#define SCR_NS                (1U << 0)
-#define SCR_IRQ               (1U << 1)
-#define SCR_FIQ               (1U << 2)
-#define SCR_EA                (1U << 3)
-#define SCR_FW                (1U << 4)
-#define SCR_AW                (1U << 5)
-#define SCR_NET               (1U << 6)
-#define SCR_SMD               (1U << 7)
-#define SCR_HCE               (1U << 8)
-#define SCR_SIF               (1U << 9)
-#define SCR_RW                (1U << 10)
-#define SCR_ST                (1U << 11)
-#define SCR_TWI               (1U << 12)
-#define SCR_TWE               (1U << 13)
-#define SCR_TLOR              (1U << 14)
-#define SCR_TERR              (1U << 15)
-#define SCR_APK               (1U << 16)
-#define SCR_API               (1U << 17)
-#define SCR_EEL2              (1U << 18)
-#define SCR_EASE              (1U << 19)
-#define SCR_NMEA              (1U << 20)
-#define SCR_FIEN              (1U << 21)
-#define SCR_ENSCXT            (1U << 25)
-#define SCR_ATA               (1U << 26)
-#define SCR_FGTEN             (1U << 27)
-#define SCR_ECVEN             (1U << 28)
-#define SCR_TWEDEN            (1U << 29)
+#define SCR_NS                (1ULL << 0)
+#define SCR_IRQ               (1ULL << 1)
+#define SCR_FIQ               (1ULL << 2)
+#define SCR_EA                (1ULL << 3)
+#define SCR_FW                (1ULL << 4)
+#define SCR_AW                (1ULL << 5)
+#define SCR_NET               (1ULL << 6)
+#define SCR_SMD               (1ULL << 7)
+#define SCR_HCE               (1ULL << 8)
+#define SCR_SIF               (1ULL << 9)
+#define SCR_RW                (1ULL << 10)
+#define SCR_ST                (1ULL << 11)
+#define SCR_TWI               (1ULL << 12)
+#define SCR_TWE               (1ULL << 13)
+#define SCR_TLOR              (1ULL << 14)
+#define SCR_TERR              (1ULL << 15)
+#define SCR_APK               (1ULL << 16)
+#define SCR_API               (1ULL << 17)
+#define SCR_EEL2              (1ULL << 18)
+#define SCR_EASE              (1ULL << 19)
+#define SCR_NMEA              (1ULL << 20)
+#define SCR_FIEN              (1ULL << 21)
+#define SCR_ENSCXT            (1ULL << 25)
+#define SCR_ATA               (1ULL << 26)
+#define SCR_FGTEN             (1ULL << 27)
+#define SCR_ECVEN             (1ULL << 28)
+#define SCR_TWEDEN            (1ULL << 29)
 #define SCR_TWEDEL            MAKE_64BIT_MASK(30, 4)
 #define SCR_TME               (1ULL << 34)
 #define SCR_AMVOFFEN          (1ULL << 35)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 {
     /* Begin with base v8.0 state.  */
-    uint32_t valid_mask = 0x3fff;
+    uint64_t valid_mask = 0x3fff;
     ARMCPU *cpu = env_archcpu(env);
 
     /*
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         if (cpu_isar_feature(aa64_doublefault, cpu)) {
             valid_mask |= SCR_EASE | SCR_NMEA;
         }
+        if (cpu_isar_feature(aa64_sme, cpu)) {
+            valid_mask |= SCR_ENTP2;
+        }
     } else {
         valid_mask &= ~(SCR_RW | SCR_ST);
         if (cpu_isar_feature(aa32_ras, cpu)) {
-- 
2.25.1

From: Joel Stanley <joel@jms.id.au>

openpower.xyz was retired some time ago. The OpenBMC Jenkins is where
images can be found these days.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20221004050042.22681-1-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/nuvoton.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@ Boot options
 
 The Nuvoton machines can boot from an OpenBMC firmware image, or directly into
 a kernel using the ``-kernel`` option. OpenBMC images for ``quanta-gsj`` and
-possibly others can be downloaded from the OpenPOWER jenkins :
+possibly others can be downloaded from the OpenBMC jenkins :
 
-   https://openpower.xyz/
+   https://jenkins.openbmc.org/
 
 The firmware image should be attached as an MTD drive. Example :
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

The starting security state comes with the translation regime,
not the current state of arm_is_secure_below_el3().

Create a new local variable, s2walk_secure, which does not need
to be written back to result->attrs.secure -- we compute that
value later, after the S2 walk is complete.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221001162318.153420-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
             hwaddr ipa;
             int s1_prot;
             int ret;
-            bool ipa_secure;
+            bool ipa_secure, s2walk_secure;
             ARMCacheAttrs cacheattrs1;
             ARMMMUIdx s2_mmu_idx;
             bool is_el0;
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
 
             ipa = result->phys;
             ipa_secure = result->attrs.secure;
-            if (arm_is_secure_below_el3(env)) {
-                if (ipa_secure) {
-                    result->attrs.secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
-                } else {
-                    result->attrs.secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
-                }
+            if (is_secure) {
+                /* Select TCR based on the NS bit from the S1 walk. */
+                s2walk_secure = !(ipa_secure
+                                  ? env->cp15.vstcr_el2 & VSTCR_SW
+                                  : env->cp15.vtcr_el2 & VTCR_NSW);
             } else {
                 assert(!ipa_secure);
+                s2walk_secure = false;
             }
 
-            s2_mmu_idx = (result->attrs.secure
+            s2_mmu_idx = (s2walk_secure
                           ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2);
             is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0;
 
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
                                                     result->cacheattrs);
 
             /* Check if IPA translates to secure or non-secure PA space. */
-            if (arm_is_secure_below_el3(env)) {
+            if (is_secure) {
                 if (ipa_secure) {
                     result->attrs.secure =
                         !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW));
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

While the stage2 call to get_phys_addr_lpae should never set
attrs.secure when given a non-secure input, it's just as easy
to make the final update to attrs.secure be unconditional and
false in the case of non-secure input.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221007152159.1414065-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
             result->cacheattrs = combine_cacheattrs(env, cacheattrs1,
                                                     result->cacheattrs);
 
-            /* Check if IPA translates to secure or non-secure PA space. */
-            if (is_secure) {
-                if (ipa_secure) {
-                    result->attrs.secure =
-                        !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW));
-                } else {
-                    result->attrs.secure =
-                        !((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))
-                        || (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)));
-                }
-            }
+            /*
+             * Check if IPA translates to secure or non-secure PA space.
+             * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
+             */
+            result->attrs.secure =
+                (is_secure
+                 && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
+                 && (ipa_secure
+                     || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))));
+
             return 0;
         } else {
             /*
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Remove the use of regime_is_secure from get_phys_addr_lpae,
using the new parameter instead.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@
 
 static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
-                               bool s1_is_el0, GetPhysAddrResult *result,
-                               ARMMMUFaultInfo *fi)
+                               bool is_secure, bool s1_is_el0,
+                               GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
     __attribute__((nonnull));
 
 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
         GetPhysAddrResult s2 = {};
         int ret;
 
-        ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false,
-                                 &s2, fi);
+        ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx,
+                                 *is_secure, false, &s2, fi);
         if (ret) {
             assert(fi->type != ARMFault_None);
             fi->s2addr = addr;
@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
  */
 static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
-                               bool s1_is_el0, GetPhysAddrResult *result,
-                               ARMMMUFaultInfo *fi)
+                               bool is_secure, bool s1_is_el0,
+                               GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
 {
     ARMCPU *cpu = env_archcpu(env);
     /* Read an LPAE long-descriptor translation table. */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
      * remain non-secure. We implement this by just ORing in the NSTable/NS
      * bits at each step.
      */
-    tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
+    tableattrs = is_secure ? 0 : (1 << 4);
     for (;;) {
         uint64_t descriptor;
         bool nstable;
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
             memset(result, 0, sizeof(*result));
 
             ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx,
-                                     is_el0, result, fi);
+                                     s2walk_secure, is_el0, result, fi);
             fi->s2addr = ipa;
 
             /* Combine the S1 and S2 perms.  */
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
     }
 
     if (regime_using_lpae_format(env, mmu_idx)) {
-        return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
-                                  result, fi);
+        return get_phys_addr_lpae(env, address, access_type, mmu_idx,
+                                  is_secure, false, result, fi);
     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
         return get_phys_addr_v6(env, address, access_type, mmu_idx,
                                 is_secure, result, fi);
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Pass the correct stage2 mmu_idx to regime_translation_disabled,
which we computed afterward.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221001162318.153420-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
                                hwaddr addr, bool *is_secure,
                                ARMMMUFaultInfo *fi)
 {
+    ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
+
     if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
-        !regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
-        ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S
-                                          : ARMMMUIdx_Stage2;
+        !regime_translation_disabled(env, s2_mmu_idx)) {
         GetPhysAddrResult s2 = {};
         int ret;
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Remove the use of regime_is_secure from regime_translation_disabled,
using the new parameter instead.

This fixes a bug in S1_ptw_translate and get_phys_addr where we had
passed ARMMMUIdx_Stage2 and not ARMMMUIdx_Stage2_S to determine if
Stage2 is disabled, affecting FEAT_SEL2.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn)
 }
 
 /* Return true if the specified stage of address translation is disabled */
-static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx)
+static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
+                                        bool is_secure)
 {
     uint64_t hcr_el2;
 
     if (arm_feature(env, ARM_FEATURE_M)) {
-        switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] &
+        switch (env->v7m.mpu_ctrl[is_secure] &
                 (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
         case R_V7M_MPU_CTRL_ENABLE_MASK:
             /* Enabled, but not for HardFault and NMI */
@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx)
 
     if (hcr_el2 & HCR_TGE) {
         /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
-        if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) {
+        if (!is_secure && regime_el(env, mmu_idx) == 1) {
             return true;
         }
     }
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
     ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
 
     if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
-        !regime_translation_disabled(env, s2_mmu_idx)) {
+        !regime_translation_disabled(env, s2_mmu_idx, *is_secure)) {
         GetPhysAddrResult s2 = {};
         int ret;
 
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
     uint32_t base;
     bool is_user = regime_is_user(env, mmu_idx);
 
-    if (regime_translation_disabled(env, mmu_idx)) {
+    if (regime_translation_disabled(env, mmu_idx, is_secure)) {
         /* MPU disabled.  */
         result->phys = address;
         result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
     result->page_size = TARGET_PAGE_SIZE;
     result->prot = 0;
 
-    if (regime_translation_disabled(env, mmu_idx) ||
+    if (regime_translation_disabled(env, mmu_idx, secure) ||
         m_is_ppb_region(env, address)) {
         /*
          * MPU disabled or M profile PPB access: use default memory map.
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
      * are done in arm_v7m_load_vector(), which always does a direct
      * read using address_space_ldl(), rather than going via this function.
      */
-    if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
+    if (regime_translation_disabled(env, mmu_idx, secure)) { /* MPU disabled */
         hit = true;
     } else if (m_is_ppb_region(env, address)) {
         hit = true;
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
                                 result, fi);
 
             /* If S1 fails or S2 is disabled, return early.  */
-            if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
+            if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2,
+                                                   is_secure)) {
                 return ret;
             }
 
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
 
     /* Definitely a real MMU, not an MPU */
 
-    if (regime_translation_disabled(env, mmu_idx)) {
+    if (regime_translation_disabled(env, mmu_idx, is_secure)) {
         uint64_t hcr;
         uint8_t memattr;
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Retain the existing get_phys_addr interface using the security
state derived from mmu_idx.  Move the kerneldoc comments to the
header file where they belong.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h | 40 ++++++++++++++++++++++++++++++++++++++
 target/arm/ptw.c       | 44 ++++++++++++++----------------------------
 2 files changed, 55 insertions(+), 29 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ typedef struct GetPhysAddrResult {
     ARMCacheAttrs cacheattrs;
 } GetPhysAddrResult;
 
+/**
+ * get_phys_addr_with_secure: get the physical address for a virtual address
+ * @env: CPUARMState
+ * @address: virtual address to get physical address for
+ * @access_type: 0 for read, 1 for write, 2 for execute
+ * @mmu_idx: MMU index indicating required translation regime
+ * @is_secure: security state for the access
+ * @result: set on translation success.
+ * @fi: set to fault info if the translation fails
+ *
+ * Find the physical address corresponding to the given virtual address,
+ * by doing a translation table walk on MMU based systems or using the
+ * MPU state on MPU based systems.
+ *
+ * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
+ * prot and page_size may not be filled in, and the populated fsr value provides
+ * information on why the translation aborted, in the format of a
+ * DFSR/IFSR fault register, with the following caveats:
+ *  * we honour the short vs long DFSR format differences.
+ *  * the WnR bit is never set (the caller must do this).
+ *  * for PSMAv5 based systems we don't bother to return a full FSR format
+ *    value.
+ */
+bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
+                               MMUAccessType access_type,
+                               ARMMMUIdx mmu_idx, bool is_secure,
+                               GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
+    __attribute__((nonnull));
+
+/**
+ * get_phys_addr: get the physical address for a virtual address
+ * @env: CPUARMState
+ * @address: virtual address to get physical address for
+ * @access_type: 0 for read, 1 for write, 2 for execute
+ * @mmu_idx: MMU index indicating required translation regime
+ * @result: set on translation success.
+ * @fi: set to fault info if the translation fails
+ *
+ * Similarly, but use the security regime of @mmu_idx.
+ */
 bool get_phys_addr(CPUARMState *env, target_ulong address,
                    MMUAccessType access_type, ARMMMUIdx mmu_idx,
                    GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
     return ret;
 }
 
-/**
- * get_phys_addr - get the physical address for this virtual address
- *
- * Find the physical address corresponding to the given virtual address,
- * by doing a translation table walk on MMU based systems or using the
- * MPU state on MPU based systems.
- *
- * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
- * prot and page_size may not be filled in, and the populated fsr value provides
- * information on why the translation aborted, in the format of a
- * DFSR/IFSR fault register, with the following caveats:
- *  * we honour the short vs long DFSR format differences.
- *  * the WnR bit is never set (the caller must do this).
- *  * for PSMAv5 based systems we don't bother to return a full FSR format
- *    value.
- *
- * @env: CPUARMState
- * @address: virtual address to get physical address for
- * @access_type: 0 for read, 1 for write, 2 for execute
- * @mmu_idx: MMU index indicating required translation regime
- * @result: set on translation success.
- * @fi: set to fault info if the translation fails
- */
-bool get_phys_addr(CPUARMState *env, target_ulong address,
-                   MMUAccessType access_type, ARMMMUIdx mmu_idx,
-                   GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
+bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
+                               MMUAccessType access_type, ARMMMUIdx mmu_idx,
+                               bool is_secure, GetPhysAddrResult *result,
+                               ARMMMUFaultInfo *fi)
 {
     ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
-    bool is_secure = regime_is_secure(env, mmu_idx);
 
     if (mmu_idx != s1_mmu_idx) {
         /*
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
             ARMMMUIdx s2_mmu_idx;
             bool is_el0;
 
-            ret = get_phys_addr(env, address, access_type, s1_mmu_idx,
-                                result, fi);
+            ret = get_phys_addr_with_secure(env, address, access_type,
+                                            s1_mmu_idx, is_secure, result, fi);
 
             /* If S1 fails or S2 is disabled, return early.  */
             if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2,
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
     }
 }
 
+bool get_phys_addr(CPUARMState *env, target_ulong address,
+                   MMUAccessType access_type, ARMMMUIdx mmu_idx,
+                   GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
+{
+    return get_phys_addr_with_secure(env, address, access_type, mmu_idx,
+                                     regime_is_secure(env, mmu_idx),
+                                     result, fi);
+}
+
 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
                                          MemTxAttrs *attrs)
 {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Remove the use of regime_is_secure from v7m_read_half_insn, using
the new parameter instead.

As it happens, both callers pass true, propagated from the argument
to arm_v7m_mmu_idx_for_secstate which created the mmu_idx argument,
but that is a detail of v7m_handle_execute_nsc we need not expose
to the callee.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/m_helper.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
     return true;
 }
 
-static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
+static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure,
                                uint32_t addr, uint16_t *insn)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
     ARMMMUFaultInfo fi = {};
     MemTxResult txres;
 
-    v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx,
-                        regime_is_secure(env, mmu_idx), &sattrs);
+    v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, secure, &sattrs);
     if (!sattrs.nsc || sattrs.ns) {
         /*
          * This must be the second half of the insn, and it straddles a
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
     /* We want to do the MPU lookup as secure; work out what mmu_idx that is */
     mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
 
-    if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) {
+    if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15], &insn)) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
         goto gen_invep;
     }
 
-    if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) {
+    if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15] + 2, &insn)) {
         return false;
     }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Remove the use of regime_is_secure from arm_tr_init_disas_context.
Instead, provide the value of v8m_secure directly from tb_flags.
Rather than use regime_is_secure, use the env->v7m.secure directly,
as per arm_mmu_idx_el.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h       | 2 ++
 target/arm/helper.c    | 4 ++++
 target/arm/translate.c | 3 +--
 3 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1)     /* Not cached. */
 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1)          /* Not cached. */
 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */
 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1)            /* Not cached. */
+/* Set if in secure mode */
+FIELD(TBFLAG_M32, SECURE, 6, 1)
 
 /*
  * Bit usage when in AArch64 state
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
         DP_TBFLAG_M32(flags, STACKCHECK, 1);
     }
 
+    if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) {
+        DP_TBFLAG_M32(flags, SECURE, 1);
+    }
+
     return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
 }
 
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
         dc->vfp_enabled = 1;
         dc->be_data = MO_TE;
         dc->v7m_handler_mode = EX_TBFLAG_M32(tb_flags, HANDLER);
-        dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) &&
-            regime_is_secure(env, dc->mmu_idx);
+        dc->v8m_secure = EX_TBFLAG_M32(tb_flags, SECURE);
         dc->v8m_stackcheck = EX_TBFLAG_M32(tb_flags, STACKCHECK);
         dc->v8m_fpccr_s_wrong = EX_TBFLAG_M32(tb_flags, FPCCR_S_WRONG);
         dc->v7m_new_fp_ctxt_needed =
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This is the last use of regime_is_secure; remove it
entirely before changing the layout of ARMMMUIdx.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h | 42 ----------------------------------------
 target/arm/ptw.c       | 44 ++++++++++++++++++++++++++++++++++++++++--
 2 files changed, 42 insertions(+), 44 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx)
     }
 }
 
-/* Return true if this address translation regime is secure */
-static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
-{
-    switch (mmu_idx) {
-    case ARMMMUIdx_E10_0:
-    case ARMMMUIdx_E10_1:
-    case ARMMMUIdx_E10_1_PAN:
-    case ARMMMUIdx_E20_0:
-    case ARMMMUIdx_E20_2:
-    case ARMMMUIdx_E20_2_PAN:
-    case ARMMMUIdx_Stage1_E0:
-    case ARMMMUIdx_Stage1_E1:
-    case ARMMMUIdx_Stage1_E1_PAN:
-    case ARMMMUIdx_E2:
-    case ARMMMUIdx_Stage2:
-    case ARMMMUIdx_MPrivNegPri:
-    case ARMMMUIdx_MUserNegPri:
-    case ARMMMUIdx_MPriv:
-    case ARMMMUIdx_MUser:
-        return false;
-    case ARMMMUIdx_SE3:
-    case ARMMMUIdx_SE10_0:
-    case ARMMMUIdx_SE10_1:
-    case ARMMMUIdx_SE10_1_PAN:
-    case ARMMMUIdx_SE20_0:
-    case ARMMMUIdx_SE20_2:
-    case ARMMMUIdx_SE20_2_PAN:
-    case ARMMMUIdx_Stage1_SE0:
-    case ARMMMUIdx_Stage1_SE1:
-    case ARMMMUIdx_Stage1_SE1_PAN:
-    case ARMMMUIdx_SE2:
-    case ARMMMUIdx_Stage2_S:
-    case ARMMMUIdx_MSPrivNegPri:
-    case ARMMMUIdx_MSUserNegPri:
-    case ARMMMUIdx_MSPriv:
-    case ARMMMUIdx_MSUser:
-        return true;
-    default:
-        g_assert_not_reached();
-    }
-}
-
 static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx)
 {
     switch (mmu_idx) {
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
                    MMUAccessType access_type, ARMMMUIdx mmu_idx,
                    GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
 {
+    bool is_secure;
+
+    switch (mmu_idx) {
+    case ARMMMUIdx_E10_0:
+    case ARMMMUIdx_E10_1:
+    case ARMMMUIdx_E10_1_PAN:
+    case ARMMMUIdx_E20_0:
+    case ARMMMUIdx_E20_2:
+    case ARMMMUIdx_E20_2_PAN:
+    case ARMMMUIdx_Stage1_E0:
+    case ARMMMUIdx_Stage1_E1:
+    case ARMMMUIdx_Stage1_E1_PAN:
+    case ARMMMUIdx_E2:
+    case ARMMMUIdx_Stage2:
+    case ARMMMUIdx_MPrivNegPri:
+    case ARMMMUIdx_MUserNegPri:
+    case ARMMMUIdx_MPriv:
+    case ARMMMUIdx_MUser:
+        is_secure = false;
+        break;
+    case ARMMMUIdx_SE3:
+    case ARMMMUIdx_SE10_0:
+    case ARMMMUIdx_SE10_1:
+    case ARMMMUIdx_SE10_1_PAN:
+    case ARMMMUIdx_SE20_0:
+    case ARMMMUIdx_SE20_2:
+    case ARMMMUIdx_SE20_2_PAN:
+    case ARMMMUIdx_Stage1_SE0:
+    case ARMMMUIdx_Stage1_SE1:
+    case ARMMMUIdx_Stage1_SE1_PAN:
+    case ARMMMUIdx_SE2:
+    case ARMMMUIdx_Stage2_S:
+    case ARMMMUIdx_MSPrivNegPri:
+    case ARMMMUIdx_MSUserNegPri:
+    case ARMMMUIdx_MSPriv:
+    case ARMMMUIdx_MSUser:
+        is_secure = true;
+        break;
+    default:
+        g_assert_not_reached();
+    }
     return get_phys_addr_with_secure(env, address, access_type, mmu_idx,
-                                     regime_is_secure(env, mmu_idx),
-                                     result, fi);
+                                     is_secure, result, fi);
 }
 
 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Use get_phys_addr_with_secure directly.  For a-profile, this is the
one place where the value of is_secure may not equal arm_is_secure(env).

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
 
 #ifdef CONFIG_TCG
 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
-                             MMUAccessType access_type, ARMMMUIdx mmu_idx)
+                             MMUAccessType access_type, ARMMMUIdx mmu_idx,
+                             bool is_secure)
 {
     bool ret;
     uint64_t par64;
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
     ARMMMUFaultInfo fi = {};
     GetPhysAddrResult res = {};
 
-    ret = get_phys_addr(env, value, access_type, mmu_idx, &res, &fi);
+    ret = get_phys_addr_with_secure(env, value, access_type, mmu_idx,
+                                    is_secure, &res, &fi);
 
     /*
      * ATS operations only do S1 or S1+S2 translations, so we never
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         switch (el) {
         case 3:
             mmu_idx = ARMMMUIdx_SE3;
+            secure = true;
             break;
         case 2:
             g_assert(!secure);  /* ARMv8.4-SecEL2 is 64-bit only */
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         switch (el) {
         case 3:
             mmu_idx = ARMMMUIdx_SE10_0;
+            secure = true;
             break;
         case 2:
             g_assert(!secure);  /* ARMv8.4-SecEL2 is 64-bit only */
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
     case 4:
         /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
         mmu_idx = ARMMMUIdx_E10_1;
+        secure = false;
         break;
     case 6:
         /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
         mmu_idx = ARMMMUIdx_E10_0;
+        secure = false;
         break;
     default:
         g_assert_not_reached();
     }
 
-    par64 = do_ats_write(env, value, access_type, mmu_idx);
+    par64 = do_ats_write(env, value, access_type, mmu_idx, secure);
 
     A32_BANKED_CURRENT_REG_SET(env, par, par64);
 #else
@@ -XXX,XX +XXX,XX @@ static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
     MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
     uint64_t par64;
 
-    par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2);
+    /* There is no SecureEL2 for AArch32. */
+    par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2, false);
 
     A32_BANKED_CURRENT_REG_SET(env, par, par64);
 #else
@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
             break;
         case 6: /* AT S1E3R, AT S1E3W */
             mmu_idx = ARMMMUIdx_SE3;
+            secure = true;
             break;
         default:
             g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
         g_assert_not_reached();
     }
 
-    env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
+    env->cp15.par_el[1] = do_ats_write(env, value, access_type,
+                                       mmu_idx, secure);
 #else
     /* Handled by hardware accelerator. */
     g_assert_not_reached();
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

For a-profile aarch64, which does not bank system registers, it takes
quite a lot of code to switch between security states.  In the process,
registers such as TCR_EL{1,2} must be swapped, which in itself requires
the flushing of softmmu tlbs.  Therefore it doesn't buy us anything to
separate tlbs by security state.

Retain the distinction between Stage2 and Stage2_S.

This will be important as we implement FEAT_RME, and do not wish to
add a third set of mmu indexes for Realm state.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu-param.h     |   2 +-
 target/arm/cpu.h           |  72 +++++++------------
 target/arm/internals.h     |  31 +-------
 target/arm/helper.c        | 144 +++++++++++++------------------------
 target/arm/ptw.c           |  25 ++-----
 target/arm/translate-a64.c |   8 ---
 target/arm/translate.c     |   6 +-
 7 files changed, 85 insertions(+), 203 deletions(-)

diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -XXX,XX +XXX,XX @@
 # define TARGET_PAGE_BITS_MIN  10
 #endif
 
-#define NB_MMU_MODES 15
+#define NB_MMU_MODES 8
 
 #endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
  *     table over and over.
  *  6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
  *     Never (PAN) bit within PSTATE.
+ *  7. we fold together the secure and non-secure regimes for A-profile,
+ *     because there are no banked system registers for aarch64, so the
+ *     process of switching between secure and non-secure is
+ *     already heavyweight.
  *
  * This gives us the following list of cases:
  *
- * NS EL0 EL1&0 stage 1+2 (aka NS PL0)
- * NS EL1 EL1&0 stage 1+2 (aka NS PL1)
- * NS EL1 EL1&0 stage 1+2 +PAN
- * NS EL0 EL2&0
- * NS EL2 EL2&0
- * NS EL2 EL2&0 +PAN
- * NS EL2 (aka NS PL2)
- * S EL0 EL1&0 (aka S PL0)
- * S EL1 EL1&0 (not used if EL3 is 32 bit)
- * S EL1 EL1&0 +PAN
- * S EL3 (aka S PL1)
+ * EL0 EL1&0 stage 1+2 (aka NS PL0)
+ * EL1 EL1&0 stage 1+2 (aka NS PL1)
+ * EL1 EL1&0 stage 1+2 +PAN
+ * EL0 EL2&0
+ * EL2 EL2&0
+ * EL2 EL2&0 +PAN
+ * EL2 (aka NS PL2)
+ * EL3 (aka S PL1)
  *
- * for a total of 11 different mmu_idx.
+ * for a total of 8 different mmu_idx.
  *
  * R profile CPUs have an MPU, but can use the same set of MMU indexes
- * as A profile. They only need to distinguish NS EL0 and NS EL1 (and
- * NS EL2 if we ever model a Cortex-R52).
+ * as A profile. They only need to distinguish EL0 and EL1 (and
+ * EL2 if we ever model a Cortex-R52).
  *
  * M profile CPUs are rather different as they do not have a true MMU.
  * They have the following different MMU indexes:
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
 #define ARM_MMU_IDX_NOTLB 0x20  /* does not have a TLB */
 #define ARM_MMU_IDX_M     0x40  /* M profile */
 
-/* Meanings of the bits for A profile mmu idx values */
-#define ARM_MMU_IDX_A_NS     0x8
-
 /* Meanings of the bits for M profile mmu idx values */
 #define ARM_MMU_IDX_M_PRIV   0x1
 #define ARM_MMU_IDX_M_NEGPRI 0x2
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
     /*
      * A-profile.
      */
-    ARMMMUIdx_SE10_0     =  0 | ARM_MMU_IDX_A,
-    ARMMMUIdx_SE20_0     =  1 | ARM_MMU_IDX_A,
-    ARMMMUIdx_SE10_1     =  2 | ARM_MMU_IDX_A,
-    ARMMMUIdx_SE20_2     =  3 | ARM_MMU_IDX_A,
-    ARMMMUIdx_SE10_1_PAN =  4 | ARM_MMU_IDX_A,
-    ARMMMUIdx_SE20_2_PAN =  5 | ARM_MMU_IDX_A,
-    ARMMMUIdx_SE2        =  6 | ARM_MMU_IDX_A,
-    ARMMMUIdx_SE3        =  7 | ARM_MMU_IDX_A,
-
-    ARMMMUIdx_E10_0     = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS,
-    ARMMMUIdx_E20_0     = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS,
-    ARMMMUIdx_E10_1     = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS,
-    ARMMMUIdx_E20_2     = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS,
-    ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS,
-    ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS,
-    ARMMMUIdx_E2        = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS,
+    ARMMMUIdx_E10_0     = 0 | ARM_MMU_IDX_A,
+    ARMMMUIdx_E20_0     = 1 | ARM_MMU_IDX_A,
+    ARMMMUIdx_E10_1     = 2 | ARM_MMU_IDX_A,
+    ARMMMUIdx_E20_2     = 3 | ARM_MMU_IDX_A,
+    ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A,
+    ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A,
+    ARMMMUIdx_E2        = 6 | ARM_MMU_IDX_A,
+    ARMMMUIdx_E3        = 7 | ARM_MMU_IDX_A,
 
     /*
      * These are not allocated TLBs and are used only for AT system
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
     ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
     ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
     ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
-    ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB,
-    ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB,
-    ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB,
     /*
      * Not allocated a TLB: used only for second stage of an S12 page
      * table walk, or for descriptor loads during first stage of an S1
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
      * then various TLB flush insns which currently are no-ops or flush
      * only stage 1 MMU indexes will need to change to flush stage 2.
      */
-    ARMMMUIdx_Stage2     = 6 | ARM_MMU_IDX_NOTLB,
-    ARMMMUIdx_Stage2_S   = 7 | ARM_MMU_IDX_NOTLB,
+    ARMMMUIdx_Stage2     = 3 | ARM_MMU_IDX_NOTLB,
+    ARMMMUIdx_Stage2_S   = 4 | ARM_MMU_IDX_NOTLB,
 
     /*
      * M-profile.
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit {
     TO_CORE_BIT(E2),
     TO_CORE_BIT(E20_2),
     TO_CORE_BIT(E20_2_PAN),
-    TO_CORE_BIT(SE10_0),
-    TO_CORE_BIT(SE20_0),
-    TO_CORE_BIT(SE10_1),
-    TO_CORE_BIT(SE20_2),
-    TO_CORE_BIT(SE10_1_PAN),
-    TO_CORE_BIT(SE20_2_PAN),
-    TO_CORE_BIT(SE2),
-    TO_CORE_BIT(SE3),
+    TO_CORE_BIT(E3),
 
     TO_CORE_BIT(MUser),
     TO_CORE_BIT(MPriv),
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx)
     case ARMMMUIdx_Stage1_E0:
     case ARMMMUIdx_Stage1_E1:
     case ARMMMUIdx_Stage1_E1_PAN:
-    case ARMMMUIdx_Stage1_SE0:
-    case ARMMMUIdx_Stage1_SE1:
-    case ARMMMUIdx_Stage1_SE1_PAN:
     case ARMMMUIdx_E10_0:
     case ARMMMUIdx_E10_1:
     case ARMMMUIdx_E10_1_PAN:
     case ARMMMUIdx_E20_0:
     case ARMMMUIdx_E20_2:
     case ARMMMUIdx_E20_2_PAN:
-    case ARMMMUIdx_SE10_0:
-    case ARMMMUIdx_SE10_1:
-    case ARMMMUIdx_SE10_1_PAN:
-    case ARMMMUIdx_SE20_0:
-    case ARMMMUIdx_SE20_2:
-    case ARMMMUIdx_SE20_2_PAN:
         return true;
     default:
         return false;
@@ -XXX,XX +XXX,XX @@ static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx)
 {
     switch (mmu_idx) {
     case ARMMMUIdx_Stage1_E1_PAN:
-    case ARMMMUIdx_Stage1_SE1_PAN:
     case ARMMMUIdx_E10_1_PAN:
     case ARMMMUIdx_E20_2_PAN:
-    case ARMMMUIdx_SE10_1_PAN:
-    case ARMMMUIdx_SE20_2_PAN:
         return true;
     default:
         return false;
@@ -XXX,XX +XXX,XX @@ static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx)
 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
 {
     switch (mmu_idx) {
-    case ARMMMUIdx_SE20_0:
-    case ARMMMUIdx_SE20_2:
-    case ARMMMUIdx_SE20_2_PAN:
     case ARMMMUIdx_E20_0:
     case ARMMMUIdx_E20_2:
     case ARMMMUIdx_E20_2_PAN:
     case ARMMMUIdx_Stage2:
     case ARMMMUIdx_Stage2_S:
-    case ARMMMUIdx_SE2:
     case ARMMMUIdx_E2:
         return 2;
-    case ARMMMUIdx_SE3:
+    case ARMMMUIdx_E3:
         return 3;
-    case ARMMMUIdx_SE10_0:
-    case ARMMMUIdx_Stage1_SE0:
-        return arm_el_is_aa64(env, 3) ? 1 : 3;
-    case ARMMMUIdx_SE10_1:
-    case ARMMMUIdx_SE10_1_PAN:
+    case ARMMMUIdx_E10_0:
     case ARMMMUIdx_Stage1_E0:
+        return arm_el_is_aa64(env, 3) || !arm_is_secure_below_el3(env) ? 1 : 3;
     case ARMMMUIdx_Stage1_E1:
     case ARMMMUIdx_Stage1_E1_PAN:
-    case ARMMMUIdx_Stage1_SE1:
-    case ARMMMUIdx_Stage1_SE1_PAN:
-    case ARMMMUIdx_E10_0:
     case ARMMMUIdx_E10_1:
     case ARMMMUIdx_E10_1_PAN:
     case ARMMMUIdx_MPrivNegPri:
@@ -XXX,XX +XXX,XX @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx)
     case ARMMMUIdx_Stage1_E0:
     case ARMMMUIdx_Stage1_E1:
     case ARMMMUIdx_Stage1_E1_PAN:
-    case ARMMMUIdx_Stage1_SE0:
-    case ARMMMUIdx_Stage1_SE1:
-    case ARMMMUIdx_Stage1_SE1_PAN:
         return true;
     default:
         return false;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
     /* Begin with base v8.0 state.  */
     uint64_t valid_mask = 0x3fff;
     ARMCPU *cpu = env_archcpu(env);
+    uint64_t changed;
 
     /*
      * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 
     /* Clear all-context RES0 bits.  */
     value &= valid_mask;
-    raw_write(env, ri, value);
+    changed = env->cp15.scr_el3 ^ value;
+    env->cp15.scr_el3 = value;
+
+    /*
+     * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then
+     * we must invalidate all TLBs below EL3.
+     */
+    if (changed & SCR_NS) {
+        tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 |
+                                           ARMMMUIdxBit_E20_0 |
+                                           ARMMMUIdxBit_E10_1 |
+                                           ARMMMUIdxBit_E20_2 |
+                                           ARMMMUIdxBit_E10_1_PAN |
+                                           ARMMMUIdxBit_E20_2_PAN |
+                                           ARMMMUIdxBit_E2));
+    }
 }
 
 static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static int gt_phys_redir_timeridx(CPUARMState *env)
     case ARMMMUIdx_E20_0:
     case ARMMMUIdx_E20_2:
     case ARMMMUIdx_E20_2_PAN:
-    case ARMMMUIdx_SE20_0:
-    case ARMMMUIdx_SE20_2:
-    case ARMMMUIdx_SE20_2_PAN:
         return GTIMER_HYP;
     default:
         return GTIMER_PHYS;
@@ -XXX,XX +XXX,XX @@ static int gt_virt_redir_timeridx(CPUARMState *env)
     case ARMMMUIdx_E20_0:
     case ARMMMUIdx_E20_2:
     case ARMMMUIdx_E20_2_PAN:
-    case ARMMMUIdx_SE20_0:
-    case ARMMMUIdx_SE20_2:
-    case ARMMMUIdx_SE20_2_PAN:
         return GTIMER_HYPVIRT;
     default:
         return GTIMER_VIRT;
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
         switch (el) {
         case 3:
-            mmu_idx = ARMMMUIdx_SE3;
+            mmu_idx = ARMMMUIdx_E3;
             secure = true;
             break;
         case 2:
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
             /* fall through */
         case 1:
             if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) {
-                mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN
-                           : ARMMMUIdx_Stage1_E1_PAN);
+                mmu_idx = ARMMMUIdx_Stage1_E1_PAN;
             } else {
-                mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1;
+                mmu_idx = ARMMMUIdx_Stage1_E1;
             }
             break;
         default:
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
         switch (el) {
         case 3:
-            mmu_idx = ARMMMUIdx_SE10_0;
+            mmu_idx = ARMMMUIdx_E10_0;
             secure = true;
             break;
         case 2:
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
             mmu_idx = ARMMMUIdx_Stage1_E0;
             break;
         case 1:
-            mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0;
+            mmu_idx = ARMMMUIdx_Stage1_E0;
             break;
         default:
             g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
         switch (ri->opc1) {
         case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
             if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) {
-                mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN
-                           : ARMMMUIdx_Stage1_E1_PAN);
+                mmu_idx = ARMMMUIdx_Stage1_E1_PAN;
             } else {
-                mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1;
+                mmu_idx = ARMMMUIdx_Stage1_E1;
             }
             break;
         case 4: /* AT S1E2R, AT S1E2W */
-            mmu_idx = secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2;
+            mmu_idx = ARMMMUIdx_E2;
             break;
         case 6: /* AT S1E3R, AT S1E3W */
-            mmu_idx = ARMMMUIdx_SE3;
+            mmu_idx = ARMMMUIdx_E3;
             secure = true;
             break;
         default:
@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
         }
         break;
     case 2: /* AT S1E0R, AT S1E0W */
-        mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0;
+        mmu_idx = ARMMMUIdx_Stage1_E0;
         break;
     case 4: /* AT S12E1R, AT S12E1W */
-        mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1;
+        mmu_idx = ARMMMUIdx_E10_1;
         break;
     case 6: /* AT S12E0R, AT S12E0W */
-        mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0;
+        mmu_idx = ARMMMUIdx_E10_0;
         break;
     default:
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
         uint16_t mask = ARMMMUIdxBit_E20_2 |
                         ARMMMUIdxBit_E20_2_PAN |
                         ARMMMUIdxBit_E20_0;
-
-        if (arm_is_secure_below_el3(env)) {
-            mask >>= ARM_MMU_IDX_A_NS;
-        }
-
         tlb_flush_by_mmuidx(env_cpu(env), mask);
     }
     raw_write(env, ri, value);
@@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
         uint16_t mask = ARMMMUIdxBit_E10_1 |
                         ARMMMUIdxBit_E10_1_PAN |
                         ARMMMUIdxBit_E10_0;
-
-        if (arm_is_secure_below_el3(env)) {
-            mask >>= ARM_MMU_IDX_A_NS;
-        }
-
         tlb_flush_by_mmuidx(cs, mask);
         raw_write(env, ri, value);
     }
@@ -XXX,XX +XXX,XX @@ static int vae1_tlbmask(CPUARMState *env)
                ARMMMUIdxBit_E10_1_PAN |
                ARMMMUIdxBit_E10_0;
     }
-
-    if (arm_is_secure_below_el3(env)) {
-        mask >>= ARM_MMU_IDX_A_NS;
-    }
-
     return mask;
 }
 
@@ -XXX,XX +XXX,XX @@ static int vae1_tlbbits(CPUARMState *env, uint64_t addr)
         mmu_idx = ARMMMUIdx_E10_0;
     }
 
-    if (arm_is_secure_below_el3(env)) {
-        mmu_idx &= ~ARM_MMU_IDX_A_NS;
-    }
-
     return tlbbits_for_regime(env, mmu_idx, addr);
 }
 
@@ -XXX,XX +XXX,XX @@ static int alle1_tlbmask(CPUARMState *env)
      * stage 2 translations, whereas most other scopes only invalidate
      * stage 1 translations.
      */
-    if (arm_is_secure_below_el3(env)) {
-        return ARMMMUIdxBit_SE10_1 |
-               ARMMMUIdxBit_SE10_1_PAN |
-               ARMMMUIdxBit_SE10_0;
-    } else {
-        return ARMMMUIdxBit_E10_1 |
-               ARMMMUIdxBit_E10_1_PAN |
-               ARMMMUIdxBit_E10_0;
-    }
+    return (ARMMMUIdxBit_E10_1 |
+            ARMMMUIdxBit_E10_1_PAN |
+            ARMMMUIdxBit_E10_0);
 }
 
 static int e2_tlbmask(CPUARMState *env)
 {
-    if (arm_is_secure_below_el3(env)) {
-        return ARMMMUIdxBit_SE20_0 |
-               ARMMMUIdxBit_SE20_2 |
-               ARMMMUIdxBit_SE20_2_PAN |
-               ARMMMUIdxBit_SE2;
-    } else {
-        return ARMMMUIdxBit_E20_0 |
-               ARMMMUIdxBit_E20_2 |
-               ARMMMUIdxBit_E20_2_PAN |
-               ARMMMUIdxBit_E2;
-    }
+    return (ARMMMUIdxBit_E20_0 |
+            ARMMMUIdxBit_E20_2 |
+            ARMMMUIdxBit_E20_2_PAN |
+            ARMMMUIdxBit_E2);
 }
 
 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
     ARMCPU *cpu = env_archcpu(env);
     CPUState *cs = CPU(cpu);
 
-    tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3);
+    tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E3);
 }
 
 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     CPUState *cs = env_cpu(env);
 
-    tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3);
+    tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3);
 }
 
 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
     CPUState *cs = CPU(cpu);
     uint64_t pageaddr = sextract64(value << 12, 0, 56);
 
-    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3);
+    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E3);
 }
 
 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     CPUState *cs = env_cpu(env);
     uint64_t pageaddr = sextract64(value << 12, 0, 56);
-    bool secure = arm_is_secure_below_el3(env);
-    int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2;
-    int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2,
-                                  pageaddr);
+    int bits = tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr);
 
-    tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
+    tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
+                                                  ARMMMUIdxBit_E2, bits);
 }
 
 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     CPUState *cs = env_cpu(env);
     uint64_t pageaddr = sextract64(value << 12, 0, 56);
-    int bits = tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr);
+    int bits = tlbbits_for_regime(env, ARMMMUIdx_E3, pageaddr);
 
     tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
-                                                  ARMMMUIdxBit_SE3, bits);
+                                                  ARMMMUIdxBit_E3, bits);
 }
 
 #ifdef TARGET_AARCH64
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_rvae1is_write(CPUARMState *env,
 
 static int vae2_tlbmask(CPUARMState *env)
 {
-    return (arm_is_secure_below_el3(env)
-            ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2);
+    return ARMMMUIdxBit_E2;
 }
 
 static void tlbi_aa64_rvae2_write(CPUARMState *env,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_rvae3_write(CPUARMState *env,
      * flush-last-level-only.
      */
 
-    do_rvae_write(env, value, ARMMMUIdxBit_SE3,
-                  tlb_force_broadcast(env));
+    do_rvae_write(env, value, ARMMMUIdxBit_E3, tlb_force_broadcast(env));
 }
 
 static void tlbi_aa64_rvae3is_write(CPUARMState *env,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_rvae3is_write(CPUARMState *env,
      * flush-last-level-only or inner/outer specific flushes.
      */
 
-    do_rvae_write(env, value, ARMMMUIdxBit_SE3, true);
+    do_rvae_write(env, value, ARMMMUIdxBit_E3, true);
 }
 #endif
 
@@ -XXX,XX +XXX,XX @@ uint64_t arm_sctlr(CPUARMState *env, int el)
     /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
     if (el == 0) {
         ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0);
-        el = (mmu_idx == ARMMMUIdx_E20_0 || mmu_idx == ARMMMUIdx_SE20_0)
-             ? 2 : 1;
+        el = mmu_idx == ARMMMUIdx_E20_0 ? 2 : 1;
     }
     return env->cp15.sctlr_el[el];
 }
@@ -XXX,XX +XXX,XX @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
     switch (mmu_idx) {
     case ARMMMUIdx_E10_0:
     case ARMMMUIdx_E20_0:
-    case ARMMMUIdx_SE10_0:
-    case ARMMMUIdx_SE20_0:
         return 0;
     case ARMMMUIdx_E10_1:
     case ARMMMUIdx_E10_1_PAN:
-    case ARMMMUIdx_SE10_1:
-    case ARMMMUIdx_SE10_1_PAN:
         return 1;
     case ARMMMUIdx_E2:
     case ARMMMUIdx_E20_2:
     case ARMMMUIdx_E20_2_PAN:
-    case ARMMMUIdx_SE2:
-    case ARMMMUIdx_SE20_2:
-    case ARMMMUIdx_SE20_2_PAN:
         return 2;
-    case ARMMMUIdx_SE3:
+    case ARMMMUIdx_E3:
         return 3;
     default:
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
         }
         break;
     case 3:
-        return ARMMMUIdx_SE3;
+        return ARMMMUIdx_E3;
     default:
         g_assert_not_reached();
     }
 
-    if (arm_is_secure_below_el3(env)) {
-        idx &= ~ARM_MMU_IDX_A_NS;
-    }
-
     return idx;
 }
 
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
         switch (mmu_idx) {
         case ARMMMUIdx_E10_1:
         case ARMMMUIdx_E10_1_PAN:
-        case ARMMMUIdx_SE10_1:
-        case ARMMMUIdx_SE10_1_PAN:
             /* TODO: ARMv8.3-NV */
             DP_TBFLAG_A64(flags, UNPRIV, 1);
             break;
         case ARMMMUIdx_E20_2:
         case ARMMMUIdx_E20_2_PAN:
-        case ARMMMUIdx_SE20_2:
-        case ARMMMUIdx_SE20_2_PAN:
             /*
              * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
              * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ unsigned int arm_pamax(ARMCPU *cpu)
 ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
 {
     switch (mmu_idx) {
-    case ARMMMUIdx_SE10_0:
-        return ARMMMUIdx_Stage1_SE0;
-    case ARMMMUIdx_SE10_1:
-        return ARMMMUIdx_Stage1_SE1;
-    case ARMMMUIdx_SE10_1_PAN:
-        return ARMMMUIdx_Stage1_SE1_PAN;
     case ARMMMUIdx_E10_0:
         return ARMMMUIdx_Stage1_E0;
     case ARMMMUIdx_E10_1:
@@ -XXX,XX +XXX,XX @@ static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx)
 static bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
 {
     switch (mmu_idx) {
-    case ARMMMUIdx_SE10_0:
     case ARMMMUIdx_E20_0:
-    case ARMMMUIdx_SE20_0:
     case ARMMMUIdx_Stage1_E0:
-    case ARMMMUIdx_Stage1_SE0:
     case ARMMMUIdx_MUser:
     case ARMMMUIdx_MSUser:
     case ARMMMUIdx_MUserNegPri:
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
 
             s2_mmu_idx = (s2walk_secure
                           ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2);
-            is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0;
+            is_el0 = mmu_idx == ARMMMUIdx_E10_0;
 
             /*
              * S1 is done, now do S2 translation.
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
     case ARMMMUIdx_Stage1_E1:
     case ARMMMUIdx_Stage1_E1_PAN:
     case ARMMMUIdx_E2:
+        is_secure = arm_is_secure_below_el3(env);
+        break;
     case ARMMMUIdx_Stage2:
     case ARMMMUIdx_MPrivNegPri:
     case ARMMMUIdx_MUserNegPri:
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
     case ARMMMUIdx_MUser:
         is_secure = false;
         break;
-    case ARMMMUIdx_SE3:
-    case ARMMMUIdx_SE10_0:
-    case ARMMMUIdx_SE10_1:
-    case ARMMMUIdx_SE10_1_PAN:
-    case ARMMMUIdx_SE20_0:
-    case ARMMMUIdx_SE20_2:
-    case ARMMMUIdx_SE20_2_PAN:
-    case ARMMMUIdx_Stage1_SE0:
-    case ARMMMUIdx_Stage1_SE1:
-    case ARMMMUIdx_Stage1_SE1_PAN:
-    case ARMMMUIdx_SE2:
+    case ARMMMUIdx_E3:
     case ARMMMUIdx_Stage2_S:
     case ARMMMUIdx_MSPrivNegPri:
     case ARMMMUIdx_MSUserNegPri:
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static int get_a64_user_mem_index(DisasContext *s)
         case ARMMMUIdx_E20_2_PAN:
             useridx = ARMMMUIdx_E20_0;
             break;
-        case ARMMMUIdx_SE10_1:
-        case ARMMMUIdx_SE10_1_PAN:
-            useridx = ARMMMUIdx_SE10_0;
-            break;
-        case ARMMMUIdx_SE20_2:
-        case ARMMMUIdx_SE20_2_PAN:
-            useridx = ARMMMUIdx_SE20_0;
-            break;
         default:
             g_assert_not_reached();
         }
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline int get_a32_user_mem_index(DisasContext *s)
      *  otherwise, access as if at PL0.
      */
     switch (s->mmu_idx) {
+    case ARMMMUIdx_E3:
     case ARMMMUIdx_E2:        /* this one is UNPREDICTABLE */
     case ARMMMUIdx_E10_0:
     case ARMMMUIdx_E10_1:
     case ARMMMUIdx_E10_1_PAN:
         return arm_to_core_mmu_idx(ARMMMUIdx_E10_0);
-    case ARMMMUIdx_SE3:
-    case ARMMMUIdx_SE10_0:
-    case ARMMMUIdx_SE10_1:
-    case ARMMMUIdx_SE10_1_PAN:
-        return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0);
     case ARMMMUIdx_MUser:
     case ARMMMUIdx_MPriv:
         return arm_to_core_mmu_idx(ARMMMUIdx_MUser);
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Use a switch on mmu_idx for the a-profile indexes, instead of
three different if's vs regime_el and arm_mmu_idx_is_stage1_of_2.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 32 +++++++++++++++++++++++++-------
 1 file changed, 25 insertions(+), 7 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
 
     hcr_el2 = arm_hcr_el2_eff(env);
 
-    if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
+    switch (mmu_idx) {
+    case ARMMMUIdx_Stage2:
+    case ARMMMUIdx_Stage2_S:
         /* HCR.DC means HCR.VM behaves as 1 */
         return (hcr_el2 & (HCR_DC | HCR_VM)) == 0;
-    }
 
-    if (hcr_el2 & HCR_TGE) {
+    case ARMMMUIdx_E10_0:
+    case ARMMMUIdx_E10_1:
+    case ARMMMUIdx_E10_1_PAN:
         /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
-        if (!is_secure && regime_el(env, mmu_idx) == 1) {
+        if (!is_secure && (hcr_el2 & HCR_TGE)) {
             return true;
         }
-    }
+        break;
 
-    if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) {
+    case ARMMMUIdx_Stage1_E0:
+    case ARMMMUIdx_Stage1_E1:
+    case ARMMMUIdx_Stage1_E1_PAN:
         /* HCR.DC means SCTLR_EL1.M behaves as 0 */
-        return true;
+        if (hcr_el2 & HCR_DC) {
+            return true;
+        }
+        break;
+
+    case ARMMMUIdx_E20_0:
+    case ARMMMUIdx_E20_2:
+    case ARMMMUIdx_E20_2_PAN:
+    case ARMMMUIdx_E2:
+    case ARMMMUIdx_E3:
+        break;
+
+    default:
+        g_assert_not_reached();
     }
 
     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

The effect of TGE does not only apply to non-secure state,
now that Secure EL2 exists.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
     case ARMMMUIdx_E10_0:
     case ARMMMUIdx_E10_1:
     case ARMMMUIdx_E10_1_PAN:
-        /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
-        if (!is_secure && (hcr_el2 & HCR_TGE)) {
+        /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */
+        if (hcr_el2 & HCR_TGE) {
             return true;
         }
         break;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

For page walking, we may require HCR for a security state
that is not "current".

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h    | 20 +++++++++++++-------
 target/arm/helper.c | 11 ++++++++---
 2 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure(CPUARMState *env)
  * Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
  * This corresponds to the pseudocode EL2Enabled()
  */
+static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
+{
+    return arm_feature(env, ARM_FEATURE_EL2)
+           && (!secure || (env->cp15.scr_el3 & SCR_EEL2));
+}
+
 static inline bool arm_is_el2_enabled(CPUARMState *env)
 {
-    if (arm_feature(env, ARM_FEATURE_EL2)) {
-        if (arm_is_secure_below_el3(env)) {
-            return (env->cp15.scr_el3 & SCR_EEL2) != 0;
-        }
-        return true;
-    }
-    return false;
+    return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env));
 }
 
 #else
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure(CPUARMState *env)
     return false;
 }
 
+static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
+{
+    return false;
+}
+
 static inline bool arm_is_el2_enabled(CPUARMState *env)
 {
     return false;
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_el2_enabled(CPUARMState *env)
  * "for all purposes other than a direct read or write access of HCR_EL2."
  * Not included here is HCR_RW.
  */
+uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure);
 uint64_t arm_hcr_el2_eff(CPUARMState *env);
 uint64_t arm_hcrx_el2_eff(CPUARMState *env);
 
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,
 }
 
 /*
- * Return the effective value of HCR_EL2.
+ * Return the effective value of HCR_EL2, at the given security state.
  * Bits that are not included here:
  * RW       (read from SCR_EL3.RW as needed)
  */
-uint64_t arm_hcr_el2_eff(CPUARMState *env)
+uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure)
 {
     uint64_t ret = env->cp15.hcr_el2;
 
-    if (!arm_is_el2_enabled(env)) {
+    if (!arm_is_el2_enabled_secstate(env, secure)) {
         /*
          * "This register has no effect if EL2 is not enabled in the
          * current Security state".  This is ARMv8.4-SecEL2 speak for
@@ -XXX,XX +XXX,XX @@ uint64_t arm_hcr_el2_eff(CPUARMState *env)
     return ret;
 }
 
+uint64_t arm_hcr_el2_eff(CPUARMState *env)
+{
+    return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env));
+}
+
 /*
  * Corresponds to ARM pseudocode function ELIsInHost().
  */
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Rename the argument to is_secure_ptr, and introduce a
local variable is_secure with the value.  We only write
back to the pointer toward the end of the function.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs)
 
 /* Translate a S1 pagetable walk through S2 if needed.  */
 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
-                               hwaddr addr, bool *is_secure,
+                               hwaddr addr, bool *is_secure_ptr,
                                ARMMMUFaultInfo *fi)
 {
-    ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
+    bool is_secure = *is_secure_ptr;
+    ARMMMUIdx s2_mmu_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
 
     if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
-        !regime_translation_disabled(env, s2_mmu_idx, *is_secure)) {
+        !regime_translation_disabled(env, s2_mmu_idx, is_secure)) {
         GetPhysAddrResult s2 = {};
         int ret;
 
         ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx,
-                                 *is_secure, false, &s2, fi);
+                                 is_secure, false, &s2, fi);
         if (ret) {
             assert(fi->type != ARMFault_None);
             fi->s2addr = addr;
             fi->stage2 = true;
             fi->s1ptw = true;
-            fi->s1ns = !*is_secure;
+            fi->s1ns = !is_secure;
             return ~0;
         }
         if ((arm_hcr_el2_eff(env) & HCR_PTW) &&
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
             fi->s2addr = addr;
             fi->stage2 = true;
             fi->s1ptw = true;
-            fi->s1ns = !*is_secure;
+            fi->s1ns = !is_secure;
             return ~0;
         }
 
         if (arm_is_secure_below_el3(env)) {
             /* Check if page table walk is to secure or non-secure PA space. */
-            if (*is_secure) {
-                *is_secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
+            if (is_secure) {
+                is_secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
             } else {
-                *is_secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
+                is_secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
             }
+            *is_secure_ptr = is_secure;
         } else {
-            assert(!*is_secure);
+            assert(!is_secure);
         }
 
         addr = s2.phys;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This value is unused.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221001162318.153420-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr)
  * s1 and s2 for the HCR_EL2.FWB == 1 case, returning the
  * combined attributes in MAIR_EL1 format.
  */
-static uint8_t combined_attrs_fwb(CPUARMState *env,
-                                  ARMCacheAttrs s1, ARMCacheAttrs s2)
+static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2)
 {
     switch (s2.attrs) {
     case 7:
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
 
     /* Combine memory type and cacheability attributes */
     if (arm_hcr_el2_eff(env) & HCR_FWB) {
-        ret.attrs = combined_attrs_fwb(env, s1, s2);
+        ret.attrs = combined_attrs_fwb(s1, s2);
     } else {
         ret.attrs = combined_attrs_nofwb(env, s1, s2);
     }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

These subroutines did not need ENV for anything except
retrieving the effective value of HCR anyway.

We have computed the effective value of HCR in the callers,
and this will be especially important for interpreting HCR
in a non-current security state.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 30 +++++++++++++++++-------------
 1 file changed, 17 insertions(+), 13 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
 }
 
-static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs)
+static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs)
 {
     /*
      * For an S1 page table walk, the stage 1 attributes are always
@@ -XXX,XX +XXX,XX @@ static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs)
      * when cacheattrs.attrs bit [2] is 0.
      */
     assert(cacheattrs.is_s2_format);
-    if (arm_hcr_el2_eff(env) & HCR_FWB) {
+    if (hcr & HCR_FWB) {
         return (cacheattrs.attrs & 0x4) == 0;
     } else {
         return (cacheattrs.attrs & 0xc) == 0;
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
     if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
         !regime_translation_disabled(env, s2_mmu_idx, is_secure)) {
         GetPhysAddrResult s2 = {};
+        uint64_t hcr;
         int ret;
 
         ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx,
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
             fi->s1ns = !is_secure;
             return ~0;
         }
-        if ((arm_hcr_el2_eff(env) & HCR_PTW) &&
-            ptw_attrs_are_device(env, s2.cacheattrs)) {
+
+        hcr = arm_hcr_el2_eff(env);
+        if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) {
             /*
              * PTW set and S1 walk touched S2 Device memory:
              * generate Permission fault.
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
  * ref: shared/translation/attrs/S2AttrDecode()
  *      .../S2ConvertAttrsHints()
  */
-static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
+static uint8_t convert_stage2_attrs(uint64_t hcr, uint8_t s2attrs)
 {
     uint8_t hiattr = extract32(s2attrs, 2, 2);
     uint8_t loattr = extract32(s2attrs, 0, 2);
     uint8_t hihint = 0, lohint = 0;
 
     if (hiattr != 0) { /* normal memory */
-        if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */
+        if (hcr & HCR_CD) { /* cache disabled */
             hiattr = loattr = 1; /* non-cacheable */
         } else {
             if (hiattr != 1) { /* Write-through or write-back */
@@ -XXX,XX +XXX,XX @@ static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2)
  * s1 and s2 for the HCR_EL2.FWB == 0 case, returning the
  * combined attributes in MAIR_EL1 format.
  */
-static uint8_t combined_attrs_nofwb(CPUARMState *env,
+static uint8_t combined_attrs_nofwb(uint64_t hcr,
                                     ARMCacheAttrs s1, ARMCacheAttrs s2)
 {
     uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs;
 
-    s2_mair_attrs = convert_stage2_attrs(env, s2.attrs);
+    s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs);
 
     s1lo = extract32(s1.attrs, 0, 4);
     s2lo = extract32(s2_mair_attrs, 0, 4);
@@ -XXX,XX +XXX,XX @@ static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2)
  * @s1:      Attributes from stage 1 walk
  * @s2:      Attributes from stage 2 walk
  */
-static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
+static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
                                         ARMCacheAttrs s1, ARMCacheAttrs s2)
 {
     ARMCacheAttrs ret;
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
     }
 
     /* Combine memory type and cacheability attributes */
-    if (arm_hcr_el2_eff(env) & HCR_FWB) {
+    if (hcr & HCR_FWB) {
         ret.attrs = combined_attrs_fwb(s1, s2);
     } else {
-        ret.attrs = combined_attrs_nofwb(env, s1, s2);
+        ret.attrs = combined_attrs_nofwb(hcr, s1, s2);
     }
 
     /*
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
             ARMCacheAttrs cacheattrs1;
             ARMMMUIdx s2_mmu_idx;
             bool is_el0;
+            uint64_t hcr;
 
             ret = get_phys_addr_with_secure(env, address, access_type,
                                             s1_mmu_idx, is_secure, result, fi);
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
             }
 
             /* Combine the S1 and S2 cache attributes. */
-            if (arm_hcr_el2_eff(env) & HCR_DC) {
+            hcr = arm_hcr_el2_eff(env);
+            if (hcr & HCR_DC) {
                 /*
                  * HCR.DC forces the first stage attributes to
                  *  Normal Non-Shareable,
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
                 }
                 cacheattrs1.shareability = 0;
             }
-            result->cacheattrs = combine_cacheattrs(env, cacheattrs1,
+            result->cacheattrs = combine_cacheattrs(hcr, cacheattrs1,
                                                     result->cacheattrs);
 
             /*
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Use arm_hcr_el2_eff_secstate instead of arm_hcr_el2_eff, so
that we use is_secure instead of the current security state.
These AT* operations have been broken since arm_hcr_el2_eff
gained a check for "el2 enabled" for Secure EL2.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
         }
     }
 
-    hcr_el2 = arm_hcr_el2_eff(env);
+    hcr_el2 = arm_hcr_el2_eff_secstate(env, is_secure);
 
     switch (mmu_idx) {
     case ARMMMUIdx_Stage2:
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
             return ~0;
         }
 
-        hcr = arm_hcr_el2_eff(env);
+        hcr = arm_hcr_el2_eff_secstate(env, is_secure);
         if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) {
             /*
              * PTW set and S1 walk touched S2 Device memory:
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
             }
 
             /* Combine the S1 and S2 cache attributes. */
-            hcr = arm_hcr_el2_eff(env);
+            hcr = arm_hcr_el2_eff_secstate(env, is_secure);
             if (hcr & HCR_DC) {
                 /*
                  * HCR.DC forces the first stage attributes to
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
         result->page_size = TARGET_PAGE_SIZE;
 
         /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
-        hcr = arm_hcr_el2_eff(env);
+        hcr = arm_hcr_el2_eff_secstate(env, is_secure);
         result->cacheattrs.shareability = 0;
         result->cacheattrs.is_s2_format = false;
         if (hcr & HCR_DC) {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 138 +++++++++++++++++++++++++----------------------
 1 file changed, 74 insertions(+), 64 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
     return ret;
 }
 
+/*
+ * MMU disabled.  S1 addresses within aa64 translation regimes are
+ * still checked for bounds -- see AArch64.S1DisabledOutput().
+ */
+static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
+                                   MMUAccessType access_type,
+                                   ARMMMUIdx mmu_idx, bool is_secure,
+                                   GetPhysAddrResult *result,
+                                   ARMMMUFaultInfo *fi)
+{
+    uint64_t hcr;
+    uint8_t memattr;
+
+    if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) {
+        int r_el = regime_el(env, mmu_idx);
+        if (arm_el_is_aa64(env, r_el)) {
+            int pamax = arm_pamax(env_archcpu(env));
+            uint64_t tcr = env->cp15.tcr_el[r_el];
+            int addrtop, tbi;
+
+            tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
+            if (access_type == MMU_INST_FETCH) {
+                tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
+            }
+            tbi = (tbi >> extract64(address, 55, 1)) & 1;
+            addrtop = (tbi ? 55 : 63);
+
+            if (extract64(address, pamax, addrtop - pamax + 1) != 0) {
+                fi->type = ARMFault_AddressSize;
+                fi->level = 0;
+                fi->stage2 = false;
+                return 1;
+            }
+
+            /*
+             * When TBI is disabled, we've just validated that all of the
+             * bits above PAMax are zero, so logically we only need to
+             * clear the top byte for TBI.  But it's clearer to follow
+             * the pseudocode set of addrdesc.paddress.
+             */
+            address = extract64(address, 0, 52);
+        }
+    }
+
+    result->phys = address;
+    result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+    result->page_size = TARGET_PAGE_SIZE;
+
+    /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
+    hcr = arm_hcr_el2_eff_secstate(env, is_secure);
+    result->cacheattrs.shareability = 0;
+    result->cacheattrs.is_s2_format = false;
+    if (hcr & HCR_DC) {
+        if (hcr & HCR_DCT) {
+            memattr = 0xf0;  /* Tagged, Normal, WB, RWA */
+        } else {
+            memattr = 0xff;  /* Normal, WB, RWA */
+        }
+    } else if (access_type == MMU_INST_FETCH) {
+        if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
+            memattr = 0xee;  /* Normal, WT, RA, NT */
+        } else {
+            memattr = 0x44;  /* Normal, NC, No */
+        }
+        result->cacheattrs.shareability = 2; /* outer sharable */
+    } else {
+        memattr = 0x00;      /* Device, nGnRnE */
+    }
+    result->cacheattrs.attrs = memattr;
+    return 0;
+}
+
 bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
                                bool is_secure, GetPhysAddrResult *result,
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
     /* Definitely a real MMU, not an MPU */
 
     if (regime_translation_disabled(env, mmu_idx, is_secure)) {
-        uint64_t hcr;
-        uint8_t memattr;
-
-        /*
-         * MMU disabled.  S1 addresses within aa64 translation regimes are
-         * still checked for bounds -- see AArch64.TranslateAddressS1Off.
-         */
-        if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) {
-            int r_el = regime_el(env, mmu_idx);
-            if (arm_el_is_aa64(env, r_el)) {
-                int pamax = arm_pamax(env_archcpu(env));
-                uint64_t tcr = env->cp15.tcr_el[r_el];
-                int addrtop, tbi;
-
-                tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
-                if (access_type == MMU_INST_FETCH) {
-                    tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
-                }
-                tbi = (tbi >> extract64(address, 55, 1)) & 1;
-                addrtop = (tbi ? 55 : 63);
-
-                if (extract64(address, pamax, addrtop - pamax + 1) != 0) {
-                    fi->type = ARMFault_AddressSize;
-                    fi->level = 0;
-                    fi->stage2 = false;
-                    return 1;
-                }
-
-                /*
-                 * When TBI is disabled, we've just validated that all of the
-                 * bits above PAMax are zero, so logically we only need to
-                 * clear the top byte for TBI.  But it's clearer to follow
-                 * the pseudocode set of addrdesc.paddress.
-                 */
-                address = extract64(address, 0, 52);
-            }
-        }
-        result->phys = address;
-        result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
-        result->page_size = TARGET_PAGE_SIZE;
-
-        /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
-        hcr = arm_hcr_el2_eff_secstate(env, is_secure);
-        result->cacheattrs.shareability = 0;
-        result->cacheattrs.is_s2_format = false;
-        if (hcr & HCR_DC) {
-            if (hcr & HCR_DCT) {
-                memattr = 0xf0;  /* Tagged, Normal, WB, RWA */
-            } else {
-                memattr = 0xff;  /* Normal, WB, RWA */
-            }
-        } else if (access_type == MMU_INST_FETCH) {
-            if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
-                memattr = 0xee;  /* Normal, WT, RA, NT */
-            } else {
-                memattr = 0x44;  /* Normal, NC, No */
-            }
-            result->cacheattrs.shareability = 2; /* outer sharable */
-        } else {
-            memattr = 0x00;      /* Device, nGnRnE */
-        }
-        result->cacheattrs.attrs = memattr;
-        return 0;
+        return get_phys_addr_disabled(env, address, access_type, mmu_idx,
+                                      is_secure, result, fi);
     }
-
     if (regime_using_lpae_format(env, mmu_idx)) {
         return get_phys_addr_lpae(env, address, access_type, mmu_idx,
                                   is_secure, false, result, fi);
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Do not apply memattr or shareability for Stage2 translations.
Make sure to apply HCR_{DC,DCT} only to Regime_EL10, per the
pseudocode in AArch64.S1DisabledOutput.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221001162318.153420-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 48 +++++++++++++++++++++++++-----------------------
 1 file changed, 25 insertions(+), 23 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
                                    GetPhysAddrResult *result,
                                    ARMMMUFaultInfo *fi)
 {
-    uint64_t hcr;
-    uint8_t memattr;
+    uint8_t memattr = 0x00;    /* Device nGnRnE */
+    uint8_t shareability = 0;  /* non-sharable */
 
     if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) {
         int r_el = regime_el(env, mmu_idx);
+
         if (arm_el_is_aa64(env, r_el)) {
             int pamax = arm_pamax(env_archcpu(env));
             uint64_t tcr = env->cp15.tcr_el[r_el];
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
              */
             address = extract64(address, 0, 52);
         }
+
+        /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
+        if (r_el == 1) {
+            uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure);
+            if (hcr & HCR_DC) {
+                if (hcr & HCR_DCT) {
+                    memattr = 0xf0;  /* Tagged, Normal, WB, RWA */
+                } else {
+                    memattr = 0xff;  /* Normal, WB, RWA */
+                }
+            }
+        }
+        if (memattr == 0 && access_type == MMU_INST_FETCH) {
+            if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
+                memattr = 0xee;  /* Normal, WT, RA, NT */
+            } else {
+                memattr = 0x44;  /* Normal, NC, No */
+            }
+            shareability = 2; /* outer sharable */
+        }
+        result->cacheattrs.is_s2_format = false;
     }
 
     result->phys = address;
     result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
     result->page_size = TARGET_PAGE_SIZE;
-
-    /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
-    hcr = arm_hcr_el2_eff_secstate(env, is_secure);
-    result->cacheattrs.shareability = 0;
-    result->cacheattrs.is_s2_format = false;
-    if (hcr & HCR_DC) {
-        if (hcr & HCR_DCT) {
-            memattr = 0xf0;  /* Tagged, Normal, WB, RWA */
-        } else {
-            memattr = 0xff;  /* Normal, WB, RWA */
-        }
-    } else if (access_type == MMU_INST_FETCH) {
-        if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
-            memattr = 0xee;  /* Normal, WT, RA, NT */
-        } else {
-            memattr = 0x44;  /* Normal, NC, No */
-        }
-        result->cacheattrs.shareability = 2; /* outer sharable */
-    } else {
-        memattr = 0x00;      /* Device, nGnRnE */
-    }
+    result->cacheattrs.shareability = shareability;
     result->cacheattrs.attrs = memattr;
     return 0;
 }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Adjust GetPhysAddrResult to fill in CPUTLBEntryFull,
so that it may be passed directly to tlb_set_page_full.

The change is large, but mostly mechanical.  The major
non-mechanical change is page_size -> lg_page_size.
Most of the time this is obvious, and is related to
TARGET_PAGE_BITS.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221001162318.153420-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h  |   5 +-
 target/arm/helper.c     |  12 +--
 target/arm/m_helper.c   |  20 ++---
 target/arm/ptw.c        | 179 ++++++++++++++++++++--------------------
 target/arm/tlb_helper.c |   9 +-
 5 files changed, 111 insertions(+), 114 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ typedef struct ARMCacheAttrs {
 
 /* Fields that are valid upon success. */
 typedef struct GetPhysAddrResult {
-    hwaddr phys;
-    target_ulong page_size;
-    int prot;
-    MemTxAttrs attrs;
+    CPUTLBEntryFull f;
     ARMCacheAttrs cacheattrs;
 } GetPhysAddrResult;
 
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
         /* Create a 64-bit PAR */
         par64 = (1 << 11); /* LPAE bit always set */
         if (!ret) {
-            par64 |= res.phys & ~0xfffULL;
-            if (!res.attrs.secure) {
+            par64 |= res.f.phys_addr & ~0xfffULL;
+            if (!res.f.attrs.secure) {
                 par64 |= (1 << 9); /* NS */
             }
             par64 |= (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
          */
         if (!ret) {
             /* We do not set any attribute bits in the PAR */
-            if (res.page_size == (1 << 24)
+            if (res.f.lg_page_size == 24
                 && arm_feature(env, ARM_FEATURE_V7)) {
-                par64 = (res.phys & 0xff000000) | (1 << 1);
+                par64 = (res.f.phys_addr & 0xff000000) | (1 << 1);
             } else {
-                par64 = res.phys & 0xfffff000;
+                par64 = res.f.phys_addr & 0xfffff000;
             }
-            if (!res.attrs.secure) {
+            if (!res.f.attrs.secure) {
                 par64 |= (1 << 9); /* NS */
             }
         } else {
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
         }
         goto pend_fault;
     }
-    address_space_stl_le(arm_addressspace(cs, res.attrs), res.phys, value,
-                         res.attrs, &txres);
+    address_space_stl_le(arm_addressspace(cs, res.f.attrs), res.f.phys_addr,
+                         value, res.f.attrs, &txres);
     if (txres != MEMTX_OK) {
         /* BusFault trying to write the data */
         if (mode == STACK_LAZYFP) {
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
         goto pend_fault;
     }
 
-    value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys,
-                              res.attrs, &txres);
+    value = address_space_ldl(arm_addressspace(cs, res.f.attrs),
+                              res.f.phys_addr, res.f.attrs, &txres);
     if (txres != MEMTX_OK) {
         /* BusFault trying to read the data */
         qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n");
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure,
         qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL\n");
         return false;
     }
-    *insn = address_space_lduw_le(arm_addressspace(cs, res.attrs), res.phys,
-                                  res.attrs, &txres);
+    *insn = address_space_lduw_le(arm_addressspace(cs, res.f.attrs),
+                                  res.f.phys_addr, res.f.attrs, &txres);
     if (txres != MEMTX_OK) {
         env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK;
         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
         }
         return false;
     }
-    value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys,
-                              res.attrs, &txres);
+    value = address_space_ldl(arm_addressspace(cs, res.f.attrs),
+                              res.f.phys_addr, res.f.attrs, &txres);
     if (txres != MEMTX_OK) {
         /* BusFault trying to read the data */
         qemu_log_mask(CPU_LOG_INT,
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
         } else {
             mrvalid = true;
         }
-        r = res.prot & PAGE_READ;
-        rw = res.prot & PAGE_WRITE;
+        r = res.f.prot & PAGE_READ;
+        rw = res.f.prot & PAGE_WRITE;
     } else {
         r = false;
         rw = false;
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
             assert(!is_secure);
         }
 
-        addr = s2.phys;
+        addr = s2.f.phys_addr;
     }
     return addr;
 }
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
         /* 1Mb section.  */
         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
         ap = (desc >> 10) & 3;
-        result->page_size = 1024 * 1024;
+        result->f.lg_page_size = 20; /* 1MB */
     } else {
         /* Lookup l2 entry.  */
         if (type == 1) {
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
         case 1: /* 64k page.  */
             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
-            result->page_size = 0x10000;
+            result->f.lg_page_size = 16;
             break;
         case 2: /* 4k page.  */
             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
-            result->page_size = 0x1000;
+            result->f.lg_page_size = 12;
             break;
         case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
             if (type == 1) {
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
                 if (arm_feature(env, ARM_FEATURE_XSCALE)
                     || arm_feature(env, ARM_FEATURE_V6)) {
                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
-                    result->page_size = 0x1000;
+                    result->f.lg_page_size = 12;
                 } else {
                     /*
                      * UNPREDICTABLE in ARMv5; we choose to take a
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
                 }
             } else {
                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
-                result->page_size = 0x400;
+                result->f.lg_page_size = 10;
             }
             ap = (desc >> 4) & 3;
             break;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
             g_assert_not_reached();
         }
     }
-    result->prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
-    result->prot |= result->prot ? PAGE_EXEC : 0;
-    if (!(result->prot & (1 << access_type))) {
+    result->f.prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
+    result->f.prot |= result->f.prot ? PAGE_EXEC : 0;
+    if (!(result->f.prot & (1 << access_type))) {
         /* Access permission fault.  */
         fi->type = ARMFault_Permission;
         goto do_fault;
     }
-    result->phys = phys_addr;
+    result->f.phys_addr = phys_addr;
     return false;
 do_fault:
     fi->domain = domain;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
             phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
             phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
-            result->page_size = 0x1000000;
+            result->f.lg_page_size = 24;  /* 16MB */
         } else {
             /* Section.  */
             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
-            result->page_size = 0x100000;
+            result->f.lg_page_size = 20;  /* 1MB */
         }
         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
         xn = desc & (1 << 4);
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
         case 1: /* 64k page.  */
             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
             xn = desc & (1 << 15);
-            result->page_size = 0x10000;
+            result->f.lg_page_size = 16;
             break;
         case 2: case 3: /* 4k page.  */
             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
             xn = desc & 1;
-            result->page_size = 0x1000;
+            result->f.lg_page_size = 12;
             break;
         default:
             /* Never happens, but compiler isn't smart enough to tell.  */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
         }
     }
     if (domain_prot == 3) {
-        result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+        result->f.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
     } else {
         if (pxn && !regime_is_user(env, mmu_idx)) {
             xn = 1;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
                 fi->type = ARMFault_AccessFlag;
                 goto do_fault;
             }
-            result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
+            result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
         } else {
-            result->prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
+            result->f.prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
         }
-        if (result->prot && !xn) {
-            result->prot |= PAGE_EXEC;
+        if (result->f.prot && !xn) {
+            result->f.prot |= PAGE_EXEC;
         }
-        if (!(result->prot & (1 << access_type))) {
+        if (!(result->f.prot & (1 << access_type))) {
             /* Access permission fault.  */
             fi->type = ARMFault_Permission;
             goto do_fault;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
          * the CPU doesn't support TZ or this is a non-secure translation
          * regime, because the attribute will already be non-secure.
          */
-        result->attrs.secure = false;
+        result->f.attrs.secure = false;
     }
-    result->phys = phys_addr;
+    result->f.phys_addr = phys_addr;
     return false;
 do_fault:
     fi->domain = domain;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
     if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
         ns = mmu_idx == ARMMMUIdx_Stage2;
         xn = extract32(attrs, 11, 2);
-        result->prot = get_S2prot(env, ap, xn, s1_is_el0);
+        result->f.prot = get_S2prot(env, ap, xn, s1_is_el0);
     } else {
         ns = extract32(attrs, 3, 1);
         xn = extract32(attrs, 12, 1);
         pxn = extract32(attrs, 11, 1);
-        result->prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
+        result->f.prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
     }
 
     fault_type = ARMFault_Permission;
-    if (!(result->prot & (1 << access_type))) {
+    if (!(result->f.prot & (1 << access_type))) {
         goto do_fault;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
          * the CPU doesn't support TZ or this is a non-secure translation
          * regime, because the attribute will already be non-secure.
          */
-        result->attrs.secure = false;
+        result->f.attrs.secure = false;
     }
     /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.  */
     if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
-        arm_tlb_bti_gp(&result->attrs) = true;
+        arm_tlb_bti_gp(&result->f.attrs) = true;
     }
 
     if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
         result->cacheattrs.shareability = extract32(attrs, 6, 2);
     }
 
-    result->phys = descaddr;
-    result->page_size = page_size;
+    result->f.phys_addr = descaddr;
+    result->f.lg_page_size = ctz64(page_size);
     return false;
 
 do_fault:
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
 
     if (regime_translation_disabled(env, mmu_idx, is_secure)) {
         /* MPU disabled.  */
-        result->phys = address;
-        result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+        result->f.phys_addr = address;
+        result->f.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
         return false;
     }
 
-    result->phys = address;
+    result->f.phys_addr = address;
     for (n = 7; n >= 0; n--) {
         base = env->cp15.c6_region[n];
         if ((base & 1) == 0) {
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
             fi->level = 1;
             return true;
         }
-        result->prot = PAGE_READ | PAGE_WRITE;
+        result->f.prot = PAGE_READ | PAGE_WRITE;
         break;
     case 2:
-        result->prot = PAGE_READ;
+        result->f.prot = PAGE_READ;
         if (!is_user) {
-            result->prot |= PAGE_WRITE;
+            result->f.prot |= PAGE_WRITE;
         }
         break;
     case 3:
-        result->prot = PAGE_READ | PAGE_WRITE;
+        result->f.prot = PAGE_READ | PAGE_WRITE;
         break;
     case 5:
         if (is_user) {
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
             fi->level = 1;
             return true;
         }
-        result->prot = PAGE_READ;
+        result->f.prot = PAGE_READ;
         break;
     case 6:
-        result->prot = PAGE_READ;
+        result->f.prot = PAGE_READ;
         break;
     default:
         /* Bad permission.  */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
         fi->level = 1;
         return true;
     }
-    result->prot |= PAGE_EXEC;
+    result->f.prot |= PAGE_EXEC;
     return false;
 }
 
 static void get_phys_addr_pmsav7_default(CPUARMState *env, ARMMMUIdx mmu_idx,
-                                         int32_t address, int *prot)
+                                         int32_t address, uint8_t *prot)
 {
     if (!arm_feature(env, ARM_FEATURE_M)) {
         *prot = PAGE_READ | PAGE_WRITE;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
     int n;
     bool is_user = regime_is_user(env, mmu_idx);
 
-    result->phys = address;
-    result->page_size = TARGET_PAGE_SIZE;
-    result->prot = 0;
+    result->f.phys_addr = address;
+    result->f.lg_page_size = TARGET_PAGE_BITS;
+    result->f.prot = 0;
 
     if (regime_translation_disabled(env, mmu_idx, secure) ||
         m_is_ppb_region(env, address)) {
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
          * which always does a direct read using address_space_ldl(), rather
          * than going via this function, so we don't need to check that here.
          */
-        get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
+        get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.prot);
     } else { /* MPU enabled */
         for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
             /* region search */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
                 if (ranges_overlap(base, rmask,
                                    address & TARGET_PAGE_MASK,
                                    TARGET_PAGE_SIZE)) {
-                    result->page_size = 1;
+                    result->f.lg_page_size = 0;
                 }
                 continue;
             }
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
                 continue;
             }
             if (rsize < TARGET_PAGE_BITS) {
-                result->page_size = 1 << rsize;
+                result->f.lg_page_size = rsize;
             }
             break;
         }
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
                 fi->type = ARMFault_Background;
                 return true;
             }
-            get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
+            get_phys_addr_pmsav7_default(env, mmu_idx, address,
+                                         &result->f.prot);
         } else { /* a MPU hit! */
             uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
             uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1);
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
                 case 5:
                     break; /* no access */
                 case 3:
-                    result->prot |= PAGE_WRITE;
+                    result->f.prot |= PAGE_WRITE;
                     /* fall through */
                 case 2:
                 case 6:
-                    result->prot |= PAGE_READ | PAGE_EXEC;
+                    result->f.prot |= PAGE_READ | PAGE_EXEC;
                     break;
                 case 7:
                     /* for v7M, same as 6; for R profile a reserved value */
                     if (arm_feature(env, ARM_FEATURE_M)) {
-                        result->prot |= PAGE_READ | PAGE_EXEC;
+                        result->f.prot |= PAGE_READ | PAGE_EXEC;
                         break;
                     }
                     /* fall through */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
                 case 1:
                 case 2:
                 case 3:
-                    result->prot |= PAGE_WRITE;
+                    result->f.prot |= PAGE_WRITE;
                     /* fall through */
                 case 5:
                 case 6:
-                    result->prot |= PAGE_READ | PAGE_EXEC;
+                    result->f.prot |= PAGE_READ | PAGE_EXEC;
                     break;
                 case 7:
                     /* for v7M, same as 6; for R profile a reserved value */
                     if (arm_feature(env, ARM_FEATURE_M)) {
-                        result->prot |= PAGE_READ | PAGE_EXEC;
+                        result->f.prot |= PAGE_READ | PAGE_EXEC;
                         break;
                     }
                     /* fall through */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
 
             /* execute never */
             if (xn) {
-                result->prot &= ~PAGE_EXEC;
+                result->f.prot &= ~PAGE_EXEC;
             }
         }
     }
 
     fi->type = ARMFault_Permission;
     fi->level = 1;
-    return !(result->prot & (1 << access_type));
+    return !(result->f.prot & (1 << access_type));
 }
 
 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
     uint32_t addr_page_base = address & TARGET_PAGE_MASK;
     uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
 
-    result->page_size = TARGET_PAGE_SIZE;
-    result->phys = address;
-    result->prot = 0;
+    result->f.lg_page_size = TARGET_PAGE_BITS;
+    result->f.phys_addr = address;
+    result->f.prot = 0;
     if (mregion) {
         *mregion = -1;
     }
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
                     ranges_overlap(base, limit - base + 1,
                                    addr_page_base,
                                    TARGET_PAGE_SIZE)) {
-                    result->page_size = 1;
+                    result->f.lg_page_size = 0;
                 }
                 continue;
             }
 
             if (base > addr_page_base || limit < addr_page_limit) {
-                result->page_size = 1;
+                result->f.lg_page_size = 0;
             }
 
             if (matchregion != -1) {
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
 
     if (matchregion == -1) {
         /* hit using the background region */
-        get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
+        get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.prot);
     } else {
         uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
         uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
             xn = 1;
         }
 
-        result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
-        if (result->prot && !xn && !(pxn && !is_user)) {
-            result->prot |= PAGE_EXEC;
+        result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
+        if (result->f.prot && !xn && !(pxn && !is_user)) {
+            result->f.prot |= PAGE_EXEC;
         }
         /*
          * We don't need to look the attribute up in the MAIR0/MAIR1
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
 
     fi->type = ARMFault_Permission;
     fi->level = 1;
-    return !(result->prot & (1 << access_type));
+    return !(result->f.prot & (1 << access_type));
 }
 
 static bool v8m_is_sau_exempt(CPUARMState *env,
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
                 } else {
                     fi->type = ARMFault_QEMU_SFault;
                 }
-                result->page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
-                result->phys = address;
-                result->prot = 0;
+                result->f.lg_page_size = sattrs.subpage ? 0 : TARGET_PAGE_BITS;
+                result->f.phys_addr = address;
+                result->f.prot = 0;
                 return true;
             }
         } else {
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
              * might downgrade a secure access to nonsecure.
              */
             if (sattrs.ns) {
-                result->attrs.secure = false;
+                result->f.attrs.secure = false;
             } else if (!secure) {
                 /*
                  * NS access to S memory must fault.
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
                  * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
                  */
                 fi->type = ARMFault_QEMU_SFault;
-                result->page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
-                result->phys = address;
-                result->prot = 0;
+                result->f.lg_page_size = sattrs.subpage ? 0 : TARGET_PAGE_BITS;
+                result->f.phys_addr = address;
+                result->f.prot = 0;
                 return true;
             }
         }
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
     ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, secure,
                             result, fi, NULL);
     if (sattrs.subpage) {
-        result->page_size = 1;
+        result->f.lg_page_size = 0;
     }
     return ret;
 }
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
         result->cacheattrs.is_s2_format = false;
     }
 
-    result->phys = address;
-    result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
-    result->page_size = TARGET_PAGE_SIZE;
+    result->f.phys_addr = address;
+    result->f.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+    result->f.lg_page_size = TARGET_PAGE_BITS;
     result->cacheattrs.shareability = shareability;
     result->cacheattrs.attrs = memattr;
     return 0;
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
                 return ret;
             }
 
-            ipa = result->phys;
-            ipa_secure = result->attrs.secure;
+            ipa = result->f.phys_addr;
+            ipa_secure = result->f.attrs.secure;
             if (is_secure) {
                 /* Select TCR based on the NS bit from the S1 walk. */
                 s2walk_secure = !(ipa_secure
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
              * Save the stage1 results so that we may merge
              * prot and cacheattrs later.
              */
-            s1_prot = result->prot;
+            s1_prot = result->f.prot;
             cacheattrs1 = result->cacheattrs;
             memset(result, 0, sizeof(*result));
 
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
             fi->s2addr = ipa;
 
             /* Combine the S1 and S2 perms.  */
-            result->prot &= s1_prot;
+            result->f.prot &= s1_prot;
 
             /* If S2 fails, return early.  */
             if (ret) {
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
              * Check if IPA translates to secure or non-secure PA space.
              * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
              */
-            result->attrs.secure =
+            result->f.attrs.secure =
                 (is_secure
                  && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
                  && (ipa_secure
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
      * cannot upgrade an non-secure translation regime's attributes
      * to secure.
      */
-    result->attrs.secure = is_secure;
-    result->attrs.user = regime_is_user(env, mmu_idx);
+    result->f.attrs.secure = is_secure;
+    result->f.attrs.user = regime_is_user(env, mmu_idx);
 
     /*
      * Fast Context Switch Extension. This doesn't exist at all in v8.
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
 
     if (arm_feature(env, ARM_FEATURE_PMSA)) {
         bool ret;
-        result->page_size = TARGET_PAGE_SIZE;
+        result->f.lg_page_size = TARGET_PAGE_BITS;
 
         if (arm_feature(env, ARM_FEATURE_V8)) {
             /* PMSAv8 */
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
                       (access_type == MMU_DATA_STORE ? "writing" : "execute"),
                       (uint32_t)address, mmu_idx,
                       ret ? "Miss" : "Hit",
-                      result->prot & PAGE_READ ? 'r' : '-',
-                      result->prot & PAGE_WRITE ? 'w' : '-',
-                      result->prot & PAGE_EXEC ? 'x' : '-');
+                      result->f.prot & PAGE_READ ? 'r' : '-',
+                      result->f.prot & PAGE_WRITE ? 'w' : '-',
+                      result->f.prot & PAGE_EXEC ? 'x' : '-');
 
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
     bool ret;
 
     ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi);
-    *attrs = res.attrs;
+    *attrs = res.f.attrs;
 
     if (ret) {
         return -1;
     }
-    return res.phys;
+    return res.f.phys_addr;
 }
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
          * target page size are handled specially, so for those we
          * pass in the exact addresses.
          */
-        if (res.page_size >= TARGET_PAGE_SIZE) {
-            res.phys &= TARGET_PAGE_MASK;
+        if (res.f.lg_page_size >= TARGET_PAGE_BITS) {
+            res.f.phys_addr &= TARGET_PAGE_MASK;
             address &= TARGET_PAGE_MASK;
         }
         /* Notice and record tagged memory. */
         if (cpu_isar_feature(aa64_mte, cpu) && res.cacheattrs.attrs == 0xf0) {
-            arm_tlb_mte_tagged(&res.attrs) = true;
+            arm_tlb_mte_tagged(&res.f.attrs) = true;
         }
 
-        tlb_set_page_with_attrs(cs, address, res.phys, res.attrs,
-                                res.prot, mmu_idx, res.page_size);
+        tlb_set_page_full(cs, mmu_idx, address, &res.f);
         return true;
     } else if (probe) {
         return false;
-- 
2.25.1

From: Jerome Forissier <jerome.forissier@linaro.org>

According to the Linux kernel booting.rst [1], CPTR_EL3.ESM and
SCR_EL3.EnTP2 must be initialized to 1 when EL3 is present and FEAT_SME
is advertised. This has to be taken care of when QEMU boots directly
into the kernel (i.e., "-M virt,secure=on -cpu max -kernel Image").

Cc: qemu-stable@nongnu.org
Fixes: 78cb9776662a ("target/arm: Enable SME for -cpu max")
Link: [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/arm64/booting.rst?h=v6.0#n321
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Message-id: 20221003145641.1921467-1-jerome.forissier@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/boot.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
                     if (cpu_isar_feature(aa64_sve, cpu)) {
                         env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
                     }
+                    if (cpu_isar_feature(aa64_sme, cpu)) {
+                        env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
+                        env->cp15.scr_el3 |= SCR_ENTP2;
+                    }
                     /* AArch64 kernels never boot in secure mode */
                     assert(!info->secure_boot);
                     /* This hook is only supported for AArch32 currently:
-- 
2.25.1

Arm CPUs support some subset of the granule (page) sizes 4K, 16K and
64K.  The guest selects the one it wants using bits in the TCR_ELx
registers.  If it tries to program these registers with a value that
is either reserved or which requests a size that the CPU does not
implement, the architecture requires that the CPU behaves as if the
field was programmed to some size that has been implemented.
Currently we don't implement this, and instead let the guest use any
granule size, even if the CPU ID register fields say it isn't
present.

Make aa64_va_parameters() check against the supported granule size
and force use of a different one if it is not implemented.

(A subsequent commit will make ARMVAParameters use the new enum
rather than the current pair of using16k/using64k bools.)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221003162315.2833797-2-peter.maydell@linaro.org
---
 target/arm/cpu.h       |  33 +++++++++++++
 target/arm/internals.h |   9 ++++
 target/arm/helper.c    | 102 +++++++++++++++++++++++++++++++++++++----
 3 files changed, 136 insertions(+), 8 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
     return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
 }
 
+static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id)
+{
+    return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0;
+}
+
+static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1;
+}
+
+static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id)
+{
+    return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0;
+}
+
+static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id)
+{
+    unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
+    return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id));
+}
+
+static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id)
+{
+    unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
+    return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id));
+}
+
+static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
+{
+    unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2);
+    return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
+}
+
 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
     return valid;
 }
 
+/* Granule size (i.e. page size) */
+typedef enum ARMGranuleSize {
+    /* Same order as TG0 encoding */
+    Gran4K,
+    Gran64K,
+    Gran16K,
+    GranInvalid,
+} ARMGranuleSize;
+
 /*
  * Parameters of a given virtual address, as extracted from the
  * translation control register (TCR) for a given regime.
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx)
     }
 }
 
+static ARMGranuleSize tg0_to_gran_size(int tg)
+{
+    switch (tg) {
+    case 0:
+        return Gran4K;
+    case 1:
+        return Gran64K;
+    case 2:
+        return Gran16K;
+    default:
+        return GranInvalid;
+    }
+}
+
+static ARMGranuleSize tg1_to_gran_size(int tg)
+{
+    switch (tg) {
+    case 1:
+        return Gran16K;
+    case 2:
+        return Gran4K;
+    case 3:
+        return Gran64K;
+    default:
+        return GranInvalid;
+    }
+}
+
+static inline bool have4k(ARMCPU *cpu, bool stage2)
+{
+    return stage2 ? cpu_isar_feature(aa64_tgran4_2, cpu)
+        : cpu_isar_feature(aa64_tgran4, cpu);
+}
+
+static inline bool have16k(ARMCPU *cpu, bool stage2)
+{
+    return stage2 ? cpu_isar_feature(aa64_tgran16_2, cpu)
+        : cpu_isar_feature(aa64_tgran16, cpu);
+}
+
+static inline bool have64k(ARMCPU *cpu, bool stage2)
+{
+    return stage2 ? cpu_isar_feature(aa64_tgran64_2, cpu)
+        : cpu_isar_feature(aa64_tgran64, cpu);
+}
+
+static ARMGranuleSize sanitize_gran_size(ARMCPU *cpu, ARMGranuleSize gran,
+                                         bool stage2)
+{
+    switch (gran) {
+    case Gran4K:
+        if (have4k(cpu, stage2)) {
+            return gran;
+        }
+        break;
+    case Gran16K:
+        if (have16k(cpu, stage2)) {
+            return gran;
+        }
+        break;
+    case Gran64K:
+        if (have64k(cpu, stage2)) {
+            return gran;
+        }
+        break;
+    case GranInvalid:
+        break;
+    }
+    /*
+     * If the guest selects a granule size that isn't implemented,
+     * the architecture requires that we behave as if it selected one
+     * that is (with an IMPDEF choice of which one to pick). We choose
+     * to implement the smallest supported granule size.
+     */
+    if (have4k(cpu, stage2)) {
+        return Gran4K;
+    }
+    if (have16k(cpu, stage2)) {
+        return Gran16K;
+    }
+    assert(have64k(cpu, stage2));
+    return Gran64K;
+}
+
 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
                                    ARMMMUIdx mmu_idx, bool data)
 {
     uint64_t tcr = regime_tcr(env, mmu_idx);
     bool epd, hpd, using16k, using64k, tsz_oob, ds;
     int select, tsz, tbi, max_tsz, min_tsz, ps, sh;
+    ARMGranuleSize gran;
     ARMCPU *cpu = env_archcpu(env);
+    bool stage2 = mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S;
 
     if (!regime_has_2_ranges(mmu_idx)) {
         select = 0;
         tsz = extract32(tcr, 0, 6);
-        using64k = extract32(tcr, 14, 1);
-        using16k = extract32(tcr, 15, 1);
-        if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
+        gran = tg0_to_gran_size(extract32(tcr, 14, 2));
+        if (stage2) {
             /* VTCR_EL2 */
             hpd = false;
         } else {
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
         select = extract64(va, 55, 1);
         if (!select) {
             tsz = extract32(tcr, 0, 6);
+            gran = tg0_to_gran_size(extract32(tcr, 14, 2));
             epd = extract32(tcr, 7, 1);
             sh = extract32(tcr, 12, 2);
-            using64k = extract32(tcr, 14, 1);
-            using16k = extract32(tcr, 15, 1);
             hpd = extract64(tcr, 41, 1);
         } else {
-            int tg = extract32(tcr, 30, 2);
-            using16k = tg == 1;
-            using64k = tg == 3;
             tsz = extract32(tcr, 16, 6);
+            gran = tg1_to_gran_size(extract32(tcr, 30, 2));
             epd = extract32(tcr, 23, 1);
             sh = extract32(tcr, 28, 2);
             hpd = extract64(tcr, 42, 1);
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
         ds = extract64(tcr, 59, 1);
     }
 
+    gran = sanitize_gran_size(cpu, gran, stage2);
+    using64k = gran == Gran64K;
+    using16k = gran == Gran16K;
+
     if (cpu_isar_feature(aa64_st, cpu)) {
         max_tsz = 48 - using64k;
     } else {
-- 
2.25.1

Now we have an enum for the granule size, use it in the
ARMVAParameters struct instead of the using16k/using64k bools.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221003162315.2833797-3-peter.maydell@linaro.org
---
 target/arm/internals.h | 23 +++++++++++++++++++++--
 target/arm/helper.c    | 39 ++++++++++++++++++++++++++++-----------
 target/arm/ptw.c       |  8 +-------
 3 files changed, 50 insertions(+), 20 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ typedef enum ARMGranuleSize {
     GranInvalid,
 } ARMGranuleSize;
 
+/**
+ * arm_granule_bits: Return address size of the granule in bits
+ *
+ * Return the address size of the granule in bits. This corresponds
+ * to the pseudocode TGxGranuleBits().
+ */
+static inline int arm_granule_bits(ARMGranuleSize gran)
+{
+    switch (gran) {
+    case Gran64K:
+        return 16;
+    case Gran16K:
+        return 14;
+    case Gran4K:
+        return 12;
+    default:
+        g_assert_not_reached();
+    }
+}
+
 /*
  * Parameters of a given virtual address, as extracted from the
  * translation control register (TCR) for a given regime.
@@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters {
     bool tbi        : 1;
     bool epd        : 1;
     bool hpd        : 1;
-    bool using16k   : 1;
-    bool using64k   : 1;
     bool tsz_oob    : 1;  /* tsz has been clamped to legal range */
     bool ds         : 1;
+    ARMGranuleSize gran : 2;
 } ARMVAParameters;
 
 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
     uint64_t length;
 } TLBIRange;
 
+static ARMGranuleSize tlbi_range_tg_to_gran_size(int tg)
+{
+    /*
+     * Note that the TLBI range TG field encoding differs from both
+     * TG0 and TG1 encodings.
+     */
+    switch (tg) {
+    case 1:
+        return Gran4K;
+    case 2:
+        return Gran16K;
+    case 3:
+        return Gran64K;
+    default:
+        return GranInvalid;
+    }
+}
+
 static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
                                      uint64_t value)
 {
@@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
     uint64_t select = sextract64(value, 36, 1);
     ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true);
     TLBIRange ret = { };
+    ARMGranuleSize gran;
 
     page_size_granule = extract64(value, 46, 2);
+    gran = tlbi_range_tg_to_gran_size(page_size_granule);
 
     /* The granule encoded in value must match the granule in use. */
-    if (page_size_granule != (param.using64k ? 3 : param.using16k ? 2 : 1)) {
+    if (gran != param.gran) {
         qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\n",
                       page_size_granule);
         return ret;
     }
 
-    page_shift = (page_size_granule - 1) * 2 + 12;
+    page_shift = arm_granule_bits(gran);
     num = extract64(value, 39, 5);
     scale = extract64(value, 44, 2);
     exponent = (5 * scale) + 1;
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
                                    ARMMMUIdx mmu_idx, bool data)
 {
     uint64_t tcr = regime_tcr(env, mmu_idx);
-    bool epd, hpd, using16k, using64k, tsz_oob, ds;
+    bool epd, hpd, tsz_oob, ds;
     int select, tsz, tbi, max_tsz, min_tsz, ps, sh;
     ARMGranuleSize gran;
     ARMCPU *cpu = env_archcpu(env);
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
     }
 
     gran = sanitize_gran_size(cpu, gran, stage2);
-    using64k = gran == Gran64K;
-    using16k = gran == Gran16K;
 
     if (cpu_isar_feature(aa64_st, cpu)) {
-        max_tsz = 48 - using64k;
+        max_tsz = 48 - (gran == Gran64K);
     } else {
         max_tsz = 39;
     }
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
      * adjust the effective value of DS, as documented.
      */
     min_tsz = 16;
-    if (using64k) {
+    if (gran == Gran64K) {
         if (cpu_isar_feature(aa64_lva, cpu)) {
             min_tsz = 12;
         }
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
         switch (mmu_idx) {
         case ARMMMUIdx_Stage2:
         case ARMMMUIdx_Stage2_S:
-            if (using16k) {
+            if (gran == Gran16K) {
                 ds = cpu_isar_feature(aa64_tgran16_2_lpa2, cpu);
             } else {
                 ds = cpu_isar_feature(aa64_tgran4_2_lpa2, cpu);
             }
             break;
         default:
-            if (using16k) {
+            if (gran == Gran16K) {
                 ds = cpu_isar_feature(aa64_tgran16_lpa2, cpu);
             } else {
                 ds = cpu_isar_feature(aa64_tgran4_lpa2, cpu);
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
         .tbi = tbi,
         .epd = epd,
         .hpd = hpd,
-        .using16k = using16k,
-        .using64k = using64k,
         .tsz_oob = tsz_oob,
         .ds = ds,
+        .gran = gran,
     };
 }
 
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
         }
     }
 
-    if (param.using64k) {
-        stride = 13;
-    } else if (param.using16k) {
-        stride = 11;
-    } else {
-        stride = 9;
-    }
+    stride = arm_granule_bits(param.gran) - 3;
 
     /*
      * Note that QEMU ignores shareability and cacheability attributes,
-- 
2.25.1

FEAT_GTG is a change tho the ID register ID_AA64MMFR0_EL1 so that it
can report a different set of supported granule (page) sizes for
stage 1 and stage 2 translation tables.  As of commit c20281b2a5048
we already report the granule sizes that way for '-cpu max', and now
we also correctly make attempts to use unimplemented granule sizes
fail, so we can report the support of the feature in the
documentation.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221003162315.2833797-4-peter.maydell@linaro.org
---
 docs/system/arm/emulation.rst | 1 +
 1 file changed, 1 insertion(+)

Hi; here's the first target-arm pullreq for the 8.1 cycle.
Nothing particularly huge in here, just the various things
that had accumulated during the freeze.

thanks
-- PMM

The following changes since commit 2d82c32b2ceaca3dc3da5e36e10976f34bfcb598:

Open 8.1 development tree (2023-04-20 10:05:25 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230420

for you to fetch changes up to 1ed1f338520cda0574b7e04f5e8e85e049740548:

arm/mcimx7d-sabre: Set fec2-phy-connected property to false (2023-04-20 10:46:43 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/arm: Fix some typos in comments (most found by codespell)
 * exynos: Fix out-of-bounds access in exynos4210_gcomp_find debug printf
 * Orangepi-PC, Cubieboard: add Allwinner WDT watchdog emulation
 * tests/avocado: Add reboot tests to Cubieboard
 * hw/timer/imx_epit: Fix bugs in timer limit checking
 * target/arm: Remove KVM AArch32 CPU definitions
 * hw/arm/virt: Restrict Cortex-A7 check to TCG
 * target/arm: Initialize debug capabilities only once
 * target/arm: Implement FEAT_PAN3
 * docs/devel/kconfig.rst: Fix incorrect markup
 * target/arm: Report pauth information to gdb as 'pauth_v2'
 * mcimxd7-sabre, mcimx6ul-evk: Correctly model the way the PHY
   on the second ethernet device must be configured via the
   first one

----------------------------------------------------------------
Akihiko Odaki (1):
      target/arm: Initialize debug capabilities only once

Axel Heider (2):
      hw/timer/imx_epit: don't shadow variable
      hw/timer/imx_epit: fix limit check

Feng Jiang (1):
      exynos: Fix out-of-bounds access in exynos4210_gcomp_find debug printf

Guenter Roeck (5):
      hw/net/imx_fec: Support two Ethernet interfaces connected to single MDIO bus
      fsl-imx6ul: Add fec[12]-phy-connected properties
      arm/mcimx6ul-evk: Set fec1-phy-connected property to false
      fsl-imx7: Add fec[12]-phy-connected properties
      arm/mcimx7d-sabre: Set fec2-phy-connected property to false

Peter Maydell (5):
      target/arm: Pass ARMMMUFaultInfo to merge_syn_data_abort()
      target/arm: Don't set ISV when reporting stage 1 faults in ESR_EL2
      target/arm: Implement FEAT_PAN3
      docs/devel/kconfig.rst: Fix incorrect markup
      target/arm: Report pauth information to gdb as 'pauth_v2'

Philippe Mathieu-Daudé (2):
      target/arm: Remove KVM AArch32 CPU definitions
      hw/arm/virt: Restrict Cortex-A7 check to TCG

Stefan Weil (1):
      hw/arm: Fix some typos in comments (most found by codespell)

Strahinja Jankovic (4):
      hw/watchdog: Allwinner WDT emulation for system reset
      hw/arm: Add WDT to Allwinner-A10 and Cubieboard
      hw/arm: Add WDT to Allwinner-H3 and Orangepi-PC
      tests/avocado: Add reboot tests to Cubieboard

From: Stefan Weil <sw@weilnetz.de>

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230409200526.1156456-1-sw@weilnetz.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/exynos4210.c       | 4 ++--
 hw/arm/musicpal.c         | 2 +-
 hw/arm/omap1.c            | 2 +-
 hw/arm/omap2.c            | 2 +-
 hw/arm/virt-acpi-build.c  | 2 +-
 hw/arm/virt.c             | 2 +-
 hw/arm/xlnx-versal-virt.c | 2 +-
 hw/arm/Kconfig            | 2 +-
 8 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static int mapline_size(const int *mapline)
 
 /*
  * Initialize board IRQs.
- * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
+ * These IRQs contain split Int/External Combiner and External Gic IRQs.
  */
 static void exynos4210_init_board_irqs(Exynos4210State *s)
 {
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
          * - SDMA
          * - ADMA2
          *
-         * As this part of the Exynos4210 is not publically available,
+         * As this part of the Exynos4210 is not publicly available,
          * we used the "HS-MMC Controller S3C2416X RISC Microprocessor"
          * public datasheet which is very similar (implementing
          * MMC Specification Version 4.0 being the only difference noted)
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -XXX,XX +XXX,XX @@
 #define MP_LCD_SPI_CMD          0x00104011
 #define MP_LCD_SPI_INVALID      0x00000000
 
-/* Commmands */
+/* Commands */
 #define MP_LCD_INST_SETPAGE0    0xB0
 /* ... */
 #define MP_LCD_INST_SETPAGE7    0xB7
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap1.c
+++ b/hw/arm/omap1.c
@@ -XXX,XX +XXX,XX @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
     s->led[1] = omap_lpg_init(system_memory,
                               0xfffbd800, omap_findclk(s, "clk32-kHz"));
 
-    /* Register mappings not currenlty implemented:
+    /* Register mappings not currently implemented:
      * MCSI2 Comm	fffb2000 - fffb27ff (not mapped on OMAP310)
      * MCSI1 Bluetooth	fffb2800 - fffb2fff (not mapped on OMAP310)
      * USB W2FC		fffb4000 - fffb47ff
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap2.c
+++ b/hw/arm/omap2.c
@@ -XXX,XX +XXX,XX @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
                     omap_findclk(s, "func_96m_clk"),
                     omap_findclk(s, "core_l4_iclk"));
 
-    /* All register mappings (includin those not currenlty implemented):
+    /* All register mappings (including those not currently implemented):
      * SystemControlMod	48000000 - 48000fff
      * SystemControlL4	48001000 - 48001fff
      * 32kHz Timer Mod	48004000 - 48004fff
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -XXX,XX +XXX,XX @@ static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size)
     build_append_int_noprefix(table_data, 0xE, 1);  /* Type */
     build_append_int_noprefix(table_data, 16, 1);   /* Length */
     build_append_int_noprefix(table_data, 0, 2);    /* Reserved */
-    /* Discovery Range Base Addres */
+    /* Discovery Range Base Address */
     build_append_int_noprefix(table_data, base, 8);
     build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */
 }
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
         int pa_bits;
 
         /*
-         * Instanciate a temporary CPU object to find out about what
+         * Instantiate a temporary CPU object to find out about what
          * we are about to deal with. Once this is done, get rid of
          * the object.
          */
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
     fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
 
     /* Make the APU cpu address space visible to virtio and other
-     * modules unaware of muliple address-spaces.  */
+     * modules unaware of multiple address-spaces.  */
     memory_region_add_subregion_overlap(get_system_memory(),
                                         0, &s->soc.fpd.apu.mr, 0);
 
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config OLIMEX_STM32_H405
 config NSERIES
     bool
     select OMAP
-    select TMP105   # tempature sensor
+    select TMP105   # temperature sensor
     select BLIZZARD # LCD/TV controller
     select ONENAND
     select TSC210X  # touchscreen/sensors/audio
-- 
2.34.1

From: Feng Jiang <jiangfeng@kylinos.cn>

One of the debug printfs in exynos4210_gcomp_find() will
access outside the 's->g_timer.reg.comp[]' array if there
was no active comparator and 'res' is -1. Add a conditional
to avoid this.

This doesn't happen in normal use because the debug printfs
are by default not compiled in.

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Message-id: 20230404074506.112615-1-jiangfeng@kylinos.cn
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: Adjusted commit message to clarify that the overrun
only happens if you've enabled debug printfs]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/timer/exynos4210_mct.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/exynos4210_mct.c
+++ b/hw/timer/exynos4210_mct.c
@@ -XXX,XX +XXX,XX @@ static int32_t exynos4210_gcomp_find(Exynos4210MCTState *s)
         res = min_comp_i;
     }
 
-    DPRINTF("found comparator %d: comp 0x%llx distance 0x%llx, gfrc 0x%llx\n",
-            res,
-            s->g_timer.reg.comp[res],
-            distance_min,
-            gfrc);
+    if (res >= 0) {
+        DPRINTF("found comparator %d: "
+                "comp 0x%llx distance 0x%llx, gfrc 0x%llx\n",
+                res,
+                s->g_timer.reg.comp[res],
+                distance_min,
+                gfrc);
+    }
 
     return res;
 }
-- 
2.34.1

From: Strahinja Jankovic <strahinjapjankovic@gmail.com>

This patch adds basic support for Allwinner WDT.
Both sun4i and sun6i variants are supported.
However, interrupt generation is not supported, so WDT can be used only to trigger system reset.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20230326202256.22980-2-strahinja.p.jankovic@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/watchdog/allwinner-wdt.h | 123 ++++++++
 hw/watchdog/allwinner-wdt.c         | 416 ++++++++++++++++++++++++++++
 hw/watchdog/Kconfig                 |   4 +
 hw/watchdog/meson.build             |   1 +
 hw/watchdog/trace-events            |   7 +
 5 files changed, 551 insertions(+)
 create mode 100644 include/hw/watchdog/allwinner-wdt.h
 create mode 100644 hw/watchdog/allwinner-wdt.c

diff --git a/include/hw/watchdog/allwinner-wdt.h b/include/hw/watchdog/allwinner-wdt.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/watchdog/allwinner-wdt.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Allwinner Watchdog emulation
+ *
+ * Copyright (C) 2023 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+ *
+ *  This file is derived from Allwinner RTC,
+ *  by Niek Linnenbank.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_WATCHDOG_ALLWINNER_WDT_H
+#define HW_WATCHDOG_ALLWINNER_WDT_H
+
+#include "qom/object.h"
+#include "hw/ptimer.h"
+#include "hw/sysbus.h"
+
+/*
+ * This is a model of the Allwinner watchdog.
+ * Since watchdog registers belong to the timer module (and are shared with the
+ * RTC module), the interrupt line from watchdog is not handled right now.
+ * In QEMU, we just wire up the watchdog reset to watchdog_perform_action(),
+ * at least for the moment.
+ */
+
+#define TYPE_AW_WDT    "allwinner-wdt"
+
+/** Allwinner WDT sun4i family (A10, A12), also sun7i (A20) */
+#define TYPE_AW_WDT_SUN4I    TYPE_AW_WDT "-sun4i"
+
+/** Allwinner WDT sun6i family and newer (A31, H2+, H3, etc) */
+#define TYPE_AW_WDT_SUN6I    TYPE_AW_WDT "-sun6i"
+
+/** Number of WDT registers */
+#define AW_WDT_REGS_NUM      (5)
+
+OBJECT_DECLARE_TYPE(AwWdtState, AwWdtClass, AW_WDT)
+
+/**
+ * Allwinner WDT object instance state.
+ */
+struct AwWdtState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
+    MemoryRegion iomem;
+    struct ptimer_state *timer;
+
+    uint32_t regs[AW_WDT_REGS_NUM];
+};
+
+/**
+ * Allwinner WDT class-level struct.
+ *
+ * This struct is filled by each sunxi device specific code
+ * such that the generic code can use this struct to support
+ * all devices.
+ */
+struct AwWdtClass {
+    /*< private >*/
+    SysBusDeviceClass parent_class;
+    /*< public >*/
+
+    /** Defines device specific register map */
+    const uint8_t *regmap;
+
+    /** Size of the regmap in bytes */
+    size_t regmap_size;
+
+    /**
+     * Read device specific register
+     *
+     * @offset: register offset to read
+     * @return true if register read successful, false otherwise
+     */
+    bool (*read)(AwWdtState *s, uint32_t offset);
+
+    /**
+     * Write device specific register
+     *
+     * @offset: register offset to write
+     * @data: value to set in register
+     * @return true if register write successful, false otherwise
+     */
+    bool (*write)(AwWdtState *s, uint32_t offset, uint32_t data);
+
+    /**
+     * Check if watchdog can generate system reset
+     *
+     * @return true if watchdog can generate system reset
+     */
+    bool (*can_reset_system)(AwWdtState *s);
+
+    /**
+     * Check if provided key is valid
+     *
+     * @value: value written to register
+     * @return true if key is valid, false otherwise
+     */
+    bool (*is_key_valid)(AwWdtState *s, uint32_t val);
+
+    /**
+     * Get current INTV_VALUE setting
+     *
+     * @return current INTV_VALUE (0-15)
+     */
+    uint8_t (*get_intv_value)(AwWdtState *s);
+};
+
+#endif /* HW_WATCHDOG_ALLWINNER_WDT_H */
diff --git a/hw/watchdog/allwinner-wdt.c b/hw/watchdog/allwinner-wdt.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/watchdog/allwinner-wdt.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Allwinner Watchdog emulation
+ *
+ * Copyright (C) 2023 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+ *
+ *  This file is derived from Allwinner RTC,
+ *  by Niek Linnenbank.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/units.h"
+#include "qemu/module.h"
+#include "trace.h"
+#include "hw/sysbus.h"
+#include "hw/registerfields.h"
+#include "hw/watchdog/allwinner-wdt.h"
+#include "sysemu/watchdog.h"
+#include "migration/vmstate.h"
+
+/* WDT registers */
+enum {
+    REG_IRQ_EN = 0,     /* Watchdog interrupt enable */
+    REG_IRQ_STA,        /* Watchdog interrupt status */
+    REG_CTRL,           /* Watchdog control register */
+    REG_CFG,            /* Watchdog configuration register */
+    REG_MODE,           /* Watchdog mode register */
+};
+
+/* Universal WDT register flags */
+#define WDT_RESTART_MASK    (1 << 0)
+#define WDT_EN_MASK         (1 << 0)
+
+/* sun4i specific WDT register flags */
+#define RST_EN_SUN4I_MASK       (1 << 1)
+#define INTV_VALUE_SUN4I_SHIFT  (3)
+#define INTV_VALUE_SUN4I_MASK   (0xfu << INTV_VALUE_SUN4I_SHIFT)
+
+/* sun6i specific WDT register flags */
+#define RST_EN_SUN6I_MASK       (1 << 0)
+#define KEY_FIELD_SUN6I_SHIFT   (1)
+#define KEY_FIELD_SUN6I_MASK    (0xfffu << KEY_FIELD_SUN6I_SHIFT)
+#define KEY_FIELD_SUN6I         (0xA57u)
+#define INTV_VALUE_SUN6I_SHIFT  (4)
+#define INTV_VALUE_SUN6I_MASK   (0xfu << INTV_VALUE_SUN6I_SHIFT)
+
+/* Map of INTV_VALUE to 0.5s units. */
+static const uint8_t allwinner_wdt_count_map[] = {
+    1,
+    2,
+    4,
+    6,
+    8,
+    10,
+    12,
+    16,
+    20,
+    24,
+    28,
+    32
+};
+
+/* WDT sun4i register map (offset to name) */
+const uint8_t allwinner_wdt_sun4i_regmap[] = {
+    [0x0000] = REG_CTRL,
+    [0x0004] = REG_MODE,
+};
+
+/* WDT sun6i register map (offset to name) */
+const uint8_t allwinner_wdt_sun6i_regmap[] = {
+    [0x0000] = REG_IRQ_EN,
+    [0x0004] = REG_IRQ_STA,
+    [0x0010] = REG_CTRL,
+    [0x0014] = REG_CFG,
+    [0x0018] = REG_MODE,
+};
+
+static bool allwinner_wdt_sun4i_read(AwWdtState *s, uint32_t offset)
+{
+    /* no sun4i specific registers currently implemented */
+    return false;
+}
+
+static bool allwinner_wdt_sun4i_write(AwWdtState *s, uint32_t offset,
+                                      uint32_t data)
+{
+    /* no sun4i specific registers currently implemented */
+    return false;
+}
+
+static bool allwinner_wdt_sun4i_can_reset_system(AwWdtState *s)
+{
+    if (s->regs[REG_MODE] & RST_EN_SUN4I_MASK) {
+        return true;
+    } else {
+        return false;
+    }
+}
+
+static bool allwinner_wdt_sun4i_is_key_valid(AwWdtState *s, uint32_t val)
+{
+    /* sun4i has no key */
+    return true;
+}
+
+static uint8_t allwinner_wdt_sun4i_get_intv_value(AwWdtState *s)
+{
+    return ((s->regs[REG_MODE] & INTV_VALUE_SUN4I_MASK) >>
+            INTV_VALUE_SUN4I_SHIFT);
+}
+
+static bool allwinner_wdt_sun6i_read(AwWdtState *s, uint32_t offset)
+{
+    const AwWdtClass *c = AW_WDT_GET_CLASS(s);
+
+    switch (c->regmap[offset]) {
+    case REG_IRQ_EN:
+    case REG_IRQ_STA:
+    case REG_CFG:
+        return true;
+    default:
+        break;
+    }
+    return false;
+}
+
+static bool allwinner_wdt_sun6i_write(AwWdtState *s, uint32_t offset,
+                                      uint32_t data)
+{
+    const AwWdtClass *c = AW_WDT_GET_CLASS(s);
+
+    switch (c->regmap[offset]) {
+    case REG_IRQ_EN:
+    case REG_IRQ_STA:
+    case REG_CFG:
+        return true;
+    default:
+        break;
+    }
+    return false;
+}
+
+static bool allwinner_wdt_sun6i_can_reset_system(AwWdtState *s)
+{
+    if (s->regs[REG_CFG] & RST_EN_SUN6I_MASK) {
+        return true;
+    } else {
+        return false;
+    }
+}
+
+static bool allwinner_wdt_sun6i_is_key_valid(AwWdtState *s, uint32_t val)
+{
+    uint16_t key = (val & KEY_FIELD_SUN6I_MASK) >> KEY_FIELD_SUN6I_SHIFT;
+    return (key == KEY_FIELD_SUN6I);
+}
+
+static uint8_t allwinner_wdt_sun6i_get_intv_value(AwWdtState *s)
+{
+    return ((s->regs[REG_MODE] & INTV_VALUE_SUN6I_MASK) >>
+            INTV_VALUE_SUN6I_SHIFT);
+}
+
+static void allwinner_wdt_update_timer(AwWdtState *s)
+{
+    const AwWdtClass *c = AW_WDT_GET_CLASS(s);
+    uint8_t count = c->get_intv_value(s);
+
+    ptimer_transaction_begin(s->timer);
+    ptimer_stop(s->timer);
+
+    /* Use map to convert. */
+    if (count < sizeof(allwinner_wdt_count_map)) {
+        ptimer_set_count(s->timer, allwinner_wdt_count_map[count]);
+    } else {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: incorrect INTV_VALUE 0x%02x\n",
+                __func__, count);
+    }
+
+    ptimer_run(s->timer, 1);
+    ptimer_transaction_commit(s->timer);
+
+    trace_allwinner_wdt_update_timer(count);
+}
+
+static uint64_t allwinner_wdt_read(void *opaque, hwaddr offset,
+                                       unsigned size)
+{
+    AwWdtState *s = AW_WDT(opaque);
+    const AwWdtClass *c = AW_WDT_GET_CLASS(s);
+    uint64_t r;
+
+    if (offset >= c->regmap_size) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+                      __func__, (uint32_t)offset);
+        return 0;
+    }
+
+    switch (c->regmap[offset]) {
+    case REG_CTRL:
+    case REG_MODE:
+        r = s->regs[c->regmap[offset]];
+        break;
+    default:
+        if (!c->read(s, offset)) {
+            qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
+                            __func__, (uint32_t)offset);
+            return 0;
+        }
+        r = s->regs[c->regmap[offset]];
+        break;
+    }
+
+    trace_allwinner_wdt_read(offset, r, size);
+
+    return r;
+}
+
+static void allwinner_wdt_write(void *opaque, hwaddr offset,
+                                   uint64_t val, unsigned size)
+{
+    AwWdtState *s = AW_WDT(opaque);
+    const AwWdtClass *c = AW_WDT_GET_CLASS(s);
+    uint32_t old_val;
+
+    if (offset >= c->regmap_size) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+                      __func__, (uint32_t)offset);
+        return;
+    }
+
+   trace_allwinner_wdt_write(offset, val, size);
+
+    switch (c->regmap[offset]) {
+    case REG_CTRL:
+        if (c->is_key_valid(s, val)) {
+            if (val & WDT_RESTART_MASK) {
+                /* Kick timer */
+                allwinner_wdt_update_timer(s);
+            }
+        }
+        break;
+    case REG_MODE:
+        old_val = s->regs[REG_MODE];
+        s->regs[REG_MODE] = (uint32_t)val;
+
+        /* Check for rising edge on WDOG_MODE_EN */
+        if ((s->regs[REG_MODE] & ~old_val) & WDT_EN_MASK) {
+            allwinner_wdt_update_timer(s);
+        }
+        break;
+    default:
+        if (!c->write(s, offset, val)) {
+            qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
+                          __func__, (uint32_t)offset);
+        }
+        s->regs[c->regmap[offset]] = (uint32_t)val;
+        break;
+    }
+}
+
+static const MemoryRegionOps allwinner_wdt_ops = {
+    .read = allwinner_wdt_read,
+    .write = allwinner_wdt_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+    .impl.min_access_size = 4,
+};
+
+static void allwinner_wdt_expired(void *opaque)
+{
+    AwWdtState *s = AW_WDT(opaque);
+    const AwWdtClass *c = AW_WDT_GET_CLASS(s);
+
+    bool enabled = s->regs[REG_MODE] & WDT_EN_MASK;
+    bool reset_enabled = c->can_reset_system(s);
+
+    trace_allwinner_wdt_expired(enabled, reset_enabled);
+
+    /* Perform watchdog action if watchdog is enabled and can trigger reset */
+    if (enabled && reset_enabled) {
+        watchdog_perform_action();
+    }
+}
+
+static void allwinner_wdt_reset_enter(Object *obj, ResetType type)
+{
+    AwWdtState *s = AW_WDT(obj);
+
+    trace_allwinner_wdt_reset_enter();
+
+    /* Clear registers */
+    memset(s->regs, 0, sizeof(s->regs));
+}
+
+static const VMStateDescription allwinner_wdt_vmstate = {
+    .name = "allwinner-wdt",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_PTIMER(timer, AwWdtState),
+        VMSTATE_UINT32_ARRAY(regs, AwWdtState, AW_WDT_REGS_NUM),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void allwinner_wdt_init(Object *obj)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    AwWdtState *s = AW_WDT(obj);
+    const AwWdtClass *c = AW_WDT_GET_CLASS(s);
+
+    /* Memory mapping */
+    memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_wdt_ops, s,
+                          TYPE_AW_WDT, c->regmap_size * 4);
+    sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static void allwinner_wdt_realize(DeviceState *dev, Error **errp)
+{
+    AwWdtState *s = AW_WDT(dev);
+
+    s->timer = ptimer_init(allwinner_wdt_expired, s,
+                           PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
+                           PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
+                           PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
+
+    ptimer_transaction_begin(s->timer);
+    /* Set to 2Hz (0.5s period); other periods are multiples of 0.5s. */
+    ptimer_set_freq(s->timer, 2);
+    ptimer_set_limit(s->timer, 0xff, 1);
+    ptimer_transaction_commit(s->timer);
+}
+
+static void allwinner_wdt_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+    rc->phases.enter = allwinner_wdt_reset_enter;
+    dc->realize = allwinner_wdt_realize;
+    dc->vmsd = &allwinner_wdt_vmstate;
+}
+
+static void allwinner_wdt_sun4i_class_init(ObjectClass *klass, void *data)
+{
+    AwWdtClass *awc = AW_WDT_CLASS(klass);
+
+    awc->regmap = allwinner_wdt_sun4i_regmap;
+    awc->regmap_size = sizeof(allwinner_wdt_sun4i_regmap);
+    awc->read = allwinner_wdt_sun4i_read;
+    awc->write = allwinner_wdt_sun4i_write;
+    awc->can_reset_system = allwinner_wdt_sun4i_can_reset_system;
+    awc->is_key_valid = allwinner_wdt_sun4i_is_key_valid;
+    awc->get_intv_value = allwinner_wdt_sun4i_get_intv_value;
+}
+
+static void allwinner_wdt_sun6i_class_init(ObjectClass *klass, void *data)
+{
+    AwWdtClass *awc = AW_WDT_CLASS(klass);
+
+    awc->regmap = allwinner_wdt_sun6i_regmap;
+    awc->regmap_size = sizeof(allwinner_wdt_sun6i_regmap);
+    awc->read = allwinner_wdt_sun6i_read;
+    awc->write = allwinner_wdt_sun6i_write;
+    awc->can_reset_system = allwinner_wdt_sun6i_can_reset_system;
+    awc->is_key_valid = allwinner_wdt_sun6i_is_key_valid;
+    awc->get_intv_value = allwinner_wdt_sun6i_get_intv_value;
+}
+
+static const TypeInfo allwinner_wdt_info = {
+    .name          = TYPE_AW_WDT,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_init = allwinner_wdt_init,
+    .instance_size = sizeof(AwWdtState),
+    .class_init    = allwinner_wdt_class_init,
+    .class_size    = sizeof(AwWdtClass),
+    .abstract      = true,
+};
+
+static const TypeInfo allwinner_wdt_sun4i_info = {
+    .name          = TYPE_AW_WDT_SUN4I,
+    .parent        = TYPE_AW_WDT,
+    .class_init    = allwinner_wdt_sun4i_class_init,
+};
+
+static const TypeInfo allwinner_wdt_sun6i_info = {
+    .name          = TYPE_AW_WDT_SUN6I,
+    .parent        = TYPE_AW_WDT,
+    .class_init    = allwinner_wdt_sun6i_class_init,
+};
+
+static void allwinner_wdt_register(void)
+{
+    type_register_static(&allwinner_wdt_info);
+    type_register_static(&allwinner_wdt_sun4i_info);
+    type_register_static(&allwinner_wdt_sun6i_info);
+}
+
+type_init(allwinner_wdt_register)
diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/watchdog/Kconfig
+++ b/hw/watchdog/Kconfig
@@ -XXX,XX +XXX,XX @@ config WDT_IMX2
 
 config WDT_SBSA
     bool
+
+config ALLWINNER_WDT
+    bool
+    select PTIMER
diff --git a/hw/watchdog/meson.build b/hw/watchdog/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/watchdog/meson.build
+++ b/hw/watchdog/meson.build
@@ -XXX,XX +XXX,XX @@
 softmmu_ss.add(files('watchdog.c'))
+softmmu_ss.add(when: 'CONFIG_ALLWINNER_WDT', if_true: files('allwinner-wdt.c'))
 softmmu_ss.add(when: 'CONFIG_CMSDK_APB_WATCHDOG', if_true: files('cmsdk-apb-watchdog.c'))
 softmmu_ss.add(when: 'CONFIG_WDT_IB6300ESB', if_true: files('wdt_i6300esb.c'))
 softmmu_ss.add(when: 'CONFIG_WDT_IB700', if_true: files('wdt_ib700.c'))
diff --git a/hw/watchdog/trace-events b/hw/watchdog/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/watchdog/trace-events
+++ b/hw/watchdog/trace-events
@@ -XXX,XX +XXX,XX @@
 # See docs/devel/tracing.rst for syntax documentation.
 
+# allwinner-wdt.c
+allwinner_wdt_read(uint64_t offset, uint64_t data, unsigned size) "Allwinner watchdog read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
+allwinner_wdt_write(uint64_t offset, uint64_t data, unsigned size) "Allwinner watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
+allwinner_wdt_reset_enter(void) "Allwinner watchdog: reset"
+allwinner_wdt_update_timer(uint8_t count) "Allwinner watchdog: count %" PRIu8
+allwinner_wdt_expired(bool enabled, bool reset_enabled) "Allwinner watchdog: enabled %u reset_enabled %u"
+
 # cmsdk-apb-watchdog.c
 cmsdk_apb_watchdog_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 cmsdk_apb_watchdog_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
-- 
2.34.1

From: Strahinja Jankovic <strahinjapjankovic@gmail.com>

This patch adds WDT to Allwinner-A10 and Cubieboard.
WDT is added as an overlay to the Timer module memory map.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20230326202256.22980-3-strahinja.p.jankovic@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/cubieboard.rst | 1 +
 include/hw/arm/allwinner-a10.h | 2 ++
 hw/arm/allwinner-a10.c         | 7 +++++++
 hw/arm/Kconfig                 | 1 +
 4 files changed, 11 insertions(+)

diff --git a/docs/system/arm/cubieboard.rst b/docs/system/arm/cubieboard.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/cubieboard.rst
+++ b/docs/system/arm/cubieboard.rst
@@ -XXX,XX +XXX,XX @@ Emulated devices:
 - USB controller
 - SATA controller
 - TWI (I2C) controller
+- Watchdog timer
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/allwinner-a10-ccm.h"
 #include "hw/misc/allwinner-a10-dramc.h"
 #include "hw/i2c/allwinner-i2c.h"
+#include "hw/watchdog/allwinner-wdt.h"
 #include "sysemu/block-backend.h"
 
 #include "target/arm/cpu.h"
@@ -XXX,XX +XXX,XX @@ struct AwA10State {
     AwSdHostState mmc0;
     AWI2CState i2c0;
     AwRtcState rtc;
+    AwWdtState wdt;
     MemoryRegion sram_a;
     EHCISysBusState ehci[AW_A10_NUM_USB];
     OHCISysBusState ohci[AW_A10_NUM_USB];
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -XXX,XX +XXX,XX @@
 #define AW_A10_EHCI_BASE        0x01c14000
 #define AW_A10_OHCI_BASE        0x01c14400
 #define AW_A10_SATA_BASE        0x01c18000
+#define AW_A10_WDT_BASE         0x01c20c90
 #define AW_A10_RTC_BASE         0x01c20d00
 #define AW_A10_I2C0_BASE        0x01c2ac00
 
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
     object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I);
 
     object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I);
+
+    object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I);
 }
 
 static void aw_a10_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7));
+
+    /* WDT */
+    sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);
+    sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0, AW_A10_WDT_BASE, 1);
 }
 
 static void aw_a10_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
     select ALLWINNER_A10_PIC
     select ALLWINNER_A10_CCM
     select ALLWINNER_A10_DRAMC
+    select ALLWINNER_WDT
     select ALLWINNER_EMAC
     select ALLWINNER_I2C
     select AXP209_PMU
-- 
2.34.1

From: Strahinja Jankovic <strahinjapjankovic@gmail.com>

This patch adds WDT to Allwinner-H3 and Orangepi-PC.
WDT is added as an overlay to the Timer module memory area.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20230326202256.22980-4-strahinja.p.jankovic@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/orangepi.rst  | 1 +
 include/hw/arm/allwinner-h3.h | 5 ++++-
 hw/arm/allwinner-h3.c         | 8 ++++++++
 hw/arm/Kconfig                | 1 +
 4 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/orangepi.rst
+++ b/docs/system/arm/orangepi.rst
@@ -XXX,XX +XXX,XX @@ The Orange Pi PC machine supports the following devices:
  * System Control module
  * Security Identifier device
  * TWI (I2C)
+ * Watchdog timer
 
 Limitations
 """""""""""
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/net/allwinner-sun8i-emac.h"
 #include "hw/rtc/allwinner-rtc.h"
 #include "hw/i2c/allwinner-i2c.h"
+#include "hw/watchdog/allwinner-wdt.h"
 #include "target/arm/cpu.h"
 #include "sysemu/block-backend.h"
 
@@ -XXX,XX +XXX,XX @@ enum {
     AW_H3_DEV_RTC,
     AW_H3_DEV_CPUCFG,
     AW_H3_DEV_R_TWI,
-    AW_H3_DEV_SDRAM
+    AW_H3_DEV_SDRAM,
+    AW_H3_DEV_WDT
 };
 
 /** Total number of CPU cores in the H3 SoC */
@@ -XXX,XX +XXX,XX @@ struct AwH3State {
     AWI2CState r_twi;
     AwSun8iEmacState emac;
     AwRtcState rtc;
+    AwWdtState wdt;
     GICState gic;
     MemoryRegion sram_a1;
     MemoryRegion sram_a2;
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
     [AW_H3_DEV_OHCI3]      = 0x01c1d400,
     [AW_H3_DEV_CCU]        = 0x01c20000,
     [AW_H3_DEV_PIT]        = 0x01c20c00,
+    [AW_H3_DEV_WDT]        = 0x01c20ca0,
     [AW_H3_DEV_UART0]      = 0x01c28000,
     [AW_H3_DEV_UART1]      = 0x01c28400,
     [AW_H3_DEV_UART2]      = 0x01c28800,
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
     object_initialize_child(obj, "twi1",  &s->i2c1,  TYPE_AW_I2C_SUN6I);
     object_initialize_child(obj, "twi2",  &s->i2c2,  TYPE_AW_I2C_SUN6I);
     object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I);
+
+    object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN6I);
 }
 
 static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0,
                        qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI));
 
+    /* WDT */
+    sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);
+    sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0,
+                            s->memmap[AW_H3_DEV_WDT], 1);
+
     /* Unimplemented devices */
     for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
         create_unimplemented_device(unimplemented[i].device_name,
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
     select ALLWINNER_A10_PIT
     select ALLWINNER_SUN8I_EMAC
     select ALLWINNER_I2C
+    select ALLWINNER_WDT
     select SERIAL
     select ARM_TIMER
     select ARM_GIC
-- 
2.34.1

From: Strahinja Jankovic <strahinjapjankovic@gmail.com>

Cubieboard tests end with comment "reboot not functioning; omit test".
Fix this so reboot is done at the end of each test.

diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self):
                                                 'Allwinner sun4i/sun5i')
         exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
                                                 'system-control@1c00000')
-        # cubieboard's reboot is not functioning; omit reboot test.
+        exec_command_and_wait_for_pattern(self, 'reboot',
+                                                'reboot: Restarting system')
+        # Wait for VM to shut down gracefully
+        self.vm.wait()
 
     def test_arm_cubieboard_sata(self):
         """
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_sata(self):
                                                 'Allwinner sun4i/sun5i')
         exec_command_and_wait_for_pattern(self, 'cat /proc/partitions',
                                                 'sda')
-        # cubieboard's reboot is not functioning; omit reboot test.
+        exec_command_and_wait_for_pattern(self, 'reboot',
+                                                'reboot: Restarting system')
+        # Wait for VM to shut down gracefully
+        self.vm.wait()
 
     @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
     def test_arm_cubieboard_openwrt_22_03_2(self):
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_openwrt_22_03_2(self):
 
         exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
                                                 'Allwinner sun4i/sun5i')
-        # cubieboard's reboot is not functioning; omit reboot test.
+        exec_command_and_wait_for_pattern(self, 'reboot',
+                                                'reboot: Restarting system')
+        # Wait for VM to shut down gracefully
+        self.vm.wait()
 
     @skipUnless(os.getenv('AVOCADO_TIMEOUT_EXPECTED'), 'Test might timeout')
     def test_arm_quanta_gsj(self):
-- 
2.34.1

From: Axel Heider <axel.heider@hensoldt.net>

Fix the limit check. If the limit is less than the compare value,
the timer can never reach this value, thus it will never fire.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1491
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Message-id: 168070611775.20412.2883242077302841473-2@git.sr.ht
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/timer/imx_epit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -XXX,XX +XXX,XX @@ static void imx_epit_update_compare_timer(IMXEPITState *s)
          * the compare value. Otherwise it may fire at most once in the
          * current round.
          */
-        is_oneshot = (limit >= s->cmp);
+        is_oneshot = (limit < s->cmp);
         if (counter >= s->cmp) {
             /* The compare timer fires in the current round. */
             counter -= s->cmp;
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Missed in commit 80485d88f9 ("target/arm: Restrict
v7A TCG cpus to TCG accel").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230405100848.76145-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm-consts.h | 9 +++------
 target/arm/cpu_tcg.c    | 2 --
 2 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm-consts.h
+++ b/target/arm/kvm-consts.h
@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_RET_INTERNAL_FAILURE, PSCI_RET_INTERNAL_FAILURE);
 MISMATCH_CHECK(QEMU_PSCI_RET_NOT_PRESENT, PSCI_RET_NOT_PRESENT);
 MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED);
 
-/* Note that KVM uses overlapping values for AArch32 and AArch64
- * target CPU numbers. AArch32 targets:
+/*
+ * Note that KVM uses overlapping values for AArch32 and AArch64
+ * target CPU numbers. AArch64 targets:
  */
-#define QEMU_KVM_ARM_TARGET_CORTEX_A15 0
-#define QEMU_KVM_ARM_TARGET_CORTEX_A7 1
-
-/* AArch64 targets: */
 #define QEMU_KVM_ARM_TARGET_AEM_V8 0
 #define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1
 #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_EL2);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
     set_feature(&cpu->env, ARM_FEATURE_PMU);
-    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
     cpu->midr = 0x410fc075;
     cpu->reset_fpsid = 0x41023075;
     cpu->isar.mvfr0 = 0x10110222;
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_EL2);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
     set_feature(&cpu->env, ARM_FEATURE_PMU);
-    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
     /* r4p0 cpu, not requiring expensive tlb flush errata */
     cpu->midr = 0x414fc0f0;
     cpu->revidr = 0x0;
-- 
2.34.1

From: Akihiko Odaki <akihiko.odaki@daynix.com>

kvm_arm_init_debug() used to be called several times on a SMP system as
kvm_arch_init_vcpu() calls it. Move the call to kvm_arch_init() to make
sure it will be called only once; otherwise it will overwrite pointers
to memory allocated with the previous call and leak it.

Fixes: e4482ab7e3 ("target-arm: kvm - add support for HW assisted debug")
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-id: 20230405153644.25300-1-akihiko.odaki@daynix.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm_arm.h |  8 ++++++++
 target/arm/kvm.c     |  2 ++
 target/arm/kvm64.c   | 18 ++++--------------
 3 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@
 #define KVM_ARM_VGIC_V2   (1 << 0)
 #define KVM_ARM_VGIC_V3   (1 << 1)
 
+/**
+ * kvm_arm_init_debug() - initialize guest debug capabilities
+ * @s: KVMState
+ *
+ * Should be called only once before using guest debug capabilities.
+ */
+void kvm_arm_init_debug(KVMState *s);
+
 /**
  * kvm_arm_vcpu_init:
  * @cs: CPUState
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s)
         }
     }
 
+    kvm_arm_init_debug(s);
+
     return ret;
 }
 
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ GArray *hw_breakpoints, *hw_watchpoints;
 #define get_hw_bp(i)    (&g_array_index(hw_breakpoints, HWBreakpoint, i))
 #define get_hw_wp(i)    (&g_array_index(hw_watchpoints, HWWatchpoint, i))
 
-/**
- * kvm_arm_init_debug() - check for guest debug capabilities
- * @cs: CPUState
- *
- * kvm_check_extension returns the number of debug registers we have
- * or 0 if we have none.
- *
- */
-static void kvm_arm_init_debug(CPUState *cs)
+void kvm_arm_init_debug(KVMState *s)
 {
-    have_guest_debug = kvm_check_extension(cs->kvm_state,
+    have_guest_debug = kvm_check_extension(s,
                                            KVM_CAP_SET_GUEST_DEBUG);
 
-    max_hw_wps = kvm_check_extension(cs->kvm_state, KVM_CAP_GUEST_DEBUG_HW_WPS);
+    max_hw_wps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS);
     hw_watchpoints = g_array_sized_new(true, true,
                                        sizeof(HWWatchpoint), max_hw_wps);
 
-    max_hw_bps = kvm_check_extension(cs->kvm_state, KVM_CAP_GUEST_DEBUG_HW_BPS);
+    max_hw_bps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_BPS);
     hw_breakpoints = g_array_sized_new(true, true,
                                        sizeof(HWBreakpoint), max_hw_bps);
     return;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
     }
     cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK;
 
-    kvm_arm_init_debug(cs);
-
     /* Check whether user space can specify guest syndrome value */
     kvm_arm_init_serror_injection(cs);
 
-- 
2.34.1

We already pass merge_syn_data_abort() two fields from the
ARMMMUFaultInfo struct, and we're about to want to use a third field.
Refactor to just pass a pointer to the fault info.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230331145045.2584941-2-peter.maydell@linaro.org
---
 target/arm/tcg/tlb_helper.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/tlb_helper.c
+++ b/target/arm/tcg/tlb_helper.c
@@ -XXX,XX +XXX,XX @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
 }
 
 static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
+                                            ARMMMUFaultInfo *fi,
                                             unsigned int target_el,
-                                            bool same_el, bool ea,
-                                            bool s1ptw, bool is_write,
+                                            bool same_el, bool is_write,
                                             int fsc)
 {
     uint32_t syn;
@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
      * ISS encoding for an exception from a Data Abort, the
      * ISV field.
      */
-    if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) {
+    if (!(template_syn & ARM_EL_ISV) || target_el != 2 || fi->s1ptw) {
         syn = syn_data_abort_no_iss(same_el, 0,
-                                    ea, 0, s1ptw, is_write, fsc);
+                                    fi->ea, 0, fi->s1ptw, is_write, fsc);
     } else {
         /*
          * Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
          */
         syn = syn_data_abort_with_iss(same_el,
                                       0, 0, 0, 0, 0,
-                                      ea, 0, s1ptw, is_write, fsc,
+                                      fi->ea, 0, fi->s1ptw, is_write, fsc,
                                       true);
         /* Merge the runtime syndrome with the template syndrome.  */
         syn |= template_syn;
@@ -XXX,XX +XXX,XX @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr,
         syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);
         exc = EXCP_PREFETCH_ABORT;
     } else {
-        syn = merge_syn_data_abort(env->exception.syndrome, target_el,
-                                   same_el, fi->ea, fi->s1ptw,
-                                   access_type == MMU_DATA_STORE,
+        syn = merge_syn_data_abort(env->exception.syndrome, fi, target_el,
+                                   same_el, access_type == MMU_DATA_STORE,
                                    fsc);
         if (access_type == MMU_DATA_STORE
             && arm_feature(env, ARM_FEATURE_V6)) {
-- 
2.34.1

The syndrome value reported to ESR_EL2 should only contain the
detailed instruction syndrome information when the fault has been
caused by a stage 2 abort, not when the fault was a stage 1 abort
(i.e.  caused by execution at EL2).  We were getting this wrong and
reporting the detailed ISV information all the time.

Fix the bug by checking fi->stage2.  Add a TODO comment noting the
cases where we'll have to come back and revisit this when we
implement FEAT_LS64 and friends.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230331145045.2584941-3-peter.maydell@linaro.org
---
 target/arm/tcg/tlb_helper.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/tlb_helper.c
+++ b/target/arm/tcg/tlb_helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
     uint32_t syn;
 
     /*
-     * ISV is only set for data aborts routed to EL2 and
-     * never for stage-1 page table walks faulting on stage 2.
+     * ISV is only set for stage-2 data aborts routed to EL2 and
+     * never for stage-1 page table walks faulting on stage 2
+     * or for stage-1 faults.
      *
      * Furthermore, ISV is only set for certain kinds of load/stores.
      * If the template syndrome does not have ISV set, we should leave
@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
      * See ARMv8 specs, D7-1974:
      * ISS encoding for an exception from a Data Abort, the
      * ISV field.
+     *
+     * TODO: FEAT_LS64/FEAT_LS64_V/FEAT_SL64_ACCDATA: Translation,
+     * Access Flag, and Permission faults caused by LD64B, ST64B,
+     * ST64BV, or ST64BV0 insns report syndrome info even for stage-1
+     * faults and regardless of the target EL.
      */
-    if (!(template_syn & ARM_EL_ISV) || target_el != 2 || fi->s1ptw) {
+    if (!(template_syn & ARM_EL_ISV) || target_el != 2
+        || fi->s1ptw || !fi->stage2) {
         syn = syn_data_abort_no_iss(same_el, 0,
                                     fi->ea, 0, fi->s1ptw, is_write, fsc);
     } else {
-- 
2.34.1

FEAT_PAN3 adds an EPAN bit to SCTLR_EL1 and SCTLR_EL2, which allows
the PAN bit to make memory non-privileged-read/write if it is
user-executable as well as if it is user-read/write.

Implement this feature and enable it in the AArch64 'max' CPU.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230331145045.2584941-4-peter.maydell@linaro.org
---
 docs/system/arm/emulation.rst |  1 +
 target/arm/cpu.h              |  5 +++++
 target/arm/cpu64.c            |  2 +-
 target/arm/ptw.c              | 14 +++++++++++++-
 4 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_MTE3 (MTE Asymmetric Fault Handling)
 - FEAT_PAN (Privileged access never)
 - FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN)
+- FEAT_PAN3 (Support for SCTLR_ELx.EPAN)
 - FEAT_PAuth (Pointer authentication)
 - FEAT_PMULL (PMULL, PMULL2 instructions)
 - FEAT_PMUv3p1 (PMU Extensions v3.1)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
 }
 
+static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 3;
+}
+
 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
     t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
     t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
-    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2);      /* FEAT_PAN2 */
+    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3);      /* FEAT_PAN3 */
     t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
     t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1);      /* FEAT_ETS */
     t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1);      /* FEAT_HCX */
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)
 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
                       int ap, int ns, int xn, int pxn)
 {
+    ARMCPU *cpu = env_archcpu(env);
     bool is_user = regime_is_user(env, mmu_idx);
     int prot_rw, user_rw;
     bool have_wxn;
@@ -XXX,XX +XXX,XX @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
     if (is_user) {
         prot_rw = user_rw;
     } else {
+        /*
+         * PAN controls can forbid data accesses but don't affect insn fetch.
+         * Plain PAN forbids data accesses if EL0 has data permissions;
+         * PAN3 forbids data accesses if EL0 has either data or exec perms.
+         * Note that for AArch64 the 'user can exec' case is exactly !xn.
+         * We make the IMPDEF choices that SCR_EL3.SIF and Realm EL2&0
+         * do not affect EPAN.
+         */
         if (user_rw && regime_is_pan(env, mmu_idx)) {
-            /* PAN forbids data accesses but doesn't affect insn fetch */
+            prot_rw = 0;
+        } else if (cpu_isar_feature(aa64_pan3, cpu) && is_aa64 &&
+                   regime_is_pan(env, mmu_idx) &&
+                   (regime_sctlr(env, mmu_idx) & SCTLR_EPAN) && !xn) {
             prot_rw = 0;
         } else {
             prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
-- 
2.34.1

In rST markup syntax, the inline markup (*italics*, **bold** and
``monospaced``) must be separated from the surrending text by
non-word characters, otherwise it is not interpreted as markup.
To force interpretation as markup in the middle of a word,
you need to use a backslash-escaped space (which will not
appear as a space in the output).

Fix a missing backslash-space in this file, which meant that the ``
after "select" was output literally and the monospacing was
incorrectly extended all the way to the end of the next monospaced
word.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230411105424.3994585-1-peter.maydell@linaro.org
---
 docs/devel/kconfig.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/devel/kconfig.rst b/docs/devel/kconfig.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/devel/kconfig.rst
+++ b/docs/devel/kconfig.rst
@@ -XXX,XX +XXX,XX @@ or commenting out lines in the second group.
 
 It is also possible to run QEMU's configure script with the
 ``--without-default-devices`` option.  When this is done, everything defaults
-to ``n`` unless it is ``select``ed or explicitly switched on in the
+to ``n`` unless it is ``select``\ ed or explicitly switched on in the
 ``.mak`` files.  In other words, ``default`` and ``imply`` directives
 are disabled.  When QEMU is built with this option, the user will probably
 want to change some lines in the first group, for example like this::
-- 
2.34.1

So that we can avoid the "older gdb crashes" problem described in
commit 5787d17a42f7af4 and which caused us to disable reporting pauth
information via the gdbstub, newer gdb is going to implement support
for recognizing the pauth information via a new feature name:
 org.gnu.gdb.aarch64.pauth_v2

Older gdb won't recognize this feature name, so we can re-enable the
pauth support under the new name without risking them crashing.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230406150827.3322670-1-peter.maydell@linaro.org
---
 target/arm/gdbstub.c      | 9 ++++-----
 gdb-xml/aarch64-pauth.xml | 2 +-
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
                                      aarch64_gdb_set_fpu_reg,
                                      34, "aarch64-fpu.xml", 0);
         }
-#if 0
         /*
-         * GDB versions 9 through 12 have a bug which means they will
-         * crash if they see this XML from QEMU; disable it for the 8.0
-         * release, pending a better solution.
+         * Note that we report pauth information via the feature name
+         * org.gnu.gdb.aarch64.pauth_v2, not org.gnu.gdb.aarch64.pauth.
+         * GDB versions 9 through 12 have a bug where they will crash
+         * if they see the latter XML from QEMU.
          */
         if (isar_feature_aa64_pauth(&cpu->isar)) {
             gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg,
                                      aarch64_gdb_set_pauth_reg,
                                      4, "aarch64-pauth.xml", 0);
         }
-#endif
 #endif
     } else {
         if (arm_feature(env, ARM_FEATURE_NEON)) {
diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml
index XXXXXXX..XXXXXXX 100644
--- a/gdb-xml/aarch64-pauth.xml
+++ b/gdb-xml/aarch64-pauth.xml
@@ -XXX,XX +XXX,XX @@
      notice and this notice are preserved.  -->
 
 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
-<feature name="org.gnu.gdb.aarch64.pauth">
+<feature name="org.gnu.gdb.aarch64.pauth_v2">
   <reg name="pauth_dmask" bitsize="64"/>
   <reg name="pauth_cmask" bitsize="64"/>
   <reg name="pauth_dmask_high" bitsize="64"/>
-- 
2.34.1

From: Guenter Roeck <linux@roeck-us.net>

The SOC on i.MX6UL and i.MX7 has 2 Ethernet interfaces. The PHY on each may
be connected to separate MDIO busses, or both may be connected on the same
MDIO bus using different PHY addresses. Commit 461c51ad4275 ("Add a phy-num
property to the i.MX FEC emulator") added support for specifying PHY
addresses, but it did not provide support for linking the second PHY on
a given MDIO bus to the other Ethernet interface.

To be able to support two PHY instances on a single MDIO bus, two properties
are needed: First, there needs to be a flag indicating if the MDIO bus on
a given Ethernet interface is connected. If not, attempts to read from this
bus must always return 0xffff. Implement this property as phy-connected.
Second, if the MDIO bus on an interface is active, it needs a link to the
consumer interface to be able to provide PHY access for it. Implement this
property as phy-consumer.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20230315145248.1639364-2-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/net/imx_fec.h |  2 ++
 hw/net/imx_fec.c         | 27 +++++++++++++++++++++++----
 2 files changed, 25 insertions(+), 4 deletions(-)

diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/net/imx_fec.h
+++ b/include/hw/net/imx_fec.h
@@ -XXX,XX +XXX,XX @@ struct IMXFECState {
     uint32_t phy_int;
     uint32_t phy_int_mask;
     uint32_t phy_num;
+    bool phy_connected;
+    struct IMXFECState *phy_consumer;
 
     bool is_fec;
 
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
     uint32_t val;
     uint32_t phy = reg / 32;
 
-    if (phy != s->phy_num) {
-        trace_imx_phy_read_num(phy, s->phy_num);
+    if (!s->phy_connected) {
         return 0xffff;
     }
 
+    if (phy != s->phy_num) {
+        if (s->phy_consumer && phy == s->phy_consumer->phy_num) {
+            s = s->phy_consumer;
+        } else {
+            trace_imx_phy_read_num(phy, s->phy_num);
+            return 0xffff;
+        }
+    }
+
     reg %= 32;
 
     switch (reg) {
@@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
 {
     uint32_t phy = reg / 32;
 
-    if (phy != s->phy_num) {
-        trace_imx_phy_write_num(phy, s->phy_num);
+    if (!s->phy_connected) {
         return;
     }
 
+    if (phy != s->phy_num) {
+        if (s->phy_consumer && phy == s->phy_consumer->phy_num) {
+            s = s->phy_consumer;
+        } else {
+            trace_imx_phy_write_num(phy, s->phy_num);
+            return;
+        }
+    }
+
     reg %= 32;
 
     trace_imx_phy_write(val, phy, reg);
@@ -XXX,XX +XXX,XX @@ static Property imx_eth_properties[] = {
     DEFINE_NIC_PROPERTIES(IMXFECState, conf),
     DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1),
     DEFINE_PROP_UINT32("phy-num", IMXFECState, phy_num, 0),
+    DEFINE_PROP_BOOL("phy-connected", IMXFECState, phy_connected, true),
+    DEFINE_PROP_LINK("phy-consumer", IMXFECState, phy_consumer, TYPE_IMX_FEC,
+                     IMXFECState *),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
2.34.1

From: Guenter Roeck <linux@roeck-us.net>

Add fec[12]-phy-connected properties and use it to set phy-connected
and phy-consumer properties for imx_fec.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20230315145248.1639364-3-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h |  1 +
 hw/arm/fsl-imx6ul.c         | 20 ++++++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
     MemoryRegion       ocram_alias;
 
     uint32_t           phy_num[FSL_IMX6UL_NUM_ETHS];
+    bool               phy_connected[FSL_IMX6UL_NUM_ETHS];
 };
 
 enum FslIMX6ULMemoryMap {
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
 
     /*
      * Ethernet
+     *
+     * We must use two loops since phy_connected affects the other interface
+     * and we have to set all properties before calling sysbus_realize().
      */
+    for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
+        object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected",
+                                 s->phy_connected[i], &error_abort);
+        /*
+         * If the MDIO bus on this controller is not connected, assume the
+         * other controller provides support for it.
+         */
+        if (!s->phy_connected[i]) {
+            object_property_set_link(OBJECT(&s->eth[1 - i]), "phy-consumer",
+                                     OBJECT(&s->eth[i]), &error_abort);
+        }
+    }
+
     for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
         static const hwaddr FSL_IMX6UL_ENETn_ADDR[FSL_IMX6UL_NUM_ETHS] = {
             FSL_IMX6UL_ENET1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
 static Property fsl_imx6ul_properties[] = {
     DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0),
     DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1),
+    DEFINE_PROP_BOOL("fec1-phy-connected", FslIMX6ULState, phy_connected[0],
+                     true),
+    DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX6ULState, phy_connected[1],
+                     true),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
2.34.1

From: Guenter Roeck <linux@roeck-us.net>

On mcimx6ul-evk, the MDIO bus is connected to the second Ethernet
interface. Set fec1-phy-connected to false to reflect this.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20230315145248.1639364-4-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/mcimx6ul-evk.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mcimx6ul-evk.c
+++ b/hw/arm/mcimx6ul-evk.c
@@ -XXX,XX +XXX,XX @@ static void mcimx6ul_evk_init(MachineState *machine)
     object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
     object_property_set_uint(OBJECT(s), "fec1-phy-num", 2, &error_fatal);
     object_property_set_uint(OBJECT(s), "fec2-phy-num", 1, &error_fatal);
+    object_property_set_bool(OBJECT(s), "fec1-phy-connected", false,
+                             &error_fatal);
     qdev_realize(DEVICE(s), NULL, &error_fatal);
 
     memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR,
-- 
2.34.1

From: Guenter Roeck <linux@roeck-us.net>

Add fec[12]-phy-connected properties and use it to set phy-connected
and phy-consumer properties for imx_fec.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20230315145248.1639364-5-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h |  1 +
 hw/arm/fsl-imx7.c         | 20 ++++++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
     ChipideaState      usb[FSL_IMX7_NUM_USBS];
     DesignwarePCIEHost pcie;
     uint32_t           phy_num[FSL_IMX7_NUM_ETHS];
+    bool               phy_connected[FSL_IMX7_NUM_ETHS];
 };
 
 enum FslIMX7MemoryMap {
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
 
     /*
      * Ethernet
+     *
+     * We must use two loops since phy_connected affects the other interface
+     * and we have to set all properties before calling sysbus_realize().
      */
+    for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
+        object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected",
+                                 s->phy_connected[i], &error_abort);
+        /*
+         * If the MDIO bus on this controller is not connected, assume the
+         * other controller provides support for it.
+         */
+        if (!s->phy_connected[i]) {
+            object_property_set_link(OBJECT(&s->eth[1 - i]), "phy-consumer",
+                                     OBJECT(&s->eth[i]), &error_abort);
+        }
+    }
+
     for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
         static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] = {
             FSL_IMX7_ENET1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
 static Property fsl_imx7_properties[] = {
     DEFINE_PROP_UINT32("fec1-phy-num", FslIMX7State, phy_num[0], 0),
     DEFINE_PROP_UINT32("fec2-phy-num", FslIMX7State, phy_num[1], 1),
+    DEFINE_PROP_BOOL("fec1-phy-connected", FslIMX7State, phy_connected[0],
+                     true),
+    DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX7State, phy_connected[1],
+                     true),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
2.34.1

From: Guenter Roeck <linux@roeck-us.net>

On mcimx7d-sabre, the MDIO bus is connected to the first Ethernet
interface. Set fec2-phy-connected to false to reflect this.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20230315145248.1639364-6-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/mcimx7d-sabre.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mcimx7d-sabre.c
+++ b/hw/arm/mcimx7d-sabre.c
@@ -XXX,XX +XXX,XX @@ static void mcimx7d_sabre_init(MachineState *machine)
 
     s = FSL_IMX7(object_new(TYPE_FSL_IMX7));
     object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
+    object_property_set_bool(OBJECT(s), "fec2-phy-connected", false,
+                             &error_fatal);
     qdev_realize(DEVICE(s), NULL, &error_fatal);
 
     memory_region_add_subregion(get_system_memory(), FSL_IMX7_MMDC_ADDR,
-- 
2.34.1