Series comparison

-[PULL 00/10] target-arm queue
+[PULL 00/30] target-arm queue
-Hi; not so many patches in this one, but notably it includes the
+The following changes since commit 003ba52a8b327180e284630b289c6ece5a3e08b9:
 fix for various Avocado CI tests failing (incorrectly reported by
 Avocado as a timeout, but really a QEMU exit-with-error).
-thanks
+  Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-02-16 11:16:39 +0000)
 -- PMM
 The following changes since commit c8de6ec63d766ca1998c5af468483ce912fdc0c2:
   Merge tag 'pull-request-2022-09-28' of https://gitlab.com/thuth/qemu into staging (2022-09-28 17:04:11 -0400)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220930
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230216
-for you to fetch changes up to beeec926d24aac28f95cc7694ef3837d7a4cd3bb:
+for you to fetch changes up to caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8:
-  target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP (2022-09-29 18:01:09 +0100)
+  tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG (2023-02-16 16:28:53 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * Fix breakage of icount mode when guest touches MDCR_EL3, MDCR_EL2,
+ * Some mostly M-profile-related code cleanups
-   PMCNTENSET_EL0 or PMCNTENCLR_EL0
+ * avocado: Retire the boot_linux.py AArch64 TCG tests
- * Make writes to MDCR_EL3 use PMU start/finish calls
+ * hw/arm/smmuv3: Add GBPA register
- * Let AArch32 write to SDCR.SCCD
+ * arm/virt: don't try to spell out the accelerator
- * Rearrange cpu64.c so all the CPU initfns are together
+ * hw/arm: Attach PSPI module to NPCM7XX SoC
- * hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
+ * Some cleanup/refactoring patches aiming towards
- * hw/arm/virt: fix some minor issues with generated device tree
+   allowing building Arm targets without CONFIG_TCG
  * Fix regression where EL3 could not write to SP_EL1 if there is no EL2
 ----------------------------------------------------------------
-Francisco Iglesias (1):
+Alex Bennée (1):
-      hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
+      tests/avocado: retire the Aarch64 TCG tests from boot_linux.py
-Jean-Philippe Brucker (4):
+Claudio Fontana (3):
-      hw/arm/virt: Fix devicetree warning about the root node
+      target/arm: rename handle_semihosting to tcg_handle_semihosting
-      hw/arm/virt: Fix devicetree warning about the GIC node
+      target/arm: wrap psci call with tcg_enabled
-      hw/arm/virt: Use "msi-map" devicetree property for PCI
+      target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()
       hw/arm/virt: Fix devicetree warning about the SMMU node
-Jerome Forissier (1):
+Cornelia Huck (1):
-      target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP
+      arm/virt: don't try to spell out the accelerator
-Peter Maydell (4):
+Fabiano Rosas (7):
-      target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO
+      target/arm: Move PC alignment check
-      target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
+      target/arm: Move cpregs code out of cpu.h
-      target/arm: Update SDCR_VALID_MASK to include SCCD
+      tests/avocado: Skip tests that require a missing accelerator
-      target/arm: Rearrange cpu64.c so all the CPU initfns are together
+      tests/avocado: Tag TCG tests with accel:tcg
       target/arm: Use "max" as default cpu for the virt machine with KVM
       tests/qtest: arm-cpu-features: Match tests to required accelerators
       tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
- include/hw/arm/xlnx-zynqmp.h |   3 +
+Hao Wu (3):
- target/arm/cpu.h             |   8 +-
+      MAINTAINERS: Add myself to maintainers and remove Havard
- hw/arm/virt.c                |   8 +-
+      hw/ssi: Add Nuvoton PSPI Module
- hw/arm/xlnx-zynqmp.c         |  36 +++
+      hw/arm: Attach PSPI module to NPCM7XX SoC
- target/arm/cpu64.c           | 712 +++++++++++++++++++++----------------------
- target/arm/helper.c          |  32 +-
+Jean-Philippe Brucker (2):
-files changed, 427 insertions(+), 372 deletions(-)
+      hw/arm/smmu-common: Support 64-bit addresses
       hw/arm/smmu-common: Fix TTB1 handling
 Mostafa Saleh (1):
       hw/arm/smmuv3: Add GBPA register
 Philippe Mathieu-Daudé (12):
       hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro
       target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation
       target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope
       target/arm: Constify ID_PFR1 on user emulation
       target/arm: Convert CPUARMState::eabi to boolean
       target/arm: Avoid resetting CPUARMState::eabi field
       target/arm: Restrict CPUARMState::gicv3state to sysemu
       target/arm: Restrict CPUARMState::arm_boot_info to sysemu
       target/arm: Restrict CPUARMState::nvic to sysemu
       target/arm: Store CPUARMState::nvic as NVICState*
       target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
       hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency
  MAINTAINERS                            |   8 +-
  docs/system/arm/nuvoton.rst            |   2 +-
  hw/arm/smmuv3-internal.h               |   7 +
  include/hw/arm/npcm7xx.h               |   2 +
  include/hw/arm/smmu-common.h           |   2 -
  include/hw/arm/smmuv3.h                |   1 +
  include/hw/intc/armv7m_nvic.h          | 128 +++++++++++++++++-
  include/hw/ssi/npcm_pspi.h             |  53 ++++++++
  linux-user/user-internals.h            |   2 +-
  target/arm/cpregs.h                    |  98 ++++++++++++++
  target/arm/cpu.h                       | 228 ++-------------------------------
  target/arm/internals.h                 |  14 --
  hw/arm/npcm7xx.c                       |  25 +++-
  hw/arm/smmu-common.c                   |   4 +-
  hw/arm/smmuv3.c                        |  43 ++++++-
  hw/arm/virt.c                          |  10 +-
  hw/intc/armv7m_nvic.c                  |  38 ++----
  hw/ssi/npcm_pspi.c                     | 221 ++++++++++++++++++++++++++++++++
  linux-user/arm/cpu_loop.c              |   4 +-
  target/arm/cpu.c                       |   5 +-
  target/arm/cpu_tcg.c                   |   3 +
  target/arm/helper.c                    |  31 +++--
  target/arm/m_helper.c                  |  86 +++++++------
  target/arm/machine.c                   |  18 +--
  tests/qtest/arm-cpu-features.c         |  28 ++--
  hw/arm/Kconfig                         |   1 +
  hw/ssi/meson.build                     |   2 +-
  hw/ssi/trace-events                    |   5 +
  tests/avocado/avocado_qemu/__init__.py |   4 +
  tests/avocado/boot_linux.py            |  48 ++-----
  tests/avocado/boot_linux_console.py    |   1 +
  tests/avocado/machine_aarch64_virt.py  |  63 ++++++++-
  tests/avocado/reverse_debugging.py     |   8 ++
  tests/qtest/meson.build                |   4 +-
 files changed, 798 insertions(+), 399 deletions(-)
  create mode 100644 include/hw/ssi/npcm_pspi.h
  create mode 100644 hw/ssi/npcm_pspi.c

-New patch
+[PULL 01/30] hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro,
+similarly to automatic conversion from commit 8063396bf3
+("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-2-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/intc/armv7m_nvic.h | 5 +----
+file changed, 1 insertion(+), 4 deletions(-)
+diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/intc/armv7m_nvic.h
++++ b/include/hw/intc/armv7m_nvic.h
+@@ -XXX,XX +XXX,XX @@
+ #include "qom/object.h"
+ #define TYPE_NVIC "armv7m_nvic"
+-
+-typedef struct NVICState NVICState;
+-DECLARE_INSTANCE_CHECKER(NVICState, NVIC,
+-                         TYPE_NVIC)
++OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC)
+ /* Highest permitted number of exceptions (architectural limit) */
+ #define NVIC_MAX_VECTORS 512
+--
+.34.1

-New patch
+[PULL 02/30] target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Suggested-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-3-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/m_helper.c | 11 ++++++++---
+file changed, 8 insertions(+), 3 deletions(-)
+diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/m_helper.c
++++ b/target/arm/m_helper.c
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
+     return 0;
+ }
+-#else
++ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
++{
++    return ARMMMUIdx_MUser;
++}
++
++#else /* !CONFIG_USER_ONLY */
+ /*
+  * What kind of stack write are we doing? This affects how exceptions
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
+     return tt_resp;
+ }
+-#endif /* !CONFIG_USER_ONLY */
+-
+ ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+                               bool secstate, bool priv, bool negpri)
+ {
+@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+     return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
+ }
++
++#endif /* !CONFIG_USER_ONLY */
+--
+.34.1

-[PULL 04/10] target/arm: Rearrange cpu64.c so all the CPU initfns are together
+[PULL 03/30] target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope
-cpu64.c has ended up in a slightly odd order -- it starts with the
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 initfns for most of the models-real-hardware CPUs; after that comes a
 bunch of support code for SVE, SME, pauth and LPA2 properties.  Then
 come the initfns for the 'host' and 'max' CPU types, and then after
 that one more models-real-hardware CPU initfn, for a64fx.  (This
 ordering is partly historical and partly required because a64fx needs
 the SVE properties.)
-Reorder the file into:
+arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv()
- * CPU property support functions
+are only used for system emulation in m_helper.c.
- * initfns for real hardware CPUs
+Move the definitions to avoid prototype forward declarations.
  * initfns for host and max
  * class boilerplate
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-4-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- target/arm/cpu64.c | 712 ++++++++++++++++++++++-----------------------
+ target/arm/internals.h | 14 --------
-file changed, 356 insertions(+), 356 deletions(-)
+ target/arm/m_helper.c  | 74 +++++++++++++++++++++---------------------
 files changed, 37 insertions(+), 51 deletions(-)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
+--- a/target/arm/internals.h
-+++ b/target/arm/cpu64.c
++++ b/target/arm/internals.h
-@@ -XXX,XX +XXX,XX @@ static void aarch64_a35_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx)
-     define_cortex_a72_a57_a53_cp_reginfo(cpu);
  int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
 -/*
 - * Return the MMU index for a v7M CPU with all relevant information
 - * manually specified.
 - */
 -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
 -                              bool secstate, bool priv, bool negpri);
 -
 -/*
 - * Return the MMU index for a v7M CPU in the specified security and
 - * privilege state.
 - */
 -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
 -                                                bool secstate, bool priv);
 -
  /* Return the MMU index for a v7M CPU in the specified security state */
  ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/m_helper.c
 +++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
  #else /* !CONFIG_USER_ONLY */
 +static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
 +                                     bool secstate, bool priv, bool negpri)
 +{
 +    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
 +
 +    if (priv) {
 +        mmu_idx |= ARM_MMU_IDX_M_PRIV;
 +    }
 +
 +    if (negpri) {
 +        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
 +    }
 +
 +    if (secstate) {
 +        mmu_idx |= ARM_MMU_IDX_M_S;
 +    }
 +
 +    return mmu_idx;
 +}
 +
 +static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
 +                                                       bool secstate, bool priv)
 +{
 +    bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
 +
 +    return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
 +}
 +
 +/* Return the MMU index for a v7M CPU in the specified security state */
 +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
 +{
 +    bool priv = arm_v7m_is_handler_mode(env) ||
 +        !(env->v7m.control[secstate] & 1);
 +
 +    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
 +}
 +
  /*
   * What kind of stack write are we doing? This affects how exceptions
   * generated during the stacking are treated.
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
      return tt_resp;
  }
--static void aarch64_a57_initfn(Object *obj)
+-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
 -                              bool secstate, bool priv, bool negpri)
 -{
--    ARMCPU *cpu = ARM_CPU(obj);
+-    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
 -
--    cpu->dtb_compatible = "arm,cortex-a57";
+-    if (priv) {
--    set_feature(&cpu->env, ARM_FEATURE_V8);
+-        mmu_idx |= ARM_MMU_IDX_M_PRIV;
--    set_feature(&cpu->env, ARM_FEATURE_NEON);
+-    }
--    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+-
--    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+-    if (negpri) {
--    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+-        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
--    set_feature(&cpu->env, ARM_FEATURE_EL2);
+-    }
--    set_feature(&cpu->env, ARM_FEATURE_EL3);
+-
--    set_feature(&cpu->env, ARM_FEATURE_PMU);
+-    if (secstate) {
--    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
+-        mmu_idx |= ARM_MMU_IDX_M_S;
--    cpu->midr = 0x411fd070;
+-    }
--    cpu->revidr = 0x00000000;
+-
--    cpu->reset_fpsid = 0x41034070;
+-    return mmu_idx;
 -    cpu->isar.mvfr0 = 0x10110222;
 -    cpu->isar.mvfr1 = 0x12111111;
 -    cpu->isar.mvfr2 = 0x00000043;
 -    cpu->ctr = 0x8444c004;
 -    cpu->reset_sctlr = 0x00c50838;
 -    cpu->isar.id_pfr0 = 0x00000131;
 -    cpu->isar.id_pfr1 = 0x00011011;
 -    cpu->isar.id_dfr0 = 0x03010066;
 -    cpu->id_afr0 = 0x00000000;
 -    cpu->isar.id_mmfr0 = 0x10101105;
 -    cpu->isar.id_mmfr1 = 0x40000000;
 -    cpu->isar.id_mmfr2 = 0x01260000;
 -    cpu->isar.id_mmfr3 = 0x02102211;
 -    cpu->isar.id_isar0 = 0x02101110;
 -    cpu->isar.id_isar1 = 0x13112111;
 -    cpu->isar.id_isar2 = 0x21232042;
 -    cpu->isar.id_isar3 = 0x01112131;
 -    cpu->isar.id_isar4 = 0x00011142;
 -    cpu->isar.id_isar5 = 0x00011121;
 -    cpu->isar.id_isar6 = 0;
 -    cpu->isar.id_aa64pfr0 = 0x00002222;
 -    cpu->isar.id_aa64dfr0 = 0x10305106;
 -    cpu->isar.id_aa64isar0 = 0x00011120;
 -    cpu->isar.id_aa64mmfr0 = 0x00001124;
 -    cpu->isar.dbgdidr = 0x3516d000;
 -    cpu->isar.dbgdevid = 0x01110f13;
 -    cpu->isar.dbgdevid1 = 0x2;
 -    cpu->isar.reset_pmcr_el0 = 0x41013000;
 -    cpu->clidr = 0x0a200023;
 -    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 -    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 -    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
 -    cpu->dcz_blocksize = 4; /* 64 bytes */
 -    cpu->gic_num_lrs = 4;
 -    cpu->gic_vpribits = 5;
 -    cpu->gic_vprebits = 5;
 -    cpu->gic_pribits = 5;
 -    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 -}
 -
--static void aarch64_a53_initfn(Object *obj)
+-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
 -                                                bool secstate, bool priv)
 -{
--    ARMCPU *cpu = ARM_CPU(obj);
+-    bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
 -
--    cpu->dtb_compatible = "arm,cortex-a53";
+-    return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
 -    set_feature(&cpu->env, ARM_FEATURE_V8);
 -    set_feature(&cpu->env, ARM_FEATURE_NEON);
 -    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 -    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 -    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 -    set_feature(&cpu->env, ARM_FEATURE_EL2);
 -    set_feature(&cpu->env, ARM_FEATURE_EL3);
 -    set_feature(&cpu->env, ARM_FEATURE_PMU);
 -    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
 -    cpu->midr = 0x410fd034;
 -    cpu->revidr = 0x00000000;
 -    cpu->reset_fpsid = 0x41034070;
 -    cpu->isar.mvfr0 = 0x10110222;
 -    cpu->isar.mvfr1 = 0x12111111;
 -    cpu->isar.mvfr2 = 0x00000043;
 -    cpu->ctr = 0x84448004; /* L1Ip = VIPT */
 -    cpu->reset_sctlr = 0x00c50838;
 -    cpu->isar.id_pfr0 = 0x00000131;
 -    cpu->isar.id_pfr1 = 0x00011011;
 -    cpu->isar.id_dfr0 = 0x03010066;
 -    cpu->id_afr0 = 0x00000000;
 -    cpu->isar.id_mmfr0 = 0x10101105;
 -    cpu->isar.id_mmfr1 = 0x40000000;
 -    cpu->isar.id_mmfr2 = 0x01260000;
 -    cpu->isar.id_mmfr3 = 0x02102211;
 -    cpu->isar.id_isar0 = 0x02101110;
 -    cpu->isar.id_isar1 = 0x13112111;
 -    cpu->isar.id_isar2 = 0x21232042;
 -    cpu->isar.id_isar3 = 0x01112131;
 -    cpu->isar.id_isar4 = 0x00011142;
 -    cpu->isar.id_isar5 = 0x00011121;
 -    cpu->isar.id_isar6 = 0;
 -    cpu->isar.id_aa64pfr0 = 0x00002222;
 -    cpu->isar.id_aa64dfr0 = 0x10305106;
 -    cpu->isar.id_aa64isar0 = 0x00011120;
 -    cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
 -    cpu->isar.dbgdidr = 0x3516d000;
 -    cpu->isar.dbgdevid = 0x00110f13;
 -    cpu->isar.dbgdevid1 = 0x1;
 -    cpu->isar.reset_pmcr_el0 = 0x41033000;
 -    cpu->clidr = 0x0a200023;
 -    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
 -    cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
 -    cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
 -    cpu->dcz_blocksize = 4; /* 64 bytes */
 -    cpu->gic_num_lrs = 4;
 -    cpu->gic_vpribits = 5;
 -    cpu->gic_vprebits = 5;
 -    cpu->gic_pribits = 5;
 -    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 -}
 -
--static void aarch64_a72_initfn(Object *obj)
+-/* Return the MMU index for a v7M CPU in the specified security state */
 -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
 -{
--    ARMCPU *cpu = ARM_CPU(obj);
+-    bool priv = arm_v7m_is_handler_mode(env) ||
 -        !(env->v7m.control[secstate] & 1);
 -
--    cpu->dtb_compatible = "arm,cortex-a72";
+-    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
 -    set_feature(&cpu->env, ARM_FEATURE_V8);
 -    set_feature(&cpu->env, ARM_FEATURE_NEON);
 -    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 -    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 -    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 -    set_feature(&cpu->env, ARM_FEATURE_EL2);
 -    set_feature(&cpu->env, ARM_FEATURE_EL3);
 -    set_feature(&cpu->env, ARM_FEATURE_PMU);
 -    cpu->midr = 0x410fd083;
 -    cpu->revidr = 0x00000000;
 -    cpu->reset_fpsid = 0x41034080;
 -    cpu->isar.mvfr0 = 0x10110222;
 -    cpu->isar.mvfr1 = 0x12111111;
 -    cpu->isar.mvfr2 = 0x00000043;
 -    cpu->ctr = 0x8444c004;
 -    cpu->reset_sctlr = 0x00c50838;
 -    cpu->isar.id_pfr0 = 0x00000131;
 -    cpu->isar.id_pfr1 = 0x00011011;
 -    cpu->isar.id_dfr0 = 0x03010066;
 -    cpu->id_afr0 = 0x00000000;
 -    cpu->isar.id_mmfr0 = 0x10201105;
 -    cpu->isar.id_mmfr1 = 0x40000000;
 -    cpu->isar.id_mmfr2 = 0x01260000;
 -    cpu->isar.id_mmfr3 = 0x02102211;
 -    cpu->isar.id_isar0 = 0x02101110;
 -    cpu->isar.id_isar1 = 0x13112111;
 -    cpu->isar.id_isar2 = 0x21232042;
 -    cpu->isar.id_isar3 = 0x01112131;
 -    cpu->isar.id_isar4 = 0x00011142;
 -    cpu->isar.id_isar5 = 0x00011121;
 -    cpu->isar.id_aa64pfr0 = 0x00002222;
 -    cpu->isar.id_aa64dfr0 = 0x10305106;
 -    cpu->isar.id_aa64isar0 = 0x00011120;
 -    cpu->isar.id_aa64mmfr0 = 0x00001124;
 -    cpu->isar.dbgdidr = 0x3516d000;
 -    cpu->isar.dbgdevid = 0x01110f13;
 -    cpu->isar.dbgdevid1 = 0x2;
 -    cpu->isar.reset_pmcr_el0 = 0x41023000;
 -    cpu->clidr = 0x0a200023;
 -    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 -    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 -    cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
 -    cpu->dcz_blocksize = 4; /* 64 bytes */
 -    cpu->gic_num_lrs = 4;
 -    cpu->gic_vpribits = 5;
 -    cpu->gic_vprebits = 5;
 -    cpu->gic_pribits = 5;
 -    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 -}
 -
--static void aarch64_a76_initfn(Object *obj)
+ #endif /* !CONFIG_USER_ONLY */
 -{
 -    ARMCPU *cpu = ARM_CPU(obj);
 -
 -    cpu->dtb_compatible = "arm,cortex-a76";
 -    set_feature(&cpu->env, ARM_FEATURE_V8);
 -    set_feature(&cpu->env, ARM_FEATURE_NEON);
 -    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 -    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 -    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 -    set_feature(&cpu->env, ARM_FEATURE_EL2);
 -    set_feature(&cpu->env, ARM_FEATURE_EL3);
 -    set_feature(&cpu->env, ARM_FEATURE_PMU);
 -
 -    /* Ordered by B2.4 AArch64 registers by functional group */
 -    cpu->clidr = 0x82000023;
 -    cpu->ctr = 0x8444C004;
 -    cpu->dcz_blocksize = 4;
 -    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
 -    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
 -    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
 -    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
 -    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
 -    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
 -    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
 -    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
 -    cpu->id_afr0       = 0x00000000;
 -    cpu->isar.id_dfr0  = 0x04010088;
 -    cpu->isar.id_isar0 = 0x02101110;
 -    cpu->isar.id_isar1 = 0x13112111;
 -    cpu->isar.id_isar2 = 0x21232042;
 -    cpu->isar.id_isar3 = 0x01112131;
 -    cpu->isar.id_isar4 = 0x00010142;
 -    cpu->isar.id_isar5 = 0x01011121;
 -    cpu->isar.id_isar6 = 0x00000010;
 -    cpu->isar.id_mmfr0 = 0x10201105;
 -    cpu->isar.id_mmfr1 = 0x40000000;
 -    cpu->isar.id_mmfr2 = 0x01260000;
 -    cpu->isar.id_mmfr3 = 0x02122211;
 -    cpu->isar.id_mmfr4 = 0x00021110;
 -    cpu->isar.id_pfr0  = 0x10010131;
 -    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
 -    cpu->isar.id_pfr2  = 0x00000011;
 -    cpu->midr = 0x414fd0b1;          /* r4p1 */
 -    cpu->revidr = 0;
 -
 -    /* From B2.18 CCSIDR_EL1 */
 -    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
 -    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
 -    cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
 -
 -    /* From B2.93 SCTLR_EL3 */
 -    cpu->reset_sctlr = 0x30c50838;
 -
 -    /* From B4.23 ICH_VTR_EL2 */
 -    cpu->gic_num_lrs = 4;
 -    cpu->gic_vpribits = 5;
 -    cpu->gic_vprebits = 5;
 -    cpu->gic_pribits = 5;
 -
 -    /* From B5.1 AdvSIMD AArch64 register summary */
 -    cpu->isar.mvfr0 = 0x10110222;
 -    cpu->isar.mvfr1 = 0x13211111;
 -    cpu->isar.mvfr2 = 0x00000043;
 -
 -    /* From D5.1 AArch64 PMU register summary */
 -    cpu->isar.reset_pmcr_el0 = 0x410b3000;
 -}
 -
 -static void aarch64_neoverse_n1_initfn(Object *obj)
 -{
 -    ARMCPU *cpu = ARM_CPU(obj);
 -
 -    cpu->dtb_compatible = "arm,neoverse-n1";
 -    set_feature(&cpu->env, ARM_FEATURE_V8);
 -    set_feature(&cpu->env, ARM_FEATURE_NEON);
 -    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 -    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 -    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 -    set_feature(&cpu->env, ARM_FEATURE_EL2);
 -    set_feature(&cpu->env, ARM_FEATURE_EL3);
 -    set_feature(&cpu->env, ARM_FEATURE_PMU);
 -
 -    /* Ordered by B2.4 AArch64 registers by functional group */
 -    cpu->clidr = 0x82000023;
 -    cpu->ctr = 0x8444c004;
 -    cpu->dcz_blocksize = 4;
 -    cpu->isar.id_aa64dfr0  = 0x0000000110305408ull;
 -    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
 -    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
 -    cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
 -    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
 -    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
 -    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
 -    cpu->isar.id_aa64pfr1  = 0x0000000000000020ull;
 -    cpu->id_afr0       = 0x00000000;
 -    cpu->isar.id_dfr0  = 0x04010088;
 -    cpu->isar.id_isar0 = 0x02101110;
 -    cpu->isar.id_isar1 = 0x13112111;
 -    cpu->isar.id_isar2 = 0x21232042;
 -    cpu->isar.id_isar3 = 0x01112131;
 -    cpu->isar.id_isar4 = 0x00010142;
 -    cpu->isar.id_isar5 = 0x01011121;
 -    cpu->isar.id_isar6 = 0x00000010;
 -    cpu->isar.id_mmfr0 = 0x10201105;
 -    cpu->isar.id_mmfr1 = 0x40000000;
 -    cpu->isar.id_mmfr2 = 0x01260000;
 -    cpu->isar.id_mmfr3 = 0x02122211;
 -    cpu->isar.id_mmfr4 = 0x00021110;
 -    cpu->isar.id_pfr0  = 0x10010131;
 -    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
 -    cpu->isar.id_pfr2  = 0x00000011;
 -    cpu->midr = 0x414fd0c1;          /* r4p1 */
 -    cpu->revidr = 0;
 -
 -    /* From B2.23 CCSIDR_EL1 */
 -    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
 -    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
 -    cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
 -
 -    /* From B2.98 SCTLR_EL3 */
 -    cpu->reset_sctlr = 0x30c50838;
 -
 -    /* From B4.23 ICH_VTR_EL2 */
 -    cpu->gic_num_lrs = 4;
 -    cpu->gic_vpribits = 5;
 -    cpu->gic_vprebits = 5;
 -    cpu->gic_pribits = 5;
 -
 -    /* From B5.1 AdvSIMD AArch64 register summary */
 -    cpu->isar.mvfr0 = 0x10110222;
 -    cpu->isar.mvfr1 = 0x13211111;
 -    cpu->isar.mvfr2 = 0x00000043;
 -
 -    /* From D5.1 AArch64 PMU register summary */
 -    cpu->isar.reset_pmcr_el0 = 0x410c3000;
 -}
 -
  void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
  {
      /*
@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
      cpu->isar.id_aa64mmfr0 = t;
  }
 +static void aarch64_a57_initfn(Object *obj)
 +{
 +    ARMCPU *cpu = ARM_CPU(obj);
 +
 +    cpu->dtb_compatible = "arm,cortex-a57";
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
 +    cpu->midr = 0x411fd070;
 +    cpu->revidr = 0x00000000;
 +    cpu->reset_fpsid = 0x41034070;
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x12111111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +    cpu->ctr = 0x8444c004;
 +    cpu->reset_sctlr = 0x00c50838;
 +    cpu->isar.id_pfr0 = 0x00000131;
 +    cpu->isar.id_pfr1 = 0x00011011;
 +    cpu->isar.id_dfr0 = 0x03010066;
 +    cpu->id_afr0 = 0x00000000;
 +    cpu->isar.id_mmfr0 = 0x10101105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02102211;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00011142;
 +    cpu->isar.id_isar5 = 0x00011121;
 +    cpu->isar.id_isar6 = 0;
 +    cpu->isar.id_aa64pfr0 = 0x00002222;
 +    cpu->isar.id_aa64dfr0 = 0x10305106;
 +    cpu->isar.id_aa64isar0 = 0x00011120;
 +    cpu->isar.id_aa64mmfr0 = 0x00001124;
 +    cpu->isar.dbgdidr = 0x3516d000;
 +    cpu->isar.dbgdevid = 0x01110f13;
 +    cpu->isar.dbgdevid1 = 0x2;
 +    cpu->isar.reset_pmcr_el0 = 0x41013000;
 +    cpu->clidr = 0x0a200023;
 +    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 +    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
 +    cpu->dcz_blocksize = 4; /* 64 bytes */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +    cpu->gic_pribits = 5;
 +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 +}
 +
 +static void aarch64_a53_initfn(Object *obj)
 +{
 +    ARMCPU *cpu = ARM_CPU(obj);
 +
 +    cpu->dtb_compatible = "arm,cortex-a53";
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
 +    cpu->midr = 0x410fd034;
 +    cpu->revidr = 0x00000000;
 +    cpu->reset_fpsid = 0x41034070;
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x12111111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +    cpu->ctr = 0x84448004; /* L1Ip = VIPT */
 +    cpu->reset_sctlr = 0x00c50838;
 +    cpu->isar.id_pfr0 = 0x00000131;
 +    cpu->isar.id_pfr1 = 0x00011011;
 +    cpu->isar.id_dfr0 = 0x03010066;
 +    cpu->id_afr0 = 0x00000000;
 +    cpu->isar.id_mmfr0 = 0x10101105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02102211;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00011142;
 +    cpu->isar.id_isar5 = 0x00011121;
 +    cpu->isar.id_isar6 = 0;
 +    cpu->isar.id_aa64pfr0 = 0x00002222;
 +    cpu->isar.id_aa64dfr0 = 0x10305106;
 +    cpu->isar.id_aa64isar0 = 0x00011120;
 +    cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
 +    cpu->isar.dbgdidr = 0x3516d000;
 +    cpu->isar.dbgdevid = 0x00110f13;
 +    cpu->isar.dbgdevid1 = 0x1;
 +    cpu->isar.reset_pmcr_el0 = 0x41033000;
 +    cpu->clidr = 0x0a200023;
 +    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
 +    cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
 +    cpu->dcz_blocksize = 4; /* 64 bytes */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +    cpu->gic_pribits = 5;
 +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 +}
 +
 +static void aarch64_a72_initfn(Object *obj)
 +{
 +    ARMCPU *cpu = ARM_CPU(obj);
 +
 +    cpu->dtb_compatible = "arm,cortex-a72";
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +    cpu->midr = 0x410fd083;
 +    cpu->revidr = 0x00000000;
 +    cpu->reset_fpsid = 0x41034080;
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x12111111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +    cpu->ctr = 0x8444c004;
 +    cpu->reset_sctlr = 0x00c50838;
 +    cpu->isar.id_pfr0 = 0x00000131;
 +    cpu->isar.id_pfr1 = 0x00011011;
 +    cpu->isar.id_dfr0 = 0x03010066;
 +    cpu->id_afr0 = 0x00000000;
 +    cpu->isar.id_mmfr0 = 0x10201105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02102211;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00011142;
 +    cpu->isar.id_isar5 = 0x00011121;
 +    cpu->isar.id_aa64pfr0 = 0x00002222;
 +    cpu->isar.id_aa64dfr0 = 0x10305106;
 +    cpu->isar.id_aa64isar0 = 0x00011120;
 +    cpu->isar.id_aa64mmfr0 = 0x00001124;
 +    cpu->isar.dbgdidr = 0x3516d000;
 +    cpu->isar.dbgdevid = 0x01110f13;
 +    cpu->isar.dbgdevid1 = 0x2;
 +    cpu->isar.reset_pmcr_el0 = 0x41023000;
 +    cpu->clidr = 0x0a200023;
 +    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 +    cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
 +    cpu->dcz_blocksize = 4; /* 64 bytes */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +    cpu->gic_pribits = 5;
 +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 +}
 +
 +static void aarch64_a76_initfn(Object *obj)
 +{
 +    ARMCPU *cpu = ARM_CPU(obj);
 +
 +    cpu->dtb_compatible = "arm,cortex-a76";
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +
 +    /* Ordered by B2.4 AArch64 registers by functional group */
 +    cpu->clidr = 0x82000023;
 +    cpu->ctr = 0x8444C004;
 +    cpu->dcz_blocksize = 4;
 +    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
 +    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
 +    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
 +    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
 +    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
 +    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
 +    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
 +    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
 +    cpu->id_afr0       = 0x00000000;
 +    cpu->isar.id_dfr0  = 0x04010088;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00010142;
 +    cpu->isar.id_isar5 = 0x01011121;
 +    cpu->isar.id_isar6 = 0x00000010;
 +    cpu->isar.id_mmfr0 = 0x10201105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02122211;
 +    cpu->isar.id_mmfr4 = 0x00021110;
 +    cpu->isar.id_pfr0  = 0x10010131;
 +    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
 +    cpu->isar.id_pfr2  = 0x00000011;
 +    cpu->midr = 0x414fd0b1;          /* r4p1 */
 +    cpu->revidr = 0;
 +
 +    /* From B2.18 CCSIDR_EL1 */
 +    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
 +    cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
 +
 +    /* From B2.93 SCTLR_EL3 */
 +    cpu->reset_sctlr = 0x30c50838;
 +
 +    /* From B4.23 ICH_VTR_EL2 */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +    cpu->gic_pribits = 5;
 +
 +    /* From B5.1 AdvSIMD AArch64 register summary */
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x13211111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +
 +    /* From D5.1 AArch64 PMU register summary */
 +    cpu->isar.reset_pmcr_el0 = 0x410b3000;
 +}
 +
 +static void aarch64_a64fx_initfn(Object *obj)
 +{
 +    ARMCPU *cpu = ARM_CPU(obj);
 +
 +    cpu->dtb_compatible = "arm,a64fx";
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +    cpu->midr = 0x461f0010;
 +    cpu->revidr = 0x00000000;
 +    cpu->ctr = 0x86668006;
 +    cpu->reset_sctlr = 0x30000180;
 +    cpu->isar.id_aa64pfr0 =   0x0000000101111111; /* No RAS Extensions */
 +    cpu->isar.id_aa64pfr1 = 0x0000000000000000;
 +    cpu->isar.id_aa64dfr0 = 0x0000000010305408;
 +    cpu->isar.id_aa64dfr1 = 0x0000000000000000;
 +    cpu->id_aa64afr0 = 0x0000000000000000;
 +    cpu->id_aa64afr1 = 0x0000000000000000;
 +    cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
 +    cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
 +    cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
 +    cpu->isar.id_aa64isar0 = 0x0000000010211120;
 +    cpu->isar.id_aa64isar1 = 0x0000000000010001;
 +    cpu->isar.id_aa64zfr0 = 0x0000000000000000;
 +    cpu->clidr = 0x0000000080000023;
 +    cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
 +    cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
 +    cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
 +    cpu->dcz_blocksize = 6; /* 256 bytes */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +    cpu->gic_pribits = 5;
 +
 +    /* The A64FX supports only 128, 256 and 512 bit vector lengths */
 +    aarch64_add_sve_properties(obj);
 +    cpu->sve_vq.supported = (1 << 0)  /* 128bit */
 +                          | (1 << 1)  /* 256bit */
 +                          | (1 << 3); /* 512bit */
 +
 +    cpu->isar.reset_pmcr_el0 = 0x46014040;
 +
 +    /* TODO:  Add A64FX specific HPC extension registers */
 +}
 +
 +static void aarch64_neoverse_n1_initfn(Object *obj)
 +{
 +    ARMCPU *cpu = ARM_CPU(obj);
 +
 +    cpu->dtb_compatible = "arm,neoverse-n1";
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +
 +    /* Ordered by B2.4 AArch64 registers by functional group */
 +    cpu->clidr = 0x82000023;
 +    cpu->ctr = 0x8444c004;
 +    cpu->dcz_blocksize = 4;
 +    cpu->isar.id_aa64dfr0  = 0x0000000110305408ull;
 +    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
 +    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
 +    cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
 +    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
 +    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
 +    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
 +    cpu->isar.id_aa64pfr1  = 0x0000000000000020ull;
 +    cpu->id_afr0       = 0x00000000;
 +    cpu->isar.id_dfr0  = 0x04010088;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00010142;
 +    cpu->isar.id_isar5 = 0x01011121;
 +    cpu->isar.id_isar6 = 0x00000010;
 +    cpu->isar.id_mmfr0 = 0x10201105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02122211;
 +    cpu->isar.id_mmfr4 = 0x00021110;
 +    cpu->isar.id_pfr0  = 0x10010131;
 +    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
 +    cpu->isar.id_pfr2  = 0x00000011;
 +    cpu->midr = 0x414fd0c1;          /* r4p1 */
 +    cpu->revidr = 0;
 +
 +    /* From B2.23 CCSIDR_EL1 */
 +    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
 +    cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
 +
 +    /* From B2.98 SCTLR_EL3 */
 +    cpu->reset_sctlr = 0x30c50838;
 +
 +    /* From B4.23 ICH_VTR_EL2 */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +    cpu->gic_pribits = 5;
 +
 +    /* From B5.1 AdvSIMD AArch64 register summary */
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x13211111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +
 +    /* From D5.1 AArch64 PMU register summary */
 +    cpu->isar.reset_pmcr_el0 = 0x410c3000;
 +}
 +
  static void aarch64_host_initfn(Object *obj)
  {
  #if defined(CONFIG_KVM)
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
      qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
  }
 -static void aarch64_a64fx_initfn(Object *obj)
 -{
 -    ARMCPU *cpu = ARM_CPU(obj);
 -
 -    cpu->dtb_compatible = "arm,a64fx";
 -    set_feature(&cpu->env, ARM_FEATURE_V8);
 -    set_feature(&cpu->env, ARM_FEATURE_NEON);
 -    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 -    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 -    set_feature(&cpu->env, ARM_FEATURE_EL2);
 -    set_feature(&cpu->env, ARM_FEATURE_EL3);
 -    set_feature(&cpu->env, ARM_FEATURE_PMU);
 -    cpu->midr = 0x461f0010;
 -    cpu->revidr = 0x00000000;
 -    cpu->ctr = 0x86668006;
 -    cpu->reset_sctlr = 0x30000180;
 -    cpu->isar.id_aa64pfr0 =   0x0000000101111111; /* No RAS Extensions */
 -    cpu->isar.id_aa64pfr1 = 0x0000000000000000;
 -    cpu->isar.id_aa64dfr0 = 0x0000000010305408;
 -    cpu->isar.id_aa64dfr1 = 0x0000000000000000;
 -    cpu->id_aa64afr0 = 0x0000000000000000;
 -    cpu->id_aa64afr1 = 0x0000000000000000;
 -    cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
 -    cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
 -    cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
 -    cpu->isar.id_aa64isar0 = 0x0000000010211120;
 -    cpu->isar.id_aa64isar1 = 0x0000000000010001;
 -    cpu->isar.id_aa64zfr0 = 0x0000000000000000;
 -    cpu->clidr = 0x0000000080000023;
 -    cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
 -    cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
 -    cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
 -    cpu->dcz_blocksize = 6; /* 256 bytes */
 -    cpu->gic_num_lrs = 4;
 -    cpu->gic_vpribits = 5;
 -    cpu->gic_vprebits = 5;
 -    cpu->gic_pribits = 5;
 -
 -    /* The A64FX supports only 128, 256 and 512 bit vector lengths */
 -    aarch64_add_sve_properties(obj);
 -    cpu->sve_vq.supported = (1 << 0)  /* 128bit */
 -                          | (1 << 1)  /* 256bit */
 -                          | (1 << 3); /* 512bit */
 -
 -    cpu->isar.reset_pmcr_el0 = 0x46014040;
 -
 -    /* TODO:  Add A64FX specific HPC extension registers */
 -}
 -
  static const ARMCPUInfo aarch64_cpus[] = {
      { .name = "cortex-a35",         .initfn = aarch64_a35_initfn },
      { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
 --
-.25.1
+.34.1

-[PULL 02/10] target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
+[PULL 04/30] target/arm: Constify ID_PFR1 on user emulation
-In commit 01765386a88868 we fixed a bug where we weren't correctly
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 bracketing changes to some registers with pmu_op_start() and
 pmu_op_finish() calls for changes which affect whether the PMU
 counters might be enabled.  However, we missed the case of writes to
 the AArch64 MDCR_EL3 register, because (unlike its AArch32
 counterpart) they are currently done directly to the CPU state struct
 without going through the sdcr_write() function.
-Give MDCR_EL3 a writefn which handles the PMU start/finish calls.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-The SDCR writefn then simplfies to "call the MDCR_EL3 writefn after
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-masking off the bits which don't exist in the AArch32 register".
+Message-id: 20230206223502.25122-5-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220923123412.1214041-3-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 18 ++++++++++++++----
+ target/arm/helper.c | 12 ++++++++++--
-file changed, 14 insertions(+), 4 deletions(-)
+file changed, 10 insertions(+), 2 deletions(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
      }
  }
--static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
++#ifndef CONFIG_USER_ONLY
--                       uint64_t value)
+ /*
-+static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
+  * We don't know until after realize whether there's a GICv3
-+                           uint64_t value)
+  * attached, and that is what registers the gicv3 sysregs.
@@ -XXX,XX +XXX,XX @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
      return pfr1;
  }
 -#ifndef CONFIG_USER_ONLY
  static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
  {
-     /*
+     ARMCPU *cpu = env_archcpu(env);
-      * Some MDCR_EL3 bits affect whether PMU counters are running:
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-@@ -XXX,XX +XXX,XX @@ static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
-     if (pmu_op) {
+               .access = PL1_R, .type = ARM_CP_NO_RAW,
-         pmu_op_start(env);
+               .accessfn = access_aa32_tid3,
-     }
++#ifdef CONFIG_USER_ONLY
--    env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
++              .type = ARM_CP_CONST,
-+    env->cp15.mdcr_el3 = value;
++              .resetvalue = cpu->isar.id_pfr1,
-     if (pmu_op) {
++#else
-         pmu_op_finish(env);
++              .type = ARM_CP_NO_RAW,
-     }
++              .accessfn = access_aa32_tid3,
- }
+               .readfn = id_pfr1_read,
+-              .writefn = arm_cp_write_ignore },
-+static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
++              .writefn = arm_cp_write_ignore
-+                       uint64_t value)
++#endif
-+{
++            },
-+    /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
+             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
-+    mdcr_el3_write(env, ri, value & SDCR_VALID_MASK);
+               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
-+}
+               .access = PL1_R, .type = ARM_CP_CONST,
 +
  static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
                             uint64_t value)
  {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
        .access = PL2_RW,
        .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
      { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
 +      .type = ARM_CP_IO,
        .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
        .resetvalue = 0,
 -      .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
 +      .access = PL3_RW,
 +      .writefn = mdcr_el3_write,
 +      .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
      { .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
        .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
        .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
 --
-.25.1
+.34.1

-New patch
+[PULL 05/30] target/arm: Convert CPUARMState::eabi to boolean
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Suggested-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-6-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ linux-user/user-internals.h | 2 +-
+ target/arm/cpu.h            | 2 +-
+ linux-user/arm/cpu_loop.c   | 4 ++--
+files changed, 4 insertions(+), 4 deletions(-)
+diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/linux-user/user-internals.h
++++ b/linux-user/user-internals.h
+@@ -XXX,XX +XXX,XX @@ void print_termios(void *arg);
+ #ifdef TARGET_ARM
+ static inline int regpairs_aligned(CPUArchState *cpu_env, int num)
+ {
+-    return cpu_env->eabi == 1;
++    return cpu_env->eabi;
+ }
+ #elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32)
+ static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; }
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+ #if defined(CONFIG_USER_ONLY)
+     /* For usermode syscall translation.  */
+-    int eabi;
++    bool eabi;
+ #endif
+     struct CPUBreakpoint *cpu_breakpoint[16];
+diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
+index XXXXXXX..XXXXXXX 100644
+--- a/linux-user/arm/cpu_loop.c
++++ b/linux-user/arm/cpu_loop.c
+@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
+             break;
+         case EXCP_SWI:
+             {
+-                env->eabi = 1;
++                env->eabi = true;
+                 /* system call */
+                 if (env->thumb) {
+                     /* Thumb is always EABI style with syscall number in r7 */
+@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
+                          * > 0xfffff and are handled below as out-of-range.
+                          */
+                         n ^= ARM_SYSCALL_BASE;
+-                        env->eabi = 0;
++                        env->eabi = false;
+                     }
+                 }
+--
+.34.1

-New patch
+[PULL 06/30] target/arm: Avoid resetting CPUARMState::eabi field
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Although the 'eabi' field is only used in user emulation where
+CPU reset doesn't occur, it doesn't belong to the area to reset.
+Move it after the 'end_reset_fields' for consistency.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230206223502.25122-7-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 9 ++++-----
+file changed, 4 insertions(+), 5 deletions(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+     ARMVectorReg zarray[ARM_MAX_VQ * 16];
+ #endif
+-#if defined(CONFIG_USER_ONLY)
+-    /* For usermode syscall translation.  */
+-    bool eabi;
+-#endif
+-
+     struct CPUBreakpoint *cpu_breakpoint[16];
+     struct CPUWatchpoint *cpu_watchpoint[16];
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+     const struct arm_boot_info *boot_info;
+     /* Store GICv3CPUState to access from this struct */
+     void *gicv3state;
++#if defined(CONFIG_USER_ONLY)
++    /* For usermode syscall translation.  */
++    bool eabi;
++#endif /* CONFIG_USER_ONLY */
+ #ifdef TARGET_TAGGED_ADDRESSES
+     /* Linux syscall tagged address support */
+--
+.34.1

-New patch
+[PULL 07/30] target/arm: Restrict CPUARMState::gicv3state to sysemu
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230206223502.25122-8-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 3 ++-
+file changed, 2 insertions(+), 1 deletion(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+     void *nvic;
+     const struct arm_boot_info *boot_info;
++#if !defined(CONFIG_USER_ONLY)
+     /* Store GICv3CPUState to access from this struct */
+     void *gicv3state;
+-#if defined(CONFIG_USER_ONLY)
++#else /* CONFIG_USER_ONLY */
+     /* For usermode syscall translation.  */
+     bool eabi;
+ #endif /* CONFIG_USER_ONLY */
+--
+.34.1

-New patch
+[PULL 08/30] target/arm: Restrict CPUARMState::arm_boot_info to sysemu
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230206223502.25122-9-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+     } sau;
+     void *nvic;
+-    const struct arm_boot_info *boot_info;
+ #if !defined(CONFIG_USER_ONLY)
++    const struct arm_boot_info *boot_info;
+     /* Store GICv3CPUState to access from this struct */
+     void *gicv3state;
+ #else /* CONFIG_USER_ONLY */
+--
+.34.1

-New patch
+[PULL 09/30] target/arm: Restrict CPUARMState::nvic to sysemu
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-10-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+         uint32_t ctrl;
+     } sau;
+-    void *nvic;
+ #if !defined(CONFIG_USER_ONLY)
++    void *nvic;
+     const struct arm_boot_info *boot_info;
+     /* Store GICv3CPUState to access from this struct */
+     void *gicv3state;
+--
+.34.1

-[PULL 03/10] target/arm: Update SDCR_VALID_MASK to include SCCD
+[PULL 10/30] target/arm: Store CPUARMState::nvic as NVICState*
-Our SDCR_VALID_MASK doesn't include all of the bits which are defined
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-by the current architecture.  In particular in commit 0b42f4fab9d3 we
-forgot to add SCCD, which meant that an AArch32 guest couldn't
+There is no point in using a void pointer to access the NVIC.
-actually use the SCCD bit to disable counting in Secure state.
+Use the real type to avoid casting it while debugging.
-Add all the currently defined bits; we don't implement all of them,
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-but this makes them be reads-as-written, which is architecturally
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-valid and matches how we currently handle most of the others in the
+Message-id: 20230206223502.25122-11-philmd@linaro.org
 mask.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220923123412.1214041-4-peter.maydell@linaro.org
 ---
- target/arm/cpu.h | 8 +++++++-
+ target/arm/cpu.h      | 46 ++++++++++++++++++++++---------------------
-file changed, 7 insertions(+), 1 deletion(-)
+ hw/intc/armv7m_nvic.c | 38 ++++++++++++-----------------------
  target/arm/cpu.c      |  1 +
  target/arm/m_helper.c |  2 +-
 files changed, 39 insertions(+), 48 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TTA, 20, 1)
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMTBFlags {
- FIELD(CPTR_EL3, TAM, 30, 1)
- FIELD(CPTR_EL3, TCPAC, 31, 1)
+ typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
-+#define MDCR_MTPME    (1U << 28)
++typedef struct NVICState NVICState;
-+#define MDCR_TDCC     (1U << 27)
++
- #define MDCR_HLP      (1U << 26)  /* MDCR_EL2 */
+ typedef struct CPUArchState {
- #define MDCR_SCCD     (1U << 23)  /* MDCR_EL3 */
+     /* Regs for current mode.  */
- #define MDCR_HCCD     (1U << 23)  /* MDCR_EL2 */
+     uint32_t regs[16];
- #define MDCR_EPMAD    (1U << 21)
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
- #define MDCR_EDAD     (1U << 20)
+     } sau;
-+#define MDCR_TTRF     (1U << 19)
-+#define MDCR_STE      (1U << 18)  /* MDCR_EL3 */
+ #if !defined(CONFIG_USER_ONLY)
- #define MDCR_SPME     (1U << 17)  /* MDCR_EL3 */
+-    void *nvic;
- #define MDCR_HPMD     (1U << 17)  /* MDCR_EL2 */
++    NVICState *nvic;
- #define MDCR_SDD      (1U << 16)
+     const struct arm_boot_info *boot_info;
-@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
+     /* Store GICv3CPUState to access from this struct */
- #define MDCR_HPMN     (0x1fU)
+     void *gicv3state;
+@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
- /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
--#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
+ /* Interface between CPU and Interrupt controller.  */
-+#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
+ #ifndef CONFIG_USER_ONLY
-+                         MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
+-bool armv7m_nvic_can_take_pending_exception(void *opaque);
-+                         MDCR_STE | MDCR_SPME | MDCR_SPD)
++bool armv7m_nvic_can_take_pending_exception(NVICState *s);
+ #else
- #define CPSR_M (0x1fU)
+-static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
- #define CPSR_T (1U << 5)
++static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
  {
      return true;
  }
  #endif
  /**
   * armv7m_nvic_set_pending: mark the specified exception as pending
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to mark pending
   * @secure: false for non-banked exceptions or for the nonsecure
   * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
   * if @secure is true and @irq does not specify one of the fixed set
   * of architecturally banked exceptions.
   */
 -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
 +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_set_pending_derived: mark this derived exception as pending
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to mark pending
   * @secure: false for non-banked exceptions or for the nonsecure
   * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
   * exceptions (exceptions generated in the course of trying to take
   * a different exception).
   */
 -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
 +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to mark pending
   * @secure: false for non-banked exceptions or for the nonsecure
   * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
   * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
   * generated in the course of lazy stacking of FP registers.
   */
 -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
 +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_get_pending_irq_info: return highest priority pending
   *    exception, and whether it targets Secure state
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @pirq: set to pending exception number
   * @ptargets_secure: set to whether pending exception targets Secure
   *
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
   * to true if the current highest priority pending exception should
   * be taken to Secure state, false for NS.
   */
 -void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
 +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
                                        bool *ptargets_secure);
  /**
   * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
 - * @opaque: the NVIC
 + * @s: the NVIC
   *
   * Move the current highest priority pending exception from the pending
   * state to the active state, and update v7m.exception to indicate that
   * it is the exception currently being handled.
   */
 -void armv7m_nvic_acknowledge_irq(void *opaque);
 +void armv7m_nvic_acknowledge_irq(NVICState *s);
  /**
   * armv7m_nvic_complete_irq: complete specified interrupt or exception
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to complete
   * @secure: true if this exception was secure
   *
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque);
   *           0 if there is still an irq active after this one was completed
   * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
   */
 -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
 +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to mark pending
   * @secure: false for non-banked exceptions or for the nonsecure
   * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
   * interrupt the current execution priority. This controls whether the
   * RDY bit for it in the FPCCR is set.
   */
 -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
 +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_raw_execution_priority: return the raw execution priority
 - * @opaque: the NVIC
 + * @s: the NVIC
   *
   * Returns: the raw execution priority as defined by the v8M architecture.
   * This is the execution priority minus the effects of AIRCR.PRIS,
   * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
   * (v8M ARM ARM I_PKLD.)
   */
 -int armv7m_nvic_raw_execution_priority(void *opaque);
 +int armv7m_nvic_raw_execution_priority(NVICState *s);
  /**
   * armv7m_nvic_neg_prio_requested: return true if the requested execution
   * priority is negative for the specified security state.
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @secure: the security state to test
   * This corresponds to the pseudocode IsReqExecPriNeg().
   */
  #ifndef CONFIG_USER_ONLY
 -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
 +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
  #else
 -static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
 +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
  {
      return false;
  }
 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/armv7m_nvic.c
 +++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
      return MIN(running, s->exception_prio);
  }
 -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
 +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
  {
      /* Return true if the requested execution priority is negative
       * for the specified security state, ie that security state
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
       * mean we don't allow FAULTMASK_NS to actually make the execution
       * priority negative). Compare pseudocode IsReqExcPriNeg().
       */
 -    NVICState *s = opaque;
 -
      if (s->cpu->env.v7m.faultmask[secure]) {
          return true;
      }
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
      return false;
  }
 -bool armv7m_nvic_can_take_pending_exception(void *opaque)
 +bool armv7m_nvic_can_take_pending_exception(NVICState *s)
  {
 -    NVICState *s = opaque;
 -
      return nvic_exec_prio(s) > nvic_pending_prio(s);
  }
 -int armv7m_nvic_raw_execution_priority(void *opaque)
 +int armv7m_nvic_raw_execution_priority(NVICState *s)
  {
 -    NVICState *s = opaque;
 -
      return s->exception_prio;
  }
@@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s)
   * if @secure is true and @irq does not specify one of the fixed set
   * of architecturally banked exceptions.
   */
 -static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
 +static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure)
  {
 -    NVICState *s = (NVICState *)opaque;
      VecInfo *vec;
      assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
@@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
      }
  }
 -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
 +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure)
  {
 -    do_armv7m_nvic_set_pending(opaque, irq, secure, false);
 +    do_armv7m_nvic_set_pending(s, irq, secure, false);
  }
 -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure)
 +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure)
  {
 -    do_armv7m_nvic_set_pending(opaque, irq, secure, true);
 +    do_armv7m_nvic_set_pending(s, irq, secure, true);
  }
 -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
 +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure)
  {
      /*
       * Pend an exception during lazy FP stacking. This differs
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
       * whether we should escalate depends on the saved context
       * in the FPCCR register, not on the current state of the CPU/NVIC.
       */
 -    NVICState *s = (NVICState *)opaque;
      bool banked = exc_is_banked(irq);
      VecInfo *vec;
      bool targets_secure;
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
  }
  /* Make pending IRQ active.  */
 -void armv7m_nvic_acknowledge_irq(void *opaque)
 +void armv7m_nvic_acknowledge_irq(NVICState *s)
  {
 -    NVICState *s = (NVICState *)opaque;
      CPUARMState *env = &s->cpu->env;
      const int pending = s->vectpending;
      const int running = nvic_exec_prio(s);
@@ -XXX,XX +XXX,XX @@ static bool vectpending_targets_secure(NVICState *s)
          exc_targets_secure(s, s->vectpending);
  }
 -void armv7m_nvic_get_pending_irq_info(void *opaque,
 +void armv7m_nvic_get_pending_irq_info(NVICState *s,
                                        int *pirq, bool *ptargets_secure)
  {
 -    NVICState *s = (NVICState *)opaque;
      const int pending = s->vectpending;
      bool targets_secure;
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque,
      *pirq = pending;
  }
 -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
 +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure)
  {
 -    NVICState *s = (NVICState *)opaque;
      VecInfo *vec = NULL;
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
      return ret;
  }
 -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
 +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure)
  {
      /*
       * Return whether an exception is "ready", i.e. it is enabled and is
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
       * for non-banked exceptions secure is always false; for banked exceptions
       * it indicates which of the exceptions is required.
       */
 -    NVICState *s = (NVICState *)opaque;
      bool banked = exc_is_banked(irq);
      VecInfo *vec;
      int running = nvic_exec_prio(s);
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
  #if !defined(CONFIG_USER_ONLY)
  #include "hw/loader.h"
  #include "hw/boards.h"
 +#include "hw/intc/armv7m_nvic.h"
  #endif
  #include "sysemu/tcg.h"
  #include "sysemu/qtest.h"
 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/m_helper.c
 +++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr,
       * that we will need later in order to do lazy FP reg stacking.
       */
      bool is_secure = env->v7m.secure;
 -    void *nvic = env->nvic;
 +    NVICState *nvic = env->nvic;
      /*
       * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits
       * are banked and we want to update the bit in the bank for the
 --
-.25.1
+.34.1

-New patch
+[PULL 11/30] target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 While dozens of files include "cpu.h", only 3 files require
 these NVIC helper declarations.
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20230206223502.25122-12-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++
  target/arm/cpu.h              | 123 ----------------------------------
  target/arm/cpu.c              |   4 +-
  target/arm/cpu_tcg.c          |   3 +
  target/arm/m_helper.c         |   3 +
 files changed, 132 insertions(+), 124 deletions(-)
 diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/intc/armv7m_nvic.h
 +++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@ struct NVICState {
      qemu_irq sysresetreq;
  };
 +/* Interface between CPU and Interrupt controller.  */
 +/**
 + * armv7m_nvic_set_pending: mark the specified exception as pending
 + * @s: the NVIC
 + * @irq: the exception number to mark pending
 + * @secure: false for non-banked exceptions or for the nonsecure
 + * version of a banked exception, true for the secure version of a banked
 + * exception.
 + *
 + * Marks the specified exception as pending. Note that we will assert()
 + * if @secure is true and @irq does not specify one of the fixed set
 + * of architecturally banked exceptions.
 + */
 +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_set_pending_derived: mark this derived exception as pending
 + * @s: the NVIC
 + * @irq: the exception number to mark pending
 + * @secure: false for non-banked exceptions or for the nonsecure
 + * version of a banked exception, true for the secure version of a banked
 + * exception.
 + *
 + * Similar to armv7m_nvic_set_pending(), but specifically for derived
 + * exceptions (exceptions generated in the course of trying to take
 + * a different exception).
 + */
 +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
 + * @s: the NVIC
 + * @irq: the exception number to mark pending
 + * @secure: false for non-banked exceptions or for the nonsecure
 + * version of a banked exception, true for the secure version of a banked
 + * exception.
 + *
 + * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
 + * generated in the course of lazy stacking of FP registers.
 + */
 +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_get_pending_irq_info: return highest priority pending
 + *    exception, and whether it targets Secure state
 + * @s: the NVIC
 + * @pirq: set to pending exception number
 + * @ptargets_secure: set to whether pending exception targets Secure
 + *
 + * This function writes the number of the highest priority pending
 + * exception (the one which would be made active by
 + * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
 + * to true if the current highest priority pending exception should
 + * be taken to Secure state, false for NS.
 + */
 +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
 +                                      bool *ptargets_secure);
 +/**
 + * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
 + * @s: the NVIC
 + *
 + * Move the current highest priority pending exception from the pending
 + * state to the active state, and update v7m.exception to indicate that
 + * it is the exception currently being handled.
 + */
 +void armv7m_nvic_acknowledge_irq(NVICState *s);
 +/**
 + * armv7m_nvic_complete_irq: complete specified interrupt or exception
 + * @s: the NVIC
 + * @irq: the exception number to complete
 + * @secure: true if this exception was secure
 + *
 + * Returns: -1 if the irq was not active
 + *           1 if completing this irq brought us back to base (no active irqs)
 + *           0 if there is still an irq active after this one was completed
 + * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
 + */
 +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
 + * @s: the NVIC
 + * @irq: the exception number to mark pending
 + * @secure: false for non-banked exceptions or for the nonsecure
 + * version of a banked exception, true for the secure version of a banked
 + * exception.
 + *
 + * Return whether an exception is "ready", i.e. whether the exception is
 + * enabled and is configured at a priority which would allow it to
 + * interrupt the current execution priority. This controls whether the
 + * RDY bit for it in the FPCCR is set.
 + */
 +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_raw_execution_priority: return the raw execution priority
 + * @s: the NVIC
 + *
 + * Returns: the raw execution priority as defined by the v8M architecture.
 + * This is the execution priority minus the effects of AIRCR.PRIS,
 + * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
 + * (v8M ARM ARM I_PKLD.)
 + */
 +int armv7m_nvic_raw_execution_priority(NVICState *s);
 +/**
 + * armv7m_nvic_neg_prio_requested: return true if the requested execution
 + * priority is negative for the specified security state.
 + * @s: the NVIC
 + * @secure: the security state to test
 + * This corresponds to the pseudocode IsReqExecPriNeg().
 + */
 +#ifndef CONFIG_USER_ONLY
 +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
 +#else
 +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
 +{
 +    return false;
 +}
 +#endif
 +#ifndef CONFIG_USER_ONLY
 +bool armv7m_nvic_can_take_pending_exception(NVICState *s);
 +#else
 +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
 +{
 +    return true;
 +}
 +#endif
 +
  #endif
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
  uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                   uint32_t cur_el, bool secure);
 -/* Interface between CPU and Interrupt controller.  */
 -#ifndef CONFIG_USER_ONLY
 -bool armv7m_nvic_can_take_pending_exception(NVICState *s);
 -#else
 -static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
 -{
 -    return true;
 -}
 -#endif
 -/**
 - * armv7m_nvic_set_pending: mark the specified exception as pending
 - * @s: the NVIC
 - * @irq: the exception number to mark pending
 - * @secure: false for non-banked exceptions or for the nonsecure
 - * version of a banked exception, true for the secure version of a banked
 - * exception.
 - *
 - * Marks the specified exception as pending. Note that we will assert()
 - * if @secure is true and @irq does not specify one of the fixed set
 - * of architecturally banked exceptions.
 - */
 -void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_set_pending_derived: mark this derived exception as pending
 - * @s: the NVIC
 - * @irq: the exception number to mark pending
 - * @secure: false for non-banked exceptions or for the nonsecure
 - * version of a banked exception, true for the secure version of a banked
 - * exception.
 - *
 - * Similar to armv7m_nvic_set_pending(), but specifically for derived
 - * exceptions (exceptions generated in the course of trying to take
 - * a different exception).
 - */
 -void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
 - * @s: the NVIC
 - * @irq: the exception number to mark pending
 - * @secure: false for non-banked exceptions or for the nonsecure
 - * version of a banked exception, true for the secure version of a banked
 - * exception.
 - *
 - * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
 - * generated in the course of lazy stacking of FP registers.
 - */
 -void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_get_pending_irq_info: return highest priority pending
 - *    exception, and whether it targets Secure state
 - * @s: the NVIC
 - * @pirq: set to pending exception number
 - * @ptargets_secure: set to whether pending exception targets Secure
 - *
 - * This function writes the number of the highest priority pending
 - * exception (the one which would be made active by
 - * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
 - * to true if the current highest priority pending exception should
 - * be taken to Secure state, false for NS.
 - */
 -void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
 -                                      bool *ptargets_secure);
 -/**
 - * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
 - * @s: the NVIC
 - *
 - * Move the current highest priority pending exception from the pending
 - * state to the active state, and update v7m.exception to indicate that
 - * it is the exception currently being handled.
 - */
 -void armv7m_nvic_acknowledge_irq(NVICState *s);
 -/**
 - * armv7m_nvic_complete_irq: complete specified interrupt or exception
 - * @s: the NVIC
 - * @irq: the exception number to complete
 - * @secure: true if this exception was secure
 - *
 - * Returns: -1 if the irq was not active
 - *           1 if completing this irq brought us back to base (no active irqs)
 - *           0 if there is still an irq active after this one was completed
 - * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
 - */
 -int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
 - * @s: the NVIC
 - * @irq: the exception number to mark pending
 - * @secure: false for non-banked exceptions or for the nonsecure
 - * version of a banked exception, true for the secure version of a banked
 - * exception.
 - *
 - * Return whether an exception is "ready", i.e. whether the exception is
 - * enabled and is configured at a priority which would allow it to
 - * interrupt the current execution priority. This controls whether the
 - * RDY bit for it in the FPCCR is set.
 - */
 -bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_raw_execution_priority: return the raw execution priority
 - * @s: the NVIC
 - *
 - * Returns: the raw execution priority as defined by the v8M architecture.
 - * This is the execution priority minus the effects of AIRCR.PRIS,
 - * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
 - * (v8M ARM ARM I_PKLD.)
 - */
 -int armv7m_nvic_raw_execution_priority(NVICState *s);
 -/**
 - * armv7m_nvic_neg_prio_requested: return true if the requested execution
 - * priority is negative for the specified security state.
 - * @s: the NVIC
 - * @secure: the security state to test
 - * This corresponds to the pseudocode IsReqExecPriNeg().
 - */
 -#ifndef CONFIG_USER_ONLY
 -bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
 -#else
 -static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
 -{
 -    return false;
 -}
 -#endif
 -
  /* Interface for defining coprocessor registers.
   * Registers are defined in tables of arm_cp_reginfo structs
   * which are passed to define_arm_cp_regs().
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
  #if !defined(CONFIG_USER_ONLY)
  #include "hw/loader.h"
  #include "hw/boards.h"
 +#ifdef CONFIG_TCG
  #include "hw/intc/armv7m_nvic.h"
 -#endif
 +#endif /* CONFIG_TCG */
 +#endif /* !CONFIG_USER_ONLY */
  #include "sysemu/tcg.h"
  #include "sysemu/qtest.h"
  #include "sysemu/hw_accel.h"
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/boards.h"
  #endif
  #include "cpregs.h"
 +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
 +#include "hw/intc/armv7m_nvic.h"
 +#endif
  /* Share AArch32 -cpu max features with AArch64. */
 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/m_helper.c
 +++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@
  #include "exec/cpu_ldst.h"
  #include "semihosting/common-semi.h"
  #endif
 +#if !defined(CONFIG_USER_ONLY)
 +#include "hw/intc/armv7m_nvic.h"
 +#endif
  static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask,
                           uint32_t reg, uint32_t val)
 --
 .34.1

-New patch
+[PULL 12/30] tests/avocado: retire the Aarch64 TCG tests from boot_linux.py
+From: Alex Bennée <alex.bennee@linaro.org>
 The two TCG tests for GICv2 and GICv3 are very heavy weight distros
 that take a long time to boot up, especially for an --enable-debug
 build. The total code coverage they give is:
   Overall coverage rate:
     lines......: 11.2% (59584 of 530123 lines)
     functions..: 15.0% (7436 of 49443 functions)
     branches...: 6.3% (19273 of 303933 branches)
 We already get pretty close to that with the machine_aarch64_virt
 tests which only does one full boot (~120s vs ~600s) of alpine. We
 expand the kernel+initrd boot (~8s) to test both GICs and also add an
 RNG device and a block device to generate a few IRQs and exercise the
 storage layer. With that we get to a coverage of:
   Overall coverage rate:
     lines......: 11.0% (58121 of 530123 lines)
     functions..: 14.9% (7343 of 49443 functions)
     branches...: 6.0% (18269 of 303933 branches)
 which I feel is close enough given the massive time saving. If we want
 to target any more sub-systems we can use lighter weight more directed
 tests.
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Fabiano Rosas <farosas@suse.de>
 Acked-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230203181632.2919715-1-alex.bennee@linaro.org
 Cc: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  tests/avocado/boot_linux.py           | 48 ++++----------------
  tests/avocado/machine_aarch64_virt.py | 63 ++++++++++++++++++++++++---
 files changed, 65 insertions(+), 46 deletions(-)
 diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/avocado/boot_linux.py
 +++ b/tests/avocado/boot_linux.py
@@ -XXX,XX +XXX,XX @@ def test_pc_q35_kvm(self):
          self.launch_and_wait(set_up_ssh_connection=False)
 -# For Aarch64 we only boot KVM tests in CI as the TCG tests are very
 -# heavyweight. There are lighter weight distros which we use in the
 -# machine_aarch64_virt.py tests.
 +# For Aarch64 we only boot KVM tests in CI as booting the current
 +# Fedora OS in TCG tests is very heavyweight. There are lighter weight
 +# distros which we use in the machine_aarch64_virt.py tests.
  class BootLinuxAarch64(LinuxTest):
      """
      :avocado: tags=arch:aarch64
      :avocado: tags=machine:virt
 -    :avocado: tags=machine:gic-version=2
      """
      timeout = 720
 -    def add_common_args(self):
 -        self.vm.add_args('-bios',
 -                         os.path.join(BUILD_DIR, 'pc-bios',
 -                                      'edk2-aarch64-code.fd'))
 -        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
 -        self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
 -
 -    @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
 -    def test_fedora_cloud_tcg_gicv2(self):
 -        """
 -        :avocado: tags=accel:tcg
 -        :avocado: tags=cpu:max
 -        :avocado: tags=device:gicv2
 -        """
 -        self.require_accelerator("tcg")
 -        self.vm.add_args("-accel", "tcg")
 -        self.vm.add_args("-cpu", "max,lpa2=off")
 -        self.vm.add_args("-machine", "virt,gic-version=2")
 -        self.add_common_args()
 -        self.launch_and_wait(set_up_ssh_connection=False)
 -
 -    @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
 -    def test_fedora_cloud_tcg_gicv3(self):
 -        """
 -        :avocado: tags=accel:tcg
 -        :avocado: tags=cpu:max
 -        :avocado: tags=device:gicv3
 -        """
 -        self.require_accelerator("tcg")
 -        self.vm.add_args("-accel", "tcg")
 -        self.vm.add_args("-cpu", "max,lpa2=off")
 -        self.vm.add_args("-machine", "virt,gic-version=3")
 -        self.add_common_args()
 -        self.launch_and_wait(set_up_ssh_connection=False)
 -
      def test_virt_kvm(self):
          """
          :avocado: tags=accel:kvm
@@ -XXX,XX +XXX,XX @@ def test_virt_kvm(self):
          self.require_accelerator("kvm")
          self.vm.add_args("-accel", "kvm")
          self.vm.add_args("-machine", "virt,gic-version=host")
 -        self.add_common_args()
 +        self.vm.add_args('-bios',
 +                         os.path.join(BUILD_DIR, 'pc-bios',
 +                                      'edk2-aarch64-code.fd'))
 +        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
 +        self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
          self.launch_and_wait(set_up_ssh_connection=False)
 diff --git a/tests/avocado/machine_aarch64_virt.py b/tests/avocado/machine_aarch64_virt.py
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/avocado/machine_aarch64_virt.py
 +++ b/tests/avocado/machine_aarch64_virt.py
@@ -XXX,XX +XXX,XX @@
  import time
  import os
 +import logging
  from avocado_qemu import QemuSystemTest
  from avocado_qemu import wait_for_console_pattern
  from avocado_qemu import exec_command
  from avocado_qemu import BUILD_DIR
 +from avocado.utils import process
 +from avocado.utils.path import find_command
  class Aarch64VirtMachine(QemuSystemTest):
      KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
@@ -XXX,XX +XXX,XX @@ def test_alpine_virt_tcg_gic_max(self):
          self.wait_for_console_pattern('Welcome to Alpine Linux 3.16')
 -    def test_aarch64_virt(self):
 +    def common_aarch64_virt(self, machine):
          """
 -        :avocado: tags=arch:aarch64
 -        :avocado: tags=machine:virt
 -        :avocado: tags=accel:tcg
 -        :avocado: tags=cpu:max
 +        Common code to launch basic virt machine with kernel+initrd
 +        and a scratch disk.
          """
 +        logger = logging.getLogger('aarch64_virt')
 +
          kernel_url = ('https://fileserver.linaro.org/s/'
                        'z6B2ARM7DQT3HWN/download')
 -
          kernel_hash = 'ed11daab50c151dde0e1e9c9cb8b2d9bd3215347'
          kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
@@ -XXX,XX +XXX,XX @@ def test_aarch64_virt(self):
                                 'console=ttyAMA0')
          self.require_accelerator("tcg")
          self.vm.add_args('-cpu', 'max,pauth-impdef=on',
 +                         '-machine', machine,
                           '-accel', 'tcg',
                           '-kernel', kernel_path,
                           '-append', kernel_command_line)
 +
 +        # A RNG offers an easy way to generate a few IRQs
 +        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
 +        self.vm.add_args('-object',
 +                         'rng-random,id=rng0,filename=/dev/urandom')
 +
 +        # Also add a scratch block device
 +        logger.info('creating scratch qcow2 image')
 +        image_path = os.path.join(self.workdir, 'scratch.qcow2')
 +        qemu_img = os.path.join(BUILD_DIR, 'qemu-img')
 +        if not os.path.exists(qemu_img):
 +            qemu_img = find_command('qemu-img', False)
 +        if qemu_img is False:
 +            self.cancel('Could not find "qemu-img", which is required to '
 +                        'create the temporary qcow2 image')
 +        cmd = '%s create -f qcow2 %s 8M' % (qemu_img, image_path)
 +        process.run(cmd)
 +
 +        # Add the device
 +        self.vm.add_args('-blockdev',
 +                         f"driver=qcow2,file.driver=file,file.filename={image_path},node-name=scratch")
 +        self.vm.add_args('-device',
 +                         'virtio-blk-device,drive=scratch')
 +
          self.vm.launch()
          self.wait_for_console_pattern('Welcome to Buildroot')
          time.sleep(0.1)
          exec_command(self, 'root')
          time.sleep(0.1)
 +        exec_command(self, 'dd if=/dev/hwrng of=/dev/vda bs=512 count=4')
 +        time.sleep(0.1)
 +        exec_command(self, 'md5sum /dev/vda')
 +        time.sleep(0.1)
 +        exec_command(self, 'cat /proc/interrupts')
 +        time.sleep(0.1)
          exec_command(self, 'cat /proc/self/maps')
          time.sleep(0.1)
 +
 +    def test_aarch64_virt_gicv3(self):
 +        """
 +        :avocado: tags=arch:aarch64
 +        :avocado: tags=machine:virt
 +        :avocado: tags=accel:tcg
 +        :avocado: tags=cpu:max
 +        """
 +        self.common_aarch64_virt("virt,gic_version=3")
 +
 +    def test_aarch64_virt_gicv2(self):
 +        """
 +        :avocado: tags=arch:aarch64
 +        :avocado: tags=machine:virt
 +        :avocado: tags=accel:tcg
 +        :avocado: tags=cpu:max
 +        """
 +        self.common_aarch64_virt("virt,gic-version=2")
 --
 .34.1

-[PULL 05/10] hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
+[PULL 13/30] hw/arm/smmuv3: Add GBPA register
-From: Francisco Iglesias <francisco.iglesias@amd.com>
+From: Mostafa Saleh <smostafa@google.com>
-Connect ZynqMP's USB controllers.
+GBPA register can be used to globally abort all
 transactions.
-Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
+It is described in the SMMU manual in "6.3.14 SMMU_GBPA".
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to
-Message-id: 20220920081517.25401-1-frasse.iglesias@gmail.com
+be zero(Do not abort incoming transactions).
 Other fields have default values of Use Incoming.
 If UPDATE is not set, the write is ignored. This is the only permitted
 behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure)
 As this patch adds a new state to the SMMU (GBPA), it is added
 in a new subsection for forward migration compatibility.
 GBPA is only migrated if its value is different from the reset value.
 It does this to be backward migration compatible if SW didn't write
 the register.
 Signed-off-by: Mostafa Saleh <smostafa@google.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 20230214094009.2445653-1-smostafa@google.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/xlnx-zynqmp.h |  3 +++
+ hw/arm/smmuv3-internal.h |  7 +++++++
- hw/arm/xlnx-zynqmp.c         | 36 ++++++++++++++++++++++++++++++++++++
+ include/hw/arm/smmuv3.h  |  1 +
-files changed, 39 insertions(+)
+ hw/arm/smmuv3.c          | 43 +++++++++++++++++++++++++++++++++++++++-
 files changed, 50 insertions(+), 1 deletion(-)
-diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
+diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/xlnx-zynqmp.h
+--- a/hw/arm/smmuv3-internal.h
-+++ b/include/hw/arm/xlnx-zynqmp.h
++++ b/hw/arm/smmuv3-internal.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ REG32(CR0ACK,              0x24)
- #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
+ REG32(CR1,                 0x28)
- #include "hw/misc/xlnx-zynqmp-crf.h"
+ REG32(CR2,                 0x2c)
- #include "hw/timer/cadence_ttc.h"
+ REG32(STATUSR,             0x40)
-+#include "hw/usb/hcd-dwc3.h"
++REG32(GBPA,                0x44)
++    FIELD(GBPA, ABORT,        20, 1)
- #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
++    FIELD(GBPA, UPDATE,       31, 1)
- OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
++
-@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
++/* Use incoming. */
- #define XLNX_ZYNQMP_NUM_SPIS 2
++#define SMMU_GBPA_RESET_VAL 0x1000
- #define XLNX_ZYNQMP_NUM_GDMA_CH 8
++
- #define XLNX_ZYNQMP_NUM_ADMA_CH 8
+ REG32(IRQ_CTRL,            0x50)
-+#define XLNX_ZYNQMP_NUM_USB 2
+     FIELD(IRQ_CTRL, GERROR_IRQEN,        0, 1)
+     FIELD(IRQ_CTRL, PRI_IRQEN,           1, 1)
- #define XLNX_ZYNQMP_NUM_QSPI_BUS 2
+diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
  #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
      XlnxZynqMPAPUCtrl apu_ctrl;
      XlnxZynqMPCRF crf;
      CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
 +    USBDWC3 usb[XLNX_ZYNQMP_NUM_USB];
      char *boot_cpu;
      ARMCPU *boot_cpu_ptr;
 diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-zynqmp.c
+--- a/include/hw/arm/smmuv3.h
-+++ b/hw/arm/xlnx-zynqmp.c
++++ b/include/hw/arm/smmuv3.h
-@@ -XXX,XX +XXX,XX @@ static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
+@@ -XXX,XX +XXX,XX @@ struct SMMUv3State {
-, 78, 79, 80, 81, 82, 83, 84
+     uint32_t cr[3];
      uint32_t cr0ack;
      uint32_t statusr;
 +    uint32_t gbpa;
      uint32_t irq_ctrl;
      uint32_t gerror;
      uint32_t gerrorn;
 diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/smmuv3.c
 +++ b/hw/arm/smmuv3.c
@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
      s->gerror = 0;
      s->gerrorn = 0;
      s->statusr = 0;
 +    s->gbpa = SMMU_GBPA_RESET_VAL;
  }
  static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
      qemu_mutex_lock(&s->mutex);
      if (!smmu_enabled(s)) {
 -        status = SMMU_TRANS_DISABLE;
 +        if (FIELD_EX32(s->gbpa, GBPA, ABORT)) {
 +            status = SMMU_TRANS_ABORT;
 +        } else {
 +            status = SMMU_TRANS_DISABLE;
 +        }
          goto epilogue;
      }
@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,
      case A_GERROR_IRQ_CFG2:
          s->gerror_irq_cfg2 = data;
          return MEMTX_OK;
 +    case A_GBPA:
 +        /*
 +         * If UPDATE is not set, the write is ignored. This is the only
 +         * permitted behavior in SMMUv3.2 and later.
 +         */
 +        if (data & R_GBPA_UPDATE_MASK) {
 +            /* Ignore update bit as write is synchronous. */
 +            s->gbpa = data & ~R_GBPA_UPDATE_MASK;
 +        }
 +        return MEMTX_OK;
      case A_STRTAB_BASE: /* 64b */
          s->strtab_base = deposit64(s->strtab_base, 0, 32, data);
          return MEMTX_OK;
@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset,
      case A_STATUSR:
          *data = s->statusr;
          return MEMTX_OK;
 +    case A_GBPA:
 +        *data = s->gbpa;
 +        return MEMTX_OK;
      case A_IRQ_CTRL:
      case A_IRQ_CTRL_ACK:
          *data = s->irq_ctrl;
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3_queue = {
      },
  };
-+static const uint64_t usb_addr[XLNX_ZYNQMP_NUM_USB] = {
++static bool smmuv3_gbpa_needed(void *opaque)
-+    0xFE200000, 0xFE300000
++{
 +    SMMUv3State *s = opaque;
 +
 +    /* Only migrate GBPA if it has different reset value. */
 +    return s->gbpa != SMMU_GBPA_RESET_VAL;
 +}
 +
 +static const VMStateDescription vmstate_gbpa = {
 +    .name = "smmuv3/gbpa",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .needed = smmuv3_gbpa_needed,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32(gbpa, SMMUv3State),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
-+static const int usb_intr[XLNX_ZYNQMP_NUM_USB] = {
+ static const VMStateDescription vmstate_smmuv3 = {
-+    65, 70
+     .name = "smmuv3",
-+};
+     .version_id = 1,
-+
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = {
- typedef struct XlnxZynqMPGICRegion {
-     int region_index;
+         VMSTATE_END_OF_LIST(),
-     uint32_t address;
+     },
-@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj)
++    .subsections = (const VMStateDescription * []) {
-     object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
++        &vmstate_gbpa,
-     object_initialize_child(obj, "qspi-irq-orgate",
++        NULL
                              &s->qspi_irq_orgate, TYPE_OR_IRQ);
 +
 +    for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
 +        object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3);
 +    }
- }
+ };
- static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
+ static void smmuv3_instance_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
          object_property_add_alias(OBJECT(s), bus_name,
                                    OBJECT(&s->qspi), target_bus);
      }
 +
 +    for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
 +        if (!object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma",
 +                                      OBJECT(system_memory), errp)) {
 +            return;
 +        }
 +
 +        qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4);
 +        qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2);
 +
 +        if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) {
 +            return;
 +        }
 +
 +        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_addr[i]);
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0,
 +                           gic_spi[usb_intr[i]]);
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 1,
 +                           gic_spi[usb_intr[i] + 1]);
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 2,
 +                           gic_spi[usb_intr[i] + 2]);
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 3,
 +                           gic_spi[usb_intr[i] + 3]);
 +    }
  }
  static Property xlnx_zynqmp_props[] = {
 --
-.25.1
+.34.1

-New patch
+[PULL 14/30] hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Since commit acc0b8b05a when running the ZynqMP ZCU102 board with
+a QEMU configured using --without-default-devices, we get:
+  $ qemu-system-aarch64 -M xlnx-zcu102
+  qemu-system-aarch64: missing object type 'usb_dwc3'
+  Abort trap: 6
+Fix by adding the missing Kconfig dependency.
+Fixes: acc0b8b05a ("hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers")
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230216092327.2203-1-philmd@linaro.org
+Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/Kconfig | 1 +
+file changed, 1 insertion(+)
+diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/Kconfig
++++ b/hw/arm/Kconfig
+@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP_ARM
+     select XLNX_CSU_DMA
+     select XLNX_ZYNQMP
+     select XLNX_ZDMA
++    select USB_DWC3
+ config XLNX_VERSAL
+     bool
+--
+.34.1

-[PULL 08/10] hw/arm/virt: Use "msi-map" devicetree property for PCI
+[PULL 15/30] arm/virt: don't try to spell out the accelerator
-From: Jean-Philippe Brucker <jean-philippe@linaro.org>
+From: Cornelia Huck <cohuck@redhat.com>
-The "msi-parent" property can be used on the PCI node when MSIs do not
+Just use current_accel_name() directly.
 contain sideband data (device IDs) [1]. In QEMU, MSI transactions
 contain the requester ID, so the PCI node should use the "msi-map"
 property instead of "msi-parent". In our case the property describes an
 identity map between requester ID and sideband data.
-This fixes a warning when passing the DTB generated by QEMU to dtc,
+Signed-off-by: Cornelia Huck <cohuck@redhat.com>
 following a recent change to the GICv3 node:
   Warning (msi_parent_property): /pcie@10000000:msi-parent: property size (4) too small for cell size 1
 [1] linux/Documentation/devicetree/bindings/pci/pci-msi.txt
 Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Message-id: 20220927100347.176606-4-jean-philippe@linaro.org
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 4 ++--
+ hw/arm/virt.c | 6 +++---
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 3 insertions(+), 3 deletions(-)
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ static void create_pcie(VirtMachineState *vms)
+@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
-     qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
+     if (vms->secure && (kvm_enabled() || hvf_enabled())) {
+         error_report("mach-virt: %s does not support providing "
-     if (vms->msi_phandle) {
+                      "Security extensions (TrustZone) to the guest CPU",
--        qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",
+-                     kvm_enabled() ? "KVM" : "HVF");
--                               vms->msi_phandle);
++                     current_accel_name());
-+        qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
+         exit(1);
 +                               0, vms->msi_phandle, 0, 0x10000);
      }
-     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
+     if (vms->virt && (kvm_enabled() || hvf_enabled())) {
          error_report("mach-virt: %s does not support providing "
                       "Virtualization extensions to the guest CPU",
 -                     kvm_enabled() ? "KVM" : "HVF");
 +                     current_accel_name());
          exit(1);
      }
      if (vms->mte && (kvm_enabled() || hvf_enabled())) {
          error_report("mach-virt: %s does not support providing "
                       "MTE to the guest CPU",
 -                     kvm_enabled() ? "KVM" : "HVF");
 +                     current_accel_name());
          exit(1);
      }
 --
-.25.1
+.34.1

-New patch
+[PULL 16/30] MAINTAINERS: Add myself to maintainers and remove Havard
+From: Hao Wu <wuhaotsh@google.com>
+Havard is no longer working on the Nuvoton systems for a while
+and won't be able to do any work on it in the future. So I'll
+take over maintaining the Nuvoton system from him.
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Acked-by: Havard Skinnemoen <hskinnemoen@google.com>
+Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
+Message-id: 20230208235433.3989937-2-wuhaotsh@google.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ MAINTAINERS | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ F: include/hw/net/mv88w8618_eth.h
+ F: docs/system/arm/musicpal.rst
+ Nuvoton NPCM7xx
+-M: Havard Skinnemoen <hskinnemoen@google.com>
+ M: Tyrone Ting <kfting@nuvoton.com>
++M: Hao Wu <wuhaotsh@google.com>
+ L: qemu-arm@nongnu.org
+ S: Supported
+ F: hw/*/npcm7xx*
+--
+.34.1

-New patch
+[PULL 17/30] hw/ssi: Add Nuvoton PSPI Module
+From: Hao Wu <wuhaotsh@google.com>
+Nuvoton's PSPI is a general purpose SPI module which enables
+connections to SPI-based peripheral devices.
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Reviewed-by: Chris Rauer <crauer@google.com>
+Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
+Message-id: 20230208235433.3989937-3-wuhaotsh@google.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ MAINTAINERS                |   6 +-
+ include/hw/ssi/npcm_pspi.h |  53 +++++++++
+ hw/ssi/npcm_pspi.c         | 221 +++++++++++++++++++++++++++++++++++++
+ hw/ssi/meson.build         |   2 +-
+ hw/ssi/trace-events        |   5 +
+files changed, 283 insertions(+), 4 deletions(-)
+ create mode 100644 include/hw/ssi/npcm_pspi.h
+ create mode 100644 hw/ssi/npcm_pspi.c
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ M: Tyrone Ting <kfting@nuvoton.com>
+ M: Hao Wu <wuhaotsh@google.com>
+ L: qemu-arm@nongnu.org
+ S: Supported
+-F: hw/*/npcm7xx*
+-F: include/hw/*/npcm7xx*
+-F: tests/qtest/npcm7xx*
++F: hw/*/npcm*
++F: include/hw/*/npcm*
++F: tests/qtest/npcm*
+ F: pc-bios/npcm7xx_bootrom.bin
+ F: roms/vbootrom
+ F: docs/system/arm/nuvoton.rst
+diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/include/hw/ssi/npcm_pspi.h
+@@ -XXX,XX +XXX,XX @@
++/*
++ * Nuvoton Peripheral SPI Module
++ *
++ * Copyright 2023 Google LLC
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++#ifndef NPCM_PSPI_H
++#define NPCM_PSPI_H
++
++#include "hw/ssi/ssi.h"
++#include "hw/sysbus.h"
++
++/*
++ * Number of registers in our device state structure. Don't change this without
++ * incrementing the version_id in the vmstate.
++ */
++#define NPCM_PSPI_NR_REGS 3
++
++/**
++ * NPCMPSPIState - Device state for one Flash Interface Unit.
++ * @parent: System bus device.
++ * @mmio: Memory region for register access.
++ * @spi: The SPI bus mastered by this controller.
++ * @regs: Register contents.
++ * @irq: The interrupt request queue for this module.
++ *
++ * Each PSPI has a shared bank of registers, and controls up to four chip
++ * selects. Each chip select has a dedicated memory region which may be used to
++ * read and write the flash connected to that chip select as if it were memory.
++ */
++typedef struct NPCMPSPIState {
++    SysBusDevice parent;
++
++    MemoryRegion mmio;
++
++    SSIBus *spi;
++    uint16_t regs[NPCM_PSPI_NR_REGS];
++    qemu_irq irq;
++} NPCMPSPIState;
++
++#define TYPE_NPCM_PSPI "npcm-pspi"
++OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI)
++
++#endif /* NPCM_PSPI_H */
+diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/hw/ssi/npcm_pspi.c
+@@ -XXX,XX +XXX,XX @@
++/*
++ * Nuvoton NPCM Peripheral SPI Module (PSPI)
++ *
++ * Copyright 2023 Google LLC
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++
++#include "qemu/osdep.h"
++
++#include "hw/irq.h"
++#include "hw/registerfields.h"
++#include "hw/ssi/npcm_pspi.h"
++#include "migration/vmstate.h"
++#include "qapi/error.h"
++#include "qemu/error-report.h"
++#include "qemu/log.h"
++#include "qemu/module.h"
++#include "qemu/units.h"
++
++#include "trace.h"
++
++REG16(PSPI_DATA, 0x0)
++REG16(PSPI_CTL1, 0x2)
++    FIELD(PSPI_CTL1, SPIEN, 0,  1)
++    FIELD(PSPI_CTL1, MOD,   2,  1)
++    FIELD(PSPI_CTL1, EIR,   5,  1)
++    FIELD(PSPI_CTL1, EIW,   6,  1)
++    FIELD(PSPI_CTL1, SCM,   7,  1)
++    FIELD(PSPI_CTL1, SCIDL, 8,  1)
++    FIELD(PSPI_CTL1, SCDV,  9,  7)
++REG16(PSPI_STAT, 0x4)
++    FIELD(PSPI_STAT, BSY,  0,  1)
++    FIELD(PSPI_STAT, RBF,  1,  1)
++
++static void npcm_pspi_update_irq(NPCMPSPIState *s)
++{
++    int level = 0;
++
++    /* Only fire IRQ when the module is enabled. */
++    if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) {
++        /* Update interrupt as BSY is cleared. */
++        if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) &&
++            FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) {
++            level = 1;
++        }
++
++        /* Update interrupt as RBF is set. */
++        if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) &&
++            FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) {
++            level = 1;
++        }
++    }
++    qemu_set_irq(s->irq, level);
++}
++
++static uint16_t npcm_pspi_read_data(NPCMPSPIState *s)
++{
++    uint16_t value = s->regs[R_PSPI_DATA];
++
++    /* Clear stat bits as the value are read out. */
++    s->regs[R_PSPI_STAT] = 0;
++
++    return value;
++}
++
++static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data)
++{
++    uint16_t value = 0;
++
++    if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) {
++        value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8;
++    }
++    value |= ssi_transfer(s->spi, extract16(data, 0, 8));
++    s->regs[R_PSPI_DATA] = value;
++
++    /* Mark data as available */
++    s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK;
++}
++
++/* Control register read handler. */
++static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr,
++                                    unsigned int size)
++{
++    NPCMPSPIState *s = opaque;
++    uint16_t value;
++
++    switch (addr) {
++    case A_PSPI_DATA:
++        value = npcm_pspi_read_data(s);
++        break;
++
++    case A_PSPI_CTL1:
++        value = s->regs[R_PSPI_CTL1];
++        break;
++
++    case A_PSPI_STAT:
++        value = s->regs[R_PSPI_STAT];
++        break;
++
++    default:
++        qemu_log_mask(LOG_GUEST_ERROR,
++                      "%s: write to invalid offset 0x%" PRIx64 "\n",
++                      DEVICE(s)->canonical_path, addr);
++        return 0;
++    }
++    trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value);
++    npcm_pspi_update_irq(s);
++
++    return value;
++}
++
++/* Control register write handler. */
++static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v,
++                                 unsigned int size)
++{
++    NPCMPSPIState *s = opaque;
++    uint16_t value = v;
++
++    trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value);
++
++    switch (addr) {
++    case A_PSPI_DATA:
++        npcm_pspi_write_data(s, value);
++        break;
++
++    case A_PSPI_CTL1:
++        s->regs[R_PSPI_CTL1] = value;
++        break;
++
++    case A_PSPI_STAT:
++        qemu_log_mask(LOG_GUEST_ERROR,
++                      "%s: write to read-only register PSPI_STAT: 0x%08"
++                      PRIx64 "\n", DEVICE(s)->canonical_path, v);
++        break;
++
++    default:
++        qemu_log_mask(LOG_GUEST_ERROR,
++                      "%s: write to invalid offset 0x%" PRIx64 "\n",
++                      DEVICE(s)->canonical_path, addr);
++        return;
++    }
++    npcm_pspi_update_irq(s);
++}
++
++static const MemoryRegionOps npcm_pspi_ctrl_ops = {
++    .read = npcm_pspi_ctrl_read,
++    .write = npcm_pspi_ctrl_write,
++    .endianness = DEVICE_LITTLE_ENDIAN,
++    .valid = {
++        .min_access_size = 1,
++        .max_access_size = 2,
++        .unaligned = false,
++    },
++    .impl = {
++        .min_access_size = 2,
++        .max_access_size = 2,
++        .unaligned = false,
++    },
++};
++
++static void npcm_pspi_enter_reset(Object *obj, ResetType type)
++{
++    NPCMPSPIState *s = NPCM_PSPI(obj);
++
++    trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type);
++    memset(s->regs, 0, sizeof(s->regs));
++}
++
++static void npcm_pspi_realize(DeviceState *dev, Error **errp)
++{
++    NPCMPSPIState *s = NPCM_PSPI(dev);
++    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
++    Object *obj = OBJECT(dev);
++
++    s->spi = ssi_create_bus(dev, "pspi");
++    memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s,
++                          "mmio", 4 * KiB);
++    sysbus_init_mmio(sbd, &s->mmio);
++    sysbus_init_irq(sbd, &s->irq);
++}
++
++static const VMStateDescription vmstate_npcm_pspi = {
++    .name = "npcm-pspi",
++    .version_id = 0,
++    .minimum_version_id = 0,
++    .fields = (VMStateField[]) {
++        VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS),
++        VMSTATE_END_OF_LIST(),
++    },
++};
++
++
++static void npcm_pspi_class_init(ObjectClass *klass, void *data)
++{
++    ResettableClass *rc = RESETTABLE_CLASS(klass);
++    DeviceClass *dc = DEVICE_CLASS(klass);
++
++    dc->desc = "NPCM Peripheral SPI Module";
++    dc->realize = npcm_pspi_realize;
++    dc->vmsd = &vmstate_npcm_pspi;
++    rc->phases.enter = npcm_pspi_enter_reset;
++}
++
++static const TypeInfo npcm_pspi_types[] = {
++    {
++        .name = TYPE_NPCM_PSPI,
++        .parent = TYPE_SYS_BUS_DEVICE,
++        .instance_size = sizeof(NPCMPSPIState),
++        .class_init = npcm_pspi_class_init,
++    },
++};
++DEFINE_TYPES(npcm_pspi_types);
+diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/ssi/meson.build
++++ b/hw/ssi/meson.build
+@@ -XXX,XX +XXX,XX @@
+ softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c'))
+ softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c'))
+-softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c'))
++softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'npcm_pspi.c'))
+ softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c'))
+ softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c'))
+ softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c'))
+diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/ssi/trace-events
++++ b/hw/ssi/trace-events
+@@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset:
+ npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
+ npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
++# npcm_pspi.c
++npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d"
++npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
++npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
++
+ # ibex_spi_host.c
+ ibex_spi_host_reset(const char *msg) "%s"
+--
+.34.1

-New patch
+[PULL 18/30] hw/arm: Attach PSPI module to NPCM7XX SoC
+From: Hao Wu <wuhaotsh@google.com>
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Reviewed-by: Titus Rwantare <titusr@google.com>
+Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
+Message-id: 20230208235433.3989937-4-wuhaotsh@google.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ docs/system/arm/nuvoton.rst |  2 +-
+ include/hw/arm/npcm7xx.h    |  2 ++
+ hw/arm/npcm7xx.c            | 25 +++++++++++++++++++++++--
+files changed, 26 insertions(+), 3 deletions(-)
+diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/system/arm/nuvoton.rst
++++ b/docs/system/arm/nuvoton.rst
+@@ -XXX,XX +XXX,XX @@ Supported devices
+  * SMBus controller (SMBF)
+  * Ethernet controller (EMC)
+  * Tachometer
++ * Peripheral SPI controller (PSPI)
+ Missing devices
+ ---------------
+@@ -XXX,XX +XXX,XX @@ Missing devices
+  * Ethernet controller (GMAC)
+  * USB device (USBD)
+- * Peripheral SPI controller (PSPI)
+  * SD/MMC host
+  * PECI interface
+  * PCI and PCIe root complex and bridges
+diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/npcm7xx.h
++++ b/include/hw/arm/npcm7xx.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/nvram/npcm7xx_otp.h"
+ #include "hw/timer/npcm7xx_timer.h"
+ #include "hw/ssi/npcm7xx_fiu.h"
++#include "hw/ssi/npcm_pspi.h"
+ #include "hw/usb/hcd-ehci.h"
+ #include "hw/usb/hcd-ohci.h"
+ #include "target/arm/cpu.h"
+@@ -XXX,XX +XXX,XX @@ struct NPCM7xxState {
+     NPCM7xxFIUState     fiu[2];
+     NPCM7xxEMCState     emc[2];
+     NPCM7xxSDHCIState   mmc;
++    NPCMPSPIState       pspi[2];
+ };
+ #define TYPE_NPCM7XX    "npcm7xx"
+diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/npcm7xx.c
++++ b/hw/arm/npcm7xx.c
+@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
+     NPCM7XX_EMC1RX_IRQ          = 15,
+     NPCM7XX_EMC1TX_IRQ,
+     NPCM7XX_MMC_IRQ             = 26,
++    NPCM7XX_PSPI2_IRQ           = 28,
++    NPCM7XX_PSPI1_IRQ           = 31,
+     NPCM7XX_TIMER0_IRQ          = 32,   /* Timer Module 0 */
+     NPCM7XX_TIMER1_IRQ,
+     NPCM7XX_TIMER2_IRQ,
+@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_emc_addr[] = {
+xf0826000,
+ };
++/* Register base address for each PSPI Module */
++static const hwaddr npcm7xx_pspi_addr[] = {
++    0xf0200000,
++    0xf0201000,
++};
++
+ static const struct {
+     hwaddr regs_addr;
+     uint32_t unconnected_pins;
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
+         object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC);
+     }
++    for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
++        object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI);
++    }
++
+     object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
+ }
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0,
+             npcm7xx_irq(s, NPCM7XX_MMC_IRQ));
++    /* PSPI */
++    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi));
++    for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
++        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]);
++        int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ;
++
++        sysbus_realize(sbd, &error_abort);
++        sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]);
++        sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq));
++    }
++
+     create_unimplemented_device("npcm7xx.shm",          0xc0001000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
+     create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
+-    create_unimplemented_device("npcm7xx.pspi1",        0xf0200000,   4 * KiB);
+-    create_unimplemented_device("npcm7xx.pspi2",        0xf0201000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.ahbpci",       0xf0400000,   1 * MiB);
+     create_unimplemented_device("npcm7xx.mcphy",        0xf05f0000,  64 * KiB);
+     create_unimplemented_device("npcm7xx.gmac1",        0xf0802000,   8 * KiB);
+--
+.34.1

-[PULL 06/10] hw/arm/virt: Fix devicetree warning about the root node
+[PULL 19/30] hw/arm/smmu-common: Support 64-bit addresses
 From: Jean-Philippe Brucker <jean-philippe@linaro.org>
-The devicetree specification requires a 'model' property in the root
+Addresses targeting the second translation table (TTB1) in the SMMU have
-node. Fix the corresponding dt-validate warning:
+all upper bits set. Ensure the IOMMU region covers all 64 bits.
-  /: 'model' is a required property
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
   From schema: dtschema/schemas/root-node.yaml
 Use the same name for model as for compatible. The specification
 recommends that 'compatible' follows the format 'manufacturer,model' and
 'model' follows the format 'manufacturer,model-number'. Since our
 'compatible' doesn't observe this, 'model' doesn't really need to
 either.
 Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Message-id: 20220927100347.176606-2-jean-philippe@linaro.org
+Message-id: 20230214171921.1917916-2-jean-philippe@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 1 +
+ include/hw/arm/smmu-common.h | 2 --
-file changed, 1 insertion(+)
+ hw/arm/smmu-common.c         | 2 +-
 files changed, 1 insertion(+), 3 deletions(-)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/include/hw/arm/smmu-common.h
-+++ b/hw/arm/virt.c
++++ b/include/hw/arm/smmu-common.h
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms)
+@@ -XXX,XX +XXX,XX @@
-     qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
+ #define SMMU_PCI_DEVFN_MAX    256
-     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
+ #define SMMU_PCI_DEVFN(sid)   (sid & 0xFF)
-     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
-+    qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
+-#define SMMU_MAX_VA_BITS      48
+-
-     /* /chosen must exist for load_dtb to fill in necessary properties later */
+ /*
-     qemu_fdt_add_subnode(fdt, "/chosen");
+  * Page table walk error types
   */
 diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/smmu-common.c
 +++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn)
          memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu),
                                   s->mrtypename,
 -                                 OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS);
 +                                 OBJECT(s), name, UINT64_MAX);
          address_space_init(&sdev->as,
                             MEMORY_REGION(&sdev->iommu), name);
          trace_smmu_add_mr(name);
 --
-.25.1
+.34.1

-[PULL 09/10] hw/arm/virt: Fix devicetree warning about the SMMU node
+[PULL 20/30] hw/arm/smmu-common: Fix TTB1 handling
 From: Jean-Philippe Brucker <jean-philippe@linaro.org>
-The SMMUv3 node isn't expected to have clock properties
+Addresses targeting the second translation table (TTB1) in the SMMU have
-(unlike the SMMUv2). Fix the corresponding dt-validate warning:
+all upper bits set (except for the top byte when TBI is enabled). Fix
 the TTB1 check.
-  smmuv3@9050000: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
+Reported-by: Ola Hugosson <ola.hugosson@arm.com>
-  From schema: linux/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230214171921.1917916-3-jean-philippe@linaro.org
 [PMM: tweaked commit message as suggested by Eric]
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 20220927100347.176606-7-jean-philippe@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 2 --
+ hw/arm/smmu-common.c | 2 +-
-file changed, 2 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/hw/arm/smmu-common.c
-+++ b/hw/arm/virt.c
++++ b/hw/arm/smmu-common.c
-@@ -XXX,XX +XXX,XX @@ static void create_smmu(const VirtMachineState *vms,
+@@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
-     qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
+         /* there is a ttbr0 region and we are in it (high bits all zero) */
-                      sizeof(irq_names));
+         return &cfg->tt[0];
+     } else if (cfg->tt[1].tsz &&
--    qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);
+-           !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) {
--    qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");
++        sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) {
-     qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
+         /* there is a ttbr1 region and we are in it (high bits all one) */
+         return &cfg->tt[1];
-     qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
+     } else if (!cfg->tt[0].tsz) {
 --
-.25.1
+.34.1

-New patch
+[PULL 21/30] target/arm: rename handle_semihosting to tcg_handle_semihosting
+From: Claudio Fontana <cfontana@suse.de>
+make it clearer from the name that this is a tcg-only function.
+Signed-off-by: Claudio Fontana <cfontana@suse.de>
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/helper.c | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
+  * trapped to the hypervisor in KVM.
+  */
+ #ifdef CONFIG_TCG
+-static void handle_semihosting(CPUState *cs)
++static void tcg_handle_semihosting(CPUState *cs)
+ {
+     ARMCPU *cpu = ARM_CPU(cs);
+     CPUARMState *env = &cpu->env;
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
+      */
+ #ifdef CONFIG_TCG
+     if (cs->exception_index == EXCP_SEMIHOST) {
+-        handle_semihosting(cs);
++        tcg_handle_semihosting(cs);
+         return;
+     }
+ #endif
+--
+.34.1

-[PULL 10/10] target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP
+[PULL 22/30] target/arm: wrap psci call with tcg_enabled
-From: Jerome Forissier <jerome.forissier@linaro.org>
+From: Claudio Fontana <cfontana@suse.de>
-SP_EL1 must be kept when EL3 is present but EL2 is not. Therefore mark
+for "all" builds (tcg + kvm), we want to avoid doing
-it with ARM_CP_EL3_NO_EL2_KEEP.
+the psci check if tcg is built-in, but not enabled.
-Cc: qemu-stable@nongnu.org
+Signed-off-by: Claudio Fontana <cfontana@suse.de>
 Fixes: 696ba3771894 ("target/arm: Handle cpreg registration for missing EL")
 Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220927120058.670901-1-jerome.forissier@linaro.org
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
 Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 2 +-
+ target/arm/helper.c | 3 ++-
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 2 insertions(+), 1 deletion(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
+@@ -XXX,XX +XXX,XX @@
-       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
+ #include "hw/irq.h"
-     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
+ #include "sysemu/cpu-timers.h"
-       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
+ #include "sysemu/kvm.h"
--      .access = PL2_RW, .type = ARM_CP_ALIAS,
++#include "sysemu/tcg.h"
-+      .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP,
+ #include "qapi/qapi-commands-machine-target.h"
-       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
+ #include "qapi/error.h"
-     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
+ #include "qemu/guest-random.h"
-       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
                        env->exception.syndrome);
      }
 -    if (arm_is_psci_call(cpu, cs->exception_index)) {
 +    if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) {
          arm_handle_psci_call(cpu);
          qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
          return;
 --
-.25.1
+.34.1

-[PULL 01/10] target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO
+[PULL 23/30] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()
-In commit 01765386a888 we made some system register write functions
+From: Claudio Fontana <cfontana@suse.de>
 call pmu_op_start()/pmu_op_finish(). This means that they now touch
 timers, so for icount to work these registers must have the ARM_CP_IO
 flag set.
-This fixes a bug where when icount is enabled a guest that touches
+Signed-off-by: Claudio Fontana <cfontana@suse.de>
-MDCR_EL3, MDCR_EL2, PMCNTENSET_EL0 or PMCNTENCLR_EL0 would cause
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-QEMU to print an error message and exit, for example:
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 [    2.495971] TCP: Hash tables configured (established 1024 bind 1024)
 [    2.496213] UDP hash table entries: 256 (order: 1, 8192 bytes)
 [    2.496386] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
 [    2.496917] NET: Registered protocol family 1
 qemu-system-aarch64: Bad icount read
 Reported-by: Thomas Huth <thuth@redhat.com>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220923123412.1214041-2-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 12 ++++++------
+ target/arm/helper.c | 12 +++++++-----
-file changed, 6 insertions(+), 6 deletions(-)
+file changed, 7 insertions(+), 5 deletions(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
-      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
+     unsigned int cur_el = arm_current_el(env);
-      */
+     int rt;
-     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
--      .access = PL0_RW, .type = ARM_CP_ALIAS,
+-    /*
-+      .access = PL0_RW, .type = ARM_CP_ALIAS | ARM_CP_IO,
+-     * Note that new_el can never be 0.  If cur_el is 0, then
-       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
+-     * el0_a64 is is_a64(), else el0_a64 is ignored.
-       .writefn = pmcntenset_write,
+-     */
-       .accessfn = pmreg_access,
+-    aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
-       .raw_writefn = raw_write },
++    if (tcg_enabled()) {
--    { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
++        /*
-+    { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
++         * Note that new_el can never be 0.  If cur_el is 0, then
-       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
++         * el0_a64 is is_a64(), else el0_a64 is ignored.
-       .access = PL0_RW, .accessfn = pmreg_access,
++         */
-       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
++        aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
++    }
-       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
-       .accessfn = pmreg_access,
+     if (cur_el < new_el) {
-       .writefn = pmcntenclr_write,
+         /*
 -      .type = ARM_CP_ALIAS },
 +      .type = ARM_CP_ALIAS | ARM_CP_IO },
      { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
        .access = PL0_RW, .accessfn = pmreg_access,
 -      .type = ARM_CP_ALIAS,
 +      .type = ARM_CP_ALIAS | ARM_CP_IO,
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
        .writefn = pmcntenclr_write },
      { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
        .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
        .resetvalue = 0,
        .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
 -    { .name = "SDCR", .type = ARM_CP_ALIAS,
 +    { .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
        .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
        .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
        .writefn = sdcr_write,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
           * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
           */
          ARMCPRegInfo mdcr_el2 = {
 -            .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
 +            .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, .type = ARM_CP_IO,
              .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
              .writefn = mdcr_el2_write,
              .access = PL2_RW, .resetvalue = pmu_num_counters(env),
 --
-.25.1
+.34.1

-New patch
+[PULL 24/30] target/arm: Move PC alignment check
+From: Fabiano Rosas <farosas@suse.de>
+Move this earlier to make the next patch diff cleaner. While here
+update the comment slightly to not give the impression that the
+misalignment affects only TCG.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/machine.c | 18 +++++++++---------
+file changed, 9 insertions(+), 9 deletions(-)
+diff --git a/target/arm/machine.c b/target/arm/machine.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/machine.c
++++ b/target/arm/machine.c
+@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
+         }
+     }
++    /*
++     * Misaligned thumb pc is architecturally impossible. Fail the
++     * incoming migration. For TCG it would trigger the assert in
++     * thumb_tr_translate_insn().
++     */
++    if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
++        return -1;
++    }
++
+     hw_breakpoint_update_all(cpu);
+     hw_watchpoint_update_all(cpu);
+@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
+         }
+     }
+-    /*
+-     * Misaligned thumb pc is architecturally impossible.
+-     * We have an assert in thumb_tr_translate_insn to verify this.
+-     * Fail an incoming migrate to avoid this assert.
+-     */
+-    if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
+-        return -1;
+-    }
+-
+     if (!kvm_enabled()) {
+         pmu_op_finish(&cpu->env);
+     }
+--
+.34.1

-New patch
+[PULL 25/30] target/arm: Move cpregs code out of cpu.h
+From: Fabiano Rosas <farosas@suse.de>
 Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have
 a cpregs.h header which is more suitable for this code.
 Code moved verbatim.
 Signed-off-by: Fabiano Rosas <farosas@suse.de>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpregs.h | 98 +++++++++++++++++++++++++++++++++++++++++++++
  target/arm/cpu.h    | 91 -----------------------------------------
 files changed, 98 insertions(+), 91 deletions(-)
 diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpregs.h
 +++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
      ARM_CP_SME                   = 1 << 19,
  };
 +/*
 + * Interface for defining coprocessor registers.
 + * Registers are defined in tables of arm_cp_reginfo structs
 + * which are passed to define_arm_cp_regs().
 + */
 +
 +/*
 + * When looking up a coprocessor register we look for it
 + * via an integer which encodes all of:
 + *  coprocessor number
 + *  Crn, Crm, opc1, opc2 fields
 + *  32 or 64 bit register (ie is it accessed via MRC/MCR
 + *    or via MRRC/MCRR?)
 + *  non-secure/secure bank (AArch32 only)
 + * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 + * (In this case crn and opc2 should be zero.)
 + * For AArch64, there is no 32/64 bit size distinction;
 + * instead all registers have a 2 bit op0, 3 bit op1 and op2,
 + * and 4 bit CRn and CRm. The encoding patterns are chosen
 + * to be easy to convert to and from the KVM encodings, and also
 + * so that the hashtable can contain both AArch32 and AArch64
 + * registers (to allow for interprocessing where we might run
 + * 32 bit code on a 64 bit core).
 + */
 +/*
 + * This bit is private to our hashtable cpreg; in KVM register
 + * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
 + * in the upper bits of the 64 bit ID.
 + */
 +#define CP_REG_AA64_SHIFT 28
 +#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
 +
 +/*
 + * To enable banking of coprocessor registers depending on ns-bit we
 + * add a bit to distinguish between secure and non-secure cpregs in the
 + * hashtable.
 + */
 +#define CP_REG_NS_SHIFT 29
 +#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
 +
 +#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
 +    ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
 +     ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
 +
 +#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
 +    (CP_REG_AA64_MASK |                                 \
 +     ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
 +     ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
 +     ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
 +     ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
 +     ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
 +     ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
 +
 +/*
 + * Convert a full 64 bit KVM register ID to the truncated 32 bit
 + * version used as a key for the coprocessor register hashtable
 + */
 +static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
 +{
 +    uint32_t cpregid = kvmid;
 +    if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
 +        cpregid |= CP_REG_AA64_MASK;
 +    } else {
 +        if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
 +            cpregid |= (1 << 15);
 +        }
 +
 +        /*
 +         * KVM is always non-secure so add the NS flag on AArch32 register
 +         * entries.
 +         */
 +         cpregid |= 1 << CP_REG_NS_SHIFT;
 +    }
 +    return cpregid;
 +}
 +
 +/*
 + * Convert a truncated 32 bit hashtable key into the full
 + * 64 bit KVM register ID.
 + */
 +static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
 +{
 +    uint64_t kvmid;
 +
 +    if (cpregid & CP_REG_AA64_MASK) {
 +        kvmid = cpregid & ~CP_REG_AA64_MASK;
 +        kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
 +    } else {
 +        kvmid = cpregid & ~(1 << 15);
 +        if (cpregid & (1 << 15)) {
 +            kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
 +        } else {
 +            kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
 +        }
 +    }
 +    return kvmid;
 +}
 +
  /*
   * Valid values for ARMCPRegInfo state field, indicating which of
   * the AArch32 and AArch64 execution states this register is visible in.
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
  uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                   uint32_t cur_el, bool secure);
 -/* Interface for defining coprocessor registers.
 - * Registers are defined in tables of arm_cp_reginfo structs
 - * which are passed to define_arm_cp_regs().
 - */
 -
 -/* When looking up a coprocessor register we look for it
 - * via an integer which encodes all of:
 - *  coprocessor number
 - *  Crn, Crm, opc1, opc2 fields
 - *  32 or 64 bit register (ie is it accessed via MRC/MCR
 - *    or via MRRC/MCRR?)
 - *  non-secure/secure bank (AArch32 only)
 - * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 - * (In this case crn and opc2 should be zero.)
 - * For AArch64, there is no 32/64 bit size distinction;
 - * instead all registers have a 2 bit op0, 3 bit op1 and op2,
 - * and 4 bit CRn and CRm. The encoding patterns are chosen
 - * to be easy to convert to and from the KVM encodings, and also
 - * so that the hashtable can contain both AArch32 and AArch64
 - * registers (to allow for interprocessing where we might run
 - * 32 bit code on a 64 bit core).
 - */
 -/* This bit is private to our hashtable cpreg; in KVM register
 - * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
 - * in the upper bits of the 64 bit ID.
 - */
 -#define CP_REG_AA64_SHIFT 28
 -#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
 -
 -/* To enable banking of coprocessor registers depending on ns-bit we
 - * add a bit to distinguish between secure and non-secure cpregs in the
 - * hashtable.
 - */
 -#define CP_REG_NS_SHIFT 29
 -#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
 -
 -#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
 -    ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
 -     ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
 -
 -#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
 -    (CP_REG_AA64_MASK |                                 \
 -     ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
 -     ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
 -     ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
 -     ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
 -     ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
 -     ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
 -
 -/* Convert a full 64 bit KVM register ID to the truncated 32 bit
 - * version used as a key for the coprocessor register hashtable
 - */
 -static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
 -{
 -    uint32_t cpregid = kvmid;
 -    if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
 -        cpregid |= CP_REG_AA64_MASK;
 -    } else {
 -        if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
 -            cpregid |= (1 << 15);
 -        }
 -
 -        /* KVM is always non-secure so add the NS flag on AArch32 register
 -         * entries.
 -         */
 -         cpregid |= 1 << CP_REG_NS_SHIFT;
 -    }
 -    return cpregid;
 -}
 -
 -/* Convert a truncated 32 bit hashtable key into the full
 - * 64 bit KVM register ID.
 - */
 -static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
 -{
 -    uint64_t kvmid;
 -
 -    if (cpregid & CP_REG_AA64_MASK) {
 -        kvmid = cpregid & ~CP_REG_AA64_MASK;
 -        kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
 -    } else {
 -        kvmid = cpregid & ~(1 << 15);
 -        if (cpregid & (1 << 15)) {
 -            kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
 -        } else {
 -            kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
 -        }
 -    }
 -    return kvmid;
 -}
 -
  /* Return the highest implemented Exception Level */
  static inline int arm_highest_el(CPUARMState *env)
  {
 --
 .34.1

-New patch
+[PULL 26/30] tests/avocado: Skip tests that require a missing accelerator
+From: Fabiano Rosas <farosas@suse.de>
+If a test was tagged with the "accel" tag and the specified
+accelerator it not present in the qemu binary, cancel the test.
+We can now write tests without explicit calls to require_accelerator,
+just the tag is enough.
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ tests/avocado/avocado_qemu/__init__.py | 4 ++++
+file changed, 4 insertions(+)
+diff --git a/tests/avocado/avocado_qemu/__init__.py b/tests/avocado/avocado_qemu/__init__.py
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/avocado/avocado_qemu/__init__.py
++++ b/tests/avocado/avocado_qemu/__init__.py
+@@ -XXX,XX +XXX,XX @@ def setUp(self):
+         super().setUp('qemu-system-')
++        accel_required = self._get_unique_tag_val('accel')
++        if accel_required:
++            self.require_accelerator(accel_required)
++
+         self.machine = self.params.get('machine',
+                                        default=self._get_unique_tag_val('machine'))
+--
+.34.1

-New patch
+[PULL 27/30] tests/avocado: Tag TCG tests with accel:tcg
+From: Fabiano Rosas <farosas@suse.de>
+This allows the test to be skipped when TCG is not present in the QEMU
+binary.
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ tests/avocado/boot_linux_console.py | 1 +
+ tests/avocado/reverse_debugging.py  | 8 ++++++++
+files changed, 9 insertions(+)
+diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/avocado/boot_linux_console.py
++++ b/tests/avocado/boot_linux_console.py
+@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_uboot_netbsd9(self):
+     def test_aarch64_raspi3_atf(self):
+         """
++        :avocado: tags=accel:tcg
+         :avocado: tags=arch:aarch64
+         :avocado: tags=machine:raspi3b
+         :avocado: tags=cpu:cortex-a53
+diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/avocado/reverse_debugging.py
++++ b/tests/avocado/reverse_debugging.py
+@@ -XXX,XX +XXX,XX @@ def reverse_debugging(self, shift=7, args=None):
+         vm.shutdown()
+ class ReverseDebugging_X86_64(ReverseDebugging):
++    """
++    :avocado: tags=accel:tcg
++    """
++
+     REG_PC = 0x10
+     REG_CS = 0x12
+     def get_pc(self, g):
+@@ -XXX,XX +XXX,XX @@ def test_x86_64_pc(self):
+         self.reverse_debugging()
+ class ReverseDebugging_AArch64(ReverseDebugging):
++    """
++    :avocado: tags=accel:tcg
++    """
++
+     REG_PC = 32
+     # unidentified gitlab timeout problem
+--
+.34.1

-[PULL 07/10] hw/arm/virt: Fix devicetree warning about the GIC node
+[PULL 28/30] target/arm: Use "max" as default cpu for the virt machine with KVM
-From: Jean-Philippe Brucker <jean-philippe@linaro.org>
+From: Fabiano Rosas <farosas@suse.de>
-The GICv3 bindings requires a #msi-cells property for the ITS node. Fix
+Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a
-the corresponding dt-validate warning:
+KVM-only build the 'max' cpu.
-  interrupt-controller@8000000: msi-controller@8080000: '#msi-cells' is a required property
+Note that we cannot use 'host' here because the qtests can run without
-  From schema: linux/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
+any other accelerator (than qtest) and 'host' depends on KVM being
 enabled.
-Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Acked-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
 Message-id: 20220927100347.176606-3-jean-philippe@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 1 +
+ hw/arm/virt.c | 4 ++++
-file changed, 1 insertion(+)
+file changed, 4 insertions(+)
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ static void fdt_add_its_gic_node(VirtMachineState *vms)
+@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
-     qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
+     mc->minimum_page_bits = 12;
-                             "arm,gic-v3-its");
+     mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
-     qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
+     mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
-+    qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
++#ifdef CONFIG_TCG
-     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
+     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
-, vms->memmap[VIRT_GIC_ITS].base,
++#else
-, vms->memmap[VIRT_GIC_ITS].size);
++    mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
 +#endif
      mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
      mc->kvm_type = virt_kvm_type;
      assert(!mc->get_hotplug_handler);
 --
-.25.1
+.34.1

-New patch
+[PULL 29/30] tests/qtest: arm-cpu-features: Match tests to required accelerators
+From: Fabiano Rosas <farosas@suse.de>
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Acked-by: Thomas Huth <thuth@redhat.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ tests/qtest/arm-cpu-features.c | 28 ++++++++++++++++++----------
+file changed, 18 insertions(+), 10 deletions(-)
+diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/qtest/arm-cpu-features.c
++++ b/tests/qtest/arm-cpu-features.c
+@@ -XXX,XX +XXX,XX @@
+ #define SVE_MAX_VQ 16
+ #define MACHINE     "-machine virt,gic-version=max -accel tcg "
+-#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg "
++#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm "
+ #define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
+                     "  'arguments': { 'type': 'full', "
+ #define QUERY_TAIL  "}}"
+@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
+ {
+     g_test_init(&argc, &argv, NULL);
+-    qtest_add_data_func("/arm/query-cpu-model-expansion",
+-                        NULL, test_query_cpu_model_expansion);
++    if (qtest_has_accel("tcg")) {
++        qtest_add_data_func("/arm/query-cpu-model-expansion",
++                            NULL, test_query_cpu_model_expansion);
++    }
++
++    if (!g_str_equal(qtest_get_arch(), "aarch64")) {
++        goto out;
++    }
+     /*
+      * For now we only run KVM specific tests with AArch64 QEMU in
+      * order avoid attempting to run an AArch32 QEMU with KVM on
+      * AArch64 hosts. That won't work and isn't easy to detect.
+      */
+-    if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) {
++    if (qtest_has_accel("kvm")) {
+         /*
+          * This tests target the 'host' CPU type, so register it only if
+          * KVM is available.
+          */
+         qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
+                             NULL, test_query_cpu_model_expansion_kvm);
+-    }
+-    if (g_str_equal(qtest_get_arch(), "aarch64")) {
+-        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
+-                            NULL, sve_tests_sve_max_vq_8);
+-        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
+-                            NULL, sve_tests_sve_off);
+         qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
+                             NULL, sve_tests_sve_off_kvm);
+     }
++    if (qtest_has_accel("tcg")) {
++        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
++                            NULL, sve_tests_sve_max_vq_8);
++        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
++                            NULL, sve_tests_sve_off);
++    }
++
++out:
+     return g_test_run();
+ }
+--
+.34.1

-New patch
+[PULL 30/30] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
+From: Fabiano Rosas <farosas@suse.de>
+These tests set -accel tcg, so restrict them to when TCG is present.
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Acked-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ tests/qtest/meson.build | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/qtest/meson.build
++++ b/tests/qtest/meson.build
+@@ -XXX,XX +XXX,XX @@ qtests_arm = \
+ # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional
+ qtests_aarch64 = \
+   (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) +                            \
+-  (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) +        \
+-  (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) +  \
++  (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ?            \
++    ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) +                                         \
+   (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \
+   (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) +  \
+   ['arm-cpu-features',
+--
+.34.1

Hi; not so many patches in this one, but notably it includes the
fix for various Avocado CI tests failing (incorrectly reported by
Avocado as a timeout, but really a QEMU exit-with-error).

thanks
-- PMM

The following changes since commit c8de6ec63d766ca1998c5af468483ce912fdc0c2:

Merge tag 'pull-request-2022-09-28' of https://gitlab.com/thuth/qemu into staging (2022-09-28 17:04:11 -0400)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220930

for you to fetch changes up to beeec926d24aac28f95cc7694ef3837d7a4cd3bb:

target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP (2022-09-29 18:01:09 +0100)

----------------------------------------------------------------
target-arm queue:
 * Fix breakage of icount mode when guest touches MDCR_EL3, MDCR_EL2,
   PMCNTENSET_EL0 or PMCNTENCLR_EL0
 * Make writes to MDCR_EL3 use PMU start/finish calls
 * Let AArch32 write to SDCR.SCCD
 * Rearrange cpu64.c so all the CPU initfns are together
 * hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
 * hw/arm/virt: fix some minor issues with generated device tree
 * Fix regression where EL3 could not write to SP_EL1 if there is no EL2

----------------------------------------------------------------
Francisco Iglesias (1):
      hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers

Jean-Philippe Brucker (4):
      hw/arm/virt: Fix devicetree warning about the root node
      hw/arm/virt: Fix devicetree warning about the GIC node
      hw/arm/virt: Use "msi-map" devicetree property for PCI
      hw/arm/virt: Fix devicetree warning about the SMMU node

Jerome Forissier (1):
      target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP

Peter Maydell (4):
      target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO
      target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
      target/arm: Update SDCR_VALID_MASK to include SCCD
      target/arm: Rearrange cpu64.c so all the CPU initfns are together

In commit 01765386a888 we made some system register write functions
call pmu_op_start()/pmu_op_finish(). This means that they now touch
timers, so for icount to work these registers must have the ARM_CP_IO
flag set.

This fixes a bug where when icount is enabled a guest that touches
MDCR_EL3, MDCR_EL2, PMCNTENSET_EL0 or PMCNTENCLR_EL0 would cause
QEMU to print an error message and exit, for example:

[    2.495971] TCP: Hash tables configured (established 1024 bind 1024)
[    2.496213] UDP hash table entries: 256 (order: 1, 8192 bytes)
[    2.496386] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[    2.496917] NET: Registered protocol family 1
qemu-system-aarch64: Bad icount read

Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220923123412.1214041-2-peter.maydell@linaro.org
---
 target/arm/helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
      */
     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
-      .access = PL0_RW, .type = ARM_CP_ALIAS,
+      .access = PL0_RW, .type = ARM_CP_ALIAS | ARM_CP_IO,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
       .writefn = pmcntenset_write,
       .accessfn = pmreg_access,
       .raw_writefn = raw_write },
-    { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
+    { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
       .access = PL0_RW, .accessfn = pmreg_access,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
       .accessfn = pmreg_access,
       .writefn = pmcntenclr_write,
-      .type = ARM_CP_ALIAS },
+      .type = ARM_CP_ALIAS | ARM_CP_IO },
     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
       .access = PL0_RW, .accessfn = pmreg_access,
-      .type = ARM_CP_ALIAS,
+      .type = ARM_CP_ALIAS | ARM_CP_IO,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
       .writefn = pmcntenclr_write },
     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
       .resetvalue = 0,
       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
-    { .name = "SDCR", .type = ARM_CP_ALIAS,
+    { .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
       .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
       .writefn = sdcr_write,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
          * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
          */
         ARMCPRegInfo mdcr_el2 = {
-            .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
+            .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, .type = ARM_CP_IO,
             .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
             .writefn = mdcr_el2_write,
             .access = PL2_RW, .resetvalue = pmu_num_counters(env),
-- 
2.25.1

In commit 01765386a88868 we fixed a bug where we weren't correctly
bracketing changes to some registers with pmu_op_start() and
pmu_op_finish() calls for changes which affect whether the PMU
counters might be enabled.  However, we missed the case of writes to
the AArch64 MDCR_EL3 register, because (unlike its AArch32
counterpart) they are currently done directly to the CPU state struct
without going through the sdcr_write() function.

Give MDCR_EL3 a writefn which handles the PMU start/finish calls.
The SDCR writefn then simplfies to "call the MDCR_EL3 writefn after
masking off the bits which don't exist in the AArch32 register".

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220923123412.1214041-3-peter.maydell@linaro.org
---
 target/arm/helper.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     }
 }
 
-static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                       uint64_t value)
+static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                           uint64_t value)
 {
     /*
      * Some MDCR_EL3 bits affect whether PMU counters are running:
@@ -XXX,XX +XXX,XX @@ static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     if (pmu_op) {
         pmu_op_start(env);
     }
-    env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
+    env->cp15.mdcr_el3 = value;
     if (pmu_op) {
         pmu_op_finish(env);
     }
 }
 
+static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                       uint64_t value)
+{
+    /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
+    mdcr_el3_write(env, ri, value & SDCR_VALID_MASK);
+}
+
 static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
                            uint64_t value)
 {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .access = PL2_RW,
       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
     { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
+      .type = ARM_CP_IO,
       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
       .resetvalue = 0,
-      .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
+      .access = PL3_RW,
+      .writefn = mdcr_el3_write,
+      .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
     { .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
       .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
-- 
2.25.1

Our SDCR_VALID_MASK doesn't include all of the bits which are defined
by the current architecture.  In particular in commit 0b42f4fab9d3 we
forgot to add SCCD, which meant that an AArch32 guest couldn't
actually use the SCCD bit to disable counting in Secure state.

Add all the currently defined bits; we don't implement all of them,
but this makes them be reads-as-written, which is architecturally
valid and matches how we currently handle most of the others in the
mask.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220923123412.1214041-4-peter.maydell@linaro.org
---
 target/arm/cpu.h | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TTA, 20, 1)
 FIELD(CPTR_EL3, TAM, 30, 1)
 FIELD(CPTR_EL3, TCPAC, 31, 1)
 
+#define MDCR_MTPME    (1U << 28)
+#define MDCR_TDCC     (1U << 27)
 #define MDCR_HLP      (1U << 26)  /* MDCR_EL2 */
 #define MDCR_SCCD     (1U << 23)  /* MDCR_EL3 */
 #define MDCR_HCCD     (1U << 23)  /* MDCR_EL2 */
 #define MDCR_EPMAD    (1U << 21)
 #define MDCR_EDAD     (1U << 20)
+#define MDCR_TTRF     (1U << 19)
+#define MDCR_STE      (1U << 18)  /* MDCR_EL3 */
 #define MDCR_SPME     (1U << 17)  /* MDCR_EL3 */
 #define MDCR_HPMD     (1U << 17)  /* MDCR_EL2 */
 #define MDCR_SDD      (1U << 16)
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
 #define MDCR_HPMN     (0x1fU)
 
 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
-#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
+#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
+                         MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
+                         MDCR_STE | MDCR_SPME | MDCR_SPD)
 
 #define CPSR_M (0x1fU)
 #define CPSR_T (1U << 5)
-- 
2.25.1

cpu64.c has ended up in a slightly odd order -- it starts with the
initfns for most of the models-real-hardware CPUs; after that comes a
bunch of support code for SVE, SME, pauth and LPA2 properties.  Then
come the initfns for the 'host' and 'max' CPU types, and then after
that one more models-real-hardware CPU initfn, for a64fx.  (This
ordering is partly historical and partly required because a64fx needs
the SVE properties.)

Reorder the file into:
 * CPU property support functions
 * initfns for real hardware CPUs
 * initfns for host and max
 * class boilerplate

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu64.c | 712 ++++++++++++++++++++++-----------------------
 1 file changed, 356 insertions(+), 356 deletions(-)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a35_initfn(Object *obj)
     define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
-static void aarch64_a57_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cpu->dtb_compatible = "arm,cortex-a57";
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
-    cpu->midr = 0x411fd070;
-    cpu->revidr = 0x00000000;
-    cpu->reset_fpsid = 0x41034070;
-    cpu->isar.mvfr0 = 0x10110222;
-    cpu->isar.mvfr1 = 0x12111111;
-    cpu->isar.mvfr2 = 0x00000043;
-    cpu->ctr = 0x8444c004;
-    cpu->reset_sctlr = 0x00c50838;
-    cpu->isar.id_pfr0 = 0x00000131;
-    cpu->isar.id_pfr1 = 0x00011011;
-    cpu->isar.id_dfr0 = 0x03010066;
-    cpu->id_afr0 = 0x00000000;
-    cpu->isar.id_mmfr0 = 0x10101105;
-    cpu->isar.id_mmfr1 = 0x40000000;
-    cpu->isar.id_mmfr2 = 0x01260000;
-    cpu->isar.id_mmfr3 = 0x02102211;
-    cpu->isar.id_isar0 = 0x02101110;
-    cpu->isar.id_isar1 = 0x13112111;
-    cpu->isar.id_isar2 = 0x21232042;
-    cpu->isar.id_isar3 = 0x01112131;
-    cpu->isar.id_isar4 = 0x00011142;
-    cpu->isar.id_isar5 = 0x00011121;
-    cpu->isar.id_isar6 = 0;
-    cpu->isar.id_aa64pfr0 = 0x00002222;
-    cpu->isar.id_aa64dfr0 = 0x10305106;
-    cpu->isar.id_aa64isar0 = 0x00011120;
-    cpu->isar.id_aa64mmfr0 = 0x00001124;
-    cpu->isar.dbgdidr = 0x3516d000;
-    cpu->isar.dbgdevid = 0x01110f13;
-    cpu->isar.dbgdevid1 = 0x2;
-    cpu->isar.reset_pmcr_el0 = 0x41013000;
-    cpu->clidr = 0x0a200023;
-    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
-    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
-    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
-    cpu->dcz_blocksize = 4; /* 64 bytes */
-    cpu->gic_num_lrs = 4;
-    cpu->gic_vpribits = 5;
-    cpu->gic_vprebits = 5;
-    cpu->gic_pribits = 5;
-    define_cortex_a72_a57_a53_cp_reginfo(cpu);
-}
-
-static void aarch64_a53_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cpu->dtb_compatible = "arm,cortex-a53";
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
-    cpu->midr = 0x410fd034;
-    cpu->revidr = 0x00000000;
-    cpu->reset_fpsid = 0x41034070;
-    cpu->isar.mvfr0 = 0x10110222;
-    cpu->isar.mvfr1 = 0x12111111;
-    cpu->isar.mvfr2 = 0x00000043;
-    cpu->ctr = 0x84448004; /* L1Ip = VIPT */
-    cpu->reset_sctlr = 0x00c50838;
-    cpu->isar.id_pfr0 = 0x00000131;
-    cpu->isar.id_pfr1 = 0x00011011;
-    cpu->isar.id_dfr0 = 0x03010066;
-    cpu->id_afr0 = 0x00000000;
-    cpu->isar.id_mmfr0 = 0x10101105;
-    cpu->isar.id_mmfr1 = 0x40000000;
-    cpu->isar.id_mmfr2 = 0x01260000;
-    cpu->isar.id_mmfr3 = 0x02102211;
-    cpu->isar.id_isar0 = 0x02101110;
-    cpu->isar.id_isar1 = 0x13112111;
-    cpu->isar.id_isar2 = 0x21232042;
-    cpu->isar.id_isar3 = 0x01112131;
-    cpu->isar.id_isar4 = 0x00011142;
-    cpu->isar.id_isar5 = 0x00011121;
-    cpu->isar.id_isar6 = 0;
-    cpu->isar.id_aa64pfr0 = 0x00002222;
-    cpu->isar.id_aa64dfr0 = 0x10305106;
-    cpu->isar.id_aa64isar0 = 0x00011120;
-    cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
-    cpu->isar.dbgdidr = 0x3516d000;
-    cpu->isar.dbgdevid = 0x00110f13;
-    cpu->isar.dbgdevid1 = 0x1;
-    cpu->isar.reset_pmcr_el0 = 0x41033000;
-    cpu->clidr = 0x0a200023;
-    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
-    cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
-    cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
-    cpu->dcz_blocksize = 4; /* 64 bytes */
-    cpu->gic_num_lrs = 4;
-    cpu->gic_vpribits = 5;
-    cpu->gic_vprebits = 5;
-    cpu->gic_pribits = 5;
-    define_cortex_a72_a57_a53_cp_reginfo(cpu);
-}
-
-static void aarch64_a72_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cpu->dtb_compatible = "arm,cortex-a72";
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-    cpu->midr = 0x410fd083;
-    cpu->revidr = 0x00000000;
-    cpu->reset_fpsid = 0x41034080;
-    cpu->isar.mvfr0 = 0x10110222;
-    cpu->isar.mvfr1 = 0x12111111;
-    cpu->isar.mvfr2 = 0x00000043;
-    cpu->ctr = 0x8444c004;
-    cpu->reset_sctlr = 0x00c50838;
-    cpu->isar.id_pfr0 = 0x00000131;
-    cpu->isar.id_pfr1 = 0x00011011;
-    cpu->isar.id_dfr0 = 0x03010066;
-    cpu->id_afr0 = 0x00000000;
-    cpu->isar.id_mmfr0 = 0x10201105;
-    cpu->isar.id_mmfr1 = 0x40000000;
-    cpu->isar.id_mmfr2 = 0x01260000;
-    cpu->isar.id_mmfr3 = 0x02102211;
-    cpu->isar.id_isar0 = 0x02101110;
-    cpu->isar.id_isar1 = 0x13112111;
-    cpu->isar.id_isar2 = 0x21232042;
-    cpu->isar.id_isar3 = 0x01112131;
-    cpu->isar.id_isar4 = 0x00011142;
-    cpu->isar.id_isar5 = 0x00011121;
-    cpu->isar.id_aa64pfr0 = 0x00002222;
-    cpu->isar.id_aa64dfr0 = 0x10305106;
-    cpu->isar.id_aa64isar0 = 0x00011120;
-    cpu->isar.id_aa64mmfr0 = 0x00001124;
-    cpu->isar.dbgdidr = 0x3516d000;
-    cpu->isar.dbgdevid = 0x01110f13;
-    cpu->isar.dbgdevid1 = 0x2;
-    cpu->isar.reset_pmcr_el0 = 0x41023000;
-    cpu->clidr = 0x0a200023;
-    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
-    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
-    cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
-    cpu->dcz_blocksize = 4; /* 64 bytes */
-    cpu->gic_num_lrs = 4;
-    cpu->gic_vpribits = 5;
-    cpu->gic_vprebits = 5;
-    cpu->gic_pribits = 5;
-    define_cortex_a72_a57_a53_cp_reginfo(cpu);
-}
-
-static void aarch64_a76_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cpu->dtb_compatible = "arm,cortex-a76";
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-
-    /* Ordered by B2.4 AArch64 registers by functional group */
-    cpu->clidr = 0x82000023;
-    cpu->ctr = 0x8444C004;
-    cpu->dcz_blocksize = 4;
-    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
-    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
-    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
-    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
-    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
-    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
-    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
-    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
-    cpu->id_afr0       = 0x00000000;
-    cpu->isar.id_dfr0  = 0x04010088;
-    cpu->isar.id_isar0 = 0x02101110;
-    cpu->isar.id_isar1 = 0x13112111;
-    cpu->isar.id_isar2 = 0x21232042;
-    cpu->isar.id_isar3 = 0x01112131;
-    cpu->isar.id_isar4 = 0x00010142;
-    cpu->isar.id_isar5 = 0x01011121;
-    cpu->isar.id_isar6 = 0x00000010;
-    cpu->isar.id_mmfr0 = 0x10201105;
-    cpu->isar.id_mmfr1 = 0x40000000;
-    cpu->isar.id_mmfr2 = 0x01260000;
-    cpu->isar.id_mmfr3 = 0x02122211;
-    cpu->isar.id_mmfr4 = 0x00021110;
-    cpu->isar.id_pfr0  = 0x10010131;
-    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
-    cpu->isar.id_pfr2  = 0x00000011;
-    cpu->midr = 0x414fd0b1;          /* r4p1 */
-    cpu->revidr = 0;
-
-    /* From B2.18 CCSIDR_EL1 */
-    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
-    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
-    cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
-
-    /* From B2.93 SCTLR_EL3 */
-    cpu->reset_sctlr = 0x30c50838;
-
-    /* From B4.23 ICH_VTR_EL2 */
-    cpu->gic_num_lrs = 4;
-    cpu->gic_vpribits = 5;
-    cpu->gic_vprebits = 5;
-    cpu->gic_pribits = 5;
-
-    /* From B5.1 AdvSIMD AArch64 register summary */
-    cpu->isar.mvfr0 = 0x10110222;
-    cpu->isar.mvfr1 = 0x13211111;
-    cpu->isar.mvfr2 = 0x00000043;
-
-    /* From D5.1 AArch64 PMU register summary */
-    cpu->isar.reset_pmcr_el0 = 0x410b3000;
-}
-
-static void aarch64_neoverse_n1_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cpu->dtb_compatible = "arm,neoverse-n1";
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-
-    /* Ordered by B2.4 AArch64 registers by functional group */
-    cpu->clidr = 0x82000023;
-    cpu->ctr = 0x8444c004;
-    cpu->dcz_blocksize = 4;
-    cpu->isar.id_aa64dfr0  = 0x0000000110305408ull;
-    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
-    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
-    cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
-    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
-    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
-    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
-    cpu->isar.id_aa64pfr1  = 0x0000000000000020ull;
-    cpu->id_afr0       = 0x00000000;
-    cpu->isar.id_dfr0  = 0x04010088;
-    cpu->isar.id_isar0 = 0x02101110;
-    cpu->isar.id_isar1 = 0x13112111;
-    cpu->isar.id_isar2 = 0x21232042;
-    cpu->isar.id_isar3 = 0x01112131;
-    cpu->isar.id_isar4 = 0x00010142;
-    cpu->isar.id_isar5 = 0x01011121;
-    cpu->isar.id_isar6 = 0x00000010;
-    cpu->isar.id_mmfr0 = 0x10201105;
-    cpu->isar.id_mmfr1 = 0x40000000;
-    cpu->isar.id_mmfr2 = 0x01260000;
-    cpu->isar.id_mmfr3 = 0x02122211;
-    cpu->isar.id_mmfr4 = 0x00021110;
-    cpu->isar.id_pfr0  = 0x10010131;
-    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
-    cpu->isar.id_pfr2  = 0x00000011;
-    cpu->midr = 0x414fd0c1;          /* r4p1 */
-    cpu->revidr = 0;
-
-    /* From B2.23 CCSIDR_EL1 */
-    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
-    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
-    cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
-
-    /* From B2.98 SCTLR_EL3 */
-    cpu->reset_sctlr = 0x30c50838;
-
-    /* From B4.23 ICH_VTR_EL2 */
-    cpu->gic_num_lrs = 4;
-    cpu->gic_vpribits = 5;
-    cpu->gic_vprebits = 5;
-    cpu->gic_pribits = 5;
-
-    /* From B5.1 AdvSIMD AArch64 register summary */
-    cpu->isar.mvfr0 = 0x10110222;
-    cpu->isar.mvfr1 = 0x13211111;
-    cpu->isar.mvfr2 = 0x00000043;
-
-    /* From D5.1 AArch64 PMU register summary */
-    cpu->isar.reset_pmcr_el0 = 0x410c3000;
-}
-
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 {
     /*
@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
     cpu->isar.id_aa64mmfr0 = t;
 }
 
+static void aarch64_a57_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a57";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
+    cpu->midr = 0x411fd070;
+    cpu->revidr = 0x00000000;
+    cpu->reset_fpsid = 0x41034070;
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x12111111;
+    cpu->isar.mvfr2 = 0x00000043;
+    cpu->ctr = 0x8444c004;
+    cpu->reset_sctlr = 0x00c50838;
+    cpu->isar.id_pfr0 = 0x00000131;
+    cpu->isar.id_pfr1 = 0x00011011;
+    cpu->isar.id_dfr0 = 0x03010066;
+    cpu->id_afr0 = 0x00000000;
+    cpu->isar.id_mmfr0 = 0x10101105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02102211;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00011142;
+    cpu->isar.id_isar5 = 0x00011121;
+    cpu->isar.id_isar6 = 0;
+    cpu->isar.id_aa64pfr0 = 0x00002222;
+    cpu->isar.id_aa64dfr0 = 0x10305106;
+    cpu->isar.id_aa64isar0 = 0x00011120;
+    cpu->isar.id_aa64mmfr0 = 0x00001124;
+    cpu->isar.dbgdidr = 0x3516d000;
+    cpu->isar.dbgdevid = 0x01110f13;
+    cpu->isar.dbgdevid1 = 0x2;
+    cpu->isar.reset_pmcr_el0 = 0x41013000;
+    cpu->clidr = 0x0a200023;
+    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
+    cpu->dcz_blocksize = 4; /* 64 bytes */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+    cpu->gic_pribits = 5;
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
+}
+
+static void aarch64_a53_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a53";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
+    cpu->midr = 0x410fd034;
+    cpu->revidr = 0x00000000;
+    cpu->reset_fpsid = 0x41034070;
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x12111111;
+    cpu->isar.mvfr2 = 0x00000043;
+    cpu->ctr = 0x84448004; /* L1Ip = VIPT */
+    cpu->reset_sctlr = 0x00c50838;
+    cpu->isar.id_pfr0 = 0x00000131;
+    cpu->isar.id_pfr1 = 0x00011011;
+    cpu->isar.id_dfr0 = 0x03010066;
+    cpu->id_afr0 = 0x00000000;
+    cpu->isar.id_mmfr0 = 0x10101105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02102211;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00011142;
+    cpu->isar.id_isar5 = 0x00011121;
+    cpu->isar.id_isar6 = 0;
+    cpu->isar.id_aa64pfr0 = 0x00002222;
+    cpu->isar.id_aa64dfr0 = 0x10305106;
+    cpu->isar.id_aa64isar0 = 0x00011120;
+    cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
+    cpu->isar.dbgdidr = 0x3516d000;
+    cpu->isar.dbgdevid = 0x00110f13;
+    cpu->isar.dbgdevid1 = 0x1;
+    cpu->isar.reset_pmcr_el0 = 0x41033000;
+    cpu->clidr = 0x0a200023;
+    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
+    cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
+    cpu->dcz_blocksize = 4; /* 64 bytes */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+    cpu->gic_pribits = 5;
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
+}
+
+static void aarch64_a72_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a72";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    cpu->midr = 0x410fd083;
+    cpu->revidr = 0x00000000;
+    cpu->reset_fpsid = 0x41034080;
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x12111111;
+    cpu->isar.mvfr2 = 0x00000043;
+    cpu->ctr = 0x8444c004;
+    cpu->reset_sctlr = 0x00c50838;
+    cpu->isar.id_pfr0 = 0x00000131;
+    cpu->isar.id_pfr1 = 0x00011011;
+    cpu->isar.id_dfr0 = 0x03010066;
+    cpu->id_afr0 = 0x00000000;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02102211;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00011142;
+    cpu->isar.id_isar5 = 0x00011121;
+    cpu->isar.id_aa64pfr0 = 0x00002222;
+    cpu->isar.id_aa64dfr0 = 0x10305106;
+    cpu->isar.id_aa64isar0 = 0x00011120;
+    cpu->isar.id_aa64mmfr0 = 0x00001124;
+    cpu->isar.dbgdidr = 0x3516d000;
+    cpu->isar.dbgdevid = 0x01110f13;
+    cpu->isar.dbgdevid1 = 0x2;
+    cpu->isar.reset_pmcr_el0 = 0x41023000;
+    cpu->clidr = 0x0a200023;
+    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+    cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
+    cpu->dcz_blocksize = 4; /* 64 bytes */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+    cpu->gic_pribits = 5;
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
+}
+
+static void aarch64_a76_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a76";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+    /* Ordered by B2.4 AArch64 registers by functional group */
+    cpu->clidr = 0x82000023;
+    cpu->ctr = 0x8444C004;
+    cpu->dcz_blocksize = 4;
+    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
+    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
+    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
+    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
+    cpu->id_afr0       = 0x00000000;
+    cpu->isar.id_dfr0  = 0x04010088;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00010142;
+    cpu->isar.id_isar5 = 0x01011121;
+    cpu->isar.id_isar6 = 0x00000010;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02122211;
+    cpu->isar.id_mmfr4 = 0x00021110;
+    cpu->isar.id_pfr0  = 0x10010131;
+    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
+    cpu->isar.id_pfr2  = 0x00000011;
+    cpu->midr = 0x414fd0b1;          /* r4p1 */
+    cpu->revidr = 0;
+
+    /* From B2.18 CCSIDR_EL1 */
+    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+    cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
+
+    /* From B2.93 SCTLR_EL3 */
+    cpu->reset_sctlr = 0x30c50838;
+
+    /* From B4.23 ICH_VTR_EL2 */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+    cpu->gic_pribits = 5;
+
+    /* From B5.1 AdvSIMD AArch64 register summary */
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x13211111;
+    cpu->isar.mvfr2 = 0x00000043;
+
+    /* From D5.1 AArch64 PMU register summary */
+    cpu->isar.reset_pmcr_el0 = 0x410b3000;
+}
+
+static void aarch64_a64fx_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,a64fx";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    cpu->midr = 0x461f0010;
+    cpu->revidr = 0x00000000;
+    cpu->ctr = 0x86668006;
+    cpu->reset_sctlr = 0x30000180;
+    cpu->isar.id_aa64pfr0 =   0x0000000101111111; /* No RAS Extensions */
+    cpu->isar.id_aa64pfr1 = 0x0000000000000000;
+    cpu->isar.id_aa64dfr0 = 0x0000000010305408;
+    cpu->isar.id_aa64dfr1 = 0x0000000000000000;
+    cpu->id_aa64afr0 = 0x0000000000000000;
+    cpu->id_aa64afr1 = 0x0000000000000000;
+    cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
+    cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
+    cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
+    cpu->isar.id_aa64isar0 = 0x0000000010211120;
+    cpu->isar.id_aa64isar1 = 0x0000000000010001;
+    cpu->isar.id_aa64zfr0 = 0x0000000000000000;
+    cpu->clidr = 0x0000000080000023;
+    cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
+    cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
+    cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
+    cpu->dcz_blocksize = 6; /* 256 bytes */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+    cpu->gic_pribits = 5;
+
+    /* The A64FX supports only 128, 256 and 512 bit vector lengths */
+    aarch64_add_sve_properties(obj);
+    cpu->sve_vq.supported = (1 << 0)  /* 128bit */
+                          | (1 << 1)  /* 256bit */
+                          | (1 << 3); /* 512bit */
+
+    cpu->isar.reset_pmcr_el0 = 0x46014040;
+
+    /* TODO:  Add A64FX specific HPC extension registers */
+}
+
+static void aarch64_neoverse_n1_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,neoverse-n1";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+    /* Ordered by B2.4 AArch64 registers by functional group */
+    cpu->clidr = 0x82000023;
+    cpu->ctr = 0x8444c004;
+    cpu->dcz_blocksize = 4;
+    cpu->isar.id_aa64dfr0  = 0x0000000110305408ull;
+    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+    cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
+    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
+    cpu->isar.id_aa64pfr1  = 0x0000000000000020ull;
+    cpu->id_afr0       = 0x00000000;
+    cpu->isar.id_dfr0  = 0x04010088;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00010142;
+    cpu->isar.id_isar5 = 0x01011121;
+    cpu->isar.id_isar6 = 0x00000010;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02122211;
+    cpu->isar.id_mmfr4 = 0x00021110;
+    cpu->isar.id_pfr0  = 0x10010131;
+    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
+    cpu->isar.id_pfr2  = 0x00000011;
+    cpu->midr = 0x414fd0c1;          /* r4p1 */
+    cpu->revidr = 0;
+
+    /* From B2.23 CCSIDR_EL1 */
+    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+    cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
+
+    /* From B2.98 SCTLR_EL3 */
+    cpu->reset_sctlr = 0x30c50838;
+
+    /* From B4.23 ICH_VTR_EL2 */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+    cpu->gic_pribits = 5;
+
+    /* From B5.1 AdvSIMD AArch64 register summary */
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x13211111;
+    cpu->isar.mvfr2 = 0x00000043;
+
+    /* From D5.1 AArch64 PMU register summary */
+    cpu->isar.reset_pmcr_el0 = 0x410c3000;
+}
+
 static void aarch64_host_initfn(Object *obj)
 {
 #if defined(CONFIG_KVM)
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
 }
 
-static void aarch64_a64fx_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cpu->dtb_compatible = "arm,a64fx";
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-    cpu->midr = 0x461f0010;
-    cpu->revidr = 0x00000000;
-    cpu->ctr = 0x86668006;
-    cpu->reset_sctlr = 0x30000180;
-    cpu->isar.id_aa64pfr0 =   0x0000000101111111; /* No RAS Extensions */
-    cpu->isar.id_aa64pfr1 = 0x0000000000000000;
-    cpu->isar.id_aa64dfr0 = 0x0000000010305408;
-    cpu->isar.id_aa64dfr1 = 0x0000000000000000;
-    cpu->id_aa64afr0 = 0x0000000000000000;
-    cpu->id_aa64afr1 = 0x0000000000000000;
-    cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
-    cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
-    cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
-    cpu->isar.id_aa64isar0 = 0x0000000010211120;
-    cpu->isar.id_aa64isar1 = 0x0000000000010001;
-    cpu->isar.id_aa64zfr0 = 0x0000000000000000;
-    cpu->clidr = 0x0000000080000023;
-    cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
-    cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
-    cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
-    cpu->dcz_blocksize = 6; /* 256 bytes */
-    cpu->gic_num_lrs = 4;
-    cpu->gic_vpribits = 5;
-    cpu->gic_vprebits = 5;
-    cpu->gic_pribits = 5;
-
-    /* The A64FX supports only 128, 256 and 512 bit vector lengths */
-    aarch64_add_sve_properties(obj);
-    cpu->sve_vq.supported = (1 << 0)  /* 128bit */
-                          | (1 << 1)  /* 256bit */
-                          | (1 << 3); /* 512bit */
-
-    cpu->isar.reset_pmcr_el0 = 0x46014040;
-
-    /* TODO:  Add A64FX specific HPC extension registers */
-}
-
 static const ARMCPUInfo aarch64_cpus[] = {
     { .name = "cortex-a35",         .initfn = aarch64_a35_initfn },
     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
-- 
2.25.1

From: Francisco Iglesias <francisco.iglesias@amd.com>

Connect ZynqMP's USB controllers.

Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220920081517.25401-1-frasse.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-zynqmp.h |  3 +++
 hw/arm/xlnx-zynqmp.c         | 36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 39 insertions(+)

diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
 #include "hw/misc/xlnx-zynqmp-crf.h"
 #include "hw/timer/cadence_ttc.h"
+#include "hw/usb/hcd-dwc3.h"
 
 #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
 #define XLNX_ZYNQMP_NUM_SPIS 2
 #define XLNX_ZYNQMP_NUM_GDMA_CH 8
 #define XLNX_ZYNQMP_NUM_ADMA_CH 8
+#define XLNX_ZYNQMP_NUM_USB 2
 
 #define XLNX_ZYNQMP_NUM_QSPI_BUS 2
 #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
     XlnxZynqMPAPUCtrl apu_ctrl;
     XlnxZynqMPCRF crf;
     CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
+    USBDWC3 usb[XLNX_ZYNQMP_NUM_USB];
 
     char *boot_cpu;
     ARMCPU *boot_cpu_ptr;
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -XXX,XX +XXX,XX @@ static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
     77, 78, 79, 80, 81, 82, 83, 84
 };
 
+static const uint64_t usb_addr[XLNX_ZYNQMP_NUM_USB] = {
+    0xFE200000, 0xFE300000
+};
+
+static const int usb_intr[XLNX_ZYNQMP_NUM_USB] = {
+    65, 70
+};
+
 typedef struct XlnxZynqMPGICRegion {
     int region_index;
     uint32_t address;
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj)
     object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
     object_initialize_child(obj, "qspi-irq-orgate",
                             &s->qspi_irq_orgate, TYPE_OR_IRQ);
+
+    for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
+        object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3);
+    }
 }
 
 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
         object_property_add_alias(OBJECT(s), bus_name,
                                   OBJECT(&s->qspi), target_bus);
     }
+
+    for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
+        if (!object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma",
+                                      OBJECT(system_memory), errp)) {
+            return;
+        }
+
+        qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4);
+        qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2);
+
+        if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) {
+            return;
+        }
+
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_addr[i]);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0,
+                           gic_spi[usb_intr[i]]);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 1,
+                           gic_spi[usb_intr[i] + 1]);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 2,
+                           gic_spi[usb_intr[i] + 2]);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 3,
+                           gic_spi[usb_intr[i] + 3]);
+    }
 }
 
 static Property xlnx_zynqmp_props[] = {
-- 
2.25.1

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

The devicetree specification requires a 'model' property in the root
node. Fix the corresponding dt-validate warning:

/: 'model' is a required property
  From schema: dtschema/schemas/root-node.yaml

Use the same name for model as for compatible. The specification
recommends that 'compatible' follows the format 'manufacturer,model' and
'model' follows the format 'manufacturer,model-number'. Since our
'compatible' doesn't observe this, 'model' doesn't really need to
either.

Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20220927100347.176606-2-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms)
     qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
+    qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
 
     /* /chosen must exist for load_dtb to fill in necessary properties later */
     qemu_fdt_add_subnode(fdt, "/chosen");
-- 
2.25.1

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

The GICv3 bindings requires a #msi-cells property for the ITS node. Fix
the corresponding dt-validate warning:

interrupt-controller@8000000: msi-controller@8080000: '#msi-cells' is a required property
  From schema: linux/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml

Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20220927100347.176606-3-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void fdt_add_its_gic_node(VirtMachineState *vms)
     qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
                             "arm,gic-v3-its");
     qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
+    qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
                                  2, vms->memmap[VIRT_GIC_ITS].base,
                                  2, vms->memmap[VIRT_GIC_ITS].size);
-- 
2.25.1

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

The "msi-parent" property can be used on the PCI node when MSIs do not
contain sideband data (device IDs) [1]. In QEMU, MSI transactions
contain the requester ID, so the PCI node should use the "msi-map"
property instead of "msi-parent". In our case the property describes an
identity map between requester ID and sideband data.

This fixes a warning when passing the DTB generated by QEMU to dtc,
following a recent change to the GICv3 node:

Warning (msi_parent_property): /pcie@10000000:msi-parent: property size (4) too small for cell size 1

[1] linux/Documentation/devicetree/bindings/pci/pci-msi.txt

Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20220927100347.176606-4-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_pcie(VirtMachineState *vms)
     qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
 
     if (vms->msi_phandle) {
-        qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",
-                               vms->msi_phandle);
+        qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
+                               0, vms->msi_phandle, 0, 0x10000);
     }
 
     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
-- 
2.25.1

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

The SMMUv3 node isn't expected to have clock properties
(unlike the SMMUv2). Fix the corresponding dt-validate warning:

smmuv3@9050000: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
  From schema: linux/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml

Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tweaked commit message as suggested by Eric]
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20220927100347.176606-7-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const VirtMachineState *vms,
     qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
                      sizeof(irq_names));
 
-    qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);
-    qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");
     qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
 
     qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
-- 
2.25.1

From: Jerome Forissier <jerome.forissier@linaro.org>

SP_EL1 must be kept when EL3 is present but EL2 is not. Therefore mark
it with ARM_CP_EL3_NO_EL2_KEEP.

Cc: qemu-stable@nongnu.org
Fixes: 696ba3771894 ("target/arm: Handle cpreg registration for missing EL")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220927120058.670901-1-jerome.forissier@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_ALIAS,
+      .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP,
       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
-- 
2.25.1

The following changes since commit 003ba52a8b327180e284630b289c6ece5a3e08b9:

Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-02-16 11:16:39 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230216

for you to fetch changes up to caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8:

tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG (2023-02-16 16:28:53 +0000)

----------------------------------------------------------------
target-arm queue:
 * Some mostly M-profile-related code cleanups
 * avocado: Retire the boot_linux.py AArch64 TCG tests
 * hw/arm/smmuv3: Add GBPA register
 * arm/virt: don't try to spell out the accelerator
 * hw/arm: Attach PSPI module to NPCM7XX SoC
 * Some cleanup/refactoring patches aiming towards
   allowing building Arm targets without CONFIG_TCG

----------------------------------------------------------------
Alex Bennée (1):
      tests/avocado: retire the Aarch64 TCG tests from boot_linux.py

Claudio Fontana (3):
      target/arm: rename handle_semihosting to tcg_handle_semihosting
      target/arm: wrap psci call with tcg_enabled
      target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()

Cornelia Huck (1):
      arm/virt: don't try to spell out the accelerator

Fabiano Rosas (7):
      target/arm: Move PC alignment check
      target/arm: Move cpregs code out of cpu.h
      tests/avocado: Skip tests that require a missing accelerator
      tests/avocado: Tag TCG tests with accel:tcg
      target/arm: Use "max" as default cpu for the virt machine with KVM
      tests/qtest: arm-cpu-features: Match tests to required accelerators
      tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG

Hao Wu (3):
      MAINTAINERS: Add myself to maintainers and remove Havard
      hw/ssi: Add Nuvoton PSPI Module
      hw/arm: Attach PSPI module to NPCM7XX SoC

Jean-Philippe Brucker (2):
      hw/arm/smmu-common: Support 64-bit addresses
      hw/arm/smmu-common: Fix TTB1 handling

Mostafa Saleh (1):
      hw/arm/smmuv3: Add GBPA register

Philippe Mathieu-Daudé (12):
      hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro
      target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation
      target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope
      target/arm: Constify ID_PFR1 on user emulation
      target/arm: Convert CPUARMState::eabi to boolean
      target/arm: Avoid resetting CPUARMState::eabi field
      target/arm: Restrict CPUARMState::gicv3state to sysemu
      target/arm: Restrict CPUARMState::arm_boot_info to sysemu
      target/arm: Restrict CPUARMState::nvic to sysemu
      target/arm: Store CPUARMState::nvic as NVICState*
      target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
      hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro,
similarly to automatic conversion from commit 8063396bf3
("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/intc/armv7m_nvic.h | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@
 #include "qom/object.h"
 
 #define TYPE_NVIC "armv7m_nvic"
-
-typedef struct NVICState NVICState;
-DECLARE_INSTANCE_CHECKER(NVICState, NVIC,
-                         TYPE_NVIC)
+OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC)
 
 /* Highest permitted number of exceptions (architectural limit) */
 #define NVIC_MAX_VECTORS 512
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/m_helper.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
     return 0;
 }
 
-#else
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+{
+    return ARMMMUIdx_MUser;
+}
+
+#else /* !CONFIG_USER_ONLY */
 
 /*
  * What kind of stack write are we doing? This affects how exceptions
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
     return tt_resp;
 }
 
-#endif /* !CONFIG_USER_ONLY */
-
 ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
                               bool secstate, bool priv, bool negpri)
 {
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
 
     return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
 }
+
+#endif /* !CONFIG_USER_ONLY */
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv()
are only used for system emulation in m_helper.c.
Move the definitions to avoid prototype forward declarations.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h | 14 --------
 target/arm/m_helper.c  | 74 +++++++++++++++++++++---------------------
 2 files changed, 37 insertions(+), 51 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx)
 
 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
 
-/*
- * Return the MMU index for a v7M CPU with all relevant information
- * manually specified.
- */
-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
-                              bool secstate, bool priv, bool negpri);
-
-/*
- * Return the MMU index for a v7M CPU in the specified security and
- * privilege state.
- */
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
-                                                bool secstate, bool priv);
-
 /* Return the MMU index for a v7M CPU in the specified security state */
 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
 
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
 
 #else /* !CONFIG_USER_ONLY */
 
+static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+                                     bool secstate, bool priv, bool negpri)
+{
+    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
+
+    if (priv) {
+        mmu_idx |= ARM_MMU_IDX_M_PRIV;
+    }
+
+    if (negpri) {
+        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
+    }
+
+    if (secstate) {
+        mmu_idx |= ARM_MMU_IDX_M_S;
+    }
+
+    return mmu_idx;
+}
+
+static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+                                                       bool secstate, bool priv)
+{
+    bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
+
+    return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
+}
+
+/* Return the MMU index for a v7M CPU in the specified security state */
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+{
+    bool priv = arm_v7m_is_handler_mode(env) ||
+        !(env->v7m.control[secstate] & 1);
+
+    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
+}
+
 /*
  * What kind of stack write are we doing? This affects how exceptions
  * generated during the stacking are treated.
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
     return tt_resp;
 }
 
-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
-                              bool secstate, bool priv, bool negpri)
-{
-    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
-
-    if (priv) {
-        mmu_idx |= ARM_MMU_IDX_M_PRIV;
-    }
-
-    if (negpri) {
-        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
-    }
-
-    if (secstate) {
-        mmu_idx |= ARM_MMU_IDX_M_S;
-    }
-
-    return mmu_idx;
-}
-
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
-                                                bool secstate, bool priv)
-{
-    bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
-
-    return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
-}
-
-/* Return the MMU index for a v7M CPU in the specified security state */
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
-{
-    bool priv = arm_v7m_is_handler_mode(env) ||
-        !(env->v7m.control[secstate] & 1);
-
-    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
-}
-
 #endif /* !CONFIG_USER_ONLY */
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230206223502.25122-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
     }
 }
 
+#ifndef CONFIG_USER_ONLY
 /*
  * We don't know until after realize whether there's a GICv3
  * attached, and that is what registers the gicv3 sysregs.
@@ -XXX,XX +XXX,XX @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
     return pfr1;
 }
 
-#ifndef CONFIG_USER_ONLY
 static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     ARMCPU *cpu = env_archcpu(env);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
               .access = PL1_R, .type = ARM_CP_NO_RAW,
               .accessfn = access_aa32_tid3,
+#ifdef CONFIG_USER_ONLY
+              .type = ARM_CP_CONST,
+              .resetvalue = cpu->isar.id_pfr1,
+#else
+              .type = ARM_CP_NO_RAW,
+              .accessfn = access_aa32_tid3,
               .readfn = id_pfr1_read,
-              .writefn = arm_cp_write_ignore },
+              .writefn = arm_cp_write_ignore
+#endif
+            },
             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
               .access = PL1_R, .type = ARM_CP_CONST,
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/user-internals.h | 2 +-
 target/arm/cpu.h            | 2 +-
 linux-user/arm/cpu_loop.c   | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/user-internals.h
+++ b/linux-user/user-internals.h
@@ -XXX,XX +XXX,XX @@ void print_termios(void *arg);
 #ifdef TARGET_ARM
 static inline int regpairs_aligned(CPUArchState *cpu_env, int num)
 {
-    return cpu_env->eabi == 1;
+    return cpu_env->eabi;
 }
 #elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32)
 static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; }
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
 
 #if defined(CONFIG_USER_ONLY)
     /* For usermode syscall translation.  */
-    int eabi;
+    bool eabi;
 #endif
 
     struct CPUBreakpoint *cpu_breakpoint[16];
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/arm/cpu_loop.c
+++ b/linux-user/arm/cpu_loop.c
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
             break;
         case EXCP_SWI:
             {
-                env->eabi = 1;
+                env->eabi = true;
                 /* system call */
                 if (env->thumb) {
                     /* Thumb is always EABI style with syscall number in r7 */
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
                          * > 0xfffff and are handled below as out-of-range.
                          */
                         n ^= ARM_SYSCALL_BASE;
-                        env->eabi = 0;
+                        env->eabi = false;
                     }
                 }
 
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Although the 'eabi' field is only used in user emulation where
CPU reset doesn't occur, it doesn't belong to the area to reset.
Move it after the 'end_reset_fields' for consistency.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230206223502.25122-7-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
     ARMVectorReg zarray[ARM_MAX_VQ * 16];
 #endif
 
-#if defined(CONFIG_USER_ONLY)
-    /* For usermode syscall translation.  */
-    bool eabi;
-#endif
-
     struct CPUBreakpoint *cpu_breakpoint[16];
     struct CPUWatchpoint *cpu_watchpoint[16];
 
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
     const struct arm_boot_info *boot_info;
     /* Store GICv3CPUState to access from this struct */
     void *gicv3state;
+#if defined(CONFIG_USER_ONLY)
+    /* For usermode syscall translation.  */
+    bool eabi;
+#endif /* CONFIG_USER_ONLY */
 
 #ifdef TARGET_TAGGED_ADDRESSES
     /* Linux syscall tagged address support */
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

There is no point in using a void pointer to access the NVIC.
Use the real type to avoid casting it while debugging.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-11-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h      | 46 ++++++++++++++++++++++---------------------
 hw/intc/armv7m_nvic.c | 38 ++++++++++++-----------------------
 target/arm/cpu.c      |  1 +
 target/arm/m_helper.c |  2 +-
 4 files changed, 39 insertions(+), 48 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMTBFlags {
 
 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
 
+typedef struct NVICState NVICState;
+
 typedef struct CPUArchState {
     /* Regs for current mode.  */
     uint32_t regs[16];
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
     } sau;
 
 #if !defined(CONFIG_USER_ONLY)
-    void *nvic;
+    NVICState *nvic;
     const struct arm_boot_info *boot_info;
     /* Store GICv3CPUState to access from this struct */
     void *gicv3state;
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
 
 /* Interface between CPU and Interrupt controller.  */
 #ifndef CONFIG_USER_ONLY
-bool armv7m_nvic_can_take_pending_exception(void *opaque);
+bool armv7m_nvic_can_take_pending_exception(NVICState *s);
 #else
-static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
+static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
 {
     return true;
 }
 #endif
 /**
  * armv7m_nvic_set_pending: mark the specified exception as pending
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to mark pending
  * @secure: false for non-banked exceptions or for the nonsecure
  * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
  * if @secure is true and @irq does not specify one of the fixed set
  * of architecturally banked exceptions.
  */
-void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
+void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_set_pending_derived: mark this derived exception as pending
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to mark pending
  * @secure: false for non-banked exceptions or for the nonsecure
  * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
  * exceptions (exceptions generated in the course of trying to take
  * a different exception).
  */
-void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
+void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to mark pending
  * @secure: false for non-banked exceptions or for the nonsecure
  * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
  * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
  * generated in the course of lazy stacking of FP registers.
  */
-void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
+void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_get_pending_irq_info: return highest priority pending
  *    exception, and whether it targets Secure state
- * @opaque: the NVIC
+ * @s: the NVIC
  * @pirq: set to pending exception number
  * @ptargets_secure: set to whether pending exception targets Secure
  *
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
  * to true if the current highest priority pending exception should
  * be taken to Secure state, false for NS.
  */
-void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
+void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
                                       bool *ptargets_secure);
 /**
  * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
- * @opaque: the NVIC
+ * @s: the NVIC
  *
  * Move the current highest priority pending exception from the pending
  * state to the active state, and update v7m.exception to indicate that
  * it is the exception currently being handled.
  */
-void armv7m_nvic_acknowledge_irq(void *opaque);
+void armv7m_nvic_acknowledge_irq(NVICState *s);
 /**
  * armv7m_nvic_complete_irq: complete specified interrupt or exception
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to complete
  * @secure: true if this exception was secure
  *
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque);
  *           0 if there is still an irq active after this one was completed
  * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
  */
-int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
+int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to mark pending
  * @secure: false for non-banked exceptions or for the nonsecure
  * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
  * interrupt the current execution priority. This controls whether the
  * RDY bit for it in the FPCCR is set.
  */
-bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
+bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_raw_execution_priority: return the raw execution priority
- * @opaque: the NVIC
+ * @s: the NVIC
  *
  * Returns: the raw execution priority as defined by the v8M architecture.
  * This is the execution priority minus the effects of AIRCR.PRIS,
  * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
  * (v8M ARM ARM I_PKLD.)
  */
-int armv7m_nvic_raw_execution_priority(void *opaque);
+int armv7m_nvic_raw_execution_priority(NVICState *s);
 /**
  * armv7m_nvic_neg_prio_requested: return true if the requested execution
  * priority is negative for the specified security state.
- * @opaque: the NVIC
+ * @s: the NVIC
  * @secure: the security state to test
  * This corresponds to the pseudocode IsReqExecPriNeg().
  */
 #ifndef CONFIG_USER_ONLY
-bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
+bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
 #else
-static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
+static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
 {
     return false;
 }
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
     return MIN(running, s->exception_prio);
 }
 
-bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
+bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
 {
     /* Return true if the requested execution priority is negative
      * for the specified security state, ie that security state
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
      * mean we don't allow FAULTMASK_NS to actually make the execution
      * priority negative). Compare pseudocode IsReqExcPriNeg().
      */
-    NVICState *s = opaque;
-
     if (s->cpu->env.v7m.faultmask[secure]) {
         return true;
     }
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
     return false;
 }
 
-bool armv7m_nvic_can_take_pending_exception(void *opaque)
+bool armv7m_nvic_can_take_pending_exception(NVICState *s)
 {
-    NVICState *s = opaque;
-
     return nvic_exec_prio(s) > nvic_pending_prio(s);
 }
 
-int armv7m_nvic_raw_execution_priority(void *opaque)
+int armv7m_nvic_raw_execution_priority(NVICState *s)
 {
-    NVICState *s = opaque;
-
     return s->exception_prio;
 }
 
@@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s)
  * if @secure is true and @irq does not specify one of the fixed set
  * of architecturally banked exceptions.
  */
-static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
+static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure)
 {
-    NVICState *s = (NVICState *)opaque;
     VecInfo *vec;
 
     assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
@@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
     }
 }
 
-void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
+void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure)
 {
-    do_armv7m_nvic_set_pending(opaque, irq, secure, false);
+    do_armv7m_nvic_set_pending(s, irq, secure, false);
 }
 
-void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure)
+void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure)
 {
-    do_armv7m_nvic_set_pending(opaque, irq, secure, true);
+    do_armv7m_nvic_set_pending(s, irq, secure, true);
 }
 
-void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
+void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure)
 {
     /*
      * Pend an exception during lazy FP stacking. This differs
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
      * whether we should escalate depends on the saved context
      * in the FPCCR register, not on the current state of the CPU/NVIC.
      */
-    NVICState *s = (NVICState *)opaque;
     bool banked = exc_is_banked(irq);
     VecInfo *vec;
     bool targets_secure;
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
 }
 
 /* Make pending IRQ active.  */
-void armv7m_nvic_acknowledge_irq(void *opaque)
+void armv7m_nvic_acknowledge_irq(NVICState *s)
 {
-    NVICState *s = (NVICState *)opaque;
     CPUARMState *env = &s->cpu->env;
     const int pending = s->vectpending;
     const int running = nvic_exec_prio(s);
@@ -XXX,XX +XXX,XX @@ static bool vectpending_targets_secure(NVICState *s)
         exc_targets_secure(s, s->vectpending);
 }
 
-void armv7m_nvic_get_pending_irq_info(void *opaque,
+void armv7m_nvic_get_pending_irq_info(NVICState *s,
                                       int *pirq, bool *ptargets_secure)
 {
-    NVICState *s = (NVICState *)opaque;
     const int pending = s->vectpending;
     bool targets_secure;
 
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque,
     *pirq = pending;
 }
 
-int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
+int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure)
 {
-    NVICState *s = (NVICState *)opaque;
     VecInfo *vec = NULL;
     int ret = 0;
 
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
     return ret;
 }
 
-bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
+bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure)
 {
     /*
      * Return whether an exception is "ready", i.e. it is enabled and is
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
      * for non-banked exceptions secure is always false; for banked exceptions
      * it indicates which of the exceptions is required.
      */
-    NVICState *s = (NVICState *)opaque;
     bool banked = exc_is_banked(irq);
     VecInfo *vec;
     int running = nvic_exec_prio(s);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #include "hw/boards.h"
+#include "hw/intc/armv7m_nvic.h"
 #endif
 #include "sysemu/tcg.h"
 #include "sysemu/qtest.h"
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr,
      * that we will need later in order to do lazy FP reg stacking.
      */
     bool is_secure = env->v7m.secure;
-    void *nvic = env->nvic;
+    NVICState *nvic = env->nvic;
     /*
      * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits
      * are banked and we want to update the bit in the bank for the
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

While dozens of files include "cpu.h", only 3 files require
these NVIC helper declarations.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230206223502.25122-12-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++
 target/arm/cpu.h              | 123 ----------------------------------
 target/arm/cpu.c              |   4 +-
 target/arm/cpu_tcg.c          |   3 +
 target/arm/m_helper.c         |   3 +
 5 files changed, 132 insertions(+), 124 deletions(-)

diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@ struct NVICState {
     qemu_irq sysresetreq;
 };
 
+/* Interface between CPU and Interrupt controller.  */
+/**
+ * armv7m_nvic_set_pending: mark the specified exception as pending
+ * @s: the NVIC
+ * @irq: the exception number to mark pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Marks the specified exception as pending. Note that we will assert()
+ * if @secure is true and @irq does not specify one of the fixed set
+ * of architecturally banked exceptions.
+ */
+void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_set_pending_derived: mark this derived exception as pending
+ * @s: the NVIC
+ * @irq: the exception number to mark pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Similar to armv7m_nvic_set_pending(), but specifically for derived
+ * exceptions (exceptions generated in the course of trying to take
+ * a different exception).
+ */
+void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
+ * @s: the NVIC
+ * @irq: the exception number to mark pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
+ * generated in the course of lazy stacking of FP registers.
+ */
+void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_get_pending_irq_info: return highest priority pending
+ *    exception, and whether it targets Secure state
+ * @s: the NVIC
+ * @pirq: set to pending exception number
+ * @ptargets_secure: set to whether pending exception targets Secure
+ *
+ * This function writes the number of the highest priority pending
+ * exception (the one which would be made active by
+ * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
+ * to true if the current highest priority pending exception should
+ * be taken to Secure state, false for NS.
+ */
+void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
+                                      bool *ptargets_secure);
+/**
+ * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
+ * @s: the NVIC
+ *
+ * Move the current highest priority pending exception from the pending
+ * state to the active state, and update v7m.exception to indicate that
+ * it is the exception currently being handled.
+ */
+void armv7m_nvic_acknowledge_irq(NVICState *s);
+/**
+ * armv7m_nvic_complete_irq: complete specified interrupt or exception
+ * @s: the NVIC
+ * @irq: the exception number to complete
+ * @secure: true if this exception was secure
+ *
+ * Returns: -1 if the irq was not active
+ *           1 if completing this irq brought us back to base (no active irqs)
+ *           0 if there is still an irq active after this one was completed
+ * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
+ */
+int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
+ * @s: the NVIC
+ * @irq: the exception number to mark pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Return whether an exception is "ready", i.e. whether the exception is
+ * enabled and is configured at a priority which would allow it to
+ * interrupt the current execution priority. This controls whether the
+ * RDY bit for it in the FPCCR is set.
+ */
+bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_raw_execution_priority: return the raw execution priority
+ * @s: the NVIC
+ *
+ * Returns: the raw execution priority as defined by the v8M architecture.
+ * This is the execution priority minus the effects of AIRCR.PRIS,
+ * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
+ * (v8M ARM ARM I_PKLD.)
+ */
+int armv7m_nvic_raw_execution_priority(NVICState *s);
+/**
+ * armv7m_nvic_neg_prio_requested: return true if the requested execution
+ * priority is negative for the specified security state.
+ * @s: the NVIC
+ * @secure: the security state to test
+ * This corresponds to the pseudocode IsReqExecPriNeg().
+ */
+#ifndef CONFIG_USER_ONLY
+bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
+#else
+static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
+{
+    return false;
+}
+#endif
+#ifndef CONFIG_USER_ONLY
+bool armv7m_nvic_can_take_pending_exception(NVICState *s);
+#else
+static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
+{
+    return true;
+}
+#endif
+
 #endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                  uint32_t cur_el, bool secure);
 
-/* Interface between CPU and Interrupt controller.  */
-#ifndef CONFIG_USER_ONLY
-bool armv7m_nvic_can_take_pending_exception(NVICState *s);
-#else
-static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
-{
-    return true;
-}
-#endif
-/**
- * armv7m_nvic_set_pending: mark the specified exception as pending
- * @s: the NVIC
- * @irq: the exception number to mark pending
- * @secure: false for non-banked exceptions or for the nonsecure
- * version of a banked exception, true for the secure version of a banked
- * exception.
- *
- * Marks the specified exception as pending. Note that we will assert()
- * if @secure is true and @irq does not specify one of the fixed set
- * of architecturally banked exceptions.
- */
-void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_set_pending_derived: mark this derived exception as pending
- * @s: the NVIC
- * @irq: the exception number to mark pending
- * @secure: false for non-banked exceptions or for the nonsecure
- * version of a banked exception, true for the secure version of a banked
- * exception.
- *
- * Similar to armv7m_nvic_set_pending(), but specifically for derived
- * exceptions (exceptions generated in the course of trying to take
- * a different exception).
- */
-void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
- * @s: the NVIC
- * @irq: the exception number to mark pending
- * @secure: false for non-banked exceptions or for the nonsecure
- * version of a banked exception, true for the secure version of a banked
- * exception.
- *
- * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
- * generated in the course of lazy stacking of FP registers.
- */
-void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_get_pending_irq_info: return highest priority pending
- *    exception, and whether it targets Secure state
- * @s: the NVIC
- * @pirq: set to pending exception number
- * @ptargets_secure: set to whether pending exception targets Secure
- *
- * This function writes the number of the highest priority pending
- * exception (the one which would be made active by
- * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
- * to true if the current highest priority pending exception should
- * be taken to Secure state, false for NS.
- */
-void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
-                                      bool *ptargets_secure);
-/**
- * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
- * @s: the NVIC
- *
- * Move the current highest priority pending exception from the pending
- * state to the active state, and update v7m.exception to indicate that
- * it is the exception currently being handled.
- */
-void armv7m_nvic_acknowledge_irq(NVICState *s);
-/**
- * armv7m_nvic_complete_irq: complete specified interrupt or exception
- * @s: the NVIC
- * @irq: the exception number to complete
- * @secure: true if this exception was secure
- *
- * Returns: -1 if the irq was not active
- *           1 if completing this irq brought us back to base (no active irqs)
- *           0 if there is still an irq active after this one was completed
- * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
- */
-int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
- * @s: the NVIC
- * @irq: the exception number to mark pending
- * @secure: false for non-banked exceptions or for the nonsecure
- * version of a banked exception, true for the secure version of a banked
- * exception.
- *
- * Return whether an exception is "ready", i.e. whether the exception is
- * enabled and is configured at a priority which would allow it to
- * interrupt the current execution priority. This controls whether the
- * RDY bit for it in the FPCCR is set.
- */
-bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_raw_execution_priority: return the raw execution priority
- * @s: the NVIC
- *
- * Returns: the raw execution priority as defined by the v8M architecture.
- * This is the execution priority minus the effects of AIRCR.PRIS,
- * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
- * (v8M ARM ARM I_PKLD.)
- */
-int armv7m_nvic_raw_execution_priority(NVICState *s);
-/**
- * armv7m_nvic_neg_prio_requested: return true if the requested execution
- * priority is negative for the specified security state.
- * @s: the NVIC
- * @secure: the security state to test
- * This corresponds to the pseudocode IsReqExecPriNeg().
- */
-#ifndef CONFIG_USER_ONLY
-bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
-#else
-static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
-{
-    return false;
-}
-#endif
-
 /* Interface for defining coprocessor registers.
  * Registers are defined in tables of arm_cp_reginfo structs
  * which are passed to define_arm_cp_regs().
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #include "hw/boards.h"
+#ifdef CONFIG_TCG
 #include "hw/intc/armv7m_nvic.h"
-#endif
+#endif /* CONFIG_TCG */
+#endif /* !CONFIG_USER_ONLY */
 #include "sysemu/tcg.h"
 #include "sysemu/qtest.h"
 #include "sysemu/hw_accel.h"
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #endif
 #include "cpregs.h"
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
+#include "hw/intc/armv7m_nvic.h"
+#endif
 
 
 /* Share AArch32 -cpu max features with AArch64. */
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/cpu_ldst.h"
 #include "semihosting/common-semi.h"
 #endif
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/intc/armv7m_nvic.h"
+#endif
 
 static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask,
                          uint32_t reg, uint32_t val)
-- 
2.34.1

From: Alex Bennée <alex.bennee@linaro.org>

The two TCG tests for GICv2 and GICv3 are very heavy weight distros
that take a long time to boot up, especially for an --enable-debug
build. The total code coverage they give is:

Overall coverage rate:
    lines......: 11.2% (59584 of 530123 lines)
    functions..: 15.0% (7436 of 49443 functions)
    branches...: 6.3% (19273 of 303933 branches)

We already get pretty close to that with the machine_aarch64_virt
tests which only does one full boot (~120s vs ~600s) of alpine. We
expand the kernel+initrd boot (~8s) to test both GICs and also add an
RNG device and a block device to generate a few IRQs and exercise the
storage layer. With that we get to a coverage of:

Overall coverage rate:
    lines......: 11.0% (58121 of 530123 lines)
    functions..: 14.9% (7343 of 49443 functions)
    branches...: 6.0% (18269 of 303933 branches)

which I feel is close enough given the massive time saving. If we want
to target any more sub-systems we can use lighter weight more directed
tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230203181632.2919715-1-alex.bennee@linaro.org
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/avocado/boot_linux.py           | 48 ++++----------------
 tests/avocado/machine_aarch64_virt.py | 63 ++++++++++++++++++++++++---
 2 files changed, 65 insertions(+), 46 deletions(-)

diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/boot_linux.py
+++ b/tests/avocado/boot_linux.py
@@ -XXX,XX +XXX,XX @@ def test_pc_q35_kvm(self):
         self.launch_and_wait(set_up_ssh_connection=False)
 
 
-# For Aarch64 we only boot KVM tests in CI as the TCG tests are very
-# heavyweight. There are lighter weight distros which we use in the
-# machine_aarch64_virt.py tests.
+# For Aarch64 we only boot KVM tests in CI as booting the current
+# Fedora OS in TCG tests is very heavyweight. There are lighter weight
+# distros which we use in the machine_aarch64_virt.py tests.
 class BootLinuxAarch64(LinuxTest):
     """
     :avocado: tags=arch:aarch64
     :avocado: tags=machine:virt
-    :avocado: tags=machine:gic-version=2
     """
     timeout = 720
 
-    def add_common_args(self):
-        self.vm.add_args('-bios',
-                         os.path.join(BUILD_DIR, 'pc-bios',
-                                      'edk2-aarch64-code.fd'))
-        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
-        self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
-
-    @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
-    def test_fedora_cloud_tcg_gicv2(self):
-        """
-        :avocado: tags=accel:tcg
-        :avocado: tags=cpu:max
-        :avocado: tags=device:gicv2
-        """
-        self.require_accelerator("tcg")
-        self.vm.add_args("-accel", "tcg")
-        self.vm.add_args("-cpu", "max,lpa2=off")
-        self.vm.add_args("-machine", "virt,gic-version=2")
-        self.add_common_args()
-        self.launch_and_wait(set_up_ssh_connection=False)
-
-    @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
-    def test_fedora_cloud_tcg_gicv3(self):
-        """
-        :avocado: tags=accel:tcg
-        :avocado: tags=cpu:max
-        :avocado: tags=device:gicv3
-        """
-        self.require_accelerator("tcg")
-        self.vm.add_args("-accel", "tcg")
-        self.vm.add_args("-cpu", "max,lpa2=off")
-        self.vm.add_args("-machine", "virt,gic-version=3")
-        self.add_common_args()
-        self.launch_and_wait(set_up_ssh_connection=False)
-
     def test_virt_kvm(self):
         """
         :avocado: tags=accel:kvm
@@ -XXX,XX +XXX,XX @@ def test_virt_kvm(self):
         self.require_accelerator("kvm")
         self.vm.add_args("-accel", "kvm")
         self.vm.add_args("-machine", "virt,gic-version=host")
-        self.add_common_args()
+        self.vm.add_args('-bios',
+                         os.path.join(BUILD_DIR, 'pc-bios',
+                                      'edk2-aarch64-code.fd'))
+        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
+        self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
         self.launch_and_wait(set_up_ssh_connection=False)
 
 
diff --git a/tests/avocado/machine_aarch64_virt.py b/tests/avocado/machine_aarch64_virt.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/machine_aarch64_virt.py
+++ b/tests/avocado/machine_aarch64_virt.py
@@ -XXX,XX +XXX,XX @@
 
 import time
 import os
+import logging
 
 from avocado_qemu import QemuSystemTest
 from avocado_qemu import wait_for_console_pattern
 from avocado_qemu import exec_command
 from avocado_qemu import BUILD_DIR
+from avocado.utils import process
+from avocado.utils.path import find_command
 
 class Aarch64VirtMachine(QemuSystemTest):
     KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
@@ -XXX,XX +XXX,XX @@ def test_alpine_virt_tcg_gic_max(self):
         self.wait_for_console_pattern('Welcome to Alpine Linux 3.16')
 
 
-    def test_aarch64_virt(self):
+    def common_aarch64_virt(self, machine):
         """
-        :avocado: tags=arch:aarch64
-        :avocado: tags=machine:virt
-        :avocado: tags=accel:tcg
-        :avocado: tags=cpu:max
+        Common code to launch basic virt machine with kernel+initrd
+        and a scratch disk.
         """
+        logger = logging.getLogger('aarch64_virt')
+
         kernel_url = ('https://fileserver.linaro.org/s/'
                       'z6B2ARM7DQT3HWN/download')
-
         kernel_hash = 'ed11daab50c151dde0e1e9c9cb8b2d9bd3215347'
         kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
 
@@ -XXX,XX +XXX,XX @@ def test_aarch64_virt(self):
                                'console=ttyAMA0')
         self.require_accelerator("tcg")
         self.vm.add_args('-cpu', 'max,pauth-impdef=on',
+                         '-machine', machine,
                          '-accel', 'tcg',
                          '-kernel', kernel_path,
                          '-append', kernel_command_line)
+
+        # A RNG offers an easy way to generate a few IRQs
+        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
+        self.vm.add_args('-object',
+                         'rng-random,id=rng0,filename=/dev/urandom')
+
+        # Also add a scratch block device
+        logger.info('creating scratch qcow2 image')
+        image_path = os.path.join(self.workdir, 'scratch.qcow2')
+        qemu_img = os.path.join(BUILD_DIR, 'qemu-img')
+        if not os.path.exists(qemu_img):
+            qemu_img = find_command('qemu-img', False)
+        if qemu_img is False:
+            self.cancel('Could not find "qemu-img", which is required to '
+                        'create the temporary qcow2 image')
+        cmd = '%s create -f qcow2 %s 8M' % (qemu_img, image_path)
+        process.run(cmd)
+
+        # Add the device
+        self.vm.add_args('-blockdev',
+                         f"driver=qcow2,file.driver=file,file.filename={image_path},node-name=scratch")
+        self.vm.add_args('-device',
+                         'virtio-blk-device,drive=scratch')
+
         self.vm.launch()
         self.wait_for_console_pattern('Welcome to Buildroot')
         time.sleep(0.1)
         exec_command(self, 'root')
         time.sleep(0.1)
+        exec_command(self, 'dd if=/dev/hwrng of=/dev/vda bs=512 count=4')
+        time.sleep(0.1)
+        exec_command(self, 'md5sum /dev/vda')
+        time.sleep(0.1)
+        exec_command(self, 'cat /proc/interrupts')
+        time.sleep(0.1)
         exec_command(self, 'cat /proc/self/maps')
         time.sleep(0.1)
+
+    def test_aarch64_virt_gicv3(self):
+        """
+        :avocado: tags=arch:aarch64
+        :avocado: tags=machine:virt
+        :avocado: tags=accel:tcg
+        :avocado: tags=cpu:max
+        """
+        self.common_aarch64_virt("virt,gic_version=3")
+
+    def test_aarch64_virt_gicv2(self):
+        """
+        :avocado: tags=arch:aarch64
+        :avocado: tags=machine:virt
+        :avocado: tags=accel:tcg
+        :avocado: tags=cpu:max
+        """
+        self.common_aarch64_virt("virt,gic-version=2")
-- 
2.34.1

From: Mostafa Saleh <smostafa@google.com>

GBPA register can be used to globally abort all
transactions.

It is described in the SMMU manual in "6.3.14 SMMU_GBPA".
ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to
be zero(Do not abort incoming transactions).

Other fields have default values of Use Incoming.

If UPDATE is not set, the write is ignored. This is the only permitted
behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure)

As this patch adds a new state to the SMMU (GBPA), it is added
in a new subsection for forward migration compatibility.
GBPA is only migrated if its value is different from the reset value.
It does this to be backward migration compatible if SW didn't write
the register.

Signed-off-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230214094009.2445653-1-smostafa@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/smmuv3-internal.h |  7 +++++++
 include/hw/arm/smmuv3.h  |  1 +
 hw/arm/smmuv3.c          | 43 +++++++++++++++++++++++++++++++++++++++-
 3 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -XXX,XX +XXX,XX @@ REG32(CR0ACK,              0x24)
 REG32(CR1,                 0x28)
 REG32(CR2,                 0x2c)
 REG32(STATUSR,             0x40)
+REG32(GBPA,                0x44)
+    FIELD(GBPA, ABORT,        20, 1)
+    FIELD(GBPA, UPDATE,       31, 1)
+
+/* Use incoming. */
+#define SMMU_GBPA_RESET_VAL 0x1000
+
 REG32(IRQ_CTRL,            0x50)
     FIELD(IRQ_CTRL, GERROR_IRQEN,        0, 1)
     FIELD(IRQ_CTRL, PRI_IRQEN,           1, 1)
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/smmuv3.h
+++ b/include/hw/arm/smmuv3.h
@@ -XXX,XX +XXX,XX @@ struct SMMUv3State {
     uint32_t cr[3];
     uint32_t cr0ack;
     uint32_t statusr;
+    uint32_t gbpa;
     uint32_t irq_ctrl;
     uint32_t gerror;
     uint32_t gerrorn;
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
     s->gerror = 0;
     s->gerrorn = 0;
     s->statusr = 0;
+    s->gbpa = SMMU_GBPA_RESET_VAL;
 }
 
 static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
     qemu_mutex_lock(&s->mutex);
 
     if (!smmu_enabled(s)) {
-        status = SMMU_TRANS_DISABLE;
+        if (FIELD_EX32(s->gbpa, GBPA, ABORT)) {
+            status = SMMU_TRANS_ABORT;
+        } else {
+            status = SMMU_TRANS_DISABLE;
+        }
         goto epilogue;
     }
 
@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,
     case A_GERROR_IRQ_CFG2:
         s->gerror_irq_cfg2 = data;
         return MEMTX_OK;
+    case A_GBPA:
+        /*
+         * If UPDATE is not set, the write is ignored. This is the only
+         * permitted behavior in SMMUv3.2 and later.
+         */
+        if (data & R_GBPA_UPDATE_MASK) {
+            /* Ignore update bit as write is synchronous. */
+            s->gbpa = data & ~R_GBPA_UPDATE_MASK;
+        }
+        return MEMTX_OK;
     case A_STRTAB_BASE: /* 64b */
         s->strtab_base = deposit64(s->strtab_base, 0, 32, data);
         return MEMTX_OK;
@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset,
     case A_STATUSR:
         *data = s->statusr;
         return MEMTX_OK;
+    case A_GBPA:
+        *data = s->gbpa;
+        return MEMTX_OK;
     case A_IRQ_CTRL:
     case A_IRQ_CTRL_ACK:
         *data = s->irq_ctrl;
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3_queue = {
     },
 };
 
+static bool smmuv3_gbpa_needed(void *opaque)
+{
+    SMMUv3State *s = opaque;
+
+    /* Only migrate GBPA if it has different reset value. */
+    return s->gbpa != SMMU_GBPA_RESET_VAL;
+}
+
+static const VMStateDescription vmstate_gbpa = {
+    .name = "smmuv3/gbpa",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = smmuv3_gbpa_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(gbpa, SMMUv3State),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static const VMStateDescription vmstate_smmuv3 = {
     .name = "smmuv3",
     .version_id = 1,
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = {
 
         VMSTATE_END_OF_LIST(),
     },
+    .subsections = (const VMStateDescription * []) {
+        &vmstate_gbpa,
+        NULL
+    }
 };
 
 static void smmuv3_instance_init(Object *obj)
-- 
2.34.1

From: Cornelia Huck <cohuck@redhat.com>

Just use current_accel_name() directly.

Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
     if (vms->secure && (kvm_enabled() || hvf_enabled())) {
         error_report("mach-virt: %s does not support providing "
                      "Security extensions (TrustZone) to the guest CPU",
-                     kvm_enabled() ? "KVM" : "HVF");
+                     current_accel_name());
         exit(1);
     }
 
     if (vms->virt && (kvm_enabled() || hvf_enabled())) {
         error_report("mach-virt: %s does not support providing "
                      "Virtualization extensions to the guest CPU",
-                     kvm_enabled() ? "KVM" : "HVF");
+                     current_accel_name());
         exit(1);
     }
 
     if (vms->mte && (kvm_enabled() || hvf_enabled())) {
         error_report("mach-virt: %s does not support providing "
                      "MTE to the guest CPU",
-                     kvm_enabled() ? "KVM" : "HVF");
+                     current_accel_name());
         exit(1);
     }
 
-- 
2.34.1

From: Hao Wu <wuhaotsh@google.com>

Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices.

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Chris Rauer <crauer@google.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
Message-id: 20230208235433.3989937-3-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 MAINTAINERS                |   6 +-
 include/hw/ssi/npcm_pspi.h |  53 +++++++++
 hw/ssi/npcm_pspi.c         | 221 +++++++++++++++++++++++++++++++++++++
 hw/ssi/meson.build         |   2 +-
 hw/ssi/trace-events        |   5 +
 5 files changed, 283 insertions(+), 4 deletions(-)
 create mode 100644 include/hw/ssi/npcm_pspi.h
 create mode 100644 hw/ssi/npcm_pspi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Tyrone Ting <kfting@nuvoton.com>
 M: Hao Wu <wuhaotsh@google.com>
 L: qemu-arm@nongnu.org
 S: Supported
-F: hw/*/npcm7xx*
-F: include/hw/*/npcm7xx*
-F: tests/qtest/npcm7xx*
+F: hw/*/npcm*
+F: include/hw/*/npcm*
+F: tests/qtest/npcm*
 F: pc-bios/npcm7xx_bootrom.bin
 F: roms/vbootrom
 F: docs/system/arm/nuvoton.rst
diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/ssi/npcm_pspi.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton Peripheral SPI Module
+ *
+ * Copyright 2023 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM_PSPI_H
+#define NPCM_PSPI_H
+
+#include "hw/ssi/ssi.h"
+#include "hw/sysbus.h"
+
+/*
+ * Number of registers in our device state structure. Don't change this without
+ * incrementing the version_id in the vmstate.
+ */
+#define NPCM_PSPI_NR_REGS 3
+
+/**
+ * NPCMPSPIState - Device state for one Flash Interface Unit.
+ * @parent: System bus device.
+ * @mmio: Memory region for register access.
+ * @spi: The SPI bus mastered by this controller.
+ * @regs: Register contents.
+ * @irq: The interrupt request queue for this module.
+ *
+ * Each PSPI has a shared bank of registers, and controls up to four chip
+ * selects. Each chip select has a dedicated memory region which may be used to
+ * read and write the flash connected to that chip select as if it were memory.
+ */
+typedef struct NPCMPSPIState {
+    SysBusDevice parent;
+
+    MemoryRegion mmio;
+
+    SSIBus *spi;
+    uint16_t regs[NPCM_PSPI_NR_REGS];
+    qemu_irq irq;
+} NPCMPSPIState;
+
+#define TYPE_NPCM_PSPI "npcm-pspi"
+OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI)
+
+#endif /* NPCM_PSPI_H */
diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/ssi/npcm_pspi.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM Peripheral SPI Module (PSPI)
+ *
+ * Copyright 2023 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/irq.h"
+#include "hw/registerfields.h"
+#include "hw/ssi/npcm_pspi.h"
+#include "migration/vmstate.h"
+#include "qapi/error.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+
+#include "trace.h"
+
+REG16(PSPI_DATA, 0x0)
+REG16(PSPI_CTL1, 0x2)
+    FIELD(PSPI_CTL1, SPIEN, 0,  1)
+    FIELD(PSPI_CTL1, MOD,   2,  1)
+    FIELD(PSPI_CTL1, EIR,   5,  1)
+    FIELD(PSPI_CTL1, EIW,   6,  1)
+    FIELD(PSPI_CTL1, SCM,   7,  1)
+    FIELD(PSPI_CTL1, SCIDL, 8,  1)
+    FIELD(PSPI_CTL1, SCDV,  9,  7)
+REG16(PSPI_STAT, 0x4)
+    FIELD(PSPI_STAT, BSY,  0,  1)
+    FIELD(PSPI_STAT, RBF,  1,  1)
+
+static void npcm_pspi_update_irq(NPCMPSPIState *s)
+{
+    int level = 0;
+
+    /* Only fire IRQ when the module is enabled. */
+    if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) {
+        /* Update interrupt as BSY is cleared. */
+        if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) &&
+            FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) {
+            level = 1;
+        }
+
+        /* Update interrupt as RBF is set. */
+        if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) &&
+            FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) {
+            level = 1;
+        }
+    }
+    qemu_set_irq(s->irq, level);
+}
+
+static uint16_t npcm_pspi_read_data(NPCMPSPIState *s)
+{
+    uint16_t value = s->regs[R_PSPI_DATA];
+
+    /* Clear stat bits as the value are read out. */
+    s->regs[R_PSPI_STAT] = 0;
+
+    return value;
+}
+
+static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data)
+{
+    uint16_t value = 0;
+
+    if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) {
+        value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8;
+    }
+    value |= ssi_transfer(s->spi, extract16(data, 0, 8));
+    s->regs[R_PSPI_DATA] = value;
+
+    /* Mark data as available */
+    s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK;
+}
+
+/* Control register read handler. */
+static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr,
+                                    unsigned int size)
+{
+    NPCMPSPIState *s = opaque;
+    uint16_t value;
+
+    switch (addr) {
+    case A_PSPI_DATA:
+        value = npcm_pspi_read_data(s);
+        break;
+
+    case A_PSPI_CTL1:
+        value = s->regs[R_PSPI_CTL1];
+        break;
+
+    case A_PSPI_STAT:
+        value = s->regs[R_PSPI_STAT];
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: write to invalid offset 0x%" PRIx64 "\n",
+                      DEVICE(s)->canonical_path, addr);
+        return 0;
+    }
+    trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value);
+    npcm_pspi_update_irq(s);
+
+    return value;
+}
+
+/* Control register write handler. */
+static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v,
+                                 unsigned int size)
+{
+    NPCMPSPIState *s = opaque;
+    uint16_t value = v;
+
+    trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value);
+
+    switch (addr) {
+    case A_PSPI_DATA:
+        npcm_pspi_write_data(s, value);
+        break;
+
+    case A_PSPI_CTL1:
+        s->regs[R_PSPI_CTL1] = value;
+        break;
+
+    case A_PSPI_STAT:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: write to read-only register PSPI_STAT: 0x%08"
+                      PRIx64 "\n", DEVICE(s)->canonical_path, v);
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: write to invalid offset 0x%" PRIx64 "\n",
+                      DEVICE(s)->canonical_path, addr);
+        return;
+    }
+    npcm_pspi_update_irq(s);
+}
+
+static const MemoryRegionOps npcm_pspi_ctrl_ops = {
+    .read = npcm_pspi_ctrl_read,
+    .write = npcm_pspi_ctrl_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 1,
+        .max_access_size = 2,
+        .unaligned = false,
+    },
+    .impl = {
+        .min_access_size = 2,
+        .max_access_size = 2,
+        .unaligned = false,
+    },
+};
+
+static void npcm_pspi_enter_reset(Object *obj, ResetType type)
+{
+    NPCMPSPIState *s = NPCM_PSPI(obj);
+
+    trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type);
+    memset(s->regs, 0, sizeof(s->regs));
+}
+
+static void npcm_pspi_realize(DeviceState *dev, Error **errp)
+{
+    NPCMPSPIState *s = NPCM_PSPI(dev);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+    Object *obj = OBJECT(dev);
+
+    s->spi = ssi_create_bus(dev, "pspi");
+    memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s,
+                          "mmio", 4 * KiB);
+    sysbus_init_mmio(sbd, &s->mmio);
+    sysbus_init_irq(sbd, &s->irq);
+}
+
+static const VMStateDescription vmstate_npcm_pspi = {
+    .name = "npcm-pspi",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+
+static void npcm_pspi_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM Peripheral SPI Module";
+    dc->realize = npcm_pspi_realize;
+    dc->vmsd = &vmstate_npcm_pspi;
+    rc->phases.enter = npcm_pspi_enter_reset;
+}
+
+static const TypeInfo npcm_pspi_types[] = {
+    {
+        .name = TYPE_NPCM_PSPI,
+        .parent = TYPE_SYS_BUS_DEVICE,
+        .instance_size = sizeof(NPCMPSPIState),
+        .class_init = npcm_pspi_class_init,
+    },
+};
+DEFINE_TYPES(npcm_pspi_types);
diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/meson.build
+++ b/hw/ssi/meson.build
@@ -XXX,XX +XXX,XX @@
 softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c'))
 softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c'))
-softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c'))
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'npcm_pspi.c'))
 softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c'))
 softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c'))
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/trace-events
+++ b/hw/ssi/trace-events
@@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset:
 npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
 npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
 
+# npcm_pspi.c
+npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d"
+npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
+npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
+
 # ibex_spi_host.c
 
 ibex_spi_host_reset(const char *msg) "%s"
-- 
2.34.1

From: Hao Wu <wuhaotsh@google.com>

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
Message-id: 20230208235433.3989937-4-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/nuvoton.rst |  2 +-
 include/hw/arm/npcm7xx.h    |  2 ++
 hw/arm/npcm7xx.c            | 25 +++++++++++++++++++++++--
 3 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@ Supported devices
  * SMBus controller (SMBF)
  * Ethernet controller (EMC)
  * Tachometer
+ * Peripheral SPI controller (PSPI)
 
 Missing devices
 ---------------
@@ -XXX,XX +XXX,XX @@ Missing devices
 
  * Ethernet controller (GMAC)
  * USB device (USBD)
- * Peripheral SPI controller (PSPI)
  * SD/MMC host
  * PECI interface
  * PCI and PCIe root complex and bridges
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/nvram/npcm7xx_otp.h"
 #include "hw/timer/npcm7xx_timer.h"
 #include "hw/ssi/npcm7xx_fiu.h"
+#include "hw/ssi/npcm_pspi.h"
 #include "hw/usb/hcd-ehci.h"
 #include "hw/usb/hcd-ohci.h"
 #include "target/arm/cpu.h"
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxState {
     NPCM7xxFIUState     fiu[2];
     NPCM7xxEMCState     emc[2];
     NPCM7xxSDHCIState   mmc;
+    NPCMPSPIState       pspi[2];
 };
 
 #define TYPE_NPCM7XX    "npcm7xx"
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
     NPCM7XX_EMC1RX_IRQ          = 15,
     NPCM7XX_EMC1TX_IRQ,
     NPCM7XX_MMC_IRQ             = 26,
+    NPCM7XX_PSPI2_IRQ           = 28,
+    NPCM7XX_PSPI1_IRQ           = 31,
     NPCM7XX_TIMER0_IRQ          = 32,   /* Timer Module 0 */
     NPCM7XX_TIMER1_IRQ,
     NPCM7XX_TIMER2_IRQ,
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_emc_addr[] = {
     0xf0826000,
 };
 
+/* Register base address for each PSPI Module */
+static const hwaddr npcm7xx_pspi_addr[] = {
+    0xf0200000,
+    0xf0201000,
+};
+
 static const struct {
     hwaddr regs_addr;
     uint32_t unconnected_pins;
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
         object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC);
     }
 
+    for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
+        object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI);
+    }
+
     object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
 }
 
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0,
             npcm7xx_irq(s, NPCM7XX_MMC_IRQ));
 
+    /* PSPI */
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi));
+    for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
+        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]);
+        int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ;
+
+        sysbus_realize(sbd, &error_abort);
+        sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]);
+        sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq));
+    }
+
     create_unimplemented_device("npcm7xx.shm",          0xc0001000,   4 * KiB);
     create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
     create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
     create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
     create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.pspi1",        0xf0200000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.pspi2",        0xf0201000,   4 * KiB);
     create_unimplemented_device("npcm7xx.ahbpci",       0xf0400000,   1 * MiB);
     create_unimplemented_device("npcm7xx.mcphy",        0xf05f0000,  64 * KiB);
     create_unimplemented_device("npcm7xx.gmac1",        0xf0802000,   8 * KiB);
-- 
2.34.1

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

Addresses targeting the second translation table (TTB1) in the SMMU have
all upper bits set. Ensure the IOMMU region covers all 64 bits.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230214171921.1917916-2-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/smmu-common.h | 2 --
 hw/arm/smmu-common.c         | 2 +-
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -XXX,XX +XXX,XX @@
 #define SMMU_PCI_DEVFN_MAX    256
 #define SMMU_PCI_DEVFN(sid)   (sid & 0xFF)
 
-#define SMMU_MAX_VA_BITS      48
-
 /*
  * Page table walk error types
  */
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn)
 
         memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu),
                                  s->mrtypename,
-                                 OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS);
+                                 OBJECT(s), name, UINT64_MAX);
         address_space_init(&sdev->as,
                            MEMORY_REGION(&sdev->iommu), name);
         trace_smmu_add_mr(name);
-- 
2.34.1

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

Addresses targeting the second translation table (TTB1) in the SMMU have
all upper bits set (except for the top byte when TBI is enabled). Fix
the TTB1 check.

Reported-by: Ola Hugosson <ola.hugosson@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230214171921.1917916-3-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/smmu-common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
         /* there is a ttbr0 region and we are in it (high bits all zero) */
         return &cfg->tt[0];
     } else if (cfg->tt[1].tsz &&
-           !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) {
+        sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) {
         /* there is a ttbr1 region and we are in it (high bits all one) */
         return &cfg->tt[1];
     } else if (!cfg->tt[0].tsz) {
-- 
2.34.1

From: Claudio Fontana <cfontana@suse.de>

make it clearer from the name that this is a tcg-only function.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
  * trapped to the hypervisor in KVM.
  */
 #ifdef CONFIG_TCG
-static void handle_semihosting(CPUState *cs)
+static void tcg_handle_semihosting(CPUState *cs)
 {
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
      */
 #ifdef CONFIG_TCG
     if (cs->exception_index == EXCP_SEMIHOST) {
-        handle_semihosting(cs);
+        tcg_handle_semihosting(cs);
         return;
     }
 #endif
-- 
2.34.1

From: Claudio Fontana <cfontana@suse.de>

for "all" builds (tcg + kvm), we want to avoid doing
the psci check if tcg is built-in, but not enabled.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/irq.h"
 #include "sysemu/cpu-timers.h"
 #include "sysemu/kvm.h"
+#include "sysemu/tcg.h"
 #include "qapi/qapi-commands-machine-target.h"
 #include "qapi/error.h"
 #include "qemu/guest-random.h"
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
                       env->exception.syndrome);
     }
 
-    if (arm_is_psci_call(cpu, cs->exception_index)) {
+    if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) {
         arm_handle_psci_call(cpu);
         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
         return;
-- 
2.34.1

From: Claudio Fontana <cfontana@suse.de>

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
     unsigned int cur_el = arm_current_el(env);
     int rt;
 
-    /*
-     * Note that new_el can never be 0.  If cur_el is 0, then
-     * el0_a64 is is_a64(), else el0_a64 is ignored.
-     */
-    aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
+    if (tcg_enabled()) {
+        /*
+         * Note that new_el can never be 0.  If cur_el is 0, then
+         * el0_a64 is is_a64(), else el0_a64 is ignored.
+         */
+        aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
+    }
 
     if (cur_el < new_el) {
         /*
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

Move this earlier to make the next patch diff cleaner. While here
update the comment slightly to not give the impression that the
misalignment affects only TCG.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/machine.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/target/arm/machine.c b/target/arm/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
         }
     }
 
+    /*
+     * Misaligned thumb pc is architecturally impossible. Fail the
+     * incoming migration. For TCG it would trigger the assert in
+     * thumb_tr_translate_insn().
+     */
+    if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
+        return -1;
+    }
+
     hw_breakpoint_update_all(cpu);
     hw_watchpoint_update_all(cpu);
 
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
         }
     }
 
-    /*
-     * Misaligned thumb pc is architecturally impossible.
-     * We have an assert in thumb_tr_translate_insn to verify this.
-     * Fail an incoming migrate to avoid this assert.
-     */
-    if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
-        return -1;
-    }
-
     if (!kvm_enabled()) {
         pmu_op_finish(&cpu->env);
     }
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have
a cpregs.h header which is more suitable for this code.

Code moved verbatim.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h | 98 +++++++++++++++++++++++++++++++++++++++++++++
 target/arm/cpu.h    | 91 -----------------------------------------
 2 files changed, 98 insertions(+), 91 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
     ARM_CP_SME                   = 1 << 19,
 };
 
+/*
+ * Interface for defining coprocessor registers.
+ * Registers are defined in tables of arm_cp_reginfo structs
+ * which are passed to define_arm_cp_regs().
+ */
+
+/*
+ * When looking up a coprocessor register we look for it
+ * via an integer which encodes all of:
+ *  coprocessor number
+ *  Crn, Crm, opc1, opc2 fields
+ *  32 or 64 bit register (ie is it accessed via MRC/MCR
+ *    or via MRRC/MCRR?)
+ *  non-secure/secure bank (AArch32 only)
+ * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
+ * (In this case crn and opc2 should be zero.)
+ * For AArch64, there is no 32/64 bit size distinction;
+ * instead all registers have a 2 bit op0, 3 bit op1 and op2,
+ * and 4 bit CRn and CRm. The encoding patterns are chosen
+ * to be easy to convert to and from the KVM encodings, and also
+ * so that the hashtable can contain both AArch32 and AArch64
+ * registers (to allow for interprocessing where we might run
+ * 32 bit code on a 64 bit core).
+ */
+/*
+ * This bit is private to our hashtable cpreg; in KVM register
+ * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
+ * in the upper bits of the 64 bit ID.
+ */
+#define CP_REG_AA64_SHIFT 28
+#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
+
+/*
+ * To enable banking of coprocessor registers depending on ns-bit we
+ * add a bit to distinguish between secure and non-secure cpregs in the
+ * hashtable.
+ */
+#define CP_REG_NS_SHIFT 29
+#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
+
+#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
+    ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
+     ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
+
+#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
+    (CP_REG_AA64_MASK |                                 \
+     ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
+     ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
+     ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
+     ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
+     ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
+     ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
+
+/*
+ * Convert a full 64 bit KVM register ID to the truncated 32 bit
+ * version used as a key for the coprocessor register hashtable
+ */
+static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
+{
+    uint32_t cpregid = kvmid;
+    if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
+        cpregid |= CP_REG_AA64_MASK;
+    } else {
+        if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
+            cpregid |= (1 << 15);
+        }
+
+        /*
+         * KVM is always non-secure so add the NS flag on AArch32 register
+         * entries.
+         */
+         cpregid |= 1 << CP_REG_NS_SHIFT;
+    }
+    return cpregid;
+}
+
+/*
+ * Convert a truncated 32 bit hashtable key into the full
+ * 64 bit KVM register ID.
+ */
+static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
+{
+    uint64_t kvmid;
+
+    if (cpregid & CP_REG_AA64_MASK) {
+        kvmid = cpregid & ~CP_REG_AA64_MASK;
+        kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
+    } else {
+        kvmid = cpregid & ~(1 << 15);
+        if (cpregid & (1 << 15)) {
+            kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
+        } else {
+            kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
+        }
+    }
+    return kvmid;
+}
+
 /*
  * Valid values for ARMCPRegInfo state field, indicating which of
  * the AArch32 and AArch64 execution states this register is visible in.
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                  uint32_t cur_el, bool secure);
 
-/* Interface for defining coprocessor registers.
- * Registers are defined in tables of arm_cp_reginfo structs
- * which are passed to define_arm_cp_regs().
- */
-
-/* When looking up a coprocessor register we look for it
- * via an integer which encodes all of:
- *  coprocessor number
- *  Crn, Crm, opc1, opc2 fields
- *  32 or 64 bit register (ie is it accessed via MRC/MCR
- *    or via MRRC/MCRR?)
- *  non-secure/secure bank (AArch32 only)
- * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
- * (In this case crn and opc2 should be zero.)
- * For AArch64, there is no 32/64 bit size distinction;
- * instead all registers have a 2 bit op0, 3 bit op1 and op2,
- * and 4 bit CRn and CRm. The encoding patterns are chosen
- * to be easy to convert to and from the KVM encodings, and also
- * so that the hashtable can contain both AArch32 and AArch64
- * registers (to allow for interprocessing where we might run
- * 32 bit code on a 64 bit core).
- */
-/* This bit is private to our hashtable cpreg; in KVM register
- * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
- * in the upper bits of the 64 bit ID.
- */
-#define CP_REG_AA64_SHIFT 28
-#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
-
-/* To enable banking of coprocessor registers depending on ns-bit we
- * add a bit to distinguish between secure and non-secure cpregs in the
- * hashtable.
- */
-#define CP_REG_NS_SHIFT 29
-#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
-
-#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
-    ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
-     ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
-
-#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
-    (CP_REG_AA64_MASK |                                 \
-     ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
-     ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
-     ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
-     ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
-     ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
-     ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
-
-/* Convert a full 64 bit KVM register ID to the truncated 32 bit
- * version used as a key for the coprocessor register hashtable
- */
-static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
-{
-    uint32_t cpregid = kvmid;
-    if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
-        cpregid |= CP_REG_AA64_MASK;
-    } else {
-        if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
-            cpregid |= (1 << 15);
-        }
-
-        /* KVM is always non-secure so add the NS flag on AArch32 register
-         * entries.
-         */
-         cpregid |= 1 << CP_REG_NS_SHIFT;
-    }
-    return cpregid;
-}
-
-/* Convert a truncated 32 bit hashtable key into the full
- * 64 bit KVM register ID.
- */
-static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
-{
-    uint64_t kvmid;
-
-    if (cpregid & CP_REG_AA64_MASK) {
-        kvmid = cpregid & ~CP_REG_AA64_MASK;
-        kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
-    } else {
-        kvmid = cpregid & ~(1 << 15);
-        if (cpregid & (1 << 15)) {
-            kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
-        } else {
-            kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
-        }
-    }
-    return kvmid;
-}
-
 /* Return the highest implemented Exception Level */
 static inline int arm_highest_el(CPUARMState *env)
 {
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

If a test was tagged with the "accel" tag and the specified
accelerator it not present in the qemu binary, cancel the test.

We can now write tests without explicit calls to require_accelerator,
just the tag is enough.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/avocado/avocado_qemu/__init__.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tests/avocado/avocado_qemu/__init__.py b/tests/avocado/avocado_qemu/__init__.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/avocado_qemu/__init__.py
+++ b/tests/avocado/avocado_qemu/__init__.py
@@ -XXX,XX +XXX,XX @@ def setUp(self):
 
         super().setUp('qemu-system-')
 
+        accel_required = self._get_unique_tag_val('accel')
+        if accel_required:
+            self.require_accelerator(accel_required)
+
         self.machine = self.params.get('machine',
                                        default=self._get_unique_tag_val('machine'))
 
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

This allows the test to be skipped when TCG is not present in the QEMU
binary.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/avocado/boot_linux_console.py | 1 +
 tests/avocado/reverse_debugging.py  | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_uboot_netbsd9(self):
 
     def test_aarch64_raspi3_atf(self):
         """
+        :avocado: tags=accel:tcg
         :avocado: tags=arch:aarch64
         :avocado: tags=machine:raspi3b
         :avocado: tags=cpu:cortex-a53
diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/reverse_debugging.py
+++ b/tests/avocado/reverse_debugging.py
@@ -XXX,XX +XXX,XX @@ def reverse_debugging(self, shift=7, args=None):
         vm.shutdown()
 
 class ReverseDebugging_X86_64(ReverseDebugging):
+    """
+    :avocado: tags=accel:tcg
+    """
+
     REG_PC = 0x10
     REG_CS = 0x12
     def get_pc(self, g):
@@ -XXX,XX +XXX,XX @@ def test_x86_64_pc(self):
         self.reverse_debugging()
 
 class ReverseDebugging_AArch64(ReverseDebugging):
+    """
+    :avocado: tags=accel:tcg
+    """
+
     REG_PC = 32
 
     # unidentified gitlab timeout problem
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a
KVM-only build the 'max' cpu.

Note that we cannot use 'host' here because the qtests can run without
any other accelerator (than qtest) and 'host' depends on KVM being
enabled.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     mc->minimum_page_bits = 12;
     mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
     mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
+#ifdef CONFIG_TCG
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
+#else
+    mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
+#endif
     mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
     mc->kvm_type = virt_kvm_type;
     assert(!mc->get_hotplug_handler);
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/arm-cpu-features.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@
 #define SVE_MAX_VQ 16
 
 #define MACHINE     "-machine virt,gic-version=max -accel tcg "
-#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg "
+#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm "
 #define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
                     "  'arguments': { 'type': 'full', "
 #define QUERY_TAIL  "}}"
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
 {
     g_test_init(&argc, &argv, NULL);
 
-    qtest_add_data_func("/arm/query-cpu-model-expansion",
-                        NULL, test_query_cpu_model_expansion);
+    if (qtest_has_accel("tcg")) {
+        qtest_add_data_func("/arm/query-cpu-model-expansion",
+                            NULL, test_query_cpu_model_expansion);
+    }
+
+    if (!g_str_equal(qtest_get_arch(), "aarch64")) {
+        goto out;
+    }
 
     /*
      * For now we only run KVM specific tests with AArch64 QEMU in
      * order avoid attempting to run an AArch32 QEMU with KVM on
      * AArch64 hosts. That won't work and isn't easy to detect.
      */
-    if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) {
+    if (qtest_has_accel("kvm")) {
         /*
          * This tests target the 'host' CPU type, so register it only if
          * KVM is available.
          */
         qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
                             NULL, test_query_cpu_model_expansion_kvm);
-    }
 
-    if (g_str_equal(qtest_get_arch(), "aarch64")) {
-        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
-                            NULL, sve_tests_sve_max_vq_8);
-        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
-                            NULL, sve_tests_sve_off);
         qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
                             NULL, sve_tests_sve_off_kvm);
     }
 
+    if (qtest_has_accel("tcg")) {
+        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
+                            NULL, sve_tests_sve_max_vq_8);
+        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
+                            NULL, sve_tests_sve_off);
+    }
+
+out:
     return g_test_run();
 }
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

These tests set -accel tcg, so restrict them to when TCG is present.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/meson.build | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_arm = \
 # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional
 qtests_aarch64 = \
   (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) +                            \
-  (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) +        \
-  (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) +  \
+  (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ?            \
+    ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) +                                         \
   (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \
   (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) +  \
   ['arm-cpu-features',
-- 
2.34.1