[PULL 00/10] target-arm queue
[PULL v2 00/11] target-arm queue
1
Hi; not so many patches in this one, but notably it includes the
1
Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
2
fix for various Avocado CI tests failing (incorrectly reported by
2
ethernet device failed 'make check' on big-endian hosts.
3
Avocado as a timeout, but really a QEMU exit-with-error).
4
3
5
thanks
6
-- PMM
4
-- PMM
7
5
8
The following changes since commit c8de6ec63d766ca1998c5af468483ce912fdc0c2:
6
The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:
9
7
10
Merge tag 'pull-request-2022-09-28' of https://gitlab.com/thuth/qemu into staging (2022-09-28 17:04:11 -0400)
8
Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)
11
9
12
are available in the Git repository at:
10
are available in the Git repository at:
13
11
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220930
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1
15
13
16
for you to fetch changes up to beeec926d24aac28f95cc7694ef3837d7a4cd3bb:
14
for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:
17
15
18
target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP (2022-09-29 18:01:09 +0100)
16
target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)
19
17
20
----------------------------------------------------------------
18
----------------------------------------------------------------
21
target-arm queue:
19
target-arm queue:
22
* Fix breakage of icount mode when guest touches MDCR_EL3, MDCR_EL2,
20
* Correctly initialize MDCR_EL2.HPMN
23
PMCNTENSET_EL0 or PMCNTENCLR_EL0
21
* versal: Use nr_apu_cpus in favor of hard coding 2
24
* Make writes to MDCR_EL3 use PMU start/finish calls
22
* accel/tcg: Add URL of clang bug to comment about our workaround
25
* Let AArch32 write to SDCR.SCCD
23
* Add support for FEAT_DIT, Data Independent Timing
26
* Rearrange cpu64.c so all the CPU initfns are together
24
* Remove GPIO from unimplemented NPCM7XX
27
* hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
25
* Fix SCR RES1 handling
28
* hw/arm/virt: fix some minor issues with generated device tree
26
* Don't migrate CPUARMState.features
29
* Fix regression where EL3 could not write to SP_EL1 if there is no EL2
30
27
31
----------------------------------------------------------------
28
----------------------------------------------------------------
32
Francisco Iglesias (1):
29
Aaron Lindsay (1):
33
hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
30
target/arm: Don't migrate CPUARMState.features
34
31
35
Jean-Philippe Brucker (4):
32
Daniel Müller (1):
36
hw/arm/virt: Fix devicetree warning about the root node
33
target/arm: Correctly initialize MDCR_EL2.HPMN
37
hw/arm/virt: Fix devicetree warning about the GIC node
38
hw/arm/virt: Use "msi-map" devicetree property for PCI
39
hw/arm/virt: Fix devicetree warning about the SMMU node
40
34
41
Jerome Forissier (1):
35
Edgar E. Iglesias (1):
42
target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP
36
hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
43
37
44
Peter Maydell (4):
38
Hao Wu (1):
45
target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO
39
hw/arm: Remove GPIO from unimplemented NPCM7XX
46
target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
47
target/arm: Update SDCR_VALID_MASK to include SCCD
48
target/arm: Rearrange cpu64.c so all the CPU initfns are together
49
40
50
include/hw/arm/xlnx-zynqmp.h | 3 +
41
Mike Nawrocki (1):
51
target/arm/cpu.h | 8 +-
42
target/arm: Fix SCR RES1 handling
52
hw/arm/virt.c | 8 +-
43
53
hw/arm/xlnx-zynqmp.c | 36 +++
44
Peter Maydell (2):
54
target/arm/cpu64.c | 712 +++++++++++++++++++++----------------------
45
arm: Update infocenter.arm.com URLs
55
target/arm/helper.c | 32 +-
46
accel/tcg: Add URL of clang bug to comment about our workaround
56
6 files changed, 427 insertions(+), 372 deletions(-)
47
48
Rebecca Cran (4):
49
target/arm: Add support for FEAT_DIT, Data Independent Timing
50
target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
51
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
52
target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
53
54
include/hw/dma/pl080.h | 7 ++--
55
include/hw/misc/arm_integrator_debug.h | 2 +-
56
include/hw/ssi/pl022.h | 5 ++-
57
target/arm/cpu.h | 17 ++++++++
58
target/arm/internals.h | 6 +++
59
accel/tcg/cpu-exec.c | 25 +++++++++---
60
hw/arm/aspeed_ast2600.c | 2 +-
61
hw/arm/musca.c | 4 +-
62
hw/arm/npcm7xx.c | 8 ----
63
hw/arm/xlnx-versal.c | 4 +-
64
hw/misc/arm_integrator_debug.c | 2 +-
65
hw/timer/arm_timer.c | 7 ++--
66
target/arm/cpu.c | 4 ++
67
target/arm/cpu64.c | 5 +++
68
target/arm/helper-a64.c | 27 +++++++++++--
69
target/arm/helper.c | 71 +++++++++++++++++++++++++++-------
70
target/arm/machine.c | 2 +-
71
target/arm/op_helper.c | 9 +----
72
target/arm/translate-a64.c | 12 ++++++
73
19 files changed, 164 insertions(+), 55 deletions(-)
74
diff view generated by jsdifflib
[PULL 01/10] target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO
Deleted patch
1
In commit 01765386a888 we made some system register write functions
2
call pmu_op_start()/pmu_op_finish(). This means that they now touch
3
timers, so for icount to work these registers must have the ARM_CP_IO
4
flag set.
5
1
6
This fixes a bug where when icount is enabled a guest that touches
7
MDCR_EL3, MDCR_EL2, PMCNTENSET_EL0 or PMCNTENCLR_EL0 would cause
8
QEMU to print an error message and exit, for example:
9
10
[ 2.495971] TCP: Hash tables configured (established 1024 bind 1024)
11
[ 2.496213] UDP hash table entries: 256 (order: 1, 8192 bytes)
12
[ 2.496386] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
13
[ 2.496917] NET: Registered protocol family 1
14
qemu-system-aarch64: Bad icount read
15
16
Reported-by: Thomas Huth <thuth@redhat.com>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20220923123412.1214041-2-peter.maydell@linaro.org
20
---
21
target/arm/helper.c | 12 ++++++------
22
1 file changed, 6 insertions(+), 6 deletions(-)
23
24
diff --git a/target/arm/helper.c b/target/arm/helper.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/helper.c
27
+++ b/target/arm/helper.c
28
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
29
* or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
30
*/
31
{ .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
32
- .access = PL0_RW, .type = ARM_CP_ALIAS,
33
+ .access = PL0_RW, .type = ARM_CP_ALIAS | ARM_CP_IO,
34
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
35
.writefn = pmcntenset_write,
36
.accessfn = pmreg_access,
37
.raw_writefn = raw_write },
38
- { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
39
+ { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
40
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
41
.access = PL0_RW, .accessfn = pmreg_access,
42
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
43
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
44
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
45
.accessfn = pmreg_access,
46
.writefn = pmcntenclr_write,
47
- .type = ARM_CP_ALIAS },
48
+ .type = ARM_CP_ALIAS | ARM_CP_IO },
49
{ .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
50
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
51
.access = PL0_RW, .accessfn = pmreg_access,
52
- .type = ARM_CP_ALIAS,
53
+ .type = ARM_CP_ALIAS | ARM_CP_IO,
54
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
55
.writefn = pmcntenclr_write },
56
{ .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
57
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
58
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
59
.resetvalue = 0,
60
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
61
- { .name = "SDCR", .type = ARM_CP_ALIAS,
62
+ { .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
63
.cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
64
.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
65
.writefn = sdcr_write,
66
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
67
* value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
68
*/
69
ARMCPRegInfo mdcr_el2 = {
70
- .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
71
+ .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, .type = ARM_CP_IO,
72
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
73
.writefn = mdcr_el2_write,
74
.access = PL2_RW, .resetvalue = pmu_num_counters(env),
75
--
76
2.25.1
diff view generated by jsdifflib
[PULL 02/10] target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
Deleted patch
1
In commit 01765386a88868 we fixed a bug where we weren't correctly
2
bracketing changes to some registers with pmu_op_start() and
3
pmu_op_finish() calls for changes which affect whether the PMU
4
counters might be enabled. However, we missed the case of writes to
5
the AArch64 MDCR_EL3 register, because (unlike its AArch32
6
counterpart) they are currently done directly to the CPU state struct
7
without going through the sdcr_write() function.
8
1
9
Give MDCR_EL3 a writefn which handles the PMU start/finish calls.
10
The SDCR writefn then simplfies to "call the MDCR_EL3 writefn after
11
masking off the bits which don't exist in the AArch32 register".
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20220923123412.1214041-3-peter.maydell@linaro.org
16
---
17
target/arm/helper.c | 18 ++++++++++++++----
18
1 file changed, 14 insertions(+), 4 deletions(-)
19
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper.c
23
+++ b/target/arm/helper.c
24
@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
25
}
26
}
27
28
-static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
29
- uint64_t value)
30
+static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
31
+ uint64_t value)
32
{
33
/*
34
* Some MDCR_EL3 bits affect whether PMU counters are running:
35
@@ -XXX,XX +XXX,XX @@ static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
36
if (pmu_op) {
37
pmu_op_start(env);
38
}
39
- env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
40
+ env->cp15.mdcr_el3 = value;
41
if (pmu_op) {
42
pmu_op_finish(env);
43
}
44
}
45
46
+static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
47
+ uint64_t value)
48
+{
49
+ /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
50
+ mdcr_el3_write(env, ri, value & SDCR_VALID_MASK);
51
+}
52
+
53
static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
54
uint64_t value)
55
{
56
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
57
.access = PL2_RW,
58
.fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
59
{ .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
60
+ .type = ARM_CP_IO,
61
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
62
.resetvalue = 0,
63
- .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
64
+ .access = PL3_RW,
65
+ .writefn = mdcr_el3_write,
66
+ .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
67
{ .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
68
.cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
69
.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
70
--
71
2.25.1
diff view generated by jsdifflib
[PULL 03/10] target/arm: Update SDCR_VALID_MASK to include SCCD
Deleted patch
1
Our SDCR_VALID_MASK doesn't include all of the bits which are defined
2
by the current architecture. In particular in commit 0b42f4fab9d3 we
3
forgot to add SCCD, which meant that an AArch32 guest couldn't
4
actually use the SCCD bit to disable counting in Secure state.
5
1
6
Add all the currently defined bits; we don't implement all of them,
7
but this makes them be reads-as-written, which is architecturally
8
valid and matches how we currently handle most of the others in the
9
mask.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20220923123412.1214041-4-peter.maydell@linaro.org
14
---
15
target/arm/cpu.h | 8 +++++++-
16
1 file changed, 7 insertions(+), 1 deletion(-)
17
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
21
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TTA, 20, 1)
23
FIELD(CPTR_EL3, TAM, 30, 1)
24
FIELD(CPTR_EL3, TCPAC, 31, 1)
25
26
+#define MDCR_MTPME (1U << 28)
27
+#define MDCR_TDCC (1U << 27)
28
#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
29
#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
30
#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
31
#define MDCR_EPMAD (1U << 21)
32
#define MDCR_EDAD (1U << 20)
33
+#define MDCR_TTRF (1U << 19)
34
+#define MDCR_STE (1U << 18) /* MDCR_EL3 */
35
#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
36
#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
37
#define MDCR_SDD (1U << 16)
38
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
39
#define MDCR_HPMN (0x1fU)
40
41
/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
42
-#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
43
+#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
44
+ MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
45
+ MDCR_STE | MDCR_SPME | MDCR_SPD)
46
47
#define CPSR_M (0x1fU)
48
#define CPSR_T (1U << 5)
49
--
50
2.25.1
diff view generated by jsdifflib
[PULL 04/10] target/arm: Rearrange cpu64.c so all the CPU initfns are together
Deleted patch
1
cpu64.c has ended up in a slightly odd order -- it starts with the
2
initfns for most of the models-real-hardware CPUs; after that comes a
3
bunch of support code for SVE, SME, pauth and LPA2 properties. Then
4
come the initfns for the 'host' and 'max' CPU types, and then after
5
that one more models-real-hardware CPU initfn, for a64fx. (This
6
ordering is partly historical and partly required because a64fx needs
7
the SVE properties.)
8
1
9
Reorder the file into:
10
* CPU property support functions
11
* initfns for real hardware CPUs
12
* initfns for host and max
13
* class boilerplate
14
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
---
19
target/arm/cpu64.c | 712 ++++++++++++++++++++++-----------------------
20
1 file changed, 356 insertions(+), 356 deletions(-)
21
22
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/cpu64.c
25
+++ b/target/arm/cpu64.c
26
@@ -XXX,XX +XXX,XX @@ static void aarch64_a35_initfn(Object *obj)
27
define_cortex_a72_a57_a53_cp_reginfo(cpu);
28
}
29
30
-static void aarch64_a57_initfn(Object *obj)
31
-{
32
- ARMCPU *cpu = ARM_CPU(obj);
33
-
34
- cpu->dtb_compatible = "arm,cortex-a57";
35
- set_feature(&cpu->env, ARM_FEATURE_V8);
36
- set_feature(&cpu->env, ARM_FEATURE_NEON);
37
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
38
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
39
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
40
- set_feature(&cpu->env, ARM_FEATURE_EL2);
41
- set_feature(&cpu->env, ARM_FEATURE_EL3);
42
- set_feature(&cpu->env, ARM_FEATURE_PMU);
43
- cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
44
- cpu->midr = 0x411fd070;
45
- cpu->revidr = 0x00000000;
46
- cpu->reset_fpsid = 0x41034070;
47
- cpu->isar.mvfr0 = 0x10110222;
48
- cpu->isar.mvfr1 = 0x12111111;
49
- cpu->isar.mvfr2 = 0x00000043;
50
- cpu->ctr = 0x8444c004;
51
- cpu->reset_sctlr = 0x00c50838;
52
- cpu->isar.id_pfr0 = 0x00000131;
53
- cpu->isar.id_pfr1 = 0x00011011;
54
- cpu->isar.id_dfr0 = 0x03010066;
55
- cpu->id_afr0 = 0x00000000;
56
- cpu->isar.id_mmfr0 = 0x10101105;
57
- cpu->isar.id_mmfr1 = 0x40000000;
58
- cpu->isar.id_mmfr2 = 0x01260000;
59
- cpu->isar.id_mmfr3 = 0x02102211;
60
- cpu->isar.id_isar0 = 0x02101110;
61
- cpu->isar.id_isar1 = 0x13112111;
62
- cpu->isar.id_isar2 = 0x21232042;
63
- cpu->isar.id_isar3 = 0x01112131;
64
- cpu->isar.id_isar4 = 0x00011142;
65
- cpu->isar.id_isar5 = 0x00011121;
66
- cpu->isar.id_isar6 = 0;
67
- cpu->isar.id_aa64pfr0 = 0x00002222;
68
- cpu->isar.id_aa64dfr0 = 0x10305106;
69
- cpu->isar.id_aa64isar0 = 0x00011120;
70
- cpu->isar.id_aa64mmfr0 = 0x00001124;
71
- cpu->isar.dbgdidr = 0x3516d000;
72
- cpu->isar.dbgdevid = 0x01110f13;
73
- cpu->isar.dbgdevid1 = 0x2;
74
- cpu->isar.reset_pmcr_el0 = 0x41013000;
75
- cpu->clidr = 0x0a200023;
76
- cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
77
- cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
78
- cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
79
- cpu->dcz_blocksize = 4; /* 64 bytes */
80
- cpu->gic_num_lrs = 4;
81
- cpu->gic_vpribits = 5;
82
- cpu->gic_vprebits = 5;
83
- cpu->gic_pribits = 5;
84
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
85
-}
86
-
87
-static void aarch64_a53_initfn(Object *obj)
88
-{
89
- ARMCPU *cpu = ARM_CPU(obj);
90
-
91
- cpu->dtb_compatible = "arm,cortex-a53";
92
- set_feature(&cpu->env, ARM_FEATURE_V8);
93
- set_feature(&cpu->env, ARM_FEATURE_NEON);
94
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
95
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
96
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
97
- set_feature(&cpu->env, ARM_FEATURE_EL2);
98
- set_feature(&cpu->env, ARM_FEATURE_EL3);
99
- set_feature(&cpu->env, ARM_FEATURE_PMU);
100
- cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
101
- cpu->midr = 0x410fd034;
102
- cpu->revidr = 0x00000000;
103
- cpu->reset_fpsid = 0x41034070;
104
- cpu->isar.mvfr0 = 0x10110222;
105
- cpu->isar.mvfr1 = 0x12111111;
106
- cpu->isar.mvfr2 = 0x00000043;
107
- cpu->ctr = 0x84448004; /* L1Ip = VIPT */
108
- cpu->reset_sctlr = 0x00c50838;
109
- cpu->isar.id_pfr0 = 0x00000131;
110
- cpu->isar.id_pfr1 = 0x00011011;
111
- cpu->isar.id_dfr0 = 0x03010066;
112
- cpu->id_afr0 = 0x00000000;
113
- cpu->isar.id_mmfr0 = 0x10101105;
114
- cpu->isar.id_mmfr1 = 0x40000000;
115
- cpu->isar.id_mmfr2 = 0x01260000;
116
- cpu->isar.id_mmfr3 = 0x02102211;
117
- cpu->isar.id_isar0 = 0x02101110;
118
- cpu->isar.id_isar1 = 0x13112111;
119
- cpu->isar.id_isar2 = 0x21232042;
120
- cpu->isar.id_isar3 = 0x01112131;
121
- cpu->isar.id_isar4 = 0x00011142;
122
- cpu->isar.id_isar5 = 0x00011121;
123
- cpu->isar.id_isar6 = 0;
124
- cpu->isar.id_aa64pfr0 = 0x00002222;
125
- cpu->isar.id_aa64dfr0 = 0x10305106;
126
- cpu->isar.id_aa64isar0 = 0x00011120;
127
- cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
128
- cpu->isar.dbgdidr = 0x3516d000;
129
- cpu->isar.dbgdevid = 0x00110f13;
130
- cpu->isar.dbgdevid1 = 0x1;
131
- cpu->isar.reset_pmcr_el0 = 0x41033000;
132
- cpu->clidr = 0x0a200023;
133
- cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
134
- cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
135
- cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
136
- cpu->dcz_blocksize = 4; /* 64 bytes */
137
- cpu->gic_num_lrs = 4;
138
- cpu->gic_vpribits = 5;
139
- cpu->gic_vprebits = 5;
140
- cpu->gic_pribits = 5;
141
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
142
-}
143
-
144
-static void aarch64_a72_initfn(Object *obj)
145
-{
146
- ARMCPU *cpu = ARM_CPU(obj);
147
-
148
- cpu->dtb_compatible = "arm,cortex-a72";
149
- set_feature(&cpu->env, ARM_FEATURE_V8);
150
- set_feature(&cpu->env, ARM_FEATURE_NEON);
151
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
152
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
153
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
154
- set_feature(&cpu->env, ARM_FEATURE_EL2);
155
- set_feature(&cpu->env, ARM_FEATURE_EL3);
156
- set_feature(&cpu->env, ARM_FEATURE_PMU);
157
- cpu->midr = 0x410fd083;
158
- cpu->revidr = 0x00000000;
159
- cpu->reset_fpsid = 0x41034080;
160
- cpu->isar.mvfr0 = 0x10110222;
161
- cpu->isar.mvfr1 = 0x12111111;
162
- cpu->isar.mvfr2 = 0x00000043;
163
- cpu->ctr = 0x8444c004;
164
- cpu->reset_sctlr = 0x00c50838;
165
- cpu->isar.id_pfr0 = 0x00000131;
166
- cpu->isar.id_pfr1 = 0x00011011;
167
- cpu->isar.id_dfr0 = 0x03010066;
168
- cpu->id_afr0 = 0x00000000;
169
- cpu->isar.id_mmfr0 = 0x10201105;
170
- cpu->isar.id_mmfr1 = 0x40000000;
171
- cpu->isar.id_mmfr2 = 0x01260000;
172
- cpu->isar.id_mmfr3 = 0x02102211;
173
- cpu->isar.id_isar0 = 0x02101110;
174
- cpu->isar.id_isar1 = 0x13112111;
175
- cpu->isar.id_isar2 = 0x21232042;
176
- cpu->isar.id_isar3 = 0x01112131;
177
- cpu->isar.id_isar4 = 0x00011142;
178
- cpu->isar.id_isar5 = 0x00011121;
179
- cpu->isar.id_aa64pfr0 = 0x00002222;
180
- cpu->isar.id_aa64dfr0 = 0x10305106;
181
- cpu->isar.id_aa64isar0 = 0x00011120;
182
- cpu->isar.id_aa64mmfr0 = 0x00001124;
183
- cpu->isar.dbgdidr = 0x3516d000;
184
- cpu->isar.dbgdevid = 0x01110f13;
185
- cpu->isar.dbgdevid1 = 0x2;
186
- cpu->isar.reset_pmcr_el0 = 0x41023000;
187
- cpu->clidr = 0x0a200023;
188
- cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
189
- cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
190
- cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
191
- cpu->dcz_blocksize = 4; /* 64 bytes */
192
- cpu->gic_num_lrs = 4;
193
- cpu->gic_vpribits = 5;
194
- cpu->gic_vprebits = 5;
195
- cpu->gic_pribits = 5;
196
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
197
-}
198
-
199
-static void aarch64_a76_initfn(Object *obj)
200
-{
201
- ARMCPU *cpu = ARM_CPU(obj);
202
-
203
- cpu->dtb_compatible = "arm,cortex-a76";
204
- set_feature(&cpu->env, ARM_FEATURE_V8);
205
- set_feature(&cpu->env, ARM_FEATURE_NEON);
206
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
207
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
208
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
209
- set_feature(&cpu->env, ARM_FEATURE_EL2);
210
- set_feature(&cpu->env, ARM_FEATURE_EL3);
211
- set_feature(&cpu->env, ARM_FEATURE_PMU);
212
-
213
- /* Ordered by B2.4 AArch64 registers by functional group */
214
- cpu->clidr = 0x82000023;
215
- cpu->ctr = 0x8444C004;
216
- cpu->dcz_blocksize = 4;
217
- cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
218
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
219
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
220
- cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
221
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
222
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
223
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
224
- cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
225
- cpu->id_afr0 = 0x00000000;
226
- cpu->isar.id_dfr0 = 0x04010088;
227
- cpu->isar.id_isar0 = 0x02101110;
228
- cpu->isar.id_isar1 = 0x13112111;
229
- cpu->isar.id_isar2 = 0x21232042;
230
- cpu->isar.id_isar3 = 0x01112131;
231
- cpu->isar.id_isar4 = 0x00010142;
232
- cpu->isar.id_isar5 = 0x01011121;
233
- cpu->isar.id_isar6 = 0x00000010;
234
- cpu->isar.id_mmfr0 = 0x10201105;
235
- cpu->isar.id_mmfr1 = 0x40000000;
236
- cpu->isar.id_mmfr2 = 0x01260000;
237
- cpu->isar.id_mmfr3 = 0x02122211;
238
- cpu->isar.id_mmfr4 = 0x00021110;
239
- cpu->isar.id_pfr0 = 0x10010131;
240
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
241
- cpu->isar.id_pfr2 = 0x00000011;
242
- cpu->midr = 0x414fd0b1; /* r4p1 */
243
- cpu->revidr = 0;
244
-
245
- /* From B2.18 CCSIDR_EL1 */
246
- cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
247
- cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
248
- cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
249
-
250
- /* From B2.93 SCTLR_EL3 */
251
- cpu->reset_sctlr = 0x30c50838;
252
-
253
- /* From B4.23 ICH_VTR_EL2 */
254
- cpu->gic_num_lrs = 4;
255
- cpu->gic_vpribits = 5;
256
- cpu->gic_vprebits = 5;
257
- cpu->gic_pribits = 5;
258
-
259
- /* From B5.1 AdvSIMD AArch64 register summary */
260
- cpu->isar.mvfr0 = 0x10110222;
261
- cpu->isar.mvfr1 = 0x13211111;
262
- cpu->isar.mvfr2 = 0x00000043;
263
-
264
- /* From D5.1 AArch64 PMU register summary */
265
- cpu->isar.reset_pmcr_el0 = 0x410b3000;
266
-}
267
-
268
-static void aarch64_neoverse_n1_initfn(Object *obj)
269
-{
270
- ARMCPU *cpu = ARM_CPU(obj);
271
-
272
- cpu->dtb_compatible = "arm,neoverse-n1";
273
- set_feature(&cpu->env, ARM_FEATURE_V8);
274
- set_feature(&cpu->env, ARM_FEATURE_NEON);
275
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
276
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
277
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
278
- set_feature(&cpu->env, ARM_FEATURE_EL2);
279
- set_feature(&cpu->env, ARM_FEATURE_EL3);
280
- set_feature(&cpu->env, ARM_FEATURE_PMU);
281
-
282
- /* Ordered by B2.4 AArch64 registers by functional group */
283
- cpu->clidr = 0x82000023;
284
- cpu->ctr = 0x8444c004;
285
- cpu->dcz_blocksize = 4;
286
- cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
287
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
288
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
289
- cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
290
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
291
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
292
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
293
- cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
294
- cpu->id_afr0 = 0x00000000;
295
- cpu->isar.id_dfr0 = 0x04010088;
296
- cpu->isar.id_isar0 = 0x02101110;
297
- cpu->isar.id_isar1 = 0x13112111;
298
- cpu->isar.id_isar2 = 0x21232042;
299
- cpu->isar.id_isar3 = 0x01112131;
300
- cpu->isar.id_isar4 = 0x00010142;
301
- cpu->isar.id_isar5 = 0x01011121;
302
- cpu->isar.id_isar6 = 0x00000010;
303
- cpu->isar.id_mmfr0 = 0x10201105;
304
- cpu->isar.id_mmfr1 = 0x40000000;
305
- cpu->isar.id_mmfr2 = 0x01260000;
306
- cpu->isar.id_mmfr3 = 0x02122211;
307
- cpu->isar.id_mmfr4 = 0x00021110;
308
- cpu->isar.id_pfr0 = 0x10010131;
309
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
310
- cpu->isar.id_pfr2 = 0x00000011;
311
- cpu->midr = 0x414fd0c1; /* r4p1 */
312
- cpu->revidr = 0;
313
-
314
- /* From B2.23 CCSIDR_EL1 */
315
- cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
316
- cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
317
- cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
318
-
319
- /* From B2.98 SCTLR_EL3 */
320
- cpu->reset_sctlr = 0x30c50838;
321
-
322
- /* From B4.23 ICH_VTR_EL2 */
323
- cpu->gic_num_lrs = 4;
324
- cpu->gic_vpribits = 5;
325
- cpu->gic_vprebits = 5;
326
- cpu->gic_pribits = 5;
327
-
328
- /* From B5.1 AdvSIMD AArch64 register summary */
329
- cpu->isar.mvfr0 = 0x10110222;
330
- cpu->isar.mvfr1 = 0x13211111;
331
- cpu->isar.mvfr2 = 0x00000043;
332
-
333
- /* From D5.1 AArch64 PMU register summary */
334
- cpu->isar.reset_pmcr_el0 = 0x410c3000;
335
-}
336
-
337
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
338
{
339
/*
340
@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
341
cpu->isar.id_aa64mmfr0 = t;
342
}
343
344
+static void aarch64_a57_initfn(Object *obj)
345
+{
346
+ ARMCPU *cpu = ARM_CPU(obj);
347
+
348
+ cpu->dtb_compatible = "arm,cortex-a57";
349
+ set_feature(&cpu->env, ARM_FEATURE_V8);
350
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
351
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
352
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
353
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
354
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
355
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
356
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
357
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
358
+ cpu->midr = 0x411fd070;
359
+ cpu->revidr = 0x00000000;
360
+ cpu->reset_fpsid = 0x41034070;
361
+ cpu->isar.mvfr0 = 0x10110222;
362
+ cpu->isar.mvfr1 = 0x12111111;
363
+ cpu->isar.mvfr2 = 0x00000043;
364
+ cpu->ctr = 0x8444c004;
365
+ cpu->reset_sctlr = 0x00c50838;
366
+ cpu->isar.id_pfr0 = 0x00000131;
367
+ cpu->isar.id_pfr1 = 0x00011011;
368
+ cpu->isar.id_dfr0 = 0x03010066;
369
+ cpu->id_afr0 = 0x00000000;
370
+ cpu->isar.id_mmfr0 = 0x10101105;
371
+ cpu->isar.id_mmfr1 = 0x40000000;
372
+ cpu->isar.id_mmfr2 = 0x01260000;
373
+ cpu->isar.id_mmfr3 = 0x02102211;
374
+ cpu->isar.id_isar0 = 0x02101110;
375
+ cpu->isar.id_isar1 = 0x13112111;
376
+ cpu->isar.id_isar2 = 0x21232042;
377
+ cpu->isar.id_isar3 = 0x01112131;
378
+ cpu->isar.id_isar4 = 0x00011142;
379
+ cpu->isar.id_isar5 = 0x00011121;
380
+ cpu->isar.id_isar6 = 0;
381
+ cpu->isar.id_aa64pfr0 = 0x00002222;
382
+ cpu->isar.id_aa64dfr0 = 0x10305106;
383
+ cpu->isar.id_aa64isar0 = 0x00011120;
384
+ cpu->isar.id_aa64mmfr0 = 0x00001124;
385
+ cpu->isar.dbgdidr = 0x3516d000;
386
+ cpu->isar.dbgdevid = 0x01110f13;
387
+ cpu->isar.dbgdevid1 = 0x2;
388
+ cpu->isar.reset_pmcr_el0 = 0x41013000;
389
+ cpu->clidr = 0x0a200023;
390
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
391
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
392
+ cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
393
+ cpu->dcz_blocksize = 4; /* 64 bytes */
394
+ cpu->gic_num_lrs = 4;
395
+ cpu->gic_vpribits = 5;
396
+ cpu->gic_vprebits = 5;
397
+ cpu->gic_pribits = 5;
398
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
399
+}
400
+
401
+static void aarch64_a53_initfn(Object *obj)
402
+{
403
+ ARMCPU *cpu = ARM_CPU(obj);
404
+
405
+ cpu->dtb_compatible = "arm,cortex-a53";
406
+ set_feature(&cpu->env, ARM_FEATURE_V8);
407
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
408
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
409
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
410
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
411
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
412
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
413
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
414
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
415
+ cpu->midr = 0x410fd034;
416
+ cpu->revidr = 0x00000000;
417
+ cpu->reset_fpsid = 0x41034070;
418
+ cpu->isar.mvfr0 = 0x10110222;
419
+ cpu->isar.mvfr1 = 0x12111111;
420
+ cpu->isar.mvfr2 = 0x00000043;
421
+ cpu->ctr = 0x84448004; /* L1Ip = VIPT */
422
+ cpu->reset_sctlr = 0x00c50838;
423
+ cpu->isar.id_pfr0 = 0x00000131;
424
+ cpu->isar.id_pfr1 = 0x00011011;
425
+ cpu->isar.id_dfr0 = 0x03010066;
426
+ cpu->id_afr0 = 0x00000000;
427
+ cpu->isar.id_mmfr0 = 0x10101105;
428
+ cpu->isar.id_mmfr1 = 0x40000000;
429
+ cpu->isar.id_mmfr2 = 0x01260000;
430
+ cpu->isar.id_mmfr3 = 0x02102211;
431
+ cpu->isar.id_isar0 = 0x02101110;
432
+ cpu->isar.id_isar1 = 0x13112111;
433
+ cpu->isar.id_isar2 = 0x21232042;
434
+ cpu->isar.id_isar3 = 0x01112131;
435
+ cpu->isar.id_isar4 = 0x00011142;
436
+ cpu->isar.id_isar5 = 0x00011121;
437
+ cpu->isar.id_isar6 = 0;
438
+ cpu->isar.id_aa64pfr0 = 0x00002222;
439
+ cpu->isar.id_aa64dfr0 = 0x10305106;
440
+ cpu->isar.id_aa64isar0 = 0x00011120;
441
+ cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
442
+ cpu->isar.dbgdidr = 0x3516d000;
443
+ cpu->isar.dbgdevid = 0x00110f13;
444
+ cpu->isar.dbgdevid1 = 0x1;
445
+ cpu->isar.reset_pmcr_el0 = 0x41033000;
446
+ cpu->clidr = 0x0a200023;
447
+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
448
+ cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
449
+ cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
450
+ cpu->dcz_blocksize = 4; /* 64 bytes */
451
+ cpu->gic_num_lrs = 4;
452
+ cpu->gic_vpribits = 5;
453
+ cpu->gic_vprebits = 5;
454
+ cpu->gic_pribits = 5;
455
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
456
+}
457
+
458
+static void aarch64_a72_initfn(Object *obj)
459
+{
460
+ ARMCPU *cpu = ARM_CPU(obj);
461
+
462
+ cpu->dtb_compatible = "arm,cortex-a72";
463
+ set_feature(&cpu->env, ARM_FEATURE_V8);
464
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
465
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
466
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
467
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
468
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
469
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
470
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
471
+ cpu->midr = 0x410fd083;
472
+ cpu->revidr = 0x00000000;
473
+ cpu->reset_fpsid = 0x41034080;
474
+ cpu->isar.mvfr0 = 0x10110222;
475
+ cpu->isar.mvfr1 = 0x12111111;
476
+ cpu->isar.mvfr2 = 0x00000043;
477
+ cpu->ctr = 0x8444c004;
478
+ cpu->reset_sctlr = 0x00c50838;
479
+ cpu->isar.id_pfr0 = 0x00000131;
480
+ cpu->isar.id_pfr1 = 0x00011011;
481
+ cpu->isar.id_dfr0 = 0x03010066;
482
+ cpu->id_afr0 = 0x00000000;
483
+ cpu->isar.id_mmfr0 = 0x10201105;
484
+ cpu->isar.id_mmfr1 = 0x40000000;
485
+ cpu->isar.id_mmfr2 = 0x01260000;
486
+ cpu->isar.id_mmfr3 = 0x02102211;
487
+ cpu->isar.id_isar0 = 0x02101110;
488
+ cpu->isar.id_isar1 = 0x13112111;
489
+ cpu->isar.id_isar2 = 0x21232042;
490
+ cpu->isar.id_isar3 = 0x01112131;
491
+ cpu->isar.id_isar4 = 0x00011142;
492
+ cpu->isar.id_isar5 = 0x00011121;
493
+ cpu->isar.id_aa64pfr0 = 0x00002222;
494
+ cpu->isar.id_aa64dfr0 = 0x10305106;
495
+ cpu->isar.id_aa64isar0 = 0x00011120;
496
+ cpu->isar.id_aa64mmfr0 = 0x00001124;
497
+ cpu->isar.dbgdidr = 0x3516d000;
498
+ cpu->isar.dbgdevid = 0x01110f13;
499
+ cpu->isar.dbgdevid1 = 0x2;
500
+ cpu->isar.reset_pmcr_el0 = 0x41023000;
501
+ cpu->clidr = 0x0a200023;
502
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
503
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
504
+ cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
505
+ cpu->dcz_blocksize = 4; /* 64 bytes */
506
+ cpu->gic_num_lrs = 4;
507
+ cpu->gic_vpribits = 5;
508
+ cpu->gic_vprebits = 5;
509
+ cpu->gic_pribits = 5;
510
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
511
+}
512
+
513
+static void aarch64_a76_initfn(Object *obj)
514
+{
515
+ ARMCPU *cpu = ARM_CPU(obj);
516
+
517
+ cpu->dtb_compatible = "arm,cortex-a76";
518
+ set_feature(&cpu->env, ARM_FEATURE_V8);
519
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
520
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
521
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
522
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
523
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
524
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
525
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
526
+
527
+ /* Ordered by B2.4 AArch64 registers by functional group */
528
+ cpu->clidr = 0x82000023;
529
+ cpu->ctr = 0x8444C004;
530
+ cpu->dcz_blocksize = 4;
531
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
532
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
533
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
534
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
535
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
536
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
537
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
538
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
539
+ cpu->id_afr0 = 0x00000000;
540
+ cpu->isar.id_dfr0 = 0x04010088;
541
+ cpu->isar.id_isar0 = 0x02101110;
542
+ cpu->isar.id_isar1 = 0x13112111;
543
+ cpu->isar.id_isar2 = 0x21232042;
544
+ cpu->isar.id_isar3 = 0x01112131;
545
+ cpu->isar.id_isar4 = 0x00010142;
546
+ cpu->isar.id_isar5 = 0x01011121;
547
+ cpu->isar.id_isar6 = 0x00000010;
548
+ cpu->isar.id_mmfr0 = 0x10201105;
549
+ cpu->isar.id_mmfr1 = 0x40000000;
550
+ cpu->isar.id_mmfr2 = 0x01260000;
551
+ cpu->isar.id_mmfr3 = 0x02122211;
552
+ cpu->isar.id_mmfr4 = 0x00021110;
553
+ cpu->isar.id_pfr0 = 0x10010131;
554
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
555
+ cpu->isar.id_pfr2 = 0x00000011;
556
+ cpu->midr = 0x414fd0b1; /* r4p1 */
557
+ cpu->revidr = 0;
558
+
559
+ /* From B2.18 CCSIDR_EL1 */
560
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
561
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
562
+ cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
563
+
564
+ /* From B2.93 SCTLR_EL3 */
565
+ cpu->reset_sctlr = 0x30c50838;
566
+
567
+ /* From B4.23 ICH_VTR_EL2 */
568
+ cpu->gic_num_lrs = 4;
569
+ cpu->gic_vpribits = 5;
570
+ cpu->gic_vprebits = 5;
571
+ cpu->gic_pribits = 5;
572
+
573
+ /* From B5.1 AdvSIMD AArch64 register summary */
574
+ cpu->isar.mvfr0 = 0x10110222;
575
+ cpu->isar.mvfr1 = 0x13211111;
576
+ cpu->isar.mvfr2 = 0x00000043;
577
+
578
+ /* From D5.1 AArch64 PMU register summary */
579
+ cpu->isar.reset_pmcr_el0 = 0x410b3000;
580
+}
581
+
582
+static void aarch64_a64fx_initfn(Object *obj)
583
+{
584
+ ARMCPU *cpu = ARM_CPU(obj);
585
+
586
+ cpu->dtb_compatible = "arm,a64fx";
587
+ set_feature(&cpu->env, ARM_FEATURE_V8);
588
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
589
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
590
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
591
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
592
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
593
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
594
+ cpu->midr = 0x461f0010;
595
+ cpu->revidr = 0x00000000;
596
+ cpu->ctr = 0x86668006;
597
+ cpu->reset_sctlr = 0x30000180;
598
+ cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
599
+ cpu->isar.id_aa64pfr1 = 0x0000000000000000;
600
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408;
601
+ cpu->isar.id_aa64dfr1 = 0x0000000000000000;
602
+ cpu->id_aa64afr0 = 0x0000000000000000;
603
+ cpu->id_aa64afr1 = 0x0000000000000000;
604
+ cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
605
+ cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
606
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
607
+ cpu->isar.id_aa64isar0 = 0x0000000010211120;
608
+ cpu->isar.id_aa64isar1 = 0x0000000000010001;
609
+ cpu->isar.id_aa64zfr0 = 0x0000000000000000;
610
+ cpu->clidr = 0x0000000080000023;
611
+ cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
612
+ cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
613
+ cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
614
+ cpu->dcz_blocksize = 6; /* 256 bytes */
615
+ cpu->gic_num_lrs = 4;
616
+ cpu->gic_vpribits = 5;
617
+ cpu->gic_vprebits = 5;
618
+ cpu->gic_pribits = 5;
619
+
620
+ /* The A64FX supports only 128, 256 and 512 bit vector lengths */
621
+ aarch64_add_sve_properties(obj);
622
+ cpu->sve_vq.supported = (1 << 0) /* 128bit */
623
+ | (1 << 1) /* 256bit */
624
+ | (1 << 3); /* 512bit */
625
+
626
+ cpu->isar.reset_pmcr_el0 = 0x46014040;
627
+
628
+ /* TODO: Add A64FX specific HPC extension registers */
629
+}
630
+
631
+static void aarch64_neoverse_n1_initfn(Object *obj)
632
+{
633
+ ARMCPU *cpu = ARM_CPU(obj);
634
+
635
+ cpu->dtb_compatible = "arm,neoverse-n1";
636
+ set_feature(&cpu->env, ARM_FEATURE_V8);
637
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
638
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
639
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
640
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
641
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
642
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
643
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
644
+
645
+ /* Ordered by B2.4 AArch64 registers by functional group */
646
+ cpu->clidr = 0x82000023;
647
+ cpu->ctr = 0x8444c004;
648
+ cpu->dcz_blocksize = 4;
649
+ cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
650
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
651
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
652
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
653
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
654
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
655
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
656
+ cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
657
+ cpu->id_afr0 = 0x00000000;
658
+ cpu->isar.id_dfr0 = 0x04010088;
659
+ cpu->isar.id_isar0 = 0x02101110;
660
+ cpu->isar.id_isar1 = 0x13112111;
661
+ cpu->isar.id_isar2 = 0x21232042;
662
+ cpu->isar.id_isar3 = 0x01112131;
663
+ cpu->isar.id_isar4 = 0x00010142;
664
+ cpu->isar.id_isar5 = 0x01011121;
665
+ cpu->isar.id_isar6 = 0x00000010;
666
+ cpu->isar.id_mmfr0 = 0x10201105;
667
+ cpu->isar.id_mmfr1 = 0x40000000;
668
+ cpu->isar.id_mmfr2 = 0x01260000;
669
+ cpu->isar.id_mmfr3 = 0x02122211;
670
+ cpu->isar.id_mmfr4 = 0x00021110;
671
+ cpu->isar.id_pfr0 = 0x10010131;
672
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
673
+ cpu->isar.id_pfr2 = 0x00000011;
674
+ cpu->midr = 0x414fd0c1; /* r4p1 */
675
+ cpu->revidr = 0;
676
+
677
+ /* From B2.23 CCSIDR_EL1 */
678
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
679
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
680
+ cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
681
+
682
+ /* From B2.98 SCTLR_EL3 */
683
+ cpu->reset_sctlr = 0x30c50838;
684
+
685
+ /* From B4.23 ICH_VTR_EL2 */
686
+ cpu->gic_num_lrs = 4;
687
+ cpu->gic_vpribits = 5;
688
+ cpu->gic_vprebits = 5;
689
+ cpu->gic_pribits = 5;
690
+
691
+ /* From B5.1 AdvSIMD AArch64 register summary */
692
+ cpu->isar.mvfr0 = 0x10110222;
693
+ cpu->isar.mvfr1 = 0x13211111;
694
+ cpu->isar.mvfr2 = 0x00000043;
695
+
696
+ /* From D5.1 AArch64 PMU register summary */
697
+ cpu->isar.reset_pmcr_el0 = 0x410c3000;
698
+}
699
+
700
static void aarch64_host_initfn(Object *obj)
701
{
702
#if defined(CONFIG_KVM)
703
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
704
qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
705
}
706
707
-static void aarch64_a64fx_initfn(Object *obj)
708
-{
709
- ARMCPU *cpu = ARM_CPU(obj);
710
-
711
- cpu->dtb_compatible = "arm,a64fx";
712
- set_feature(&cpu->env, ARM_FEATURE_V8);
713
- set_feature(&cpu->env, ARM_FEATURE_NEON);
714
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
715
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
716
- set_feature(&cpu->env, ARM_FEATURE_EL2);
717
- set_feature(&cpu->env, ARM_FEATURE_EL3);
718
- set_feature(&cpu->env, ARM_FEATURE_PMU);
719
- cpu->midr = 0x461f0010;
720
- cpu->revidr = 0x00000000;
721
- cpu->ctr = 0x86668006;
722
- cpu->reset_sctlr = 0x30000180;
723
- cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
724
- cpu->isar.id_aa64pfr1 = 0x0000000000000000;
725
- cpu->isar.id_aa64dfr0 = 0x0000000010305408;
726
- cpu->isar.id_aa64dfr1 = 0x0000000000000000;
727
- cpu->id_aa64afr0 = 0x0000000000000000;
728
- cpu->id_aa64afr1 = 0x0000000000000000;
729
- cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
730
- cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
731
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
732
- cpu->isar.id_aa64isar0 = 0x0000000010211120;
733
- cpu->isar.id_aa64isar1 = 0x0000000000010001;
734
- cpu->isar.id_aa64zfr0 = 0x0000000000000000;
735
- cpu->clidr = 0x0000000080000023;
736
- cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
737
- cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
738
- cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
739
- cpu->dcz_blocksize = 6; /* 256 bytes */
740
- cpu->gic_num_lrs = 4;
741
- cpu->gic_vpribits = 5;
742
- cpu->gic_vprebits = 5;
743
- cpu->gic_pribits = 5;
744
-
745
- /* The A64FX supports only 128, 256 and 512 bit vector lengths */
746
- aarch64_add_sve_properties(obj);
747
- cpu->sve_vq.supported = (1 << 0) /* 128bit */
748
- | (1 << 1) /* 256bit */
749
- | (1 << 3); /* 512bit */
750
-
751
- cpu->isar.reset_pmcr_el0 = 0x46014040;
752
-
753
- /* TODO: Add A64FX specific HPC extension registers */
754
-}
755
-
756
static const ARMCPUInfo aarch64_cpus[] = {
757
{ .name = "cortex-a35", .initfn = aarch64_a35_initfn },
758
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
759
--
760
2.25.1
761
762
diff view generated by jsdifflib
[PULL 05/10] hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
Deleted patch
1
From: Francisco Iglesias <francisco.iglesias@amd.com>
2
1
3
Connect ZynqMP's USB controllers.
4
5
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-id: 20220920081517.25401-1-frasse.iglesias@gmail.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/xlnx-zynqmp.h | 3 +++
12
hw/arm/xlnx-zynqmp.c | 36 ++++++++++++++++++++++++++++++++++++
13
2 files changed, 39 insertions(+)
14
15
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/xlnx-zynqmp.h
18
+++ b/include/hw/arm/xlnx-zynqmp.h
19
@@ -XXX,XX +XXX,XX @@
20
#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
21
#include "hw/misc/xlnx-zynqmp-crf.h"
22
#include "hw/timer/cadence_ttc.h"
23
+#include "hw/usb/hcd-dwc3.h"
24
25
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
26
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
27
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
28
#define XLNX_ZYNQMP_NUM_SPIS 2
29
#define XLNX_ZYNQMP_NUM_GDMA_CH 8
30
#define XLNX_ZYNQMP_NUM_ADMA_CH 8
31
+#define XLNX_ZYNQMP_NUM_USB 2
32
33
#define XLNX_ZYNQMP_NUM_QSPI_BUS 2
34
#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
35
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
36
XlnxZynqMPAPUCtrl apu_ctrl;
37
XlnxZynqMPCRF crf;
38
CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
39
+ USBDWC3 usb[XLNX_ZYNQMP_NUM_USB];
40
41
char *boot_cpu;
42
ARMCPU *boot_cpu_ptr;
43
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/arm/xlnx-zynqmp.c
46
+++ b/hw/arm/xlnx-zynqmp.c
47
@@ -XXX,XX +XXX,XX @@ static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
48
77, 78, 79, 80, 81, 82, 83, 84
49
};
50
51
+static const uint64_t usb_addr[XLNX_ZYNQMP_NUM_USB] = {
52
+ 0xFE200000, 0xFE300000
53
+};
54
+
55
+static const int usb_intr[XLNX_ZYNQMP_NUM_USB] = {
56
+ 65, 70
57
+};
58
+
59
typedef struct XlnxZynqMPGICRegion {
60
int region_index;
61
uint32_t address;
62
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj)
63
object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
64
object_initialize_child(obj, "qspi-irq-orgate",
65
&s->qspi_irq_orgate, TYPE_OR_IRQ);
66
+
67
+ for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
68
+ object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3);
69
+ }
70
}
71
72
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
73
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
74
object_property_add_alias(OBJECT(s), bus_name,
75
OBJECT(&s->qspi), target_bus);
76
}
77
+
78
+ for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
79
+ if (!object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma",
80
+ OBJECT(system_memory), errp)) {
81
+ return;
82
+ }
83
+
84
+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4);
85
+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2);
86
+
87
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) {
88
+ return;
89
+ }
90
+
91
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_addr[i]);
92
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0,
93
+ gic_spi[usb_intr[i]]);
94
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 1,
95
+ gic_spi[usb_intr[i] + 1]);
96
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 2,
97
+ gic_spi[usb_intr[i] + 2]);
98
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 3,
99
+ gic_spi[usb_intr[i] + 3]);
100
+ }
101
}
102
103
static Property xlnx_zynqmp_props[] = {
104
--
105
2.25.1
diff view generated by jsdifflib
[PULL 06/10] hw/arm/virt: Fix devicetree warning about the root node
Deleted patch
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
1
3
The devicetree specification requires a 'model' property in the root
4
node. Fix the corresponding dt-validate warning:
5
6
/: 'model' is a required property
7
From schema: dtschema/schemas/root-node.yaml
8
9
Use the same name for model as for compatible. The specification
10
recommends that 'compatible' follows the format 'manufacturer,model' and
11
'model' follows the format 'manufacturer,model-number'. Since our
12
'compatible' doesn't observe this, 'model' doesn't really need to
13
either.
14
15
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Eric Auger <eric.auger@redhat.com>
18
Message-id: 20220927100347.176606-2-jean-philippe@linaro.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
hw/arm/virt.c | 1 +
22
1 file changed, 1 insertion(+)
23
24
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/virt.c
27
+++ b/hw/arm/virt.c
28
@@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms)
29
qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
30
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
31
qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
32
+ qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
33
34
/* /chosen must exist for load_dtb to fill in necessary properties later */
35
qemu_fdt_add_subnode(fdt, "/chosen");
36
--
37
2.25.1
diff view generated by jsdifflib
[PULL 07/10] hw/arm/virt: Fix devicetree warning about the GIC node
Deleted patch
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
1
3
The GICv3 bindings requires a #msi-cells property for the ITS node. Fix
4
the corresponding dt-validate warning:
5
6
interrupt-controller@8000000: msi-controller@8080000: '#msi-cells' is a required property
7
From schema: linux/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
8
9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
Message-id: 20220927100347.176606-3-jean-philippe@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/arm/virt.c | 1 +
16
1 file changed, 1 insertion(+)
17
18
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/virt.c
21
+++ b/hw/arm/virt.c
22
@@ -XXX,XX +XXX,XX @@ static void fdt_add_its_gic_node(VirtMachineState *vms)
23
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
24
"arm,gic-v3-its");
25
qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
26
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
27
qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
28
2, vms->memmap[VIRT_GIC_ITS].base,
29
2, vms->memmap[VIRT_GIC_ITS].size);
30
--
31
2.25.1
diff view generated by jsdifflib
[PULL 08/10] hw/arm/virt: Use "msi-map" devicetree property for PCI
Deleted patch
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
1
3
The "msi-parent" property can be used on the PCI node when MSIs do not
4
contain sideband data (device IDs) [1]. In QEMU, MSI transactions
5
contain the requester ID, so the PCI node should use the "msi-map"
6
property instead of "msi-parent". In our case the property describes an
7
identity map between requester ID and sideband data.
8
9
This fixes a warning when passing the DTB generated by QEMU to dtc,
10
following a recent change to the GICv3 node:
11
12
Warning (msi_parent_property): /pcie@10000000:msi-parent: property size (4) too small for cell size 1
13
14
[1] linux/Documentation/devicetree/bindings/pci/pci-msi.txt
15
16
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Eric Auger <eric.auger@redhat.com>
19
Message-id: 20220927100347.176606-4-jean-philippe@linaro.org
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
22
hw/arm/virt.c | 4 ++--
23
1 file changed, 2 insertions(+), 2 deletions(-)
24
25
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/virt.c
28
+++ b/hw/arm/virt.c
29
@@ -XXX,XX +XXX,XX @@ static void create_pcie(VirtMachineState *vms)
30
qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
31
32
if (vms->msi_phandle) {
33
- qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",
34
- vms->msi_phandle);
35
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
36
+ 0, vms->msi_phandle, 0, 0x10000);
37
}
38
39
qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
40
--
41
2.25.1
diff view generated by jsdifflib
[PULL 09/10] hw/arm/virt: Fix devicetree warning about the SMMU node
Deleted patch
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
1
3
The SMMUv3 node isn't expected to have clock properties
4
(unlike the SMMUv2). Fix the corresponding dt-validate warning:
5
6
smmuv3@9050000: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
7
From schema: linux/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
8
9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: tweaked commit message as suggested by Eric]
12
Reviewed-by: Eric Auger <eric.auger@redhat.com>
13
Message-id: 20220927100347.176606-7-jean-philippe@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/arm/virt.c | 2 --
17
1 file changed, 2 deletions(-)
18
19
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/virt.c
22
+++ b/hw/arm/virt.c
23
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const VirtMachineState *vms,
24
qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
25
sizeof(irq_names));
26
27
- qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);
28
- qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");
29
qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
30
31
qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
32
--
33
2.25.1
diff view generated by jsdifflib
[PULL 10/10] target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP
Deleted patch
1
From: Jerome Forissier <jerome.forissier@linaro.org>
2
1
3
SP_EL1 must be kept when EL3 is present but EL2 is not. Therefore mark
4
it with ARM_CP_EL3_NO_EL2_KEEP.
5
6
Cc: qemu-stable@nongnu.org
7
Fixes: 696ba3771894 ("target/arm: Handle cpreg registration for missing EL")
8
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220927120058.670901-1-jerome.forissier@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/helper.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
21
.fieldoffset = offsetof(CPUARMState, sp_el[0]) },
22
{ .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
23
.opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
24
- .access = PL2_RW, .type = ARM_CP_ALIAS,
25
+ .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP,
26
.fieldoffset = offsetof(CPUARMState, sp_el[1]) },
27
{ .name = "SPSel", .state = ARM_CP_STATE_AA64,
28
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
29
--
30
2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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