[v2] Enhance maximum priority support of PLIC

[PATCH v2 0/2] Enhance maximum priority support of PLIC

Jim Shu posted 2 patches 1 year, 6 months ago

Diff against v3
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git fetch https://github.com/patchew-project/qemu tags/patchew/20220930123239.15515-1-jim.shu@sifive.com

Maintainers: Alistair Francis <Alistair.Francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Palmer Dabbelt <palmer@dabbelt.com>

There is a newer version of this series

hw/intc/sifive_plic.c | 24 +++++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)

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[PATCH v2 0/2] Enhance maximum priority support of PLIC

Posted by Jim Shu 1 year, 6 months ago

This patchset fixes hard-coded maximum priority of interrupt priority
register and also changes this register to WARL field to align the PLIC
spec.

Changelog:

v2:
  * change interrupt priority register to WARL field.

Jim Shu (2):
  hw/intc: sifive_plic: fix hard-coded max priority level
  hw/intc: sifive_plic: change interrupt priority register to WARL field

 hw/intc/sifive_plic.c | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

-- 
2.17.1