This patchset implements RISC-V Zc* extension v1.0.0.RC5.6 version instructions. 

Specification:
https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream

To test Zc* implementation, specify cpu argument with 'x-zca=true,x-zcb=true,x-zcf=true" and "x-zcd=true" (or "x-zcmp=true,x-zcmt=true") to enable Zca/Zcb/Zcf and Zcd(or Zcmp,Zcmt) extension support. 

This implementation can pass the basic zc tests from https://github.com/yulong-plct/zc-test

Weiwei Li (8):
  target/riscv: add cfg properties for Zc* extension
  target/riscv: add support for Zca, Zcf and Zcd extension
  target/riscv: add support for Zcb extension
  target/riscv: add support for Zcmp extension
  target/riscv: add support for Zcmt extension
  target/riscv: delete redundant check for zcd instructions in
    decode_opc
  target/riscv: expose properties for Zc* extension
  disas/riscv.c: add disasm support for Zc*

 disas/riscv.c                             | 287 +++++++++++++++++++++-
 target/riscv/cpu.c                        |  37 +++
 target/riscv/cpu.h                        |   8 +
 target/riscv/cpu_bits.h                   |   6 +
 target/riscv/csr.c                        |  28 +++
 target/riscv/helper.h                     |   7 +
 target/riscv/insn16.decode                |  52 +++-
 target/riscv/insn_trans/trans_rvi.c.inc   |   5 +-
 target/riscv/insn_trans/trans_rvzce.c.inc | 279 +++++++++++++++++++++
 target/riscv/machine.c                    |  19 ++
 target/riscv/meson.build                  |   3 +-
 target/riscv/translate.c                  |  25 +-
 target/riscv/zce_helper.c                 | 244 ++++++++++++++++++
 13 files changed, 990 insertions(+), 10 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc
 create mode 100644 target/riscv/zce_helper.c

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2.25.1