[PULL 00/39] target-arm queue
[PULL 00/72] target-arm queue
1
Hi; this pullreq contains mainly a chunk of RTH's refactoring
1
First arm pullreq of the cycle; this is mostly my softfloat NaN
2
of the Arm pagetable walk code, plus a series from me fixing
2
handling series. (Lots more in my to-review queue, but I don't
3
configure checkpatch warnings, and some old patches to various
3
like pullreqs growing too close to a hundred patches at a time :-))
4
files all over the tree getting rid of dynamic stack allocation.
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4
6
thanks
5
thanks
7
-- PMM
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-- PMM
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7
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The following changes since commit 6338c30111d596d955e6bc933a82184a0b910c43:
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The following changes since commit 97f2796a3736ed37a1b85dc1c76a6c45b829dd17:
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9
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Merge tag 'm68k-for-7.2-pull-request' of https://github.com/vivier/qemu-m68k into staging (2022-09-21 13:12:36 -0400)
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Open 10.0 development tree (2024-12-10 17:41:17 +0000)
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are available in the Git repository at:
12
are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220922
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211
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for you to fetch changes up to b3b5472db0ab7a53499441c1fe1dedec05b1e285:
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for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8:
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17
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configure: Avoid use of 'local' as it is non-POSIX (2022-09-22 16:38:29 +0100)
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MAINTAINERS: Add correct email address for Vikram Garhwal (2024-12-11 15:31:09 +0000)
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19
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----------------------------------------------------------------
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----------------------------------------------------------------
22
target-arm queue:
21
target-arm queue:
23
* hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic
22
* hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs
24
* Fix alignment for Neon VLD4.32
23
* fpu: Make muladd NaN handling runtime-selected, not compile-time
25
* Refactoring of page-table-walk code
24
* fpu: Make default NaN pattern runtime-selected, not compile-time
26
* hw/acpi: Add ospm_status hook implementation for acpi-ged
25
* fpu: Minor NaN-related cleanups
27
* hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level
26
* MAINTAINERS: email address updates
28
* chardev/baum: avoid variable-length arrays
29
* io/channel-websock: avoid variable-length arrays
30
* hw/net/e1000e_core: Use definition to avoid dynamic stack allocation
31
* hw/ppc/pnv: Avoid dynamic stack allocation
32
* hw/intc/xics: Avoid dynamic stack allocation
33
* hw/i386/multiboot: Avoid dynamic stack allocation
34
* hw/usb/hcd-ohci: Use definition to avoid dynamic stack allocation
35
* ui/curses: Avoid dynamic stack allocation
36
* tests/unit/test-vmstate: Avoid dynamic stack allocation
37
* configure: fix various shellcheck-spotted issues and nits
38
27
39
----------------------------------------------------------------
28
----------------------------------------------------------------
40
Anton Kochkov (1):
29
Bernhard Beschow (5):
41
hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic
30
hw/net/lan9118: Extract lan9118_phy
31
hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
32
hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
33
hw/net/lan9118_phy: Reuse MII constants
34
hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
42
35
43
Clément Chigot (1):
36
Leif Lindholm (1):
44
target/arm: Fix alignment for VLD4.32
37
MAINTAINERS: update email address for Leif Lindholm
45
38
46
Keqian Zhu (1):
39
Peter Maydell (54):
47
hw/acpi: Add ospm_status hook implementation for acpi-ged
40
fpu: handle raising Invalid for infzero in pick_nan_muladd
41
fpu: Check for default_nan_mode before calling pickNaNMulAdd
42
softfloat: Allow runtime choice of inf * 0 + NaN result
43
tests/fp: Explicitly set inf-zero-nan rule
44
target/arm: Set FloatInfZeroNaNRule explicitly
45
target/s390: Set FloatInfZeroNaNRule explicitly
46
target/ppc: Set FloatInfZeroNaNRule explicitly
47
target/mips: Set FloatInfZeroNaNRule explicitly
48
target/sparc: Set FloatInfZeroNaNRule explicitly
49
target/xtensa: Set FloatInfZeroNaNRule explicitly
50
target/x86: Set FloatInfZeroNaNRule explicitly
51
target/loongarch: Set FloatInfZeroNaNRule explicitly
52
target/hppa: Set FloatInfZeroNaNRule explicitly
53
softfloat: Pass have_snan to pickNaNMulAdd
54
softfloat: Allow runtime choice of NaN propagation for muladd
55
tests/fp: Explicitly set 3-NaN propagation rule
56
target/arm: Set Float3NaNPropRule explicitly
57
target/loongarch: Set Float3NaNPropRule explicitly
58
target/ppc: Set Float3NaNPropRule explicitly
59
target/s390x: Set Float3NaNPropRule explicitly
60
target/sparc: Set Float3NaNPropRule explicitly
61
target/mips: Set Float3NaNPropRule explicitly
62
target/xtensa: Set Float3NaNPropRule explicitly
63
target/i386: Set Float3NaNPropRule explicitly
64
target/hppa: Set Float3NaNPropRule explicitly
65
fpu: Remove use_first_nan field from float_status
66
target/m68k: Don't pass NULL float_status to floatx80_default_nan()
67
softfloat: Create floatx80 default NaN from parts64_default_nan
68
target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
69
target/m68k: In frem helper, initialize local float_status from env->fp_status
70
target/m68k: Init local float_status from env fp_status in gdb get/set reg
71
target/sparc: Initialize local scratch float_status from env->fp_status
72
target/ppc: Use env->fp_status in helper_compute_fprf functions
73
fpu: Allow runtime choice of default NaN value
74
tests/fp: Set default NaN pattern explicitly
75
target/microblaze: Set default NaN pattern explicitly
76
target/i386: Set default NaN pattern explicitly
77
target/hppa: Set default NaN pattern explicitly
78
target/alpha: Set default NaN pattern explicitly
79
target/arm: Set default NaN pattern explicitly
80
target/loongarch: Set default NaN pattern explicitly
81
target/m68k: Set default NaN pattern explicitly
82
target/mips: Set default NaN pattern explicitly
83
target/openrisc: Set default NaN pattern explicitly
84
target/ppc: Set default NaN pattern explicitly
85
target/sh4: Set default NaN pattern explicitly
86
target/rx: Set default NaN pattern explicitly
87
target/s390x: Set default NaN pattern explicitly
88
target/sparc: Set default NaN pattern explicitly
89
target/xtensa: Set default NaN pattern explicitly
90
target/hexagon: Set default NaN pattern explicitly
91
target/riscv: Set default NaN pattern explicitly
92
target/tricore: Set default NaN pattern explicitly
93
fpu: Remove default handling for dnan_pattern
48
94
49
Lucas Dietrich (1):
95
Richard Henderson (11):
50
hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level
96
target/arm: Copy entire float_status in is_ebf
97
softfloat: Inline pickNaNMulAdd
98
softfloat: Use goto for default nan case in pick_nan_muladd
99
softfloat: Remove which from parts_pick_nan_muladd
100
softfloat: Pad array size in pick_nan_muladd
101
softfloat: Move propagateFloatx80NaN to softfloat.c
102
softfloat: Use parts_pick_nan in propagateFloatx80NaN
103
softfloat: Inline pickNaN
104
softfloat: Share code between parts_pick_nan cases
105
softfloat: Sink frac_cmp in parts_pick_nan until needed
106
softfloat: Replace WHICH with RET in parts_pick_nan
51
107
52
Peter Maydell (7):
108
Vikram Garhwal (1):
53
configure: Remove unused python_version variable
109
MAINTAINERS: Add correct email address for Vikram Garhwal
54
configure: Remove unused meson_args variable
55
configure: Add missing quoting for some easy cases
56
configure: Add './' on front of glob of */config-devices.mak.d
57
configure: Remove use of backtick `...` syntax
58
configure: Check mkdir result directly, not via $?
59
configure: Avoid use of 'local' as it is non-POSIX
60
110
61
Philippe Mathieu-Daudé (11):
111
MAINTAINERS | 4 +-
62
chardev/baum: Replace magic values by X_MAX / Y_MAX definitions
112
include/fpu/softfloat-helpers.h | 38 +++-
63
chardev/baum: Use definitions to avoid dynamic stack allocation
113
include/fpu/softfloat-types.h | 89 +++++++-
64
chardev/baum: Avoid dynamic stack allocation
114
include/hw/net/imx_fec.h | 9 +-
65
io/channel-websock: Replace strlen(const_str) by sizeof(const_str) - 1
115
include/hw/net/lan9118_phy.h | 37 ++++
66
hw/net/e1000e_core: Use definition to avoid dynamic stack allocation
116
include/hw/net/mii.h | 6 +
67
hw/ppc/pnv: Avoid dynamic stack allocation
117
target/mips/fpu_helper.h | 20 ++
68
hw/intc/xics: Avoid dynamic stack allocation
118
target/sparc/helper.h | 4 +-
69
hw/i386/multiboot: Avoid dynamic stack allocation
119
fpu/softfloat.c | 19 ++
70
hw/usb/hcd-ohci: Use definition to avoid dynamic stack allocation
120
hw/net/imx_fec.c | 146 ++------------
71
ui/curses: Avoid dynamic stack allocation
121
hw/net/lan9118.c | 137 ++-----------
72
tests/unit/test-vmstate: Avoid dynamic stack allocation
122
hw/net/lan9118_phy.c | 222 ++++++++++++++++++++
73
123
linux-user/arm/nwfpe/fpa11.c | 5 +
74
Richard Henderson (17):
124
target/alpha/cpu.c | 2 +
75
target/arm: Create GetPhysAddrResult
125
target/arm/cpu.c | 10 +
76
target/arm: Use GetPhysAddrResult in get_phys_addr_lpae
126
target/arm/tcg/vec_helper.c | 20 +-
77
target/arm: Use GetPhysAddrResult in get_phys_addr_v6
127
target/hexagon/cpu.c | 2 +
78
target/arm: Use GetPhysAddrResult in get_phys_addr_v5
128
target/hppa/fpu_helper.c | 12 ++
79
target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5
129
target/i386/tcg/fpu_helper.c | 12 ++
80
target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7
130
target/loongarch/tcg/fpu_helper.c | 14 +-
81
target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8
131
target/m68k/cpu.c | 14 +-
82
target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup
132
target/m68k/fpu_helper.c | 6 +-
83
target/arm: Remove is_subpage argument to pmsav8_mpu_lookup
133
target/m68k/helper.c | 6 +-
84
target/arm: Add is_secure parameter to v8m_security_lookup
134
target/microblaze/cpu.c | 2 +
85
target/arm: Add secure parameter to pmsav8_mpu_lookup
135
target/mips/msa.c | 10 +
86
target/arm: Add is_secure parameter to get_phys_addr_v5
136
target/openrisc/cpu.c | 2 +
87
target/arm: Add is_secure parameter to get_phys_addr_v6
137
target/ppc/cpu_init.c | 19 ++
88
target/arm: Add secure parameter to get_phys_addr_pmsav8
138
target/ppc/fpu_helper.c | 3 +-
89
target/arm: Add is_secure parameter to pmsav7_use_background_region
139
target/riscv/cpu.c | 2 +
90
target/arm: Add secure parameter to get_phys_addr_pmsav7
140
target/rx/cpu.c | 2 +
91
target/arm: Add is_secure parameter to get_phys_addr_pmsav5
141
target/s390x/cpu.c | 5 +
92
142
target/sh4/cpu.c | 2 +
93
configure | 82 +++++-----
143
target/sparc/cpu.c | 6 +
94
target/arm/internals.h | 26 +--
144
target/sparc/fop_helper.c | 8 +-
95
chardev/baum.c | 22 ++-
145
target/sparc/translate.c | 4 +-
96
hw/acpi/generic_event_device.c | 8 +
146
target/tricore/helper.c | 2 +
97
hw/i386/multiboot.c | 5 +-
147
target/xtensa/cpu.c | 4 +
98
hw/intc/xics.c | 2 +-
148
target/xtensa/fpu_helper.c | 3 +-
99
hw/net/can/xlnx-zynqmp-can.c | 32 ++--
149
tests/fp/fp-bench.c | 7 +
100
hw/net/e1000e_core.c | 7 +-
150
tests/fp/fp-test-log2.c | 1 +
101
hw/net/lan9118.c | 8 +
151
tests/fp/fp-test.c | 7 +
102
hw/ppc/pnv.c | 4 +-
152
fpu/softfloat-parts.c.inc | 152 +++++++++++---
103
hw/ppc/spapr.c | 8 +-
153
fpu/softfloat-specialize.c.inc | 412 ++------------------------------------
104
hw/ppc/spapr_pci_nvlink2.c | 2 +-
154
.mailmap | 5 +-
105
hw/usb/hcd-ohci.c | 7 +-
155
hw/net/Kconfig | 5 +
106
io/channel-websock.c | 2 +-
156
hw/net/meson.build | 1 +
107
target/arm/helper.c | 27 ++-
157
hw/net/trace-events | 10 +-
108
target/arm/m_helper.c | 78 ++++-----
158
47 files changed, 778 insertions(+), 730 deletions(-)
109
target/arm/ptw.c | 364 +++++++++++++++++++----------------------
159
create mode 100644 include/hw/net/lan9118_phy.h
110
target/arm/tlb_helper.c | 22 +--
160
create mode 100644 hw/net/lan9118_phy.c
111
target/arm/translate-neon.c | 6 +-
112
tests/unit/test-vmstate.c | 7 +-
113
ui/curses.c | 2 +-
114
21 files changed, 347 insertions(+), 374 deletions(-)
115
diff view generated by jsdifflib
[PULL 21/39] hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level
[PULL 01/72] hw/net/lan9118: Extract lan9118_phy
1
From: Lucas Dietrich <ld.adecy@gmail.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
The LAN9118 allows the guest to specify a level for both the TX and
3
A very similar implementation of the same device exists in imx_fec. Prepare for
4
RX FIFOs at which an interrupt will be generated. We implement the
4
a common implementation by extracting a device model into its own files.
5
RSFL_INT interrupt for the RX FIFO but are missing the handling of
6
the equivalent TSFL_INT for the TX FIFO. Add the missing test to set
7
the interrupt if the TX FIFO has exceeded the guest-specified level.
8
5
9
This flag is required for Micrium lan911x ethernet driver to work.
6
Some migration state has been moved into the new device model which breaks
7
migration compatibility for the following machines:
8
* smdkc210
9
* realview-*
10
* vexpress-*
11
* kzm
12
* mps2-*
10
13
11
Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com>
14
While breaking migration ABI, fix the size of the MII registers to be 16 bit,
12
[PMM: Tweaked commit message and comment]
15
as defined by IEEE 802.3u.
16
17
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
18
Tested-by: Guenter Roeck <linux@roeck-us.net>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Message-id: 20241102125724.532843-2-shentey@gmail.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
22
---
16
hw/net/lan9118.c | 8 ++++++++
23
include/hw/net/lan9118_phy.h | 37 ++++++++
17
1 file changed, 8 insertions(+)
24
hw/net/lan9118.c | 137 +++++-----------------------
25
hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++
26
hw/net/Kconfig | 4 +
27
hw/net/meson.build | 1 +
28
5 files changed, 233 insertions(+), 115 deletions(-)
29
create mode 100644 include/hw/net/lan9118_phy.h
30
create mode 100644 hw/net/lan9118_phy.c
18
31
32
diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h
33
new file mode 100644
34
index XXXXXXX..XXXXXXX
35
--- /dev/null
36
+++ b/include/hw/net/lan9118_phy.h
37
@@ -XXX,XX +XXX,XX @@
38
+/*
39
+ * SMSC LAN9118 PHY emulation
40
+ *
41
+ * Copyright (c) 2009 CodeSourcery, LLC.
42
+ * Written by Paul Brook
43
+ *
44
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
45
+ * See the COPYING file in the top-level directory.
46
+ */
47
+
48
+#ifndef HW_NET_LAN9118_PHY_H
49
+#define HW_NET_LAN9118_PHY_H
50
+
51
+#include "qom/object.h"
52
+#include "hw/sysbus.h"
53
+
54
+#define TYPE_LAN9118_PHY "lan9118-phy"
55
+OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY)
56
+
57
+typedef struct Lan9118PhyState {
58
+ SysBusDevice parent_obj;
59
+
60
+ uint16_t status;
61
+ uint16_t control;
62
+ uint16_t advertise;
63
+ uint16_t ints;
64
+ uint16_t int_mask;
65
+ qemu_irq irq;
66
+ bool link_down;
67
+} Lan9118PhyState;
68
+
69
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down);
70
+void lan9118_phy_reset(Lan9118PhyState *s);
71
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg);
72
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val);
73
+
74
+#endif
19
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
75
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
20
index XXXXXXX..XXXXXXX 100644
76
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/net/lan9118.c
77
--- a/hw/net/lan9118.c
22
+++ b/hw/net/lan9118.c
78
+++ b/hw/net/lan9118.c
79
@@ -XXX,XX +XXX,XX @@
80
#include "net/net.h"
81
#include "net/eth.h"
82
#include "hw/irq.h"
83
+#include "hw/net/lan9118_phy.h"
84
#include "hw/net/lan9118.h"
85
#include "hw/ptimer.h"
86
#include "hw/qdev-properties.h"
87
@@ -XXX,XX +XXX,XX @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
88
#define MAC_CR_RXEN 0x00000004
89
#define MAC_CR_RESERVED 0x7f404213
90
91
-#define PHY_INT_ENERGYON 0x80
92
-#define PHY_INT_AUTONEG_COMPLETE 0x40
93
-#define PHY_INT_FAULT 0x20
94
-#define PHY_INT_DOWN 0x10
95
-#define PHY_INT_AUTONEG_LP 0x08
96
-#define PHY_INT_PARFAULT 0x04
97
-#define PHY_INT_AUTONEG_PAGE 0x02
98
-
99
#define GPT_TIMER_EN 0x20000000
100
101
/*
102
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
103
uint32_t mac_mii_data;
104
uint32_t mac_flow;
105
106
- uint32_t phy_status;
107
- uint32_t phy_control;
108
- uint32_t phy_advertise;
109
- uint32_t phy_int;
110
- uint32_t phy_int_mask;
111
+ Lan9118PhyState mii;
112
+ IRQState mii_irq;
113
114
int32_t eeprom_writable;
115
uint8_t eeprom[128];
116
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
117
118
static const VMStateDescription vmstate_lan9118 = {
119
.name = "lan9118",
120
- .version_id = 2,
121
- .minimum_version_id = 1,
122
+ .version_id = 3,
123
+ .minimum_version_id = 3,
124
.fields = (const VMStateField[]) {
125
VMSTATE_PTIMER(timer, lan9118_state),
126
VMSTATE_UINT32(irq_cfg, lan9118_state),
127
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118 = {
128
VMSTATE_UINT32(mac_mii_acc, lan9118_state),
129
VMSTATE_UINT32(mac_mii_data, lan9118_state),
130
VMSTATE_UINT32(mac_flow, lan9118_state),
131
- VMSTATE_UINT32(phy_status, lan9118_state),
132
- VMSTATE_UINT32(phy_control, lan9118_state),
133
- VMSTATE_UINT32(phy_advertise, lan9118_state),
134
- VMSTATE_UINT32(phy_int, lan9118_state),
135
- VMSTATE_UINT32(phy_int_mask, lan9118_state),
136
VMSTATE_INT32(eeprom_writable, lan9118_state),
137
VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
138
VMSTATE_INT32(tx_fifo_size, lan9118_state),
139
@@ -XXX,XX +XXX,XX @@ static void lan9118_reload_eeprom(lan9118_state *s)
140
lan9118_mac_changed(s);
141
}
142
143
-static void phy_update_irq(lan9118_state *s)
144
+static void lan9118_update_irq(void *opaque, int n, int level)
145
{
146
- if (s->phy_int & s->phy_int_mask) {
147
+ lan9118_state *s = opaque;
148
+
149
+ if (level) {
150
s->int_sts |= PHY_INT;
151
} else {
152
s->int_sts &= ~PHY_INT;
153
@@ -XXX,XX +XXX,XX @@ static void phy_update_irq(lan9118_state *s)
154
lan9118_update(s);
155
}
156
157
-static void phy_update_link(lan9118_state *s)
158
-{
159
- /* Autonegotiation status mirrors link status. */
160
- if (qemu_get_queue(s->nic)->link_down) {
161
- s->phy_status &= ~0x0024;
162
- s->phy_int |= PHY_INT_DOWN;
163
- } else {
164
- s->phy_status |= 0x0024;
165
- s->phy_int |= PHY_INT_ENERGYON;
166
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
167
- }
168
- phy_update_irq(s);
169
-}
170
-
171
static void lan9118_set_link(NetClientState *nc)
172
{
173
- phy_update_link(qemu_get_nic_opaque(nc));
174
-}
175
-
176
-static void phy_reset(lan9118_state *s)
177
-{
178
- s->phy_status = 0x7809;
179
- s->phy_control = 0x3000;
180
- s->phy_advertise = 0x01e1;
181
- s->phy_int_mask = 0;
182
- s->phy_int = 0;
183
- phy_update_link(s);
184
+ lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii,
185
+ nc->link_down);
186
}
187
188
static void lan9118_reset(DeviceState *d)
189
@@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d)
190
s->read_word_n = 0;
191
s->write_word_n = 0;
192
193
- phy_reset(s);
194
-
195
s->eeprom_writable = 0;
196
lan9118_reload_eeprom(s);
197
}
23
@@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s)
198
@@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s)
24
n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511;
199
uint32_t status;
25
s->tx_status_fifo[n] = status;
200
26
s->tx_status_fifo_used++;
201
/* FIXME: Honor TX disable, and allow queueing of packets. */
27
+
202
- if (s->phy_control & 0x4000) {
28
+ /*
203
+ if (s->mii.control & 0x4000) {
29
+ * Generate TSFL interrupt if TX FIFO level exceeds the level
204
/* This assumes the receive routine doesn't touch the VLANClient. */
30
+ * specified in the FIFO_INT TX Status Level field.
205
qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
31
+ */
206
} else {
32
+ if (s->tx_status_fifo_used > ((s->fifo_int >> 16) & 0xff)) {
207
@@ -XXX,XX +XXX,XX @@ static void tx_fifo_push(lan9118_state *s, uint32_t val)
33
+ s->int_sts |= TSFL_INT;
208
}
209
}
210
211
-static uint32_t do_phy_read(lan9118_state *s, int reg)
212
-{
213
- uint32_t val;
214
-
215
- switch (reg) {
216
- case 0: /* Basic Control */
217
- return s->phy_control;
218
- case 1: /* Basic Status */
219
- return s->phy_status;
220
- case 2: /* ID1 */
221
- return 0x0007;
222
- case 3: /* ID2 */
223
- return 0xc0d1;
224
- case 4: /* Auto-neg advertisement */
225
- return s->phy_advertise;
226
- case 5: /* Auto-neg Link Partner Ability */
227
- return 0x0f71;
228
- case 6: /* Auto-neg Expansion */
229
- return 1;
230
- /* TODO 17, 18, 27, 29, 30, 31 */
231
- case 29: /* Interrupt source. */
232
- val = s->phy_int;
233
- s->phy_int = 0;
234
- phy_update_irq(s);
235
- return val;
236
- case 30: /* Interrupt mask */
237
- return s->phy_int_mask;
238
- default:
239
- qemu_log_mask(LOG_GUEST_ERROR,
240
- "do_phy_read: PHY read reg %d\n", reg);
241
- return 0;
242
- }
243
-}
244
-
245
-static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
246
-{
247
- switch (reg) {
248
- case 0: /* Basic Control */
249
- if (val & 0x8000) {
250
- phy_reset(s);
251
- break;
252
- }
253
- s->phy_control = val & 0x7980;
254
- /* Complete autonegotiation immediately. */
255
- if (val & 0x1000) {
256
- s->phy_status |= 0x0020;
257
- }
258
- break;
259
- case 4: /* Auto-neg advertisement */
260
- s->phy_advertise = (val & 0x2d7f) | 0x80;
261
- break;
262
- /* TODO 17, 18, 27, 31 */
263
- case 30: /* Interrupt mask */
264
- s->phy_int_mask = val & 0xff;
265
- phy_update_irq(s);
266
- break;
267
- default:
268
- qemu_log_mask(LOG_GUEST_ERROR,
269
- "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
270
- }
271
-}
272
-
273
static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
274
{
275
switch (reg) {
276
@@ -XXX,XX +XXX,XX @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
277
if (val & 2) {
278
DPRINTF("PHY write %d = 0x%04x\n",
279
(val >> 6) & 0x1f, s->mac_mii_data);
280
- do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
281
+ lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data);
282
} else {
283
- s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
284
+ s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f);
285
DPRINTF("PHY read %d = 0x%04x\n",
286
(val >> 6) & 0x1f, s->mac_mii_data);
287
}
288
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
289
break;
290
case CSR_PMT_CTRL:
291
if (val & 0x400) {
292
- phy_reset(s);
293
+ lan9118_phy_reset(&s->mii);
294
}
295
s->pmt_ctrl &= ~0x34e;
296
s->pmt_ctrl |= (val & 0x34e);
297
@@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp)
298
const MemoryRegionOps *mem_ops =
299
s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops;
300
301
+ qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0);
302
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
303
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
304
+ return;
34
+ }
305
+ }
35
if (s->tx_status_fifo_used == 512) {
306
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
36
s->int_sts |= TSFF_INT;
307
+
37
/* TODO: Stop transmission. */
308
memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
309
"lan9118-mmio", 0x100);
310
sysbus_init_mmio(sbd, &s->mmio);
311
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
312
new file mode 100644
313
index XXXXXXX..XXXXXXX
314
--- /dev/null
315
+++ b/hw/net/lan9118_phy.c
316
@@ -XXX,XX +XXX,XX @@
317
+/*
318
+ * SMSC LAN9118 PHY emulation
319
+ *
320
+ * Copyright (c) 2009 CodeSourcery, LLC.
321
+ * Written by Paul Brook
322
+ *
323
+ * This code is licensed under the GNU GPL v2
324
+ *
325
+ * Contributions after 2012-01-13 are licensed under the terms of the
326
+ * GNU GPL, version 2 or (at your option) any later version.
327
+ */
328
+
329
+#include "qemu/osdep.h"
330
+#include "hw/net/lan9118_phy.h"
331
+#include "hw/irq.h"
332
+#include "hw/resettable.h"
333
+#include "migration/vmstate.h"
334
+#include "qemu/log.h"
335
+
336
+#define PHY_INT_ENERGYON (1 << 7)
337
+#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
338
+#define PHY_INT_FAULT (1 << 5)
339
+#define PHY_INT_DOWN (1 << 4)
340
+#define PHY_INT_AUTONEG_LP (1 << 3)
341
+#define PHY_INT_PARFAULT (1 << 2)
342
+#define PHY_INT_AUTONEG_PAGE (1 << 1)
343
+
344
+static void lan9118_phy_update_irq(Lan9118PhyState *s)
345
+{
346
+ qemu_set_irq(s->irq, !!(s->ints & s->int_mask));
347
+}
348
+
349
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
350
+{
351
+ uint16_t val;
352
+
353
+ switch (reg) {
354
+ case 0: /* Basic Control */
355
+ return s->control;
356
+ case 1: /* Basic Status */
357
+ return s->status;
358
+ case 2: /* ID1 */
359
+ return 0x0007;
360
+ case 3: /* ID2 */
361
+ return 0xc0d1;
362
+ case 4: /* Auto-neg advertisement */
363
+ return s->advertise;
364
+ case 5: /* Auto-neg Link Partner Ability */
365
+ return 0x0f71;
366
+ case 6: /* Auto-neg Expansion */
367
+ return 1;
368
+ /* TODO 17, 18, 27, 29, 30, 31 */
369
+ case 29: /* Interrupt source. */
370
+ val = s->ints;
371
+ s->ints = 0;
372
+ lan9118_phy_update_irq(s);
373
+ return val;
374
+ case 30: /* Interrupt mask */
375
+ return s->int_mask;
376
+ default:
377
+ qemu_log_mask(LOG_GUEST_ERROR,
378
+ "lan9118_phy_read: PHY read reg %d\n", reg);
379
+ return 0;
380
+ }
381
+}
382
+
383
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
384
+{
385
+ switch (reg) {
386
+ case 0: /* Basic Control */
387
+ if (val & 0x8000) {
388
+ lan9118_phy_reset(s);
389
+ break;
390
+ }
391
+ s->control = val & 0x7980;
392
+ /* Complete autonegotiation immediately. */
393
+ if (val & 0x1000) {
394
+ s->status |= 0x0020;
395
+ }
396
+ break;
397
+ case 4: /* Auto-neg advertisement */
398
+ s->advertise = (val & 0x2d7f) | 0x80;
399
+ break;
400
+ /* TODO 17, 18, 27, 31 */
401
+ case 30: /* Interrupt mask */
402
+ s->int_mask = val & 0xff;
403
+ lan9118_phy_update_irq(s);
404
+ break;
405
+ default:
406
+ qemu_log_mask(LOG_GUEST_ERROR,
407
+ "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
408
+ }
409
+}
410
+
411
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
412
+{
413
+ s->link_down = link_down;
414
+
415
+ /* Autonegotiation status mirrors link status. */
416
+ if (link_down) {
417
+ s->status &= ~0x0024;
418
+ s->ints |= PHY_INT_DOWN;
419
+ } else {
420
+ s->status |= 0x0024;
421
+ s->ints |= PHY_INT_ENERGYON;
422
+ s->ints |= PHY_INT_AUTONEG_COMPLETE;
423
+ }
424
+ lan9118_phy_update_irq(s);
425
+}
426
+
427
+void lan9118_phy_reset(Lan9118PhyState *s)
428
+{
429
+ s->control = 0x3000;
430
+ s->status = 0x7809;
431
+ s->advertise = 0x01e1;
432
+ s->int_mask = 0;
433
+ s->ints = 0;
434
+ lan9118_phy_update_link(s, s->link_down);
435
+}
436
+
437
+static void lan9118_phy_reset_hold(Object *obj, ResetType type)
438
+{
439
+ Lan9118PhyState *s = LAN9118_PHY(obj);
440
+
441
+ lan9118_phy_reset(s);
442
+}
443
+
444
+static void lan9118_phy_init(Object *obj)
445
+{
446
+ Lan9118PhyState *s = LAN9118_PHY(obj);
447
+
448
+ qdev_init_gpio_out(DEVICE(s), &s->irq, 1);
449
+}
450
+
451
+static const VMStateDescription vmstate_lan9118_phy = {
452
+ .name = "lan9118-phy",
453
+ .version_id = 1,
454
+ .minimum_version_id = 1,
455
+ .fields = (const VMStateField[]) {
456
+ VMSTATE_UINT16(control, Lan9118PhyState),
457
+ VMSTATE_UINT16(status, Lan9118PhyState),
458
+ VMSTATE_UINT16(advertise, Lan9118PhyState),
459
+ VMSTATE_UINT16(ints, Lan9118PhyState),
460
+ VMSTATE_UINT16(int_mask, Lan9118PhyState),
461
+ VMSTATE_BOOL(link_down, Lan9118PhyState),
462
+ VMSTATE_END_OF_LIST()
463
+ }
464
+};
465
+
466
+static void lan9118_phy_class_init(ObjectClass *klass, void *data)
467
+{
468
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
469
+ DeviceClass *dc = DEVICE_CLASS(klass);
470
+
471
+ rc->phases.hold = lan9118_phy_reset_hold;
472
+ dc->vmsd = &vmstate_lan9118_phy;
473
+}
474
+
475
+static const TypeInfo types[] = {
476
+ {
477
+ .name = TYPE_LAN9118_PHY,
478
+ .parent = TYPE_SYS_BUS_DEVICE,
479
+ .instance_size = sizeof(Lan9118PhyState),
480
+ .instance_init = lan9118_phy_init,
481
+ .class_init = lan9118_phy_class_init,
482
+ }
483
+};
484
+
485
+DEFINE_TYPES(types)
486
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
487
index XXXXXXX..XXXXXXX 100644
488
--- a/hw/net/Kconfig
489
+++ b/hw/net/Kconfig
490
@@ -XXX,XX +XXX,XX @@ config VMXNET3_PCI
491
config SMC91C111
492
bool
493
494
+config LAN9118_PHY
495
+ bool
496
+
497
config LAN9118
498
bool
499
+ select LAN9118_PHY
500
select PTIMER
501
502
config NE2000_ISA
503
diff --git a/hw/net/meson.build b/hw/net/meson.build
504
index XXXXXXX..XXXXXXX 100644
505
--- a/hw/net/meson.build
506
+++ b/hw/net/meson.build
507
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c'))
508
509
system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c'))
510
system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c'))
511
+system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c'))
512
system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c'))
513
system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c'))
514
system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c'))
38
--
515
--
39
2.25.1
516
2.34.1
diff view generated by jsdifflib
New patch
[PULL 02/72] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
1
From: Bernhard Beschow <shentey@gmail.com>
1
2
3
imx_fec models the same PHY as lan9118_phy. The code is almost the same with
4
imx_fec having more logging and tracing. Merge these improvements into
5
lan9118_phy and reuse in imx_fec to fix the code duplication.
6
7
Some migration state how resides in the new device model which breaks migration
8
compatibility for the following machines:
9
* imx25-pdk
10
* sabrelite
11
* mcimx7d-sabre
12
* mcimx6ul-evk
13
14
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
15
Tested-by: Guenter Roeck <linux@roeck-us.net>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20241102125724.532843-3-shentey@gmail.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
include/hw/net/imx_fec.h | 9 ++-
21
hw/net/imx_fec.c | 146 ++++-----------------------------------
22
hw/net/lan9118_phy.c | 82 ++++++++++++++++------
23
hw/net/Kconfig | 1 +
24
hw/net/trace-events | 10 +--
25
5 files changed, 85 insertions(+), 163 deletions(-)
26
27
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/include/hw/net/imx_fec.h
30
+++ b/include/hw/net/imx_fec.h
31
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC)
32
#define TYPE_IMX_ENET "imx.enet"
33
34
#include "hw/sysbus.h"
35
+#include "hw/net/lan9118_phy.h"
36
+#include "hw/irq.h"
37
#include "net/net.h"
38
39
#define ENET_EIR 1
40
@@ -XXX,XX +XXX,XX @@ struct IMXFECState {
41
uint32_t tx_descriptor[ENET_TX_RING_NUM];
42
uint32_t tx_ring_num;
43
44
- uint32_t phy_status;
45
- uint32_t phy_control;
46
- uint32_t phy_advertise;
47
- uint32_t phy_int;
48
- uint32_t phy_int_mask;
49
+ Lan9118PhyState mii;
50
+ IRQState mii_irq;
51
uint32_t phy_num;
52
bool phy_connected;
53
struct IMXFECState *phy_consumer;
54
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/net/imx_fec.c
57
+++ b/hw/net/imx_fec.c
58
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth_txdescs = {
59
60
static const VMStateDescription vmstate_imx_eth = {
61
.name = TYPE_IMX_FEC,
62
- .version_id = 2,
63
- .minimum_version_id = 2,
64
+ .version_id = 3,
65
+ .minimum_version_id = 3,
66
.fields = (const VMStateField[]) {
67
VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX),
68
VMSTATE_UINT32(rx_descriptor, IMXFECState),
69
VMSTATE_UINT32(tx_descriptor[0], IMXFECState),
70
- VMSTATE_UINT32(phy_status, IMXFECState),
71
- VMSTATE_UINT32(phy_control, IMXFECState),
72
- VMSTATE_UINT32(phy_advertise, IMXFECState),
73
- VMSTATE_UINT32(phy_int, IMXFECState),
74
- VMSTATE_UINT32(phy_int_mask, IMXFECState),
75
VMSTATE_END_OF_LIST()
76
},
77
.subsections = (const VMStateDescription * const []) {
78
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth = {
79
},
80
};
81
82
-#define PHY_INT_ENERGYON (1 << 7)
83
-#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
84
-#define PHY_INT_FAULT (1 << 5)
85
-#define PHY_INT_DOWN (1 << 4)
86
-#define PHY_INT_AUTONEG_LP (1 << 3)
87
-#define PHY_INT_PARFAULT (1 << 2)
88
-#define PHY_INT_AUTONEG_PAGE (1 << 1)
89
-
90
static void imx_eth_update(IMXFECState *s);
91
92
/*
93
@@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s);
94
* For now we don't handle any GPIO/interrupt line, so the OS will
95
* have to poll for the PHY status.
96
*/
97
-static void imx_phy_update_irq(IMXFECState *s)
98
+static void imx_phy_update_irq(void *opaque, int n, int level)
99
{
100
- imx_eth_update(s);
101
-}
102
-
103
-static void imx_phy_update_link(IMXFECState *s)
104
-{
105
- /* Autonegotiation status mirrors link status. */
106
- if (qemu_get_queue(s->nic)->link_down) {
107
- trace_imx_phy_update_link("down");
108
- s->phy_status &= ~0x0024;
109
- s->phy_int |= PHY_INT_DOWN;
110
- } else {
111
- trace_imx_phy_update_link("up");
112
- s->phy_status |= 0x0024;
113
- s->phy_int |= PHY_INT_ENERGYON;
114
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
115
- }
116
- imx_phy_update_irq(s);
117
+ imx_eth_update(opaque);
118
}
119
120
static void imx_eth_set_link(NetClientState *nc)
121
{
122
- imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
123
-}
124
-
125
-static void imx_phy_reset(IMXFECState *s)
126
-{
127
- trace_imx_phy_reset();
128
-
129
- s->phy_status = 0x7809;
130
- s->phy_control = 0x3000;
131
- s->phy_advertise = 0x01e1;
132
- s->phy_int_mask = 0;
133
- s->phy_int = 0;
134
- imx_phy_update_link(s);
135
+ lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii,
136
+ nc->link_down);
137
}
138
139
static uint32_t imx_phy_read(IMXFECState *s, int reg)
140
{
141
- uint32_t val;
142
uint32_t phy = reg / 32;
143
144
if (!s->phy_connected) {
145
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
146
147
reg %= 32;
148
149
- switch (reg) {
150
- case 0: /* Basic Control */
151
- val = s->phy_control;
152
- break;
153
- case 1: /* Basic Status */
154
- val = s->phy_status;
155
- break;
156
- case 2: /* ID1 */
157
- val = 0x0007;
158
- break;
159
- case 3: /* ID2 */
160
- val = 0xc0d1;
161
- break;
162
- case 4: /* Auto-neg advertisement */
163
- val = s->phy_advertise;
164
- break;
165
- case 5: /* Auto-neg Link Partner Ability */
166
- val = 0x0f71;
167
- break;
168
- case 6: /* Auto-neg Expansion */
169
- val = 1;
170
- break;
171
- case 29: /* Interrupt source. */
172
- val = s->phy_int;
173
- s->phy_int = 0;
174
- imx_phy_update_irq(s);
175
- break;
176
- case 30: /* Interrupt mask */
177
- val = s->phy_int_mask;
178
- break;
179
- case 17:
180
- case 18:
181
- case 27:
182
- case 31:
183
- qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n",
184
- TYPE_IMX_FEC, __func__, reg);
185
- val = 0;
186
- break;
187
- default:
188
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
189
- TYPE_IMX_FEC, __func__, reg);
190
- val = 0;
191
- break;
192
- }
193
-
194
- trace_imx_phy_read(val, phy, reg);
195
-
196
- return val;
197
+ return lan9118_phy_read(&s->mii, reg);
198
}
199
200
static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
201
@@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
202
203
reg %= 32;
204
205
- trace_imx_phy_write(val, phy, reg);
206
-
207
- switch (reg) {
208
- case 0: /* Basic Control */
209
- if (val & 0x8000) {
210
- imx_phy_reset(s);
211
- } else {
212
- s->phy_control = val & 0x7980;
213
- /* Complete autonegotiation immediately. */
214
- if (val & 0x1000) {
215
- s->phy_status |= 0x0020;
216
- }
217
- }
218
- break;
219
- case 4: /* Auto-neg advertisement */
220
- s->phy_advertise = (val & 0x2d7f) | 0x80;
221
- break;
222
- case 30: /* Interrupt mask */
223
- s->phy_int_mask = val & 0xff;
224
- imx_phy_update_irq(s);
225
- break;
226
- case 17:
227
- case 18:
228
- case 27:
229
- case 31:
230
- qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n",
231
- TYPE_IMX_FEC, __func__, reg);
232
- break;
233
- default:
234
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
235
- TYPE_IMX_FEC, __func__, reg);
236
- break;
237
- }
238
+ lan9118_phy_write(&s->mii, reg, val);
239
}
240
241
static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr)
242
@@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d)
243
244
s->rx_descriptor = 0;
245
memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor));
246
-
247
- /* We also reset the PHY */
248
- imx_phy_reset(s);
249
}
250
251
static uint32_t imx_default_read(IMXFECState *s, uint32_t index)
252
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
253
sysbus_init_irq(sbd, &s->irq[0]);
254
sysbus_init_irq(sbd, &s->irq[1]);
255
256
+ qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0);
257
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
258
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
259
+ return;
260
+ }
261
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
262
+
263
qemu_macaddr_default_if_unset(&s->conf.macaddr);
264
265
s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf,
266
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
267
index XXXXXXX..XXXXXXX 100644
268
--- a/hw/net/lan9118_phy.c
269
+++ b/hw/net/lan9118_phy.c
270
@@ -XXX,XX +XXX,XX @@
271
* Copyright (c) 2009 CodeSourcery, LLC.
272
* Written by Paul Brook
273
*
274
+ * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
275
+ *
276
* This code is licensed under the GNU GPL v2
277
*
278
* Contributions after 2012-01-13 are licensed under the terms of the
279
@@ -XXX,XX +XXX,XX @@
280
#include "hw/resettable.h"
281
#include "migration/vmstate.h"
282
#include "qemu/log.h"
283
+#include "trace.h"
284
285
#define PHY_INT_ENERGYON (1 << 7)
286
#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
287
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
288
289
switch (reg) {
290
case 0: /* Basic Control */
291
- return s->control;
292
+ val = s->control;
293
+ break;
294
case 1: /* Basic Status */
295
- return s->status;
296
+ val = s->status;
297
+ break;
298
case 2: /* ID1 */
299
- return 0x0007;
300
+ val = 0x0007;
301
+ break;
302
case 3: /* ID2 */
303
- return 0xc0d1;
304
+ val = 0xc0d1;
305
+ break;
306
case 4: /* Auto-neg advertisement */
307
- return s->advertise;
308
+ val = s->advertise;
309
+ break;
310
case 5: /* Auto-neg Link Partner Ability */
311
- return 0x0f71;
312
+ val = 0x0f71;
313
+ break;
314
case 6: /* Auto-neg Expansion */
315
- return 1;
316
- /* TODO 17, 18, 27, 29, 30, 31 */
317
+ val = 1;
318
+ break;
319
case 29: /* Interrupt source. */
320
val = s->ints;
321
s->ints = 0;
322
lan9118_phy_update_irq(s);
323
- return val;
324
+ break;
325
case 30: /* Interrupt mask */
326
- return s->int_mask;
327
+ val = s->int_mask;
328
+ break;
329
+ case 17:
330
+ case 18:
331
+ case 27:
332
+ case 31:
333
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
334
+ __func__, reg);
335
+ val = 0;
336
+ break;
337
default:
338
- qemu_log_mask(LOG_GUEST_ERROR,
339
- "lan9118_phy_read: PHY read reg %d\n", reg);
340
- return 0;
341
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
342
+ __func__, reg);
343
+ val = 0;
344
+ break;
345
}
346
+
347
+ trace_lan9118_phy_read(val, reg);
348
+
349
+ return val;
350
}
351
352
void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
353
{
354
+ trace_lan9118_phy_write(val, reg);
355
+
356
switch (reg) {
357
case 0: /* Basic Control */
358
if (val & 0x8000) {
359
lan9118_phy_reset(s);
360
- break;
361
- }
362
- s->control = val & 0x7980;
363
- /* Complete autonegotiation immediately. */
364
- if (val & 0x1000) {
365
- s->status |= 0x0020;
366
+ } else {
367
+ s->control = val & 0x7980;
368
+ /* Complete autonegotiation immediately. */
369
+ if (val & 0x1000) {
370
+ s->status |= 0x0020;
371
+ }
372
}
373
break;
374
case 4: /* Auto-neg advertisement */
375
s->advertise = (val & 0x2d7f) | 0x80;
376
break;
377
- /* TODO 17, 18, 27, 31 */
378
case 30: /* Interrupt mask */
379
s->int_mask = val & 0xff;
380
lan9118_phy_update_irq(s);
381
break;
382
+ case 17:
383
+ case 18:
384
+ case 27:
385
+ case 31:
386
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
387
+ __func__, reg);
388
+ break;
389
default:
390
- qemu_log_mask(LOG_GUEST_ERROR,
391
- "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
392
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
393
+ __func__, reg);
394
+ break;
395
}
396
}
397
398
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
399
400
/* Autonegotiation status mirrors link status. */
401
if (link_down) {
402
+ trace_lan9118_phy_update_link("down");
403
s->status &= ~0x0024;
404
s->ints |= PHY_INT_DOWN;
405
} else {
406
+ trace_lan9118_phy_update_link("up");
407
s->status |= 0x0024;
408
s->ints |= PHY_INT_ENERGYON;
409
s->ints |= PHY_INT_AUTONEG_COMPLETE;
410
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
411
412
void lan9118_phy_reset(Lan9118PhyState *s)
413
{
414
+ trace_lan9118_phy_reset();
415
+
416
s->control = 0x3000;
417
s->status = 0x7809;
418
s->advertise = 0x01e1;
419
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_phy = {
420
.version_id = 1,
421
.minimum_version_id = 1,
422
.fields = (const VMStateField[]) {
423
- VMSTATE_UINT16(control, Lan9118PhyState),
424
VMSTATE_UINT16(status, Lan9118PhyState),
425
+ VMSTATE_UINT16(control, Lan9118PhyState),
426
VMSTATE_UINT16(advertise, Lan9118PhyState),
427
VMSTATE_UINT16(ints, Lan9118PhyState),
428
VMSTATE_UINT16(int_mask, Lan9118PhyState),
429
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
430
index XXXXXXX..XXXXXXX 100644
431
--- a/hw/net/Kconfig
432
+++ b/hw/net/Kconfig
433
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_SUN8I_EMAC
434
435
config IMX_FEC
436
bool
437
+ select LAN9118_PHY
438
439
config CADENCE
440
bool
441
diff --git a/hw/net/trace-events b/hw/net/trace-events
442
index XXXXXXX..XXXXXXX 100644
443
--- a/hw/net/trace-events
444
+++ b/hw/net/trace-events
445
@@ -XXX,XX +XXX,XX @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
446
allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
447
allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
448
449
+# lan9118_phy.c
450
+lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16
451
+lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16
452
+lan9118_phy_update_link(const char *s) "%s"
453
+lan9118_phy_reset(void) ""
454
+
455
# lance.c
456
lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x"
457
lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x"
458
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
459
i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
460
461
# imx_fec.c
462
-imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
463
imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)"
464
-imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
465
imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)"
466
-imx_phy_update_link(const char *s) "%s"
467
-imx_phy_reset(void) ""
468
imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
469
imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x"
470
imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit"
471
--
472
2.34.1
diff view generated by jsdifflib
[PULL 31/39] ui/curses: Avoid dynamic stack allocation
[PULL 03/72] hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Use autofree heap allocation instead of variable-length
3
Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and
4
array on the stack.
4
fixes the MSB of selector field to be zero, as specified in the datasheet.
5
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Fixes: 2a424990170b "LAN9118 emulation"
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
8
Tested-by: Guenter Roeck <linux@roeck-us.net>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20241102125724.532843-4-shentey@gmail.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220819153931.3147384-11-peter.maydell@linaro.org
10
---
12
---
11
ui/curses.c | 2 +-
13
hw/net/lan9118_phy.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
13
15
14
diff --git a/ui/curses.c b/ui/curses.c
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/ui/curses.c
18
--- a/hw/net/lan9118_phy.c
17
+++ b/ui/curses.c
19
+++ b/hw/net/lan9118_phy.c
18
@@ -XXX,XX +XXX,XX @@ static void curses_update(DisplayChangeListener *dcl,
20
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
19
int x, int y, int w, int h)
21
val = s->advertise;
20
{
22
break;
21
console_ch_t *line;
23
case 5: /* Auto-neg Link Partner Ability */
22
- cchar_t curses_line[width];
24
- val = 0x0f71;
23
+ g_autofree cchar_t *curses_line = g_new(cchar_t, width);
25
+ val = 0x0fe1;
24
wchar_t wch[CCHARW_MAX];
26
break;
25
attr_t attrs;
27
case 6: /* Auto-neg Expansion */
26
short colors;
28
val = 1;
27
--
29
--
28
2.25.1
30
2.34.1
29
30
diff view generated by jsdifflib
New patch
[PULL 04/72] hw/net/lan9118_phy: Reuse MII constants
1
From: Bernhard Beschow <shentey@gmail.com>
1
2
3
Prefer named constants over magic values for better readability.
4
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
7
Tested-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20241102125724.532843-5-shentey@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/net/mii.h | 6 +++++
12
hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++----------------
13
2 files changed, 46 insertions(+), 23 deletions(-)
14
15
diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/net/mii.h
18
+++ b/include/hw/net/mii.h
19
@@ -XXX,XX +XXX,XX @@
20
#define MII_BMSR_JABBER (1 << 1) /* Jabber detected */
21
#define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */
22
23
+#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */
24
#define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */
25
#define MII_ANAR_PAUSE (1 << 10) /* Try for pause */
26
#define MII_ANAR_TXFD (1 << 8)
27
@@ -XXX,XX +XXX,XX @@
28
#define MII_ANAR_10FD (1 << 6)
29
#define MII_ANAR_10 (1 << 5)
30
#define MII_ANAR_CSMACD (1 << 0)
31
+#define MII_ANAR_SELECT (0x001f) /* Selector bits */
32
33
#define MII_ANLPAR_ACK (1 << 14)
34
#define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */
35
@@ -XXX,XX +XXX,XX @@
36
#define RTL8201CP_PHYID1 0x0000
37
#define RTL8201CP_PHYID2 0x8201
38
39
+/* SMSC LAN9118 */
40
+#define SMSCLAN9118_PHYID1 0x0007
41
+#define SMSCLAN9118_PHYID2 0xc0d1
42
+
43
/* RealTek 8211E */
44
#define RTL8211E_PHYID1 0x001c
45
#define RTL8211E_PHYID2 0xc915
46
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/net/lan9118_phy.c
49
+++ b/hw/net/lan9118_phy.c
50
@@ -XXX,XX +XXX,XX @@
51
52
#include "qemu/osdep.h"
53
#include "hw/net/lan9118_phy.h"
54
+#include "hw/net/mii.h"
55
#include "hw/irq.h"
56
#include "hw/resettable.h"
57
#include "migration/vmstate.h"
58
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
59
uint16_t val;
60
61
switch (reg) {
62
- case 0: /* Basic Control */
63
+ case MII_BMCR:
64
val = s->control;
65
break;
66
- case 1: /* Basic Status */
67
+ case MII_BMSR:
68
val = s->status;
69
break;
70
- case 2: /* ID1 */
71
- val = 0x0007;
72
+ case MII_PHYID1:
73
+ val = SMSCLAN9118_PHYID1;
74
break;
75
- case 3: /* ID2 */
76
- val = 0xc0d1;
77
+ case MII_PHYID2:
78
+ val = SMSCLAN9118_PHYID2;
79
break;
80
- case 4: /* Auto-neg advertisement */
81
+ case MII_ANAR:
82
val = s->advertise;
83
break;
84
- case 5: /* Auto-neg Link Partner Ability */
85
- val = 0x0fe1;
86
+ case MII_ANLPAR:
87
+ val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 |
88
+ MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD |
89
+ MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
90
break;
91
- case 6: /* Auto-neg Expansion */
92
- val = 1;
93
+ case MII_ANER:
94
+ val = MII_ANER_NWAY;
95
break;
96
case 29: /* Interrupt source. */
97
val = s->ints;
98
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
99
trace_lan9118_phy_write(val, reg);
100
101
switch (reg) {
102
- case 0: /* Basic Control */
103
- if (val & 0x8000) {
104
+ case MII_BMCR:
105
+ if (val & MII_BMCR_RESET) {
106
lan9118_phy_reset(s);
107
} else {
108
- s->control = val & 0x7980;
109
+ s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 |
110
+ MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD |
111
+ MII_BMCR_CTST);
112
/* Complete autonegotiation immediately. */
113
- if (val & 0x1000) {
114
- s->status |= 0x0020;
115
+ if (val & MII_BMCR_AUTOEN) {
116
+ s->status |= MII_BMSR_AN_COMP;
117
}
118
}
119
break;
120
- case 4: /* Auto-neg advertisement */
121
- s->advertise = (val & 0x2d7f) | 0x80;
122
+ case MII_ANAR:
123
+ s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
124
+ MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
125
+ MII_ANAR_SELECT))
126
+ | MII_ANAR_TX;
127
break;
128
case 30: /* Interrupt mask */
129
s->int_mask = val & 0xff;
130
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
131
/* Autonegotiation status mirrors link status. */
132
if (link_down) {
133
trace_lan9118_phy_update_link("down");
134
- s->status &= ~0x0024;
135
+ s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST);
136
s->ints |= PHY_INT_DOWN;
137
} else {
138
trace_lan9118_phy_update_link("up");
139
- s->status |= 0x0024;
140
+ s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST;
141
s->ints |= PHY_INT_ENERGYON;
142
s->ints |= PHY_INT_AUTONEG_COMPLETE;
143
}
144
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_reset(Lan9118PhyState *s)
145
{
146
trace_lan9118_phy_reset();
147
148
- s->control = 0x3000;
149
- s->status = 0x7809;
150
- s->advertise = 0x01e1;
151
+ s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100;
152
+ s->status = MII_BMSR_100TX_FD
153
+ | MII_BMSR_100TX_HD
154
+ | MII_BMSR_10T_FD
155
+ | MII_BMSR_10T_HD
156
+ | MII_BMSR_AUTONEG
157
+ | MII_BMSR_EXTCAP;
158
+ s->advertise = MII_ANAR_TXFD
159
+ | MII_ANAR_TX
160
+ | MII_ANAR_10FD
161
+ | MII_ANAR_10
162
+ | MII_ANAR_CSMACD;
163
s->int_mask = 0;
164
s->ints = 0;
165
lan9118_phy_update_link(s, s->link_down);
166
--
167
2.34.1
diff view generated by jsdifflib
[PULL 19/39] target/arm: Add is_secure parameter to get_phys_addr_pmsav5
[PULL 05/72] hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Remove the use of regime_is_secure from get_phys_addr_pmsav5.
3
The real device advertises this mode and the device model already advertises
4
100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to
5
make the model more realistic.
4
6
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220822152741.1617527-21-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
9
Tested-by: Guenter Roeck <linux@roeck-us.net>
10
Message-id: 20241102125724.532843-6-shentey@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
target/arm/ptw.c | 4 ++--
13
hw/net/lan9118_phy.c | 4 ++--
12
1 file changed, 2 insertions(+), 2 deletions(-)
14
1 file changed, 2 insertions(+), 2 deletions(-)
13
15
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/ptw.c
18
--- a/hw/net/lan9118_phy.c
17
+++ b/target/arm/ptw.c
19
+++ b/hw/net/lan9118_phy.c
18
@@ -XXX,XX +XXX,XX @@ do_fault:
20
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
19
21
break;
20
static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
22
case MII_ANAR:
21
MMUAccessType access_type, ARMMMUIdx mmu_idx,
23
s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
22
- GetPhysAddrResult *result,
24
- MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
23
+ bool is_secure, GetPhysAddrResult *result,
25
- MII_ANAR_SELECT))
24
ARMMMUFaultInfo *fi)
26
+ MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD |
25
{
27
+ MII_ANAR_10 | MII_ANAR_SELECT))
26
int n;
28
| MII_ANAR_TX;
27
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
29
break;
28
} else {
30
case 30: /* Interrupt mask */
29
/* Pre-v7 MPU */
30
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
31
- result, fi);
32
+ is_secure, result, fi);
33
}
34
qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
35
" mmu_idx %u -> %s (prot %c%c%c)\n",
36
--
31
--
37
2.25.1
32
2.34.1
38
39
diff view generated by jsdifflib
[PULL 12/39] target/arm: Add is_secure parameter to v8m_security_lookup
[PULL 06/72] fpu: handle raising Invalid for infzero in pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
For IEEE fused multiply-add, the (0 * inf) + NaN case should raise
2
Invalid for the multiplication of 0 by infinity. Currently we handle
3
this in the per-architecture ifdef ladder in pickNaNMulAdd().
4
However, since this isn't really architecture specific we can hoist
5
it up to the generic code.
2
6
3
Remove the use of regime_is_secure from v8m_security_lookup,
7
For the cases where the infzero test in pickNaNMulAdd was
4
passing the new parameter to the lookup instead.
8
returning 2, we can delete the check entirely and allow the
9
code to fall into the normal pick-a-NaN handling, because this
10
will return 2 anyway (input 'c' being the only NaN in this case).
11
For the cases where infzero was returning 3 to indicate "return
12
the default NaN", we must retain that "return 3".
5
13
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
14
For Arm, this looks like it might be a behaviour change because we
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
used to set float_flag_invalid | float_flag_invalid_imz only if C is
8
Message-id: 20220822152741.1617527-12-richard.henderson@linaro.org
16
a quiet NaN. However, it is not, because Arm target code never looks
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we
18
already raised float_flag_invalid via the "abc_mask &
19
float_cmask_snan" check in pick_nan_muladd.
20
21
For any target architecture using the "default implementation" at the
22
bottom of the ifdef, this is a behaviour change but will be fixing a
23
bug (where we failed to raise the Invalid exception for (0 * inf +
24
QNaN). The architectures using the default case are:
25
* hppa
26
* i386
27
* sh4
28
* tricore
29
30
The x86, Tricore and SH4 CPU architecture manuals are clear that this
31
should have raised Invalid; HPPA is a bit vaguer but still seems
32
clear enough.
33
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
36
Message-id: 20241202131347.498124-2-peter.maydell@linaro.org
11
---
37
---
12
target/arm/internals.h | 2 +-
38
fpu/softfloat-parts.c.inc | 13 +++++++------
13
target/arm/m_helper.c | 9 ++++++---
39
fpu/softfloat-specialize.c.inc | 29 +----------------------------
14
target/arm/ptw.c | 9 +++++----
40
2 files changed, 8 insertions(+), 34 deletions(-)
15
3 files changed, 12 insertions(+), 8 deletions(-)
16
41
17
diff --git a/target/arm/internals.h b/target/arm/internals.h
42
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
18
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/internals.h
44
--- a/fpu/softfloat-parts.c.inc
20
+++ b/target/arm/internals.h
45
+++ b/fpu/softfloat-parts.c.inc
21
@@ -XXX,XX +XXX,XX @@ typedef struct V8M_SAttributes {
46
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
22
47
int ab_mask, int abc_mask)
23
void v8m_security_lookup(CPUARMState *env, uint32_t address,
48
{
24
MMUAccessType access_type, ARMMMUIdx mmu_idx,
49
int which;
25
- V8M_SAttributes *sattrs);
50
+ bool infzero = (ab_mask == float_cmask_infzero);
26
+ bool secure, V8M_SAttributes *sattrs);
51
27
52
if (unlikely(abc_mask & float_cmask_snan)) {
28
/* Cacheability and shareability attributes for a memory access */
53
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
29
typedef struct ARMCacheAttrs {
54
}
30
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
55
56
- which = pickNaNMulAdd(a->cls, b->cls, c->cls,
57
- ab_mask == float_cmask_infzero, s);
58
+ if (infzero) {
59
+ /* This is (0 * inf) + NaN or (inf * 0) + NaN */
60
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
61
+ }
62
+
63
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
64
65
if (s->default_nan_mode || which == 3) {
66
- /*
67
- * Note that this check is after pickNaNMulAdd so that function
68
- * has an opportunity to set the Invalid flag for infzero.
69
- */
70
parts_default_nan(a, s);
71
return a;
72
}
73
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
31
index XXXXXXX..XXXXXXX 100644
74
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/m_helper.c
75
--- a/fpu/softfloat-specialize.c.inc
33
+++ b/target/arm/m_helper.c
76
+++ b/fpu/softfloat-specialize.c.inc
34
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
77
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
78
* the default NaN
36
V8M_SAttributes sattrs = {};
79
*/
37
80
if (infzero && is_qnan(c_cls)) {
38
- v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs);
81
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
39
+ v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
82
return 3;
40
+ targets_secure, &sattrs);
41
if (sattrs.ns) {
42
attrs.secure = false;
43
} else if (!targets_secure) {
44
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
45
ARMMMUFaultInfo fi = {};
46
MemTxResult txres;
47
48
- v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
49
+ v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx,
50
+ regime_is_secure(env, mmu_idx), &sattrs);
51
if (!sattrs.nsc || sattrs.ns) {
52
/*
53
* This must be the second half of the insn, and it straddles a
54
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
55
}
83
}
56
84
57
if (env->v7m.secure) {
85
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
58
- v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs);
86
* case sets InvalidOp and returns the default NaN
59
+ v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
87
*/
60
+ targetsec, &sattrs);
88
if (infzero) {
61
nsr = sattrs.ns && r;
89
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
62
nsrw = sattrs.ns && rw;
90
return 3;
63
} else {
91
}
64
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
92
/* Prefer sNaN over qNaN, in the a, b, c order. */
65
index XXXXXXX..XXXXXXX 100644
93
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
66
--- a/target/arm/ptw.c
94
* For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
67
+++ b/target/arm/ptw.c
95
* case sets InvalidOp and returns the input value 'c'
68
@@ -XXX,XX +XXX,XX @@ static bool v8m_is_sau_exempt(CPUARMState *env,
96
*/
69
}
97
- if (infzero) {
70
98
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
71
void v8m_security_lookup(CPUARMState *env, uint32_t address,
99
- return 2;
72
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
100
- }
73
- V8M_SAttributes *sattrs)
101
/* Prefer sNaN over qNaN, in the c, a, b order. */
74
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
102
if (is_snan(c_cls)) {
75
+ bool is_secure, V8M_SAttributes *sattrs)
103
return 2;
76
{
104
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
77
/*
105
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
78
* Look up the security attributes for this address. Compare the
106
* case sets InvalidOp and returns the input value 'c'
79
@@ -XXX,XX +XXX,XX @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
107
*/
108
- if (infzero) {
109
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
110
- return 2;
111
- }
112
+
113
/* Prefer sNaN over qNaN, in the c, a, b order. */
114
if (is_snan(c_cls)) {
115
return 2;
116
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
117
* to return an input NaN if we have one (ie c) rather than generating
118
* a default NaN
119
*/
120
- if (infzero) {
121
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
122
- return 2;
123
- }
124
125
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
126
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
127
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
128
return 1;
80
}
129
}
81
130
#elif defined(TARGET_RISCV)
82
if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) {
131
- /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
83
- sattrs->ns = !regime_is_secure(env, mmu_idx);
132
- if (infzero) {
84
+ sattrs->ns = !is_secure;
133
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
85
return;
134
- }
135
return 3; /* default NaN */
136
#elif defined(TARGET_S390X)
137
if (infzero) {
138
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
139
return 3;
86
}
140
}
87
141
88
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
142
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
89
bool ret;
143
return 2;
90
144
}
91
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
145
#elif defined(TARGET_SPARC)
92
- v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs);
146
- /* For (inf,0,nan) return c. */
93
+ v8m_security_lookup(env, address, access_type, mmu_idx,
147
- if (infzero) {
94
+ secure, &sattrs);
148
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
95
if (access_type == MMU_INST_FETCH) {
149
- return 2;
96
/*
150
- }
97
* Instruction fetches always use the MMU bank and the
151
/* Prefer SNaN over QNaN, order C, B, A. */
152
if (is_snan(c_cls)) {
153
return 2;
154
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
155
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
156
* an input NaN if we have one (ie c).
157
*/
158
- if (infzero) {
159
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
160
- return 2;
161
- }
162
if (status->use_first_nan) {
163
if (is_nan(a_cls)) {
164
return 0;
98
--
165
--
99
2.25.1
166
2.34.1
100
101
diff view generated by jsdifflib
New patch
[PULL 07/72] fpu: Check for default_nan_mode before calling pickNaNMulAdd
1
If the target sets default_nan_mode then we're always going to return
2
the default NaN, and pickNaNMulAdd() no longer has any side effects.
3
For consistency with pickNaN(), check for default_nan_mode before
4
calling pickNaNMulAdd().
1
5
6
When we convert pickNaNMulAdd() to allow runtime selection of the NaN
7
propagation rule, this means we won't have to make the targets which
8
use default_nan_mode also set a propagation rule.
9
10
Since RiscV always uses default_nan_mode, this allows us to remove
11
its ifdef case from pickNaNMulAdd().
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-3-peter.maydell@linaro.org
16
---
17
fpu/softfloat-parts.c.inc | 8 ++++++--
18
fpu/softfloat-specialize.c.inc | 9 +++++++--
19
2 files changed, 13 insertions(+), 4 deletions(-)
20
21
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
22
index XXXXXXX..XXXXXXX 100644
23
--- a/fpu/softfloat-parts.c.inc
24
+++ b/fpu/softfloat-parts.c.inc
25
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
26
float_raise(float_flag_invalid | float_flag_invalid_imz, s);
27
}
28
29
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
30
+ if (s->default_nan_mode) {
31
+ which = 3;
32
+ } else {
33
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ }
35
36
- if (s->default_nan_mode || which == 3) {
37
+ if (which == 3) {
38
parts_default_nan(a, s);
39
return a;
40
}
41
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
42
index XXXXXXX..XXXXXXX 100644
43
--- a/fpu/softfloat-specialize.c.inc
44
+++ b/fpu/softfloat-specialize.c.inc
45
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
46
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
47
bool infzero, float_status *status)
48
{
49
+ /*
50
+ * We guarantee not to require the target to tell us how to
51
+ * pick a NaN if we're always returning the default NaN.
52
+ * But if we're not in default-NaN mode then the target must
53
+ * specify.
54
+ */
55
+ assert(!status->default_nan_mode);
56
#if defined(TARGET_ARM)
57
/* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
58
* the default NaN
59
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
60
} else {
61
return 1;
62
}
63
-#elif defined(TARGET_RISCV)
64
- return 3; /* default NaN */
65
#elif defined(TARGET_S390X)
66
if (infzero) {
67
return 3;
68
--
69
2.34.1
diff view generated by jsdifflib
New patch
[PULL 08/72] softfloat: Allow runtime choice of inf * 0 + NaN result
1
1
IEEE 758 does not define a fixed rule for what NaN to return in
2
the case of a fused multiply-add of inf * 0 + NaN. Different
3
architectures thus do different things:
4
* some return the default NaN
5
* some return the input NaN
6
* Arm returns the default NaN if the input NaN is quiet,
7
and the input NaN if it is signalling
8
9
We want to make this logic be runtime selected rather than
10
hardcoded into the binary, because:
11
* this will let us have multiple targets in one QEMU binary
12
* the Arm FEAT_AFP architectural feature includes letting
13
the guest select a NaN propagation rule at runtime
14
15
In this commit we add an enum for the propagation rule, the field in
16
float_status, and the corresponding getters and setters. We change
17
pickNaNMulAdd to honour this, but because all targets still leave
18
this field at its default 0 value, the fallback logic will pick the
19
rule type with the old ifdef ladder.
20
21
Note that four architectures both use the muladd softfloat functions
22
and did not have a branch of the ifdef ladder to specify their
23
behaviour (and so were ending up with the "default" case, probably
24
wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set
25
default_nan_mode, and so will never get into pickNaNMulAdd(). For
26
HPPA and i386 we retain the same behaviour as the old default-case,
27
which is to not ever return the default NaN. This might not be
28
correct but it is not a behaviour change.
29
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
32
Message-id: 20241202131347.498124-4-peter.maydell@linaro.org
33
---
34
include/fpu/softfloat-helpers.h | 11 ++++
35
include/fpu/softfloat-types.h | 23 +++++++++
36
fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++-----------
37
3 files changed, 95 insertions(+), 30 deletions(-)
38
39
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/include/fpu/softfloat-helpers.h
42
+++ b/include/fpu/softfloat-helpers.h
43
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
44
status->float_2nan_prop_rule = rule;
45
}
46
47
+static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
48
+ float_status *status)
49
+{
50
+ status->float_infzeronan_rule = rule;
51
+}
52
+
53
static inline void set_flush_to_zero(bool val, float_status *status)
54
{
55
status->flush_to_zero = val;
56
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
57
return status->float_2nan_prop_rule;
58
}
59
60
+static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
61
+{
62
+ return status->float_infzeronan_rule;
63
+}
64
+
65
static inline bool get_flush_to_zero(float_status *status)
66
{
67
return status->flush_to_zero;
68
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
69
index XXXXXXX..XXXXXXX 100644
70
--- a/include/fpu/softfloat-types.h
71
+++ b/include/fpu/softfloat-types.h
72
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
73
float_2nan_prop_x87,
74
} Float2NaNPropRule;
75
76
+/*
77
+ * Rule for result of fused multiply-add 0 * Inf + NaN.
78
+ * This must be a NaN, but implementations differ on whether this
79
+ * is the input NaN or the default NaN.
80
+ *
81
+ * You don't need to set this if default_nan_mode is enabled.
82
+ * When not in default-NaN mode, it is an error for the target
83
+ * not to set the rule in float_status if it uses muladd, and we
84
+ * will assert if we need to handle an input NaN and no rule was
85
+ * selected.
86
+ */
87
+typedef enum __attribute__((__packed__)) {
88
+ /* No propagation rule specified */
89
+ float_infzeronan_none = 0,
90
+ /* Result is never the default NaN (so always the input NaN) */
91
+ float_infzeronan_dnan_never,
92
+ /* Result is always the default NaN */
93
+ float_infzeronan_dnan_always,
94
+ /* Result is the default NaN if the input NaN is quiet */
95
+ float_infzeronan_dnan_if_qnan,
96
+} FloatInfZeroNaNRule;
97
+
98
/*
99
* Floating Point Status. Individual architectures may maintain
100
* several versions of float_status for different functions. The
101
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
102
FloatRoundMode float_rounding_mode;
103
FloatX80RoundPrec floatx80_rounding_precision;
104
Float2NaNPropRule float_2nan_prop_rule;
105
+ FloatInfZeroNaNRule float_infzeronan_rule;
106
bool tininess_before_rounding;
107
/* should denormalised results go to zero and set the inexact flag? */
108
bool flush_to_zero;
109
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
110
index XXXXXXX..XXXXXXX 100644
111
--- a/fpu/softfloat-specialize.c.inc
112
+++ b/fpu/softfloat-specialize.c.inc
113
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
114
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
115
bool infzero, float_status *status)
116
{
117
+ FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
118
+
119
/*
120
* We guarantee not to require the target to tell us how to
121
* pick a NaN if we're always returning the default NaN.
122
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
123
* specify.
124
*/
125
assert(!status->default_nan_mode);
126
+
127
+ if (rule == float_infzeronan_none) {
128
+ /*
129
+ * Temporarily fall back to ifdef ladder
130
+ */
131
#if defined(TARGET_ARM)
132
- /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
133
- * the default NaN
134
- */
135
- if (infzero && is_qnan(c_cls)) {
136
- return 3;
137
+ /*
138
+ * For ARM, the (inf,zero,qnan) case returns the default NaN,
139
+ * but (inf,zero,snan) returns the input NaN.
140
+ */
141
+ rule = float_infzeronan_dnan_if_qnan;
142
+#elif defined(TARGET_MIPS)
143
+ if (snan_bit_is_one(status)) {
144
+ /*
145
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
146
+ * case sets InvalidOp and returns the default NaN
147
+ */
148
+ rule = float_infzeronan_dnan_always;
149
+ } else {
150
+ /*
151
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
152
+ * case sets InvalidOp and returns the input value 'c'
153
+ */
154
+ rule = float_infzeronan_dnan_never;
155
+ }
156
+#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
157
+ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
158
+ defined(TARGET_I386) || defined(TARGET_LOONGARCH)
159
+ /*
160
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
161
+ * case sets InvalidOp and returns the input value 'c'
162
+ */
163
+ /*
164
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
165
+ * to return an input NaN if we have one (ie c) rather than generating
166
+ * a default NaN
167
+ */
168
+ rule = float_infzeronan_dnan_never;
169
+#elif defined(TARGET_S390X)
170
+ rule = float_infzeronan_dnan_always;
171
+#endif
172
}
173
174
+ if (infzero) {
175
+ /*
176
+ * Inf * 0 + NaN -- some implementations return the default NaN here,
177
+ * and some return the input NaN.
178
+ */
179
+ switch (rule) {
180
+ case float_infzeronan_dnan_never:
181
+ return 2;
182
+ case float_infzeronan_dnan_always:
183
+ return 3;
184
+ case float_infzeronan_dnan_if_qnan:
185
+ return is_qnan(c_cls) ? 3 : 2;
186
+ default:
187
+ g_assert_not_reached();
188
+ }
189
+ }
190
+
191
+#if defined(TARGET_ARM)
192
+
193
/* This looks different from the ARM ARM pseudocode, because the ARM ARM
194
* puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
195
*/
196
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
197
}
198
#elif defined(TARGET_MIPS)
199
if (snan_bit_is_one(status)) {
200
- /*
201
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
202
- * case sets InvalidOp and returns the default NaN
203
- */
204
- if (infzero) {
205
- return 3;
206
- }
207
/* Prefer sNaN over qNaN, in the a, b, c order. */
208
if (is_snan(a_cls)) {
209
return 0;
210
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
211
return 2;
212
}
213
} else {
214
- /*
215
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
216
- * case sets InvalidOp and returns the input value 'c'
217
- */
218
/* Prefer sNaN over qNaN, in the c, a, b order. */
219
if (is_snan(c_cls)) {
220
return 2;
221
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
222
}
223
}
224
#elif defined(TARGET_LOONGARCH64)
225
- /*
226
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
227
- * case sets InvalidOp and returns the input value 'c'
228
- */
229
-
230
/* Prefer sNaN over qNaN, in the c, a, b order. */
231
if (is_snan(c_cls)) {
232
return 2;
233
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
234
return 1;
235
}
236
#elif defined(TARGET_PPC)
237
- /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
238
- * to return an input NaN if we have one (ie c) rather than generating
239
- * a default NaN
240
- */
241
-
242
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
243
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
244
*/
245
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
246
return 1;
247
}
248
#elif defined(TARGET_S390X)
249
- if (infzero) {
250
- return 3;
251
- }
252
-
253
if (is_snan(a_cls)) {
254
return 0;
255
} else if (is_snan(b_cls)) {
256
--
257
2.34.1
diff view generated by jsdifflib
[PULL 32/39] tests/unit/test-vmstate: Avoid dynamic stack allocation
[PULL 09/72] tests/fp: Explicitly set inf-zero-nan rule
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Explicitly set a rule in the softfloat tests for the inf-zero-nan
2
muladd special case. In meson.build we put -DTARGET_ARM in fpcflags,
3
and so we should select here the Arm rule of
4
float_infzeronan_dnan_if_qnan.
2
5
3
Use autofree heap allocation instead of variable-length
4
array on the stack.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220819153931.3147384-12-peter.maydell@linaro.org
8
Message-id: 20241202131347.498124-5-peter.maydell@linaro.org
10
---
9
---
11
tests/unit/test-vmstate.c | 7 +++----
10
tests/fp/fp-bench.c | 5 +++++
12
1 file changed, 3 insertions(+), 4 deletions(-)
11
tests/fp/fp-test.c | 5 +++++
12
2 files changed, 10 insertions(+)
13
13
14
diff --git a/tests/unit/test-vmstate.c b/tests/unit/test-vmstate.c
14
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tests/unit/test-vmstate.c
16
--- a/tests/fp/fp-bench.c
17
+++ b/tests/unit/test-vmstate.c
17
+++ b/tests/fp/fp-bench.c
18
@@ -XXX,XX +XXX,XX @@ static void save_buffer(const uint8_t *buf, size_t buf_size)
18
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
19
static void compare_vmstate(const uint8_t *wire, size_t size)
20
{
19
{
21
QEMUFile *f = open_test_file(false);
20
bench_func_t f;
22
- uint8_t result[size];
21
23
+ g_autofree uint8_t *result = g_malloc(size);
22
+ /*
24
23
+ * These implementation-defined choices for various things IEEE
25
/* read back as binary */
24
+ * doesn't specify match those used by the Arm architecture.
26
25
+ */
27
- g_assert_cmpint(qemu_get_buffer(f, result, sizeof(result)), ==,
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
28
- sizeof(result));
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
29
+ g_assert_cmpint(qemu_get_buffer(f, result, size), ==, size);
28
30
g_assert(!qemu_file_get_error(f));
29
f = bench_funcs[operation][precision];
31
30
g_assert(f);
32
/* Compare that what is on the file is the same that what we
31
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
33
expected to be there */
32
index XXXXXXX..XXXXXXX 100644
34
- SUCCESS(memcmp(result, wire, sizeof(result)));
33
--- a/tests/fp/fp-test.c
35
+ SUCCESS(memcmp(result, wire, size));
34
+++ b/tests/fp/fp-test.c
36
35
@@ -XXX,XX +XXX,XX @@ void run_test(void)
37
/* Must reach EOF */
36
{
38
qemu_get_byte(f);
37
unsigned int i;
38
39
+ /*
40
+ * These implementation-defined choices for various things IEEE
41
+ * doesn't specify match those used by the Arm architecture.
42
+ */
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
44
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
45
46
genCases_setLevel(test_level);
47
verCases_maxErrorCount = n_max_errors;
39
--
48
--
40
2.25.1
49
2.34.1
41
42
diff view generated by jsdifflib
New patch
[PULL 10/72] target/arm: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the Arm target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-6-peter.maydell@linaro.org
7
---
8
target/arm/cpu.c | 3 +++
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 4 insertions(+), 7 deletions(-)
11
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
17
* * tininess-before-rounding
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
20
+ * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
21
+ * and the input NaN if it is signalling
22
*/
23
static void arm_set_default_fp_behaviours(float_status *s)
24
{
25
set_float_detect_tininess(float_tininess_before_rounding, s);
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
28
}
29
30
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
32
index XXXXXXX..XXXXXXX 100644
33
--- a/fpu/softfloat-specialize.c.inc
34
+++ b/fpu/softfloat-specialize.c.inc
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
/*
37
* Temporarily fall back to ifdef ladder
38
*/
39
-#if defined(TARGET_ARM)
40
- /*
41
- * For ARM, the (inf,zero,qnan) case returns the default NaN,
42
- * but (inf,zero,snan) returns the input NaN.
43
- */
44
- rule = float_infzeronan_dnan_if_qnan;
45
-#elif defined(TARGET_MIPS)
46
+#if defined(TARGET_MIPS)
47
if (snan_bit_is_one(status)) {
48
/*
49
* For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
50
--
51
2.34.1
diff view generated by jsdifflib
New patch
[PULL 11/72] target/s390: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for s390, so we
2
can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-7-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_infzeronan_rule(float_infzeronan_dnan_always,
21
+ &env->fpu_status);
22
/* fall through */
23
case RESET_TYPE_S390_CPU_NORMAL:
24
env->psw.mask &= ~PSW_MASK_RI;
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
* a default NaN
31
*/
32
rule = float_infzeronan_dnan_never;
33
-#elif defined(TARGET_S390X)
34
- rule = float_infzeronan_dnan_always;
35
#endif
36
}
37
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/72] target/ppc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the PPC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-8-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 7 +++++++
9
fpu/softfloat-specialize.c.inc | 7 +------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
22
+ * to return an input NaN if we have one (ie c) rather than generating
23
+ * a default NaN
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
27
28
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
29
ppc_spr_t *spr = &env->spr_cb[i];
30
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
31
index XXXXXXX..XXXXXXX 100644
32
--- a/fpu/softfloat-specialize.c.inc
33
+++ b/fpu/softfloat-specialize.c.inc
34
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
*/
36
rule = float_infzeronan_dnan_never;
37
}
38
-#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
39
+#elif defined(TARGET_SPARC) || \
40
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
41
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
42
/*
43
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
44
* case sets InvalidOp and returns the input value 'c'
45
*/
46
- /*
47
- * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
48
- * to return an input NaN if we have one (ie c) rather than generating
49
- * a default NaN
50
- */
51
rule = float_infzeronan_dnan_never;
52
#endif
53
}
54
--
55
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/72] target/mips: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the MIPS target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-9-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 9 +++++++++
9
target/mips/msa.c | 4 ++++
10
fpu/softfloat-specialize.c.inc | 16 +---------------
11
3 files changed, 14 insertions(+), 15 deletions(-)
12
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/mips/fpu_helper.h
16
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_flush_mode(CPUMIPSState *env)
18
static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
{
20
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
21
+ FloatInfZeroNaNRule izn_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status);
28
set_default_nan_mode(!nan2008, &env->active_fpu.fp_status);
29
+ /*
30
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
31
+ * case sets InvalidOp and returns the default NaN.
32
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
33
+ * case sets InvalidOp and returns the input value 'c'.
34
+ */
35
+ izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
36
+ set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
37
}
38
39
static inline void restore_fp_status(CPUMIPSState *env)
40
diff --git a/target/mips/msa.c b/target/mips/msa.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/mips/msa.c
43
+++ b/target/mips/msa.c
44
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
45
46
/* set proper signanling bit meaning ("1" means "quiet") */
47
set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
48
+
49
+ /* Inf * 0 + NaN returns the input NaN */
50
+ set_float_infzeronan_rule(float_infzeronan_dnan_never,
51
+ &env->active_tc.msa_fp_status);
52
}
53
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
54
index XXXXXXX..XXXXXXX 100644
55
--- a/fpu/softfloat-specialize.c.inc
56
+++ b/fpu/softfloat-specialize.c.inc
57
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
58
/*
59
* Temporarily fall back to ifdef ladder
60
*/
61
-#if defined(TARGET_MIPS)
62
- if (snan_bit_is_one(status)) {
63
- /*
64
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
65
- * case sets InvalidOp and returns the default NaN
66
- */
67
- rule = float_infzeronan_dnan_always;
68
- } else {
69
- /*
70
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
71
- * case sets InvalidOp and returns the input value 'c'
72
- */
73
- rule = float_infzeronan_dnan_never;
74
- }
75
-#elif defined(TARGET_SPARC) || \
76
+#if defined(TARGET_SPARC) || \
77
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
78
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
79
/*
80
--
81
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/72] target/sparc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the SPARC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-10-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_SPARC) || \
34
- defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
35
+#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
36
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
37
/*
38
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/72] target/xtensa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the xtensa target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-11-peter.maydell@linaro.org
7
---
8
target/xtensa/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 +-
10
2 files changed, 3 insertions(+), 1 deletion(-)
11
12
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/xtensa/cpu.c
15
+++ b/target/xtensa/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
17
reset_mmu(env);
18
cs->halted = env->runstall;
19
#endif
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
set_no_signaling_nans(!dfpu, &env->fp_status);
23
xtensa_use_first_nan(env, !dfpu);
24
}
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
34
+#if defined(TARGET_HPPA) || \
35
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
36
/*
37
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 16/72] target/x86: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the x86 target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-12-peter.maydell@linaro.org
6
---
7
target/i386/tcg/fpu_helper.c | 7 +++++++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 8 insertions(+), 1 deletion(-)
10
11
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/i386/tcg/fpu_helper.c
14
+++ b/target/i386/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status);
18
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status);
19
+ /*
20
+ * Only SSE has multiply-add instructions. In the SDM Section 14.5.2
21
+ * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is
22
+ * specified -- for 0 * inf + NaN the input NaN is selected, and if
23
+ * there are multiple input NaNs they are selected in the order a, b, c.
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
26
}
27
28
static inline uint8_t save_exception_flags(CPUX86State *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
34
* Temporarily fall back to ifdef ladder
35
*/
36
#if defined(TARGET_HPPA) || \
37
- defined(TARGET_I386) || defined(TARGET_LOONGARCH)
38
+ defined(TARGET_LOONGARCH)
39
/*
40
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
41
* case sets InvalidOp and returns the input value 'c'
42
--
43
2.34.1
diff view generated by jsdifflib
New patch
[PULL 17/72] target/loongarch: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the loongarch target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-13-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 5 +++++
8
fpu/softfloat-specialize.c.inc | 7 +------
9
2 files changed, 6 insertions(+), 6 deletions(-)
10
11
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
16
&env->fp_status);
17
set_flush_to_zero(0, &env->fp_status);
18
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
19
+ /*
20
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
21
+ * case sets InvalidOp and returns the input value 'c'
22
+ */
23
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
}
25
26
int ieee_ex_to_loongarch(int xcpt)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
32
/*
33
* Temporarily fall back to ifdef ladder
34
*/
35
-#if defined(TARGET_HPPA) || \
36
- defined(TARGET_LOONGARCH)
37
- /*
38
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
- * case sets InvalidOp and returns the input value 'c'
40
- */
41
+#if defined(TARGET_HPPA)
42
rule = float_infzeronan_dnan_never;
43
#endif
44
}
45
--
46
2.34.1
diff view generated by jsdifflib
New patch
[PULL 18/72] target/hppa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the HPPA target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
As this is the last target to be converted to explicitly setting
5
the rule, we can remove the fallback code in pickNaNMulAdd()
6
entirely.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20241202131347.498124-14-peter.maydell@linaro.org
11
---
12
target/hppa/fpu_helper.c | 2 ++
13
fpu/softfloat-specialize.c.inc | 13 +------------
14
2 files changed, 3 insertions(+), 12 deletions(-)
15
16
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/hppa/fpu_helper.c
19
+++ b/target/hppa/fpu_helper.c
20
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
21
* HPPA does note implement a CPU reset method at all...
22
*/
23
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
24
+ /* For inf * 0 + NaN, return the input NaN */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
}
27
28
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
34
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
bool infzero, float_status *status)
36
{
37
- FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
38
-
39
/*
40
* We guarantee not to require the target to tell us how to
41
* pick a NaN if we're always returning the default NaN.
42
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
43
*/
44
assert(!status->default_nan_mode);
45
46
- if (rule == float_infzeronan_none) {
47
- /*
48
- * Temporarily fall back to ifdef ladder
49
- */
50
-#if defined(TARGET_HPPA)
51
- rule = float_infzeronan_dnan_never;
52
-#endif
53
- }
54
-
55
if (infzero) {
56
/*
57
* Inf * 0 + NaN -- some implementations return the default NaN here,
58
* and some return the input NaN.
59
*/
60
- switch (rule) {
61
+ switch (status->float_infzeronan_rule) {
62
case float_infzeronan_dnan_never:
63
return 2;
64
case float_infzeronan_dnan_always:
65
--
66
2.34.1
diff view generated by jsdifflib
New patch
[PULL 19/72] softfloat: Pass have_snan to pickNaNMulAdd
1
The new implementation of pickNaNMulAdd() will find it convenient
2
to know whether at least one of the three arguments to the muladd
3
was a signaling NaN. We already calculate that in the caller,
4
so pass it in as a new bool have_snan.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-15-peter.maydell@linaro.org
9
---
10
fpu/softfloat-parts.c.inc | 5 +++--
11
fpu/softfloat-specialize.c.inc | 2 +-
12
2 files changed, 4 insertions(+), 3 deletions(-)
13
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
16
--- a/fpu/softfloat-parts.c.inc
17
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
{
20
int which;
21
bool infzero = (ab_mask == float_cmask_infzero);
22
+ bool have_snan = (abc_mask & float_cmask_snan);
23
24
- if (unlikely(abc_mask & float_cmask_snan)) {
25
+ if (unlikely(have_snan)) {
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
27
}
28
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
30
if (s->default_nan_mode) {
31
which = 3;
32
} else {
33
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
35
}
36
37
if (which == 3) {
38
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
39
index XXXXXXX..XXXXXXX 100644
40
--- a/fpu/softfloat-specialize.c.inc
41
+++ b/fpu/softfloat-specialize.c.inc
42
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
43
| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
44
*----------------------------------------------------------------------------*/
45
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
46
- bool infzero, float_status *status)
47
+ bool infzero, bool have_snan, float_status *status)
48
{
49
/*
50
* We guarantee not to require the target to tell us how to
51
--
52
2.34.1
diff view generated by jsdifflib
[PULL 09/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8
[PULL 20/72] softfloat: Allow runtime choice of NaN propagation for muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
IEEE 758 does not define a fixed rule for which NaN to pick as the
2
2
result if both operands of a 3-operand fused multiply-add operation
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
are NaNs. As a result different architectures have ended up with
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
different rules for propagating NaNs.
5
Message-id: 20220822152741.1617527-9-richard.henderson@linaro.org
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
QEMU currently hardcodes the NaN propagation logic into the binary
7
because pickNaNMulAdd() has an ifdef ladder for different targets.
8
We want to make the propagation rule instead be selectable at
9
runtime, because:
10
* this will let us have multiple targets in one QEMU binary
11
* the Arm FEAT_AFP architectural feature includes letting
12
the guest select a NaN propagation rule at runtime
13
14
In this commit we add an enum for the propagation rule, the field in
15
float_status, and the corresponding getters and setters. We change
16
pickNaNMulAdd to honour this, but because all targets still leave
17
this field at its default 0 value, the fallback logic will pick the
18
rule type with the old ifdef ladder.
19
20
It's valid not to set a propagation rule if default_nan_mode is
21
enabled, because in that case there's no need to pick a NaN; all the
22
callers of pickNaNMulAdd() catch this case and skip calling it.
23
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20241202131347.498124-16-peter.maydell@linaro.org
8
---
27
---
9
target/arm/ptw.c | 28 ++++++++++++++--------------
28
include/fpu/softfloat-helpers.h | 11 +++
10
1 file changed, 14 insertions(+), 14 deletions(-)
29
include/fpu/softfloat-types.h | 55 +++++++++++
11
30
fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
31
3 files changed, 107 insertions(+), 126 deletions(-)
32
33
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
13
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/ptw.c
35
--- a/include/fpu/softfloat-helpers.h
15
+++ b/target/arm/ptw.c
36
+++ b/include/fpu/softfloat-helpers.h
16
@@ -XXX,XX +XXX,XX @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
37
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
17
38
status->float_2nan_prop_rule = rule;
18
static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
39
}
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
40
20
- hwaddr *phys_ptr, MemTxAttrs *txattrs,
41
+static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule,
21
- int *prot, target_ulong *page_size,
42
+ float_status *status)
22
+ GetPhysAddrResult *result,
43
+{
23
ARMMMUFaultInfo *fi)
44
+ status->float_3nan_prop_rule = rule;
45
+}
46
+
47
static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
48
float_status *status)
24
{
49
{
25
uint32_t secure = regime_is_secure(env, mmu_idx);
50
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
26
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
51
return status->float_2nan_prop_rule;
27
} else {
52
}
28
fi->type = ARMFault_QEMU_SFault;
53
29
}
54
+static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status)
30
- *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
55
+{
31
- *phys_ptr = address;
56
+ return status->float_3nan_prop_rule;
32
- *prot = 0;
57
+}
33
+ result->page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
58
+
34
+ result->phys = address;
59
static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
35
+ result->prot = 0;
60
{
36
return true;
61
return status->float_infzeronan_rule;
37
}
62
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
38
} else {
63
index XXXXXXX..XXXXXXX 100644
39
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
64
--- a/include/fpu/softfloat-types.h
40
* might downgrade a secure access to nonsecure.
65
+++ b/include/fpu/softfloat-types.h
41
*/
66
@@ -XXX,XX +XXX,XX @@ this code that are retained.
42
if (sattrs.ns) {
67
#ifndef SOFTFLOAT_TYPES_H
43
- txattrs->secure = false;
68
#define SOFTFLOAT_TYPES_H
44
+ result->attrs.secure = false;
69
45
} else if (!secure) {
70
+#include "hw/registerfields.h"
46
/*
71
+
47
* NS access to S memory must fault.
72
/*
48
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
73
* Software IEC/IEEE floating-point types.
49
* for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
74
*/
50
*/
75
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
51
fi->type = ARMFault_QEMU_SFault;
76
float_2nan_prop_x87,
52
- *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
77
} Float2NaNPropRule;
53
- *phys_ptr = address;
78
54
- *prot = 0;
79
+/*
55
+ result->page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
80
+ * 3-input NaN propagation rule, for fused multiply-add. Individual
56
+ result->phys = address;
81
+ * architectures have different rules for which input NaN is
57
+ result->prot = 0;
82
+ * propagated to the output when there is more than one NaN on the
58
return true;
83
+ * input.
59
}
84
+ *
85
+ * If default_nan_mode is enabled then it is valid not to set a NaN
86
+ * propagation rule, because the softfloat code guarantees not to try
87
+ * to pick a NaN to propagate in default NaN mode. When not in
88
+ * default-NaN mode, it is an error for the target not to set the rule
89
+ * in float_status if it uses a muladd, and we will assert if we need
90
+ * to handle an input NaN and no rule was selected.
91
+ *
92
+ * The naming scheme for Float3NaNPropRule values is:
93
+ * float_3nan_prop_s_abc:
94
+ * = "Prefer SNaN over QNaN, then operand A over B over C"
95
+ * float_3nan_prop_abc:
96
+ * = "Prefer A over B over C regardless of SNaN vs QNAN"
97
+ *
98
+ * For QEMU, the multiply-add operation is A * B + C.
99
+ */
100
+
101
+/*
102
+ * We set the Float3NaNPropRule enum values up so we can select the
103
+ * right value in pickNaNMulAdd in a data driven way.
104
+ */
105
+FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */
106
+FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */
107
+FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */
108
+FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */
109
+
110
+#define PROPRULE(X, Y, Z) \
111
+ ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT))
112
+
113
+typedef enum __attribute__((__packed__)) {
114
+ float_3nan_prop_none = 0, /* No propagation rule specified */
115
+ float_3nan_prop_abc = PROPRULE(0, 1, 2),
116
+ float_3nan_prop_acb = PROPRULE(0, 2, 1),
117
+ float_3nan_prop_bac = PROPRULE(1, 0, 2),
118
+ float_3nan_prop_bca = PROPRULE(1, 2, 0),
119
+ float_3nan_prop_cab = PROPRULE(2, 0, 1),
120
+ float_3nan_prop_cba = PROPRULE(2, 1, 0),
121
+ float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK,
122
+ float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK,
123
+ float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK,
124
+ float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK,
125
+ float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK,
126
+ float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK,
127
+} Float3NaNPropRule;
128
+
129
+#undef PROPRULE
130
+
131
/*
132
* Rule for result of fused multiply-add 0 * Inf + NaN.
133
* This must be a NaN, but implementations differ on whether this
134
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
135
FloatRoundMode float_rounding_mode;
136
FloatX80RoundPrec floatx80_rounding_precision;
137
Float2NaNPropRule float_2nan_prop_rule;
138
+ Float3NaNPropRule float_3nan_prop_rule;
139
FloatInfZeroNaNRule float_infzeronan_rule;
140
bool tininess_before_rounding;
141
/* should denormalised results go to zero and set the inexact flag? */
142
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
143
index XXXXXXX..XXXXXXX 100644
144
--- a/fpu/softfloat-specialize.c.inc
145
+++ b/fpu/softfloat-specialize.c.inc
146
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
147
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
148
bool infzero, bool have_snan, float_status *status)
149
{
150
+ FloatClass cls[3] = { a_cls, b_cls, c_cls };
151
+ Float3NaNPropRule rule = status->float_3nan_prop_rule;
152
+ int which;
153
+
154
/*
155
* We guarantee not to require the target to tell us how to
156
* pick a NaN if we're always returning the default NaN.
157
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
60
}
158
}
61
}
159
}
62
160
63
- ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr,
161
+ if (rule == float_3nan_prop_none) {
64
- txattrs, prot, &mpu_is_subpage, fi, NULL);
162
#if defined(TARGET_ARM)
65
- *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
163
-
66
+ ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx,
164
- /* This looks different from the ARM ARM pseudocode, because the ARM ARM
67
+ &result->phys, &result->attrs, &result->prot,
165
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
68
+ &mpu_is_subpage, fi, NULL);
166
- */
69
+ result->page_size =
167
- if (is_snan(c_cls)) {
70
+ sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
168
- return 2;
71
return ret;
169
- } else if (is_snan(a_cls)) {
170
- return 0;
171
- } else if (is_snan(b_cls)) {
172
- return 1;
173
- } else if (is_qnan(c_cls)) {
174
- return 2;
175
- } else if (is_qnan(a_cls)) {
176
- return 0;
177
- } else {
178
- return 1;
179
- }
180
+ /*
181
+ * This looks different from the ARM ARM pseudocode, because the ARM ARM
182
+ * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
183
+ */
184
+ rule = float_3nan_prop_s_cab;
185
#elif defined(TARGET_MIPS)
186
- if (snan_bit_is_one(status)) {
187
- /* Prefer sNaN over qNaN, in the a, b, c order. */
188
- if (is_snan(a_cls)) {
189
- return 0;
190
- } else if (is_snan(b_cls)) {
191
- return 1;
192
- } else if (is_snan(c_cls)) {
193
- return 2;
194
- } else if (is_qnan(a_cls)) {
195
- return 0;
196
- } else if (is_qnan(b_cls)) {
197
- return 1;
198
+ if (snan_bit_is_one(status)) {
199
+ rule = float_3nan_prop_s_abc;
200
} else {
201
- return 2;
202
+ rule = float_3nan_prop_s_cab;
203
}
204
- } else {
205
- /* Prefer sNaN over qNaN, in the c, a, b order. */
206
- if (is_snan(c_cls)) {
207
- return 2;
208
- } else if (is_snan(a_cls)) {
209
- return 0;
210
- } else if (is_snan(b_cls)) {
211
- return 1;
212
- } else if (is_qnan(c_cls)) {
213
- return 2;
214
- } else if (is_qnan(a_cls)) {
215
- return 0;
216
- } else {
217
- return 1;
218
- }
219
- }
220
#elif defined(TARGET_LOONGARCH64)
221
- /* Prefer sNaN over qNaN, in the c, a, b order. */
222
- if (is_snan(c_cls)) {
223
- return 2;
224
- } else if (is_snan(a_cls)) {
225
- return 0;
226
- } else if (is_snan(b_cls)) {
227
- return 1;
228
- } else if (is_qnan(c_cls)) {
229
- return 2;
230
- } else if (is_qnan(a_cls)) {
231
- return 0;
232
- } else {
233
- return 1;
234
- }
235
+ rule = float_3nan_prop_s_cab;
236
#elif defined(TARGET_PPC)
237
- /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
238
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
239
- */
240
- if (is_nan(a_cls)) {
241
- return 0;
242
- } else if (is_nan(c_cls)) {
243
- return 2;
244
- } else {
245
- return 1;
246
- }
247
+ /*
248
+ * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
249
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
250
+ */
251
+ rule = float_3nan_prop_acb;
252
#elif defined(TARGET_S390X)
253
- if (is_snan(a_cls)) {
254
- return 0;
255
- } else if (is_snan(b_cls)) {
256
- return 1;
257
- } else if (is_snan(c_cls)) {
258
- return 2;
259
- } else if (is_qnan(a_cls)) {
260
- return 0;
261
- } else if (is_qnan(b_cls)) {
262
- return 1;
263
- } else {
264
- return 2;
265
- }
266
+ rule = float_3nan_prop_s_abc;
267
#elif defined(TARGET_SPARC)
268
- /* Prefer SNaN over QNaN, order C, B, A. */
269
- if (is_snan(c_cls)) {
270
- return 2;
271
- } else if (is_snan(b_cls)) {
272
- return 1;
273
- } else if (is_snan(a_cls)) {
274
- return 0;
275
- } else if (is_qnan(c_cls)) {
276
- return 2;
277
- } else if (is_qnan(b_cls)) {
278
- return 1;
279
- } else {
280
- return 0;
281
- }
282
+ rule = float_3nan_prop_s_cba;
283
#elif defined(TARGET_XTENSA)
284
- /*
285
- * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
286
- * an input NaN if we have one (ie c).
287
- */
288
- if (status->use_first_nan) {
289
- if (is_nan(a_cls)) {
290
- return 0;
291
- } else if (is_nan(b_cls)) {
292
- return 1;
293
+ if (status->use_first_nan) {
294
+ rule = float_3nan_prop_abc;
295
} else {
296
- return 2;
297
+ rule = float_3nan_prop_cba;
298
}
299
- } else {
300
- if (is_nan(c_cls)) {
301
- return 2;
302
- } else if (is_nan(b_cls)) {
303
- return 1;
304
- } else {
305
- return 0;
306
- }
307
- }
308
#else
309
- /* A default implementation: prefer a to b to c.
310
- * This is unlikely to actually match any real implementation.
311
- */
312
- if (is_nan(a_cls)) {
313
- return 0;
314
- } else if (is_nan(b_cls)) {
315
- return 1;
316
- } else {
317
- return 2;
318
- }
319
+ rule = float_3nan_prop_abc;
320
#endif
321
+ }
322
+
323
+ assert(rule != float_3nan_prop_none);
324
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
325
+ /* We have at least one SNaN input and should prefer it */
326
+ do {
327
+ which = rule & R_3NAN_1ST_MASK;
328
+ rule >>= R_3NAN_1ST_LENGTH;
329
+ } while (!is_snan(cls[which]));
330
+ } else {
331
+ do {
332
+ which = rule & R_3NAN_1ST_MASK;
333
+ rule >>= R_3NAN_1ST_LENGTH;
334
+ } while (!is_nan(cls[which]));
335
+ }
336
+ return which;
72
}
337
}
73
338
74
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
339
/*----------------------------------------------------------------------------
75
if (arm_feature(env, ARM_FEATURE_V8)) {
76
/* PMSAv8 */
77
ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
78
- &result->phys, &result->attrs,
79
- &result->prot, &result->page_size, fi);
80
+ result, fi);
81
} else if (arm_feature(env, ARM_FEATURE_V7)) {
82
/* PMSAv7 */
83
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
84
--
340
--
85
2.25.1
341
2.34.1
86
87
diff view generated by jsdifflib
New patch
[PULL 21/72] tests/fp: Explicitly set 3-NaN propagation rule
1
Explicitly set a rule in the softfloat tests for propagating NaNs in
2
the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and
3
so we should select here the Arm rule of float_3nan_prop_s_cab.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-17-peter.maydell@linaro.org
8
---
9
tests/fp/fp-bench.c | 1 +
10
tests/fp/fp-test.c | 1 +
11
2 files changed, 2 insertions(+)
12
13
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/tests/fp/fp-bench.c
16
+++ b/tests/fp/fp-bench.c
17
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
18
* doesn't specify match those used by the Arm architecture.
19
*/
20
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
22
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
23
24
f = bench_funcs[operation][precision];
25
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/tests/fp/fp-test.c
28
+++ b/tests/fp/fp-test.c
29
@@ -XXX,XX +XXX,XX @@ void run_test(void)
30
* doesn't specify match those used by the Arm architecture.
31
*/
32
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
33
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
34
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
35
36
genCases_setLevel(test_level);
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 22/72] target/arm: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-18-peter.maydell@linaro.org
7
---
8
target/arm/cpu.c | 5 +++++
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 6 insertions(+), 7 deletions(-)
11
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
17
* * tininess-before-rounding
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
20
+ * * 3-input NaN propagation prefers SNaN over QNaN, and then
21
+ * operand C over A over B (see FPProcessNaNs3() pseudocode,
22
+ * but note that for QEMU muladd is a * b + c, whereas for
23
+ * the pseudocode function the arguments are in the order c, a, b.
24
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
25
* and the input NaN if it is signalling
26
*/
27
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
28
{
29
set_float_detect_tininess(float_tininess_before_rounding, s);
30
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
31
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
32
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
33
}
34
35
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
36
index XXXXXXX..XXXXXXX 100644
37
--- a/fpu/softfloat-specialize.c.inc
38
+++ b/fpu/softfloat-specialize.c.inc
39
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
40
}
41
42
if (rule == float_3nan_prop_none) {
43
-#if defined(TARGET_ARM)
44
- /*
45
- * This looks different from the ARM ARM pseudocode, because the ARM ARM
46
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
47
- */
48
- rule = float_3nan_prop_s_cab;
49
-#elif defined(TARGET_MIPS)
50
+#if defined(TARGET_MIPS)
51
if (snan_bit_is_one(status)) {
52
rule = float_3nan_prop_s_abc;
53
} else {
54
--
55
2.34.1
diff view generated by jsdifflib
New patch
[PULL 23/72] target/loongarch: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for loongarch, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-19-peter.maydell@linaro.org
7
---
8
target/loongarch/tcg/fpu_helper.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/loongarch/tcg/fpu_helper.c
15
+++ b/target/loongarch/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
17
* case sets InvalidOp and returns the input value 'c'
18
*/
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
21
}
22
23
int ieee_ex_to_loongarch(int xcpt)
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_LOONGARCH64)
33
- rule = float_3nan_prop_s_cab;
34
#elif defined(TARGET_PPC)
35
/*
36
* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 24/72] target/ppc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for PPC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-20-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 8 ++++++++
9
fpu/softfloat-specialize.c.inc | 6 ------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * NaN propagation for fused multiply-add:
22
+ * if fRA is a NaN return it; otherwise if fRB is a NaN return it;
23
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
24
+ * whereas QEMU labels the operands as (a * b) + c.
25
+ */
26
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status);
27
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status);
28
/*
29
* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
30
* to return an input NaN if we have one (ie c) rather than generating
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
32
index XXXXXXX..XXXXXXX 100644
33
--- a/fpu/softfloat-specialize.c.inc
34
+++ b/fpu/softfloat-specialize.c.inc
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
} else {
37
rule = float_3nan_prop_s_cab;
38
}
39
-#elif defined(TARGET_PPC)
40
- /*
41
- * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
42
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
43
- */
44
- rule = float_3nan_prop_acb;
45
#elif defined(TARGET_S390X)
46
rule = float_3nan_prop_s_abc;
47
#elif defined(TARGET_SPARC)
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 25/72] target/s390x: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for s390x, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-21-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
21
set_float_infzeronan_rule(float_infzeronan_dnan_always,
22
&env->fpu_status);
23
/* fall through */
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_S390X)
33
- rule = float_3nan_prop_s_abc;
34
#elif defined(TARGET_SPARC)
35
rule = float_3nan_prop_s_cba;
36
#elif defined(TARGET_XTENSA)
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 26/72] target/sparc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for SPARC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-22-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
22
/* For inf * 0 + NaN, return the input NaN */
23
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
} else {
31
rule = float_3nan_prop_s_cab;
32
}
33
-#elif defined(TARGET_SPARC)
34
- rule = float_3nan_prop_s_cba;
35
#elif defined(TARGET_XTENSA)
36
if (status->use_first_nan) {
37
rule = float_3nan_prop_abc;
38
--
39
2.34.1
diff view generated by jsdifflib
[PULL 30/39] hw/usb/hcd-ohci: Use definition to avoid dynamic stack allocation
[PULL 27/72] target/mips: Set Float3NaNPropRule explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
The compiler isn't clever enough to figure 'width' is a constant,
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
so help it by using a definitions instead.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-23-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 4 ++++
9
target/mips/msa.c | 3 +++
10
fpu/softfloat-specialize.c.inc | 8 +-------
11
3 files changed, 8 insertions(+), 7 deletions(-)
5
12
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220819153931.3147384-10-peter.maydell@linaro.org
10
---
11
hw/usb/hcd-ohci.c | 7 ++++---
12
1 file changed, 4 insertions(+), 3 deletions(-)
13
14
diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/usb/hcd-ohci.c
15
--- a/target/mips/fpu_helper.h
17
+++ b/hw/usb/hcd-ohci.c
16
+++ b/target/mips/fpu_helper.h
18
@@ -XXX,XX +XXX,XX @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed)
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
return 1;
18
{
19
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
20
FloatInfZeroNaNRule izn_rule;
21
+ Float3NaNPropRule nan3_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
28
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
29
+ nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
30
+ set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
31
+
20
}
32
}
21
33
22
+#define HEX_CHAR_PER_LINE 16
34
static inline void restore_fp_status(CPUMIPSState *env)
35
diff --git a/target/mips/msa.c b/target/mips/msa.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/mips/msa.c
38
+++ b/target/mips/msa.c
39
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
40
set_float_2nan_prop_rule(float_2nan_prop_s_ab,
41
&env->active_tc.msa_fp_status);
42
43
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab,
44
+ &env->active_tc.msa_fp_status);
23
+
45
+
24
static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len)
46
/* clear float_status exception flags */
25
{
47
set_float_exception_flags(0, &env->active_tc.msa_fp_status);
26
bool print16;
48
27
bool printall;
49
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
- const int width = 16;
50
index XXXXXXX..XXXXXXX 100644
29
int i;
51
--- a/fpu/softfloat-specialize.c.inc
30
- char tmp[3 * width + 1];
52
+++ b/fpu/softfloat-specialize.c.inc
31
+ char tmp[3 * HEX_CHAR_PER_LINE + 1];
53
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
32
char *p = tmp;
33
34
print16 = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_SHORT);
35
@@ -XXX,XX +XXX,XX @@ static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len)
36
}
54
}
37
55
38
for (i = 0; ; i++) {
56
if (rule == float_3nan_prop_none) {
39
- if (i && (!(i % width) || (i == len))) {
57
-#if defined(TARGET_MIPS)
40
+ if (i && (!(i % HEX_CHAR_PER_LINE) || (i == len))) {
58
- if (snan_bit_is_one(status)) {
41
if (!printall) {
59
- rule = float_3nan_prop_s_abc;
42
trace_usb_ohci_td_pkt_short(msg, tmp);
60
- } else {
43
break;
61
- rule = float_3nan_prop_s_cab;
62
- }
63
-#elif defined(TARGET_XTENSA)
64
+#if defined(TARGET_XTENSA)
65
if (status->use_first_nan) {
66
rule = float_3nan_prop_abc;
67
} else {
44
--
68
--
45
2.25.1
69
2.34.1
46
47
diff view generated by jsdifflib
[PULL 04/39] target/arm: Use GetPhysAddrResult in get_phys_addr_lpae
[PULL 28/72] target/xtensa: Set Float3NaNPropRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the Float3NaNPropRule explicitly for xtensa, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20220822152741.1617527-4-richard.henderson@linaro.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-24-peter.maydell@linaro.org
8
---
7
---
9
target/arm/ptw.c | 69 ++++++++++++++++++------------------------------
8
target/xtensa/fpu_helper.c | 2 ++
10
1 file changed, 26 insertions(+), 43 deletions(-)
9
fpu/softfloat-specialize.c.inc | 8 --------
10
2 files changed, 2 insertions(+), 8 deletions(-)
11
11
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
12
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/ptw.c
14
--- a/target/xtensa/fpu_helper.c
15
+++ b/target/arm/ptw.c
15
+++ b/target/xtensa/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
17
17
set_use_first_nan(use_first, &env->fp_status);
18
static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
18
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
19
&env->fp_status);
20
- bool s1_is_el0, hwaddr *phys_ptr,
20
+ set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
21
- MemTxAttrs *txattrs, int *prot,
21
+ &env->fp_status);
22
- target_ulong *page_size_ptr,
22
}
23
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
23
24
+ bool s1_is_el0, GetPhysAddrResult *result,
24
void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v)
25
+ ARMMMUFaultInfo *fi)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
__attribute__((nonnull));
26
index XXXXXXX..XXXXXXX 100644
27
27
--- a/fpu/softfloat-specialize.c.inc
28
/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
{
31
if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
32
!regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
33
- target_ulong s2size;
34
- hwaddr s2pa;
35
- int s2prot;
36
- int ret;
37
ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S
38
: ARMMMUIdx_Stage2;
39
- ARMCacheAttrs cacheattrs = {};
40
- MemTxAttrs txattrs = {};
41
+ GetPhysAddrResult s2 = {};
42
+ int ret;
43
44
ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false,
45
- &s2pa, &txattrs, &s2prot, &s2size, fi,
46
- &cacheattrs);
47
+ &s2, fi);
48
if (ret) {
49
assert(fi->type != ARMFault_None);
50
fi->s2addr = addr;
51
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
52
return ~0;
53
}
54
if ((arm_hcr_el2_eff(env) & HCR_PTW) &&
55
- ptw_attrs_are_device(env, cacheattrs)) {
56
+ ptw_attrs_are_device(env, s2.cacheattrs)) {
57
/*
58
* PTW set and S1 walk touched S2 Device memory:
59
* generate Permission fault.
60
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
61
assert(!*is_secure);
62
}
63
64
- addr = s2pa;
65
+ addr = s2.phys;
66
}
30
}
67
return addr;
31
68
}
32
if (rule == float_3nan_prop_none) {
69
@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
33
-#if defined(TARGET_XTENSA)
70
* table walk), must be true if this is stage 2 of a stage 1+2
34
- if (status->use_first_nan) {
71
* walk for an EL0 access. If @mmu_idx is anything else,
35
- rule = float_3nan_prop_abc;
72
* @s1_is_el0 is ignored.
36
- } else {
73
- * @phys_ptr: set to the physical address corresponding to the virtual address
37
- rule = float_3nan_prop_cba;
74
- * @attrs: set to the memory transaction attributes to use
38
- }
75
- * @prot: set to the permissions for the page containing phys_ptr
39
-#else
76
- * @page_size_ptr: set to the size of the page containing phys_ptr
40
rule = float_3nan_prop_abc;
77
+ * @result: set on translation success,
41
-#endif
78
* @fi: set to fault info if the translation fails
79
- * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
80
*/
81
static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
82
MMUAccessType access_type, ARMMMUIdx mmu_idx,
83
- bool s1_is_el0, hwaddr *phys_ptr,
84
- MemTxAttrs *txattrs, int *prot,
85
- target_ulong *page_size_ptr,
86
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
87
+ bool s1_is_el0, GetPhysAddrResult *result,
88
+ ARMMMUFaultInfo *fi)
89
{
90
ARMCPU *cpu = env_archcpu(env);
91
/* Read an LPAE long-descriptor translation table. */
92
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
93
if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
94
ns = mmu_idx == ARMMMUIdx_Stage2;
95
xn = extract32(attrs, 11, 2);
96
- *prot = get_S2prot(env, ap, xn, s1_is_el0);
97
+ result->prot = get_S2prot(env, ap, xn, s1_is_el0);
98
} else {
99
ns = extract32(attrs, 3, 1);
100
xn = extract32(attrs, 12, 1);
101
pxn = extract32(attrs, 11, 1);
102
- *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
103
+ result->prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
104
}
42
}
105
43
106
fault_type = ARMFault_Permission;
44
assert(rule != float_3nan_prop_none);
107
- if (!(*prot & (1 << access_type))) {
108
+ if (!(result->prot & (1 << access_type))) {
109
goto do_fault;
110
}
111
112
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
113
* the CPU doesn't support TZ or this is a non-secure translation
114
* regime, because the attribute will already be non-secure.
115
*/
116
- txattrs->secure = false;
117
+ result->attrs.secure = false;
118
}
119
/* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
120
if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
121
- arm_tlb_bti_gp(txattrs) = true;
122
+ arm_tlb_bti_gp(&result->attrs) = true;
123
}
124
125
if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
126
- cacheattrs->is_s2_format = true;
127
- cacheattrs->attrs = extract32(attrs, 0, 4);
128
+ result->cacheattrs.is_s2_format = true;
129
+ result->cacheattrs.attrs = extract32(attrs, 0, 4);
130
} else {
131
/* Index into MAIR registers for cache attributes */
132
uint8_t attrindx = extract32(attrs, 0, 3);
133
uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
134
assert(attrindx <= 7);
135
- cacheattrs->is_s2_format = false;
136
- cacheattrs->attrs = extract64(mair, attrindx * 8, 8);
137
+ result->cacheattrs.is_s2_format = false;
138
+ result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
139
}
140
141
/*
142
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
143
* that case comes from TCR_ELx, which we extracted earlier.
144
*/
145
if (param.ds) {
146
- cacheattrs->shareability = param.sh;
147
+ result->cacheattrs.shareability = param.sh;
148
} else {
149
- cacheattrs->shareability = extract32(attrs, 6, 2);
150
+ result->cacheattrs.shareability = extract32(attrs, 6, 2);
151
}
152
153
- *phys_ptr = descaddr;
154
- *page_size_ptr = page_size;
155
+ result->phys = descaddr;
156
+ result->page_size = page_size;
157
return false;
158
159
do_fault:
160
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
161
cacheattrs1 = result->cacheattrs;
162
memset(result, 0, sizeof(*result));
163
164
- ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, is_el0,
165
- &result->phys, &result->attrs,
166
- &result->prot, &result->page_size,
167
- fi, &result->cacheattrs);
168
+ ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx,
169
+ is_el0, result, fi);
170
fi->s2addr = ipa;
171
172
/* Combine the S1 and S2 perms. */
173
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
174
175
if (regime_using_lpae_format(env, mmu_idx)) {
176
return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
177
- &result->phys, &result->attrs,
178
- &result->prot, &result->page_size,
179
- fi, &result->cacheattrs);
180
+ result, fi);
181
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
182
return get_phys_addr_v6(env, address, access_type, mmu_idx,
183
&result->phys, &result->attrs,
184
--
45
--
185
2.25.1
46
2.34.1
186
187
diff view generated by jsdifflib
New patch
[PULL 29/72] target/i386: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for i386. We had no
2
i386-specific behaviour in the old ifdef ladder, so we were using the
3
default "prefer a then b then c" fallback; this is actually the
4
correct per-the-spec handling for i386.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-25-peter.maydell@linaro.org
9
---
10
target/i386/tcg/fpu_helper.c | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/i386/tcg/fpu_helper.c
16
+++ b/target/i386/tcg/fpu_helper.c
17
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
18
* there are multiple input NaNs they are selected in the order a, b, c.
19
*/
20
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
22
}
23
24
static inline uint8_t save_exception_flags(CPUX86State *env)
25
--
26
2.34.1
diff view generated by jsdifflib
[PULL 29/39] hw/i386/multiboot: Avoid dynamic stack allocation
[PULL 30/72] target/hppa: Set Float3NaNPropRule explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the Float3NaNPropRule explicitly for HPPA, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Use autofree heap allocation instead of variable-length array on
4
HPPA is the only target that was using the default branch of the
4
the stack. Replace the snprintf() call by g_strdup_printf().
5
ifdef ladder (other targets either do not use muladd or set
6
default_nan_mode), so we can remove the ifdef fallback entirely now
7
(allowing the "rule not set" case to fall into the default of the
8
switch statement and assert).
5
9
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
We add a TODO note that the HPPA rule is probably wrong; this is
11
not a behavioural change for this refactoring.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Message-id: 20241202131347.498124-26-peter.maydell@linaro.org
9
Message-id: 20220819153931.3147384-9-peter.maydell@linaro.org
10
---
16
---
11
hw/i386/multiboot.c | 5 ++---
17
target/hppa/fpu_helper.c | 8 ++++++++
12
1 file changed, 2 insertions(+), 3 deletions(-)
18
fpu/softfloat-specialize.c.inc | 4 ----
19
2 files changed, 8 insertions(+), 4 deletions(-)
13
20
14
diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c
21
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
15
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/i386/multiboot.c
23
--- a/target/hppa/fpu_helper.c
17
+++ b/hw/i386/multiboot.c
24
+++ b/target/hppa/fpu_helper.c
18
@@ -XXX,XX +XXX,XX @@ int load_multiboot(X86MachineState *x86ms,
25
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
19
uint8_t *mb_bootinfo_data;
26
* HPPA does note implement a CPU reset method at all...
20
uint32_t cmdline_len;
27
*/
21
GList *mods = NULL;
28
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
22
+ g_autofree char *kcmdline = NULL;
29
+ /*
23
30
+ * TODO: The HPPA architecture reference only documents its NaN
24
/* Ok, let's see if it is a multiboot image.
31
+ * propagation rule for 2-operand operations. Testing on real hardware
25
The header is 12x32bit long, so the latest entry may be 8192 - 48. */
32
+ * might be necessary to confirm whether this order for muladd is correct.
26
@@ -XXX,XX +XXX,XX @@ int load_multiboot(X86MachineState *x86ms,
33
+ * Not preferring the SNaN is almost certainly incorrect as it diverges
34
+ * from the documented rules for 2-operand operations.
35
+ */
36
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
37
/* For inf * 0 + NaN, return the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
39
}
40
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
41
index XXXXXXX..XXXXXXX 100644
42
--- a/fpu/softfloat-specialize.c.inc
43
+++ b/fpu/softfloat-specialize.c.inc
44
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
45
}
27
}
46
}
28
47
29
/* Commandline support */
48
- if (rule == float_3nan_prop_none) {
30
- char kcmdline[strlen(kernel_filename) + strlen(kernel_cmdline) + 2];
49
- rule = float_3nan_prop_abc;
31
- snprintf(kcmdline, sizeof(kcmdline), "%s %s",
50
- }
32
- kernel_filename, kernel_cmdline);
51
-
33
+ kcmdline = g_strdup_printf("%s %s", kernel_filename, kernel_cmdline);
52
assert(rule != float_3nan_prop_none);
34
stl_p(bootinfo + MBI_CMDLINE, mb_add_cmdline(&mbs, kcmdline));
53
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
35
54
/* We have at least one SNaN input and should prefer it */
36
stl_p(bootinfo + MBI_BOOTLOADER, mb_add_bootloader(&mbs, bootloader_name));
37
--
55
--
38
2.25.1
56
2.34.1
39
40
diff view generated by jsdifflib
New patch
[PULL 31/72] fpu: Remove use_first_nan field from float_status
1
The use_first_nan field in float_status was an xtensa-specific way to
2
select at runtime from two different NaN propagation rules. Now that
3
xtensa is using the target-agnostic NaN propagation rule selection
4
that we've just added, we can remove use_first_nan, because there is
5
no longer any code that reads it.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20241202131347.498124-27-peter.maydell@linaro.org
10
---
11
include/fpu/softfloat-helpers.h | 5 -----
12
include/fpu/softfloat-types.h | 1 -
13
target/xtensa/fpu_helper.c | 1 -
14
3 files changed, 7 deletions(-)
15
16
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/fpu/softfloat-helpers.h
19
+++ b/include/fpu/softfloat-helpers.h
20
@@ -XXX,XX +XXX,XX @@ static inline void set_snan_bit_is_one(bool val, float_status *status)
21
status->snan_bit_is_one = val;
22
}
23
24
-static inline void set_use_first_nan(bool val, float_status *status)
25
-{
26
- status->use_first_nan = val;
27
-}
28
-
29
static inline void set_no_signaling_nans(bool val, float_status *status)
30
{
31
status->no_signaling_nans = val;
32
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/include/fpu/softfloat-types.h
35
+++ b/include/fpu/softfloat-types.h
36
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
37
* softfloat-specialize.inc.c)
38
*/
39
bool snan_bit_is_one;
40
- bool use_first_nan;
41
bool no_signaling_nans;
42
/* should overflowed results subtract re_bias to its exponent? */
43
bool rebias_overflow;
44
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/xtensa/fpu_helper.c
47
+++ b/target/xtensa/fpu_helper.c
48
@@ -XXX,XX +XXX,XX @@ static const struct {
49
50
void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
51
{
52
- set_use_first_nan(use_first, &env->fp_status);
53
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
54
&env->fp_status);
55
set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PULL 32/72] target/m68k: Don't pass NULL float_status to floatx80_default_nan()
1
Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL)
2
to get the NaN bit pattern to reset the FPU registers. This
3
works because it happens that our implementation of
4
floatx80_default_nan() doesn't actually look at the float_status
5
pointer except for TARGET_MIPS. However, this isn't guaranteed,
6
and to be able to remove the ifdef in floatx80_default_nan()
7
we're going to need a real float_status here.
1
8
9
Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status
10
earlier, and thus can pass it to floatx80_default_nan().
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20241202131347.498124-28-peter.maydell@linaro.org
15
---
16
target/m68k/cpu.c | 12 +++++++-----
17
1 file changed, 7 insertions(+), 5 deletions(-)
18
19
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/m68k/cpu.c
22
+++ b/target/m68k/cpu.c
23
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
24
CPUState *cs = CPU(obj);
25
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj);
26
CPUM68KState *env = cpu_env(cs);
27
- floatx80 nan = floatx80_default_nan(NULL);
28
+ floatx80 nan;
29
int i;
30
31
if (mcc->parent_phases.hold) {
32
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
33
#else
34
cpu_m68k_set_sr(env, SR_S | SR_I);
35
#endif
36
- for (i = 0; i < 8; i++) {
37
- env->fregs[i].d = nan;
38
- }
39
- cpu_m68k_set_fpcr(env, 0);
40
/*
41
* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
42
* 3.4 FLOATING-POINT INSTRUCTION DETAILS
43
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
44
* preceding paragraph for nonsignaling NaNs.
45
*/
46
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
47
+
48
+ nan = floatx80_default_nan(&env->fp_status);
49
+ for (i = 0; i < 8; i++) {
50
+ env->fregs[i].d = nan;
51
+ }
52
+ cpu_m68k_set_fpcr(env, 0);
53
env->fpsr = 0;
54
55
/* TODO: We should set PC from the interrupt vector. */
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PULL 33/72] softfloat: Create floatx80 default NaN from parts64_default_nan
1
We create our 128-bit default NaN by calling parts64_default_nan()
2
and then adjusting the result. We can do the same trick for creating
3
the floatx80 default NaN, which lets us drop a target ifdef.
1
4
5
floatx80 is used only by:
6
i386
7
m68k
8
arm nwfpe old floating-point emulation emulation support
9
(which is essentially dead, especially the parts involving floatx80)
10
PPC (only in the xsrqpxp instruction, which just rounds an input
11
value by converting to floatx80 and back, so will never generate
12
the default NaN)
13
14
The floatx80 default NaN as currently implemented is:
15
m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1
16
i386: sign = 1, exp = 1...1, int = 1, frac = 10...0
17
18
These are the same as the parts64_default_nan for these architectures.
19
20
This is technically a possible behaviour change for arm linux-user
21
nwfpe emulation emulation, because the default NaN will now have the
22
sign bit clear. But we were already generating a different floatx80
23
default NaN from the real kernel emulation we are supposedly
24
following, which appears to use an all-bits-1 value:
25
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267
26
27
This won't affect the only "real" use of the nwfpe emulation, which
28
is ancient binaries that used it as part of the old floating point
29
calling convention; that only uses loads and stores of 32 and 64 bit
30
floats, not any of the floatx80 behaviour the original hardware had.
31
We also get the nwfpe float64 default NaN value wrong:
32
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166
33
so if we ever cared about this obscure corner the right fix would be
34
to correct that so nwfpe used its own default-NaN setting rather
35
than the Arm VFP one.
36
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
38
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
39
Message-id: 20241202131347.498124-29-peter.maydell@linaro.org
40
---
41
fpu/softfloat-specialize.c.inc | 20 ++++++++++----------
42
1 file changed, 10 insertions(+), 10 deletions(-)
43
44
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
45
index XXXXXXX..XXXXXXX 100644
46
--- a/fpu/softfloat-specialize.c.inc
47
+++ b/fpu/softfloat-specialize.c.inc
48
@@ -XXX,XX +XXX,XX @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status)
49
floatx80 floatx80_default_nan(float_status *status)
50
{
51
floatx80 r;
52
+ /*
53
+ * Extrapolate from the choices made by parts64_default_nan to fill
54
+ * in the floatx80 format. We assume that floatx80's explicit
55
+ * integer bit is always set (this is true for i386 and m68k,
56
+ * which are the only real users of this format).
57
+ */
58
+ FloatParts64 p64;
59
+ parts64_default_nan(&p64, status);
60
61
- /* None of the targets that have snan_bit_is_one use floatx80. */
62
- assert(!snan_bit_is_one(status));
63
-#if defined(TARGET_M68K)
64
- r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
65
- r.high = 0x7FFF;
66
-#else
67
- /* X86 */
68
- r.low = UINT64_C(0xC000000000000000);
69
- r.high = 0xFFFF;
70
-#endif
71
+ r.high = 0x7FFF | (p64.sign << 15);
72
+ r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac;
73
return r;
74
}
75
76
--
77
2.34.1
diff view generated by jsdifflib
New patch
[PULL 34/72] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
1
In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass
2
a zero-initialized float_status struct to float32_is_quiet_nan() and
3
float64_is_quiet_nan(), with the cryptic comment "for
4
snan_bit_is_one".
1
5
6
This pattern appears to have been copied from target/riscv, where it
7
is used because the functions there do not have ready access to the
8
CPU state struct. The comment presumably refers to the fact that the
9
main reason the is_quiet_nan() functions want the float_state is
10
because they want to know about the snan_bit_is_one config.
11
12
In the loongarch helpers, though, we have the CPU state struct
13
to hand. Use the usual env->fp_status here. This avoids our needing
14
to track that we need to update the initializer of the local
15
float_status structs when the core softfloat code adds new
16
options for targets to configure their behaviour.
17
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20241202131347.498124-30-peter.maydell@linaro.org
21
---
22
target/loongarch/tcg/fpu_helper.c | 6 ++----
23
1 file changed, 2 insertions(+), 4 deletions(-)
24
25
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/loongarch/tcg/fpu_helper.c
28
+++ b/target/loongarch/tcg/fpu_helper.c
29
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj)
30
} else if (float32_is_zero_or_denormal(f)) {
31
return sign ? 1 << 4 : 1 << 8;
32
} else if (float32_is_any_nan(f)) {
33
- float_status s = { }; /* for snan_bit_is_one */
34
- return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
35
+ return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
36
} else {
37
return sign ? 1 << 3 : 1 << 7;
38
}
39
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj)
40
} else if (float64_is_zero_or_denormal(f)) {
41
return sign ? 1 << 4 : 1 << 8;
42
} else if (float64_is_any_nan(f)) {
43
- float_status s = { }; /* for snan_bit_is_one */
44
- return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
45
+ return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
46
} else {
47
return sign ? 1 << 3 : 1 << 7;
48
}
49
--
50
2.34.1
diff view generated by jsdifflib
New patch
[PULL 35/72] target/m68k: In frem helper, initialize local float_status from env->fp_status
1
In the frem helper, we have a local float_status because we want to
2
execute the floatx80_div() with a custom rounding mode. Instead of
3
zero-initializing the local float_status and then having to set it up
4
with the m68k standard behaviour (including the NaN propagation rule
5
and copying the rounding precision from env->fp_status), initialize
6
it as a complete copy of env->fp_status. This will avoid our having
7
to add new code in this function for every new config knob we add
8
to fp_status.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-31-peter.maydell@linaro.org
13
---
14
target/m68k/fpu_helper.c | 6 ++----
15
1 file changed, 2 insertions(+), 4 deletions(-)
16
17
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/m68k/fpu_helper.c
20
+++ b/target/m68k/fpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
22
23
fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status);
24
if (!floatx80_is_any_nan(fp_rem)) {
25
- float_status fp_status = { };
26
+ /* Use local temporary fp_status to set different rounding mode */
27
+ float_status fp_status = env->fp_status;
28
uint32_t quotient;
29
int sign;
30
31
/* Calculate quotient directly using round to nearest mode */
32
- set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status);
33
set_float_rounding_mode(float_round_nearest_even, &fp_status);
34
- set_floatx80_rounding_precision(
35
- get_floatx80_rounding_precision(&env->fp_status), &fp_status);
36
fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status);
37
38
sign = extractFloatx80Sign(fp_quot.d);
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 36/72] target/m68k: Init local float_status from env fp_status in gdb get/set reg
1
In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion
2
from float64 to floatx80 using a scratch float_status, because we
3
don't want the conversion to affect the CPU's floating point exception
4
status. Currently we use a zero-initialized float_status. This will
5
get steadily more awkward as we add config knobs to float_status
6
that the target must initialize. Avoid having to add any of that
7
configuration here by instead initializing our local float_status
8
from the env->fp_status.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-32-peter.maydell@linaro.org
13
---
14
target/m68k/helper.c | 6 ++++--
15
1 file changed, 4 insertions(+), 2 deletions(-)
16
17
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/m68k/helper.c
20
+++ b/target/m68k/helper.c
21
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n)
22
CPUM68KState *env = &cpu->env;
23
24
if (n < 8) {
25
- float_status s = {};
26
+ /* Use scratch float_status so any exceptions don't change CPU state */
27
+ float_status s = env->fp_status;
28
return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));
29
}
30
switch (n) {
31
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)
32
CPUM68KState *env = &cpu->env;
33
34
if (n < 8) {
35
- float_status s = {};
36
+ /* Use scratch float_status so any exceptions don't change CPU state */
37
+ float_status s = env->fp_status;
38
env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s);
39
return 8;
40
}
41
--
42
2.34.1
diff view generated by jsdifflib
[PULL 10/39] target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup
[PULL 37/72] target/sparc: Initialize local scratch float_status from env->fp_status
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In the helper functions flcmps and flcmpd we use a scratch float_status
2
so that we don't change the CPU state if the comparison raises any
3
floating point exception flags. Instead of zero-initializing this
4
scratch float_status, initialize it as a copy of env->fp_status. This
5
avoids the need to explicitly initialize settings like the NaN
6
propagation rule or others we might add to softfloat in future.
2
7
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
To do this we need to pass the CPU env pointer in to the helper.
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
5
Message-id: 20220822152741.1617527-10-richard.henderson@linaro.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-33-peter.maydell@linaro.org
8
---
13
---
9
target/arm/internals.h | 11 +++++------
14
target/sparc/helper.h | 4 ++--
10
target/arm/m_helper.c | 16 +++++++---------
15
target/sparc/fop_helper.c | 8 ++++----
11
target/arm/ptw.c | 20 +++++++++-----------
16
target/sparc/translate.c | 4 ++--
12
3 files changed, 21 insertions(+), 26 deletions(-)
17
3 files changed, 8 insertions(+), 8 deletions(-)
13
18
14
diff --git a/target/arm/internals.h b/target/arm/internals.h
19
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
15
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/internals.h
21
--- a/target/sparc/helper.h
17
+++ b/target/arm/internals.h
22
+++ b/target/sparc/helper.h
18
@@ -XXX,XX +XXX,XX @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64)
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
24
DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64)
20
V8M_SAttributes *sattrs);
25
DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128)
21
26
DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128)
22
-bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
27
-DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32)
23
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
28
-DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64)
24
- hwaddr *phys_ptr, MemTxAttrs *txattrs,
29
+DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32)
25
- int *prot, bool *is_subpage,
30
+DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64)
26
- ARMMMUFaultInfo *fi, uint32_t *mregion);
31
DEF_HELPER_2(raise_exception, noreturn, env, int)
27
-
32
28
/* Cacheability and shareability attributes for a memory access */
33
DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64)
29
typedef struct ARMCacheAttrs {
34
diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c
30
/*
31
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
32
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
33
__attribute__((nonnull));
34
35
+bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
36
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
37
+ GetPhysAddrResult *result, bool *is_subpage,
38
+ ARMMMUFaultInfo *fi, uint32_t *mregion);
39
+
40
void arm_log_exception(CPUState *cs);
41
42
#endif /* !CONFIG_USER_ONLY */
43
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
44
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/m_helper.c
36
--- a/target/sparc/fop_helper.c
46
+++ b/target/arm/m_helper.c
37
+++ b/target/sparc/fop_helper.c
47
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
38
@@ -XXX,XX +XXX,XX @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2)
48
V8M_SAttributes sattrs = {};
39
return finish_fcmp(env, r, GETPC());
49
uint32_t tt_resp;
40
}
50
bool r, rw, nsr, nsrw, mrvalid;
41
51
- int prot;
42
-uint32_t helper_flcmps(float32 src1, float32 src2)
52
- ARMMMUFaultInfo fi = {};
43
+uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2)
53
- MemTxAttrs attrs = {};
54
- hwaddr phys_addr;
55
ARMMMUIdx mmu_idx;
56
uint32_t mregion;
57
bool targetpriv;
58
bool targetsec = env->v7m.secure;
59
- bool is_subpage;
60
61
/*
62
* Work out what the security state and privilege level we're
63
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
64
* inspecting the other MPU state.
65
*/
66
if (arm_current_el(env) != 0 || alt) {
67
+ GetPhysAddrResult res = {};
68
+ ARMMMUFaultInfo fi = {};
69
+ bool is_subpage;
70
+
71
/* We can ignore the return value as prot is always set */
72
pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
73
- &phys_addr, &attrs, &prot, &is_subpage,
74
- &fi, &mregion);
75
+ &res, &is_subpage, &fi, &mregion);
76
if (mregion == -1) {
77
mrvalid = false;
78
mregion = 0;
79
} else {
80
mrvalid = true;
81
}
82
- r = prot & PAGE_READ;
83
- rw = prot & PAGE_WRITE;
84
+ r = res.prot & PAGE_READ;
85
+ rw = res.prot & PAGE_WRITE;
86
} else {
87
r = false;
88
rw = false;
89
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/target/arm/ptw.c
92
+++ b/target/arm/ptw.c
93
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
94
95
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
96
MMUAccessType access_type, ARMMMUIdx mmu_idx,
97
- hwaddr *phys_ptr, MemTxAttrs *txattrs,
98
- int *prot, bool *is_subpage,
99
+ GetPhysAddrResult *result, bool *is_subpage,
100
ARMMMUFaultInfo *fi, uint32_t *mregion)
101
{
44
{
102
/*
45
/*
103
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
46
* FLCMP never raises an exception nor modifies any FSR fields.
104
uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
47
* Perform the comparison with a dummy fp environment.
105
48
*/
106
*is_subpage = false;
49
- float_status discard = { };
107
- *phys_ptr = address;
50
+ float_status discard = env->fp_status;
108
- *prot = 0;
51
FloatRelation r;
109
+ result->phys = address;
52
110
+ result->prot = 0;
53
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
111
if (mregion) {
54
@@ -XXX,XX +XXX,XX @@ uint32_t helper_flcmps(float32 src1, float32 src2)
112
*mregion = -1;
55
g_assert_not_reached();
113
}
114
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
115
116
if (matchregion == -1) {
117
/* hit using the background region */
118
- get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
119
+ get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
120
} else {
121
uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
122
uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
123
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
124
xn = 1;
125
}
126
127
- *prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
128
- if (*prot && !xn && !(pxn && !is_user)) {
129
- *prot |= PAGE_EXEC;
130
+ result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
131
+ if (result->prot && !xn && !(pxn && !is_user)) {
132
+ result->prot |= PAGE_EXEC;
133
}
134
/*
135
* We don't need to look the attribute up in the MAIR0/MAIR1
136
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
137
138
fi->type = ARMFault_Permission;
139
fi->level = 1;
140
- return !(*prot & (1 << access_type));
141
+ return !(result->prot & (1 << access_type));
142
}
56
}
143
57
144
static bool v8m_is_sau_exempt(CPUARMState *env,
58
-uint32_t helper_flcmpd(float64 src1, float64 src2)
145
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
59
+uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2)
146
}
60
{
147
61
- float_status discard = { };
148
ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx,
62
+ float_status discard = env->fp_status;
149
- &result->phys, &result->attrs, &result->prot,
63
FloatRelation r;
150
- &mpu_is_subpage, fi, NULL);
64
151
+ result, &mpu_is_subpage, fi, NULL);
65
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
152
result->page_size =
66
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
153
sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
67
index XXXXXXX..XXXXXXX 100644
154
return ret;
68
--- a/target/sparc/translate.c
69
+++ b/target/sparc/translate.c
70
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a)
71
72
src1 = gen_load_fpr_F(dc, a->rs1);
73
src2 = gen_load_fpr_F(dc, a->rs2);
74
- gen_helper_flcmps(cpu_fcc[a->cc], src1, src2);
75
+ gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2);
76
return advance_pc(dc);
77
}
78
79
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a)
80
81
src1 = gen_load_fpr_D(dc, a->rs1);
82
src2 = gen_load_fpr_D(dc, a->rs2);
83
- gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2);
84
+ gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2);
85
return advance_pc(dc);
86
}
87
155
--
88
--
156
2.25.1
89
2.34.1
157
158
diff view generated by jsdifflib
[PULL 38/39] configure: Check mkdir result directly, not via $?
[PULL 38/72] target/ppc: Use env->fp_status in helper_compute_fprf functions
1
Shellcheck warns that we have one place where we run a command and
1
In the helper_compute_fprf functions, we pass a dummy float_status
2
then check if it failed using $?; this is better written to simply
2
in to the is_signaling_nan() function. This is unnecessary, because
3
check the command in the 'if' statement directly.
3
we have convenient access to the CPU env pointer here and that
4
is already set up with the correct values for the snan_bit_is_one
5
and no_signaling_nans config settings. is_signaling_nan() doesn't
6
ever update the fp_status with any exception flags, so there is
7
no reason not to use env->fp_status here.
8
9
Use env->fp_status instead of the dummy fp_status.
4
10
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20241202131347.498124-34-peter.maydell@linaro.org
8
Message-id: 20220825150703.4074125-7-peter.maydell@linaro.org
9
---
14
---
10
configure | 3 +--
15
target/ppc/fpu_helper.c | 3 +--
11
1 file changed, 1 insertion(+), 2 deletions(-)
16
1 file changed, 1 insertion(+), 2 deletions(-)
12
17
13
diff --git a/configure b/configure
18
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
14
index XXXXXXX..XXXXXXX 100755
19
index XXXXXXX..XXXXXXX 100644
15
--- a/configure
20
--- a/target/ppc/fpu_helper.c
16
+++ b/configure
21
+++ b/target/ppc/fpu_helper.c
17
@@ -XXX,XX +XXX,XX @@ fi
22
@@ -XXX,XX +XXX,XX @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
18
# it when configure exits.)
23
} else if (tp##_is_infinity(arg)) { \
19
TMPDIR1="config-temp"
24
fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \
20
rm -rf "${TMPDIR1}"
25
} else { \
21
-mkdir -p "${TMPDIR1}"
26
- float_status dummy = { }; /* snan_bit_is_one = 0 */ \
22
-if [ $? -ne 0 ]; then
27
- if (tp##_is_signaling_nan(arg, &dummy)) { \
23
+if ! mkdir -p "${TMPDIR1}"; then
28
+ if (tp##_is_signaling_nan(arg, &env->fp_status)) { \
24
echo "ERROR: failed to create temporary directory"
29
fprf = 0x00 << FPSCR_FPRF; \
25
exit 1
30
} else { \
26
fi
31
fprf = 0x11 << FPSCR_FPRF; \
27
--
32
--
28
2.25.1
33
2.34.1
29
30
diff view generated by jsdifflib
[PULL 14/39] target/arm: Add is_secure parameter to get_phys_addr_v5
[PULL 39/72] target/arm: Copy entire float_status in is_ebf
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Remove the use of regime_is_secure from get_phys_addr_v5,
3
Now that float_status has a bunch of fp parameters,
4
passing the new parameter to the lookup instead.
4
it is easier to copy an existing structure than create
5
one from scratch. Begin by copying the structure that
6
corresponds to the FPSR and make only the adjustments
7
required for BFloat16 semantics.
5
8
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
[PMM: Folded in definition of local is_secure in get_phys_addr(),
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
since I dropped the earlier patch that would have provided it]
10
Message-id: 20220822152741.1617527-14-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20241203203949.483774-2-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
---
14
target/arm/ptw.c | 14 +++++++-------
15
target/arm/tcg/vec_helper.c | 20 +++++++-------------
15
1 file changed, 7 insertions(+), 7 deletions(-)
16
1 file changed, 7 insertions(+), 13 deletions(-)
16
17
17
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
18
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/ptw.c
20
--- a/target/arm/tcg/vec_helper.c
20
+++ b/target/arm/ptw.c
21
+++ b/target/arm/tcg/vec_helper.c
21
@@ -XXX,XX +XXX,XX @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
22
@@ -XXX,XX +XXX,XX @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp)
22
23
* no effect on AArch32 instructions.
23
static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
24
*/
24
MMUAccessType access_type, ARMMMUIdx mmu_idx,
25
bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF;
25
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
26
- *statusp = (float_status){
26
+ bool is_secure, GetPhysAddrResult *result,
27
- .tininess_before_rounding = float_tininess_before_rounding,
27
+ ARMMMUFaultInfo *fi)
28
- .float_rounding_mode = float_round_to_odd_inf,
28
{
29
- .flush_to_zero = true,
29
int level = 1;
30
- .flush_inputs_to_zero = true,
30
uint32_t table;
31
- .default_nan_mode = true,
31
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
32
- };
32
fi->type = ARMFault_Translation;
33
+
33
goto do_fault;
34
+ *statusp = env->vfp.fp_status;
35
+ set_default_nan_mode(true, statusp);
36
37
if (ebf) {
38
- float_status *fpst = &env->vfp.fp_status;
39
- set_flush_to_zero(get_flush_to_zero(fpst), statusp);
40
- set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp);
41
- set_float_rounding_mode(get_float_rounding_mode(fpst), statusp);
42
-
43
/* EBF=1 needs to do a step with round-to-odd semantics */
44
*oddstatusp = *statusp;
45
set_float_rounding_mode(float_round_to_odd, oddstatusp);
46
+ } else {
47
+ set_flush_to_zero(true, statusp);
48
+ set_flush_inputs_to_zero(true, statusp);
49
+ set_float_rounding_mode(float_round_to_odd_inf, statusp);
34
}
50
}
35
- desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx),
51
-
36
- mmu_idx, fi);
52
return ebf;
37
+ desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
38
if (fi->type != ARMFault_None) {
39
goto do_fault;
40
}
41
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
42
/* Fine pagetable. */
43
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
44
}
45
- desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx),
46
- mmu_idx, fi);
47
+ desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
48
if (fi->type != ARMFault_None) {
49
goto do_fault;
50
}
51
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
52
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
53
{
54
ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
55
+ bool is_secure = regime_is_secure(env, mmu_idx);
56
57
if (mmu_idx != s1_mmu_idx) {
58
/*
59
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
60
* cannot upgrade an non-secure translation regime's attributes
61
* to secure.
62
*/
63
- result->attrs.secure = regime_is_secure(env, mmu_idx);
64
+ result->attrs.secure = is_secure;
65
result->attrs.user = regime_is_user(env, mmu_idx);
66
67
/*
68
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
69
result, fi);
70
} else {
71
return get_phys_addr_v5(env, address, access_type, mmu_idx,
72
- result, fi);
73
+ is_secure, result, fi);
74
}
75
}
53
}
76
54
77
--
55
--
78
2.25.1
56
2.34.1
79
57
80
58
diff view generated by jsdifflib
[PULL 20/39] hw/acpi: Add ospm_status hook implementation for acpi-ged
[PULL 40/72] fpu: Allow runtime choice of default NaN value
1
From: Keqian Zhu <zhukeqian1@huawei.com>
1
Currently we hardcode the default NaN value in parts64_default_nan()
2
using a compile-time ifdef ladder. This is awkward for two cases:
3
* for single-QEMU-binary we can't hard-code target-specifics like this
4
* for Arm FEAT_AFP the default NaN value depends on FPCR.AH
5
(specifically the sign bit is different)
2
6
3
Setup an ARM virtual machine of machine virt and execute qmp "query-acpi-ospm-status"
7
Add a field to float_status to specify the default NaN value; fall
4
causes segmentation fault with following dumpstack:
8
back to the old ifdef behaviour if these are not set.
5
#1 0x0000aaaaab64235c in qmp_query_acpi_ospm_status (errp=errp@entry=0xfffffffff030) at ../monitor/qmp-cmds.c:312
6
#2 0x0000aaaaabfc4e20 in qmp_marshal_query_acpi_ospm_status (args=<optimized out>, ret=0xffffea4ffe90, errp=0xffffea4ffe88) at qapi/qapi-commands-acpi.c:63
7
#3 0x0000aaaaabff8ba0 in do_qmp_dispatch_bh (opaque=0xffffea4ffe98) at ../qapi/qmp-dispatch.c:128
8
#4 0x0000aaaaac02e594 in aio_bh_call (bh=0xffffe0004d80) at ../util/async.c:150
9
#5 aio_bh_poll (ctx=ctx@entry=0xaaaaad0f6040) at ../util/async.c:178
10
#6 0x0000aaaaac00bd40 in aio_dispatch (ctx=ctx@entry=0xaaaaad0f6040) at ../util/aio-posix.c:421
11
#7 0x0000aaaaac02e010 in aio_ctx_dispatch (source=0xaaaaad0f6040, callback=<optimized out>, user_data=<optimized out>) at ../util/async.c:320
12
#8 0x0000fffff76f6884 in g_main_context_dispatch () at /usr/lib64/libglib-2.0.so.0
13
#9 0x0000aaaaac0452d4 in glib_pollfds_poll () at ../util/main-loop.c:297
14
#10 os_host_main_loop_wait (timeout=0) at ../util/main-loop.c:320
15
#11 main_loop_wait (nonblocking=nonblocking@entry=0) at ../util/main-loop.c:596
16
#12 0x0000aaaaab5c9e50 in qemu_main_loop () at ../softmmu/runstate.c:734
17
#13 0x0000aaaaab185370 in qemu_main (argc=argc@entry=47, argv=argv@entry=0xfffffffff518, envp=envp@entry=0x0) at ../softmmu/main.c:38
18
#14 0x0000aaaaab16f99c in main (argc=47, argv=0xfffffffff518) at ../softmmu/main.c:47
19
9
20
Fixes: ebb62075021a ("hw/acpi: Add ACPI Generic Event Device Support")
10
The default NaN value is specified by setting a uint8_t to a
21
Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
11
pattern corresponding to the sign and upper fraction parts of
22
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
12
the NaN; the lower bits of the fraction are set from bit 0 of
23
Message-id: 20220816094957.31700-1-zhukeqian1@huawei.com
13
the pattern.
14
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20241202131347.498124-35-peter.maydell@linaro.org
25
---
18
---
26
hw/acpi/generic_event_device.c | 8 ++++++++
19
include/fpu/softfloat-helpers.h | 11 +++++++
27
1 file changed, 8 insertions(+)
20
include/fpu/softfloat-types.h | 10 ++++++
21
fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++-------------
22
3 files changed, 54 insertions(+), 22 deletions(-)
28
23
29
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
24
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
30
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/acpi/generic_event_device.c
26
--- a/include/fpu/softfloat-helpers.h
32
+++ b/hw/acpi/generic_event_device.c
27
+++ b/include/fpu/softfloat-helpers.h
33
@@ -XXX,XX +XXX,XX @@ static void acpi_ged_unplug_cb(HotplugHandler *hotplug_dev,
28
@@ -XXX,XX +XXX,XX @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
34
}
29
status->float_infzeronan_rule = rule;
35
}
30
}
36
31
37
+static void acpi_ged_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
32
+static inline void set_float_default_nan_pattern(uint8_t dnan_pattern,
33
+ float_status *status)
38
+{
34
+{
39
+ AcpiGedState *s = ACPI_GED(adev);
35
+ status->default_nan_pattern = dnan_pattern;
40
+
41
+ acpi_memory_ospm_status(&s->memhp_state, list);
42
+}
36
+}
43
+
37
+
44
static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
38
static inline void set_flush_to_zero(bool val, float_status *status)
45
{
39
{
46
AcpiGedState *s = ACPI_GED(adev);
40
status->flush_to_zero = val;
47
@@ -XXX,XX +XXX,XX @@ static void acpi_ged_class_init(ObjectClass *class, void *data)
41
@@ -XXX,XX +XXX,XX @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status
48
hc->unplug_request = acpi_ged_unplug_request_cb;
42
return status->float_infzeronan_rule;
49
hc->unplug = acpi_ged_unplug_cb;
50
51
+ adevc->ospm_status = acpi_ged_ospm_status;
52
adevc->send_event = acpi_ged_send_event;
53
}
43
}
54
44
45
+static inline uint8_t get_float_default_nan_pattern(float_status *status)
46
+{
47
+ return status->default_nan_pattern;
48
+}
49
+
50
static inline bool get_flush_to_zero(float_status *status)
51
{
52
return status->flush_to_zero;
53
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
54
index XXXXXXX..XXXXXXX 100644
55
--- a/include/fpu/softfloat-types.h
56
+++ b/include/fpu/softfloat-types.h
57
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
58
/* should denormalised inputs go to zero and set the input_denormal flag? */
59
bool flush_inputs_to_zero;
60
bool default_nan_mode;
61
+ /*
62
+ * The pattern to use for the default NaN. Here the high bit specifies
63
+ * the default NaN's sign bit, and bits 6..0 specify the high bits of the
64
+ * fractional part. The low bits of the fractional part are copies of bit 0.
65
+ * The exponent of the default NaN is (as for any NaN) always all 1s.
66
+ * Note that a value of 0 here is not a valid NaN. The target must set
67
+ * this to the correct non-zero value, or we will assert when trying to
68
+ * create a default NaN.
69
+ */
70
+ uint8_t default_nan_pattern;
71
/*
72
* The flags below are not used on all specializations and may
73
* constant fold away (see snan_bit_is_one()/no_signalling_nans() in
74
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
75
index XXXXXXX..XXXXXXX 100644
76
--- a/fpu/softfloat-specialize.c.inc
77
+++ b/fpu/softfloat-specialize.c.inc
78
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
79
{
80
bool sign = 0;
81
uint64_t frac;
82
+ uint8_t dnan_pattern = status->default_nan_pattern;
83
84
+ if (dnan_pattern == 0) {
85
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
86
- /* !snan_bit_is_one, set all bits */
87
- frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
88
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
89
+ /* Sign bit clear, all frac bits set */
90
+ dnan_pattern = 0b01111111;
91
+#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
92
|| defined(TARGET_MICROBLAZE)
93
- /* !snan_bit_is_one, set sign and msb */
94
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
95
- sign = 1;
96
+ /* Sign bit set, most significant frac bit set */
97
+ dnan_pattern = 0b11000000;
98
#elif defined(TARGET_HPPA)
99
- /* snan_bit_is_one, set msb-1. */
100
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
101
+ /* Sign bit clear, msb-1 frac bit set */
102
+ dnan_pattern = 0b00100000;
103
#elif defined(TARGET_HEXAGON)
104
- sign = 1;
105
- frac = ~0ULL;
106
+ /* Sign bit set, all frac bits set. */
107
+ dnan_pattern = 0b11111111;
108
#else
109
- /*
110
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
111
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
112
- * do not have floating-point.
113
- */
114
- if (snan_bit_is_one(status)) {
115
- /* set all bits other than msb */
116
- frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
117
- } else {
118
- /* set msb */
119
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
120
- }
121
+ /*
122
+ * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
123
+ * S390, SH4, TriCore, and Xtensa. Our other supported targets
124
+ * do not have floating-point.
125
+ */
126
+ if (snan_bit_is_one(status)) {
127
+ /* sign bit clear, set all frac bits other than msb */
128
+ dnan_pattern = 0b00111111;
129
+ } else {
130
+ /* sign bit clear, set frac msb */
131
+ dnan_pattern = 0b01000000;
132
+ }
133
#endif
134
+ }
135
+ assert(dnan_pattern != 0);
136
+
137
+ sign = dnan_pattern >> 7;
138
+ /*
139
+ * Place default_nan_pattern [6:0] into bits [62:56],
140
+ * and replecate bit [0] down into [55:0]
141
+ */
142
+ frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern);
143
+ frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1));
144
145
*p = (FloatParts64) {
146
.cls = float_class_qnan,
55
--
147
--
56
2.25.1
148
2.34.1
diff view generated by jsdifflib
New patch
[PULL 41/72] tests/fp: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the tests/fp code.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-36-peter.maydell@linaro.org
6
---
7
tests/fp/fp-bench.c | 1 +
8
tests/fp/fp-test-log2.c | 1 +
9
tests/fp/fp-test.c | 1 +
10
3 files changed, 3 insertions(+)
11
12
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tests/fp/fp-bench.c
15
+++ b/tests/fp/fp-bench.c
16
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
17
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
18
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
19
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
20
+ set_float_default_nan_pattern(0b01000000, &soft_status);
21
22
f = bench_funcs[operation][precision];
23
g_assert(f);
24
diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/tests/fp/fp-test-log2.c
27
+++ b/tests/fp/fp-test-log2.c
28
@@ -XXX,XX +XXX,XX @@ int main(int ac, char **av)
29
int i;
30
31
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
32
+ set_float_default_nan_pattern(0b01000000, &qsf);
33
set_float_rounding_mode(float_round_nearest_even, &qsf);
34
35
test.d = 0.0;
36
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/tests/fp/fp-test.c
39
+++ b/tests/fp/fp-test.c
40
@@ -XXX,XX +XXX,XX @@ void run_test(void)
41
*/
42
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
43
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
44
+ set_float_default_nan_pattern(0b01000000, &qsf);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
46
47
genCases_setLevel(test_level);
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 42/72] target/microblaze: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-37-peter.maydell@linaro.org
7
---
8
target/microblaze/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/microblaze/cpu.c
15
+++ b/target/microblaze/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj, ResetType type)
17
* this architecture.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
23
#if defined(CONFIG_USER_ONLY)
24
/* start in user mode with interrupts enabled. */
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
34
- || defined(TARGET_MICROBLAZE)
35
+#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
/* Sign bit set, most significant frac bit set */
37
dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 43/72] target/i386: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-38-peter.maydell@linaro.org
7
---
8
target/i386/tcg/fpu_helper.c | 4 ++++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 4 insertions(+), 3 deletions(-)
11
12
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/i386/tcg/fpu_helper.c
15
+++ b/target/i386/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
17
*/
18
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
19
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
+ set_float_default_nan_pattern(0b11000000, &env->mmx_status);
23
+ set_float_default_nan_pattern(0b11000000, &env->sse_status);
24
}
25
26
static inline uint8_t save_exception_flags(CPUX86State *env)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
32
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
/* Sign bit clear, all frac bits set */
34
dnan_pattern = 0b01111111;
35
-#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
- /* Sign bit set, most significant frac bit set */
37
- dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
/* Sign bit clear, msb-1 frac bit set */
40
dnan_pattern = 0b00100000;
41
--
42
2.34.1
diff view generated by jsdifflib
New patch
[PULL 44/72] target/hppa: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-39-peter.maydell@linaro.org
7
---
8
target/hppa/fpu_helper.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 2 insertions(+), 3 deletions(-)
11
12
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/hppa/fpu_helper.c
15
+++ b/target/hppa/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
17
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN: sign bit clear, msb-1 frac bit set */
21
+ set_float_default_nan_pattern(0b00100000, &env->fp_status);
22
}
23
24
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_HPPA)
34
- /* Sign bit clear, msb-1 frac bit set */
35
- dnan_pattern = 0b00100000;
36
#elif defined(TARGET_HEXAGON)
37
/* Sign bit set, all frac bits set. */
38
dnan_pattern = 0b11111111;
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 45/72] target/alpha: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the alpha target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-40-peter.maydell@linaro.org
6
---
7
target/alpha/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/alpha/cpu.c
13
+++ b/target/alpha/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj)
15
* operand in Fa. That is float_2nan_prop_ba.
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
#if defined(CONFIG_USER_ONLY)
21
env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
22
cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 46/72] target/arm: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the arm target.
2
This includes setting it for the old linux-user nwfpe emulation.
3
For nwfpe, our default doesn't match the real kernel, but we
4
avoid making a behaviour change in this commit.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-41-peter.maydell@linaro.org
9
---
10
linux-user/arm/nwfpe/fpa11.c | 5 +++++
11
target/arm/cpu.c | 2 ++
12
2 files changed, 7 insertions(+)
13
14
diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/linux-user/arm/nwfpe/fpa11.c
17
+++ b/linux-user/arm/nwfpe/fpa11.c
18
@@ -XXX,XX +XXX,XX @@ void resetFPA11(void)
19
* this late date.
20
*/
21
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status);
22
+ /*
23
+ * Use the same default NaN value as Arm VFP. This doesn't match
24
+ * the Linux kernel's nwfpe emulation, which uses an all-1s value.
25
+ */
26
+ set_float_default_nan_pattern(0b01000000, &fpa11->fp_status);
27
}
28
29
void SetRoundingMode(const unsigned int opcode)
30
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/cpu.c
33
+++ b/target/arm/cpu.c
34
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
35
* the pseudocode function the arguments are in the order c, a, b.
36
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
37
* and the input NaN if it is signalling
38
+ * * Default NaN has sign bit clear, msb frac bit set
39
*/
40
static void arm_set_default_fp_behaviours(float_status *s)
41
{
42
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
44
set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
46
+ set_float_default_nan_pattern(0b01000000, s);
47
}
48
49
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
50
--
51
2.34.1
diff view generated by jsdifflib
[PULL 39/39] configure: Avoid use of 'local' as it is non-POSIX
[PULL 47/72] target/loongarch: Set default NaN pattern explicitly
1
We use the non-POSIX 'local' keyword in just two places in configure;
1
Set the default NaN pattern explicitly for loongarch.
2
rewrite to avoid it.
3
4
In do_compiler(), just drop the 'local' keyword. The variable
5
'compiler' is only used elsewhere in the do_compiler_werror()
6
function, which already uses the variable as a normal non-local one.
7
8
In probe_target_compiler(), $try and $t are both local; make them
9
normal variables and use a more obviously distinct variable name
10
for $t.
11
2
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-id: 20241202131347.498124-42-peter.maydell@linaro.org
15
Message-id: 20220825150703.4074125-8-peter.maydell@linaro.org
16
---
6
---
17
configure | 7 +++----
7
target/loongarch/tcg/fpu_helper.c | 2 ++
18
1 file changed, 3 insertions(+), 4 deletions(-)
8
1 file changed, 2 insertions(+)
19
9
20
diff --git a/configure b/configure
10
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
21
index XXXXXXX..XXXXXXX 100755
11
index XXXXXXX..XXXXXXX 100644
22
--- a/configure
12
--- a/target/loongarch/tcg/fpu_helper.c
23
+++ b/configure
13
+++ b/target/loongarch/tcg/fpu_helper.c
24
@@ -XXX,XX +XXX,XX @@ error_exit() {
14
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
25
do_compiler() {
15
*/
26
# Run the compiler, capturing its output to the log. First argument
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
27
# is compiler binary to execute.
17
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
28
- local compiler="$1"
18
+ /* Default NaN: sign bit clear, msb frac bit set */
29
+ compiler="$1"
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
30
shift
20
}
31
if test -n "$BASH_VERSION"; then eval '
21
32
echo >>config.log "
22
int ieee_ex_to_loongarch(int xcpt)
33
@@ -XXX,XX +XXX,XX @@ probe_target_compiler() {
34
: ${container_cross_strip:=${container_cross_prefix}strip}
35
done
36
37
- local t try
38
try=cross
39
case "$target_arch:$cpu" in
40
aarch64_be:aarch64 | \
41
@@ -XXX,XX +XXX,XX @@ probe_target_compiler() {
42
try='native cross' ;;
43
esac
44
eval "target_cflags=\${cross_cc_cflags_$target_arch}"
45
- for t in $try; do
46
- case $t in
47
+ for thistry in $try; do
48
+ case $thistry in
49
native)
50
target_cc=$cc
51
target_ccas=$ccas
52
--
23
--
53
2.25.1
24
2.34.1
54
55
diff view generated by jsdifflib
[PULL 37/39] configure: Remove use of backtick `...` syntax
[PULL 48/72] target/m68k: Set default NaN pattern explicitly
1
There's only one place in configure where we use `...` to execute a
1
Set the default NaN pattern explicitly for m68k.
2
command and capture the result. Switch to $() to match the rest of
3
the script. This silences a shellcheck warning.
4
2
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-id: 20241202131347.498124-43-peter.maydell@linaro.org
8
Message-id: 20220825150703.4074125-6-peter.maydell@linaro.org
9
---
6
---
10
configure | 2 +-
7
target/m68k/cpu.c | 2 ++
11
1 file changed, 1 insertion(+), 1 deletion(-)
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 3 insertions(+), 1 deletion(-)
12
10
13
diff --git a/configure b/configure
11
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
14
index XXXXXXX..XXXXXXX 100755
12
index XXXXXXX..XXXXXXX 100644
15
--- a/configure
13
--- a/target/m68k/cpu.c
16
+++ b/configure
14
+++ b/target/m68k/cpu.c
17
@@ -XXX,XX +XXX,XX @@ LINKS="$LINKS python"
15
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
18
LINKS="$LINKS contrib/plugins/Makefile "
16
* preceding paragraph for nonsignaling NaNs.
19
for f in $LINKS ; do
17
*/
20
if [ -e "$source_path/$f" ]; then
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
21
- mkdir -p `dirname ./$f`
19
+ /* Default NaN: sign bit clear, all frac bits set */
22
+ mkdir -p "$(dirname ./"$f")"
20
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
23
symlink "$source_path/$f" "$f"
21
24
fi
22
nan = floatx80_default_nan(&env->fp_status);
25
done
23
for (i = 0; i < 8; i++) {
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
29
uint8_t dnan_pattern = status->default_nan_pattern;
30
31
if (dnan_pattern == 0) {
32
-#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
+#if defined(TARGET_SPARC)
34
/* Sign bit clear, all frac bits set */
35
dnan_pattern = 0b01111111;
36
#elif defined(TARGET_HEXAGON)
26
--
37
--
27
2.25.1
38
2.34.1
28
29
diff view generated by jsdifflib
[PULL 36/39] configure: Add './' on front of glob of */config-devices.mak.d
[PULL 49/72] target/mips: Set default NaN pattern explicitly
1
Shellcheck warns that in
1
Set the default NaN pattern explicitly for MIPS. Note that this
2
rm -f */config-devices.mak.d
2
is our only target which currently changes the default NaN
3
the glob might expand to something with a '-' in it, which would
3
at runtime (which it was previously doing indirectly when it
4
then be misinterpreted as an option to rm. Fix this by adding './'.
4
changed the snan_bit_is_one setting).
5
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20241202131347.498124-44-peter.maydell@linaro.org
9
Message-id: 20220825150703.4074125-5-peter.maydell@linaro.org
10
---
9
---
11
configure | 2 +-
10
target/mips/fpu_helper.h | 7 +++++++
12
1 file changed, 1 insertion(+), 1 deletion(-)
11
target/mips/msa.c | 3 +++
12
2 files changed, 10 insertions(+)
13
13
14
diff --git a/configure b/configure
14
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
15
index XXXXXXX..XXXXXXX 100755
15
index XXXXXXX..XXXXXXX 100644
16
--- a/configure
16
--- a/target/mips/fpu_helper.h
17
+++ b/configure
17
+++ b/target/mips/fpu_helper.h
18
@@ -XXX,XX +XXX,XX @@ exit 0
18
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
fi
19
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
20
20
nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
21
# Remove old dependency files to make sure that they get properly regenerated
21
set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
22
-rm -f */config-devices.mak.d
22
+ /*
23
+rm -f ./*/config-devices.mak.d
23
+ * With nan2008, the default NaN value has the sign bit clear and the
24
24
+ * frac msb set; with the older mode, the sign bit is clear, and all
25
if test -z "$python"
25
+ * frac bits except the msb are set.
26
then
26
+ */
27
+ set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111,
28
+ &env->active_fpu.fp_status);
29
30
}
31
32
diff --git a/target/mips/msa.c b/target/mips/msa.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/mips/msa.c
35
+++ b/target/mips/msa.c
36
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
37
/* Inf * 0 + NaN returns the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never,
39
&env->active_tc.msa_fp_status);
40
+ /* Default NaN: sign bit clear, frac msb set */
41
+ set_float_default_nan_pattern(0b01000000,
42
+ &env->active_tc.msa_fp_status);
43
}
27
--
44
--
28
2.25.1
45
2.34.1
29
30
diff view generated by jsdifflib
[PULL 34/39] configure: Remove unused meson_args variable
[PULL 50/72] target/openrisc: Set default NaN pattern explicitly
1
The meson_args variable was added in commit 3b4da13293482134b, but
1
Set the default NaN pattern explicitly for openrisc.
2
was not used in that commit and isn't used today. Delete the
3
unnecessary assignment.
4
2
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-id: 20241202131347.498124-45-peter.maydell@linaro.org
8
Message-id: 20220825150703.4074125-3-peter.maydell@linaro.org
9
---
6
---
10
configure | 1 -
7
target/openrisc/cpu.c | 2 ++
11
1 file changed, 1 deletion(-)
8
1 file changed, 2 insertions(+)
12
9
13
diff --git a/configure b/configure
10
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
14
index XXXXXXX..XXXXXXX 100755
11
index XXXXXXX..XXXXXXX 100644
15
--- a/configure
12
--- a/target/openrisc/cpu.c
16
+++ b/configure
13
+++ b/target/openrisc/cpu.c
17
@@ -XXX,XX +XXX,XX @@ pie=""
14
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type)
18
coroutine=""
15
*/
19
plugins="$default_feature"
16
set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status);
20
meson=""
17
21
-meson_args=""
18
+ /* Default NaN: sign bit clear, frac msb set */
22
ninja=""
19
+ set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status);
23
bindir="bin"
20
24
skip_meson=no
21
#ifndef CONFIG_USER_ONLY
22
cpu->env.picmr = 0x00000000;
25
--
23
--
26
2.25.1
24
2.34.1
27
28
diff view generated by jsdifflib
[PULL 33/39] configure: Remove unused python_version variable
[PULL 51/72] target/ppc: Set default NaN pattern explicitly
1
Shellcheck correctly reports that we set python_version and never use
1
Set the default NaN pattern explicitly for ppc.
2
it. This is a leftover from commit f9332757898a7: we used to use
3
python_version purely to as part of the summary information printed
4
at the end of a configure run, and that commit changed to printing
5
the information from meson (which looks up the python version
6
itself). Remove the unused variable.
7
2
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-id: 20241202131347.498124-46-peter.maydell@linaro.org
11
Message-id: 20220825150703.4074125-2-peter.maydell@linaro.org
12
---
6
---
13
configure | 3 ---
7
target/ppc/cpu_init.c | 4 ++++
14
1 file changed, 3 deletions(-)
8
1 file changed, 4 insertions(+)
15
9
16
diff --git a/configure b/configure
10
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
17
index XXXXXXX..XXXXXXX 100755
11
index XXXXXXX..XXXXXXX 100644
18
--- a/configure
12
--- a/target/ppc/cpu_init.c
19
+++ b/configure
13
+++ b/target/ppc/cpu_init.c
20
@@ -XXX,XX +XXX,XX @@ if ! $python -c 'import sys; sys.exit(sys.version_info < (3,6))'; then
14
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
21
"Use --python=/path/to/python to specify a supported Python."
15
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
fi
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
23
17
24
-# Preserve python version since some functionality is dependent on it
18
+ /* Default NaN: sign bit clear, set frac msb */
25
-python_version=$($python -c 'import sys; print("%d.%d.%d" % (sys.version_info[0], sys.version_info[1], sys.version_info[2]))' 2>/dev/null)
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
26
-
20
+ set_float_default_nan_pattern(0b01000000, &env->vec_status);
27
# Suppress writing compiled files
21
+
28
python="$python -B"
22
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
23
ppc_spr_t *spr = &env->spr_cb[i];
29
24
30
--
25
--
31
2.25.1
26
2.34.1
32
33
diff view generated by jsdifflib
[PULL 35/39] configure: Add missing quoting for some easy cases
[PULL 52/72] target/sh4: Set default NaN pattern explicitly
1
This commit adds quotes in some places which:
1
Set the default NaN pattern explicitly for sh4. Note that sh4
2
* are spotted by shellcheck
2
is one of the only three targets (the others being HPPA and
3
* are obviously incorrect
3
sometimes MIPS) that has snan_bit_is_one set.
4
* are easy to fix just by adding the quotes
5
6
It doesn't attempt fix all of the places shellcheck finds errors,
7
or even all the ones which are easy to fix. It's just a random
8
sampling which is hopefully easy to review and which cuts
9
down the size of the problem for next time somebody wants to
10
try to look at shellcheck errors.
11
4
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20241202131347.498124-47-peter.maydell@linaro.org
15
Message-id: 20220825150703.4074125-4-peter.maydell@linaro.org
16
---
8
---
17
configure | 64 +++++++++++++++++++++++++++----------------------------
9
target/sh4/cpu.c | 2 ++
18
1 file changed, 32 insertions(+), 32 deletions(-)
10
1 file changed, 2 insertions(+)
19
11
20
diff --git a/configure b/configure
12
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
21
index XXXXXXX..XXXXXXX 100755
13
index XXXXXXX..XXXXXXX 100644
22
--- a/configure
14
--- a/target/sh4/cpu.c
23
+++ b/configure
15
+++ b/target/sh4/cpu.c
24
@@ -XXX,XX +XXX,XX @@ GNUmakefile: ;
16
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
25
17
set_flush_to_zero(1, &env->fp_status);
26
EOF
18
#endif
27
cd build
19
set_default_nan_mode(1, &env->fp_status);
28
- exec $source_path/configure "$@"
20
+ /* sign bit clear, set all frac bits other than msb */
29
+ exec "$source_path/configure" "$@"
21
+ set_float_default_nan_pattern(0b00111111, &env->fp_status);
30
fi
31
32
# Temporary directory used for files created while
33
@@ -XXX,XX +XXX,XX @@ meson_option_build_array() {
34
printf ']\n'
35
}
22
}
36
23
37
-. $source_path/scripts/meson-buildoptions.sh
24
static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
38
+. "$source_path/scripts/meson-buildoptions.sh"
39
40
meson_options=
41
meson_option_add() {
42
@@ -XXX,XX +XXX,XX @@ for opt do
43
case "$opt" in
44
--help|-h) show_help=yes
45
;;
46
- --version|-V) exec cat $source_path/VERSION
47
+ --version|-V) exec cat "$source_path/VERSION"
48
;;
49
--prefix=*) prefix="$optarg"
50
;;
51
@@ -XXX,XX +XXX,XX @@ default_target_list=""
52
mak_wilds=""
53
54
if [ "$linux_user" != no ]; then
55
- if [ "$targetos" = linux ] && [ -d $source_path/linux-user/include/host/$cpu ]; then
56
+ if [ "$targetos" = linux ] && [ -d "$source_path/linux-user/include/host/$cpu" ]; then
57
linux_user=yes
58
elif [ "$linux_user" = yes ]; then
59
error_exit "linux-user not supported on this architecture"
60
@@ -XXX,XX +XXX,XX @@ if [ "$bsd_user" != no ]; then
61
if [ "$bsd_user" = "" ]; then
62
test $targetos = freebsd && bsd_user=yes
63
fi
64
- if [ "$bsd_user" = yes ] && ! [ -d $source_path/bsd-user/$targetos ]; then
65
+ if [ "$bsd_user" = yes ] && ! [ -d "$source_path/bsd-user/$targetos" ]; then
66
error_exit "bsd-user not supported on this host OS"
67
fi
68
fi
69
@@ -XXX,XX +XXX,XX @@ python="$python -B"
70
if test -z "$meson"; then
71
if test "$explicit_python" = no && has meson && version_ge "$(meson --version)" 0.59.3; then
72
meson=meson
73
- elif test $git_submodules_action != 'ignore' ; then
74
+ elif test "$git_submodules_action" != 'ignore' ; then
75
meson=git
76
elif test -e "${source_path}/meson/meson.py" ; then
77
meson=internal
78
@@ -XXX,XX +XXX,XX @@ esac
79
container="no"
80
if test $use_containers = "yes"; then
81
if has "docker" || has "podman"; then
82
- container=$($python $source_path/tests/docker/docker.py probe)
83
+ container=$($python "$source_path"/tests/docker/docker.py probe)
84
fi
85
fi
86
87
@@ -XXX,XX +XXX,XX @@ if test "$QEMU_GA_DISTRO" = ""; then
88
QEMU_GA_DISTRO=Linux
89
fi
90
if test "$QEMU_GA_VERSION" = ""; then
91
- QEMU_GA_VERSION=$(cat $source_path/VERSION)
92
+ QEMU_GA_VERSION=$(cat "$source_path"/VERSION)
93
fi
94
95
96
@@ -XXX,XX +XXX,XX @@ fi
97
for target in $target_list; do
98
target_dir="$target"
99
target_name=$(echo $target | cut -d '-' -f 1)$EXESUF
100
- mkdir -p $target_dir
101
+ mkdir -p "$target_dir"
102
case $target in
103
*-user) symlink "../qemu-$target_name" "$target_dir/qemu-$target_name" ;;
104
*) symlink "../qemu-system-$target_name" "$target_dir/qemu-system-$target_name" ;;
105
@@ -XXX,XX +XXX,XX @@ for target in $target_list; do
106
config_target_mak=tests/tcg/config-$target.mak
107
108
echo "# Automatically generated by configure - do not modify" > $config_target_mak
109
- echo "TARGET_NAME=$arch" >> $config_target_mak
110
+ echo "TARGET_NAME=$arch" >> "$config_target_mak"
111
case $target in
112
xtensa*-linux-user)
113
# the toolchain is not complete with headers, only build softmmu tests
114
continue
115
;;
116
*-softmmu)
117
- test -f $source_path/tests/tcg/$arch/Makefile.softmmu-target || continue
118
+ test -f "$source_path/tests/tcg/$arch/Makefile.softmmu-target" || continue
119
qemu="qemu-system-$arch"
120
;;
121
*-linux-user|*-bsd-user)
122
@@ -XXX,XX +XXX,XX @@ for target in $target_list; do
123
# compilers is a requirememt for adding a new test that needs a
124
# compiler feature.
125
126
- echo "BUILD_STATIC=$build_static" >> $config_target_mak
127
- write_target_makefile >> $config_target_mak
128
+ echo "BUILD_STATIC=$build_static" >> "$config_target_mak"
129
+ write_target_makefile >> "$config_target_mak"
130
case $target in
131
aarch64-*)
132
if do_compiler "$target_cc" $target_cflags \
133
-march=armv8.1-a+sve -o $TMPE $TMPC; then
134
- echo "CROSS_CC_HAS_SVE=y" >> $config_target_mak
135
+ echo "CROSS_CC_HAS_SVE=y" >> "$config_target_mak"
136
fi
137
if do_compiler "$target_cc" $target_cflags \
138
-march=armv8.1-a+sve2 -o $TMPE $TMPC; then
139
- echo "CROSS_CC_HAS_SVE2=y" >> $config_target_mak
140
+ echo "CROSS_CC_HAS_SVE2=y" >> "$config_target_mak"
141
fi
142
if do_compiler "$target_cc" $target_cflags \
143
-march=armv8.3-a -o $TMPE $TMPC; then
144
- echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak
145
+ echo "CROSS_CC_HAS_ARMV8_3=y" >> "$config_target_mak"
146
fi
147
if do_compiler "$target_cc" $target_cflags \
148
-mbranch-protection=standard -o $TMPE $TMPC; then
149
- echo "CROSS_CC_HAS_ARMV8_BTI=y" >> $config_target_mak
150
+ echo "CROSS_CC_HAS_ARMV8_BTI=y" >> "$config_target_mak"
151
fi
152
if do_compiler "$target_cc" $target_cflags \
153
-march=armv8.5-a+memtag -o $TMPE $TMPC; then
154
- echo "CROSS_CC_HAS_ARMV8_MTE=y" >> $config_target_mak
155
+ echo "CROSS_CC_HAS_ARMV8_MTE=y" >> "$config_target_mak"
156
fi
157
;;
158
ppc*)
159
if do_compiler "$target_cc" $target_cflags \
160
-mpower8-vector -o $TMPE $TMPC; then
161
- echo "CROSS_CC_HAS_POWER8_VECTOR=y" >> $config_target_mak
162
+ echo "CROSS_CC_HAS_POWER8_VECTOR=y" >> "$config_target_mak"
163
fi
164
if do_compiler "$target_cc" $target_cflags \
165
-mpower10 -o $TMPE $TMPC; then
166
- echo "CROSS_CC_HAS_POWER10=y" >> $config_target_mak
167
+ echo "CROSS_CC_HAS_POWER10=y" >> "$config_target_mak"
168
fi
169
;;
170
i386-linux-user)
171
if do_compiler "$target_cc" $target_cflags \
172
-Werror -fno-pie -o $TMPE $TMPC; then
173
- echo "CROSS_CC_HAS_I386_NOPIE=y" >> $config_target_mak
174
+ echo "CROSS_CC_HAS_I386_NOPIE=y" >> "$config_target_mak"
175
fi
176
;;
177
esac
178
elif test -n "$container_image"; then
179
echo "build-tcg-tests-$target: docker-image-$container_image" >> $makefile
180
- echo "BUILD_STATIC=y" >> $config_target_mak
181
- write_container_target_makefile >> $config_target_mak
182
+ echo "BUILD_STATIC=y" >> "$config_target_mak"
183
+ write_container_target_makefile >> "$config_target_mak"
184
case $target in
185
aarch64-*)
186
- echo "CROSS_CC_HAS_SVE=y" >> $config_target_mak
187
- echo "CROSS_CC_HAS_SVE2=y" >> $config_target_mak
188
- echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak
189
- echo "CROSS_CC_HAS_ARMV8_BTI=y" >> $config_target_mak
190
- echo "CROSS_CC_HAS_ARMV8_MTE=y" >> $config_target_mak
191
+ echo "CROSS_CC_HAS_SVE=y" >> "$config_target_mak"
192
+ echo "CROSS_CC_HAS_SVE2=y" >> "$config_target_mak"
193
+ echo "CROSS_CC_HAS_ARMV8_3=y" >> "$config_target_mak"
194
+ echo "CROSS_CC_HAS_ARMV8_BTI=y" >> "$config_target_mak"
195
+ echo "CROSS_CC_HAS_ARMV8_MTE=y" >> "$config_target_mak"
196
;;
197
ppc*)
198
- echo "CROSS_CC_HAS_POWER8_VECTOR=y" >> $config_target_mak
199
- echo "CROSS_CC_HAS_POWER10=y" >> $config_target_mak
200
+ echo "CROSS_CC_HAS_POWER8_VECTOR=y" >> "$config_target_mak"
201
+ echo "CROSS_CC_HAS_POWER10=y" >> "$config_target_mak"
202
;;
203
i386-linux-user)
204
- echo "CROSS_CC_HAS_I386_NOPIE=y" >> $config_target_mak
205
+ echo "CROSS_CC_HAS_I386_NOPIE=y" >> "$config_target_mak"
206
;;
207
esac
208
got_cross_cc=yes
209
fi
210
if test $got_cross_cc = yes; then
211
mkdir -p tests/tcg/$target
212
- echo "QEMU=$PWD/$qemu" >> $config_target_mak
213
+ echo "QEMU=$PWD/$qemu" >> "$config_target_mak"
214
echo "run-tcg-tests-$target: $qemu\$(EXESUF)" >> $makefile
215
tcg_tests_targets="$tcg_tests_targets $target"
216
fi
217
--
25
--
218
2.25.1
26
2.34.1
219
220
diff view generated by jsdifflib
[PULL 28/39] hw/intc/xics: Avoid dynamic stack allocation
[PULL 53/72] target/rx: Set default NaN pattern explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the default NaN pattern explicitly for rx.
2
2
3
Use autofree heap allocation instead of variable-length
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
array on the stack.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-48-peter.maydell@linaro.org
6
---
7
target/rx/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
5
9
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
7
Acked-by: David Gibson <david@gibson.dropbear.id.au>
8
Reviewed-by: Greg Kurz <groug@kaod.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20220819153931.3147384-8-peter.maydell@linaro.org
11
---
12
hw/intc/xics.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
16
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/xics.c
12
--- a/target/rx/cpu.c
18
+++ b/hw/intc/xics.c
13
+++ b/target/rx/cpu.c
19
@@ -XXX,XX +XXX,XX @@ static void ics_reset_irq(ICSIRQState *irq)
14
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj, ResetType type)
20
static void ics_reset(DeviceState *dev)
15
* then prefer dest over source", which is float_2nan_prop_s_ab.
21
{
16
*/
22
ICSState *ics = ICS(dev);
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
23
+ g_autofree uint8_t *flags = g_malloc(ics->nr_irqs);
18
+ /* Default NaN value: sign bit clear, set frac msb */
24
int i;
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
25
- uint8_t flags[ics->nr_irqs];
20
}
26
21
27
for (i = 0; i < ics->nr_irqs; i++) {
22
static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
28
flags[i] = ics->irqs[i].flags;
29
--
23
--
30
2.25.1
24
2.34.1
31
32
diff view generated by jsdifflib
[PULL 25/39] io/channel-websock: Replace strlen(const_str) by sizeof(const_str) - 1
[PULL 54/72] target/s390x: Set default NaN pattern explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the default NaN pattern explicitly for s390x.
2
2
3
The combined_key[... QIO_CHANNEL_WEBSOCK_GUID_LEN ...] array in
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
qio_channel_websock_handshake_send_res_ok() expands to a call
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
to strlen(QIO_CHANNEL_WEBSOCK_GUID), and the compiler doesn't
5
Message-id: 20241202131347.498124-49-peter.maydell@linaro.org
6
realize the string is const, so consider combined_key[] being
6
---
7
a variable-length array.
7
target/s390x/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
8
9
9
To remove the variable-length array, we provide it a hint to
10
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
10
the compiler by using sizeof() - 1 instead of strlen().
11
12
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Message-id: 20220819153931.3147384-5-peter.maydell@linaro.org
16
---
17
io/channel-websock.c | 2 +-
18
1 file changed, 1 insertion(+), 1 deletion(-)
19
20
diff --git a/io/channel-websock.c b/io/channel-websock.c
21
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
22
--- a/io/channel-websock.c
12
--- a/target/s390x/cpu.c
23
+++ b/io/channel-websock.c
13
+++ b/target/s390x/cpu.c
24
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
25
15
set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
26
#define QIO_CHANNEL_WEBSOCK_CLIENT_KEY_LEN 24
16
set_float_infzeronan_rule(float_infzeronan_dnan_always,
27
#define QIO_CHANNEL_WEBSOCK_GUID "258EAFA5-E914-47DA-95CA-C5AB0DC85B11"
17
&env->fpu_status);
28
-#define QIO_CHANNEL_WEBSOCK_GUID_LEN strlen(QIO_CHANNEL_WEBSOCK_GUID)
18
+ /* Default NaN value: sign bit clear, frac msb set */
29
+#define QIO_CHANNEL_WEBSOCK_GUID_LEN (sizeof(QIO_CHANNEL_WEBSOCK_GUID) - 1)
19
+ set_float_default_nan_pattern(0b01000000, &env->fpu_status);
30
20
/* fall through */
31
#define QIO_CHANNEL_WEBSOCK_HEADER_PROTOCOL "sec-websocket-protocol"
21
case RESET_TYPE_S390_CPU_NORMAL:
32
#define QIO_CHANNEL_WEBSOCK_HEADER_VERSION "sec-websocket-version"
22
env->psw.mask &= ~PSW_MASK_RI;
33
--
23
--
34
2.25.1
24
2.34.1
35
36
diff view generated by jsdifflib
[PULL 24/39] chardev/baum: Avoid dynamic stack allocation
[PULL 55/72] target/sparc: Set default NaN pattern explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the default NaN pattern explicitly for SPARC, and remove
2
the ifdef from parts64_default_nan.
2
3
3
Use autofree heap allocation instead of variable-length
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
array on the stack.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-50-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 5 +----
10
2 files changed, 3 insertions(+), 4 deletions(-)
5
11
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
7
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
8
Reviewed-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20220819153931.3147384-4-peter.maydell@linaro.org
11
---
12
chardev/baum.c | 3 ++-
13
1 file changed, 2 insertions(+), 1 deletion(-)
14
15
diff --git a/chardev/baum.c b/chardev/baum.c
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/chardev/baum.c
14
--- a/target/sparc/cpu.c
18
+++ b/chardev/baum.c
15
+++ b/target/sparc/cpu.c
19
@@ -XXX,XX +XXX,XX @@ static void baum_chr_accept_input(struct Chardev *chr)
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
20
static void baum_write_packet(BaumChardev *baum, const uint8_t *buf, int len)
17
set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
21
{
18
/* For inf * 0 + NaN, return the input NaN */
22
Chardev *chr = CHARDEV(baum);
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
23
- uint8_t io_buf[1 + 2 * len], *cur = io_buf;
20
+ /* Default NaN value: sign bit clear, all frac bits set */
24
+ g_autofree uint8_t *io_buf = g_malloc(1 + 2 * len);
21
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
25
+ uint8_t *cur = io_buf;
22
26
int room;
23
cpu_exec_realizefn(cs, &local_err);
27
*cur++ = ESC;
24
if (local_err != NULL) {
28
while (len--)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
uint8_t dnan_pattern = status->default_nan_pattern;
31
32
if (dnan_pattern == 0) {
33
-#if defined(TARGET_SPARC)
34
- /* Sign bit clear, all frac bits set */
35
- dnan_pattern = 0b01111111;
36
-#elif defined(TARGET_HEXAGON)
37
+#if defined(TARGET_HEXAGON)
38
/* Sign bit set, all frac bits set. */
39
dnan_pattern = 0b11111111;
40
#else
29
--
41
--
30
2.25.1
42
2.34.1
31
32
diff view generated by jsdifflib
[PULL 27/39] hw/ppc/pnv: Avoid dynamic stack allocation
[PULL 56/72] target/xtensa: Set default NaN pattern explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the default NaN pattern explicitly for xtensa.
2
2
3
Use autofree heap allocation instead of variable-length
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
array on the stack.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-51-peter.maydell@linaro.org
6
---
7
target/xtensa/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
5
9
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
7
Acked-by: David Gibson <david@gibson.dropbear.id.au>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
11
Message-id: 20220819153931.3147384-7-peter.maydell@linaro.org
12
---
13
hw/ppc/pnv.c | 4 ++--
14
hw/ppc/spapr.c | 8 ++++----
15
hw/ppc/spapr_pci_nvlink2.c | 2 +-
16
3 files changed, 7 insertions(+), 7 deletions(-)
17
18
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
19
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/ppc/pnv.c
12
--- a/target/xtensa/cpu.c
21
+++ b/hw/ppc/pnv.c
13
+++ b/target/xtensa/cpu.c
22
@@ -XXX,XX +XXX,XX @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
14
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
23
int smt_threads = CPU_CORE(pc)->nr_threads;
15
/* For inf * 0 + NaN, return the input NaN */
24
CPUPPCState *env = &cpu->env;
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
25
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
17
set_no_signaling_nans(!dfpu, &env->fp_status);
26
- uint32_t servers_prop[smt_threads];
18
+ /* Default NaN value: sign bit clear, set frac msb */
27
+ g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
28
int i;
20
xtensa_use_first_nan(env, !dfpu);
29
uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
30
0xffffffff, 0xffffffff};
31
@@ -XXX,XX +XXX,XX @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
32
servers_prop[i] = cpu_to_be32(pc->pir + i);
33
}
34
_FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
35
- servers_prop, sizeof(servers_prop))));
36
+ servers_prop, sizeof(*servers_prop) * smt_threads)));
37
}
21
}
38
22
39
static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
40
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/ppc/spapr.c
43
+++ b/hw/ppc/spapr.c
44
@@ -XXX,XX +XXX,XX @@ static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
45
int smt_threads)
46
{
47
int i, ret = 0;
48
- uint32_t servers_prop[smt_threads];
49
- uint32_t gservers_prop[smt_threads * 2];
50
+ g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
51
+ g_autofree uint32_t *gservers_prop = g_new(uint32_t, smt_threads * 2);
52
int index = spapr_get_vcpu_id(cpu);
53
54
if (cpu->compat_pvr) {
55
@@ -XXX,XX +XXX,XX @@ static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
56
gservers_prop[i*2 + 1] = 0;
57
}
58
ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
59
- servers_prop, sizeof(servers_prop));
60
+ servers_prop, sizeof(*servers_prop) * smt_threads);
61
if (ret < 0) {
62
return ret;
63
}
64
ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
65
- gservers_prop, sizeof(gservers_prop));
66
+ gservers_prop, sizeof(*gservers_prop) * smt_threads * 2);
67
68
return ret;
69
}
70
diff --git a/hw/ppc/spapr_pci_nvlink2.c b/hw/ppc/spapr_pci_nvlink2.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/ppc/spapr_pci_nvlink2.c
73
+++ b/hw/ppc/spapr_pci_nvlink2.c
74
@@ -XXX,XX +XXX,XX @@ void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, int offset,
75
continue;
76
}
77
if (dev == nvslot->gpdev) {
78
- uint32_t npus[nvslot->linknum];
79
+ g_autofree uint32_t *npus = g_new(uint32_t, nvslot->linknum);
80
81
for (j = 0; j < nvslot->linknum; ++j) {
82
PCIDevice *npdev = nvslot->links[j].npdev;
83
--
23
--
84
2.25.1
24
2.34.1
85
86
diff view generated by jsdifflib
[PULL 17/39] target/arm: Add is_secure parameter to pmsav7_use_background_region
[PULL 57/72] target/hexagon: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for hexagon.
2
Remove the ifdef from parts64_default_nan(); the only
3
remaining unconverted targets all use the default case.
2
4
3
Remove the use of regime_is_secure from pmsav7_use_background_region,
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
using the new parameter instead.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-52-peter.maydell@linaro.org
8
---
9
target/hexagon/cpu.c | 2 ++
10
fpu/softfloat-specialize.c.inc | 5 -----
11
2 files changed, 2 insertions(+), 5 deletions(-)
5
12
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-17-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/ptw.c | 10 +++++-----
13
1 file changed, 5 insertions(+), 5 deletions(-)
14
15
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/ptw.c
15
--- a/target/hexagon/cpu.c
18
+++ b/target/arm/ptw.c
16
+++ b/target/hexagon/cpu.c
19
@@ -XXX,XX +XXX,XX @@ static bool m_is_system_region(CPUARMState *env, uint32_t address)
17
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
18
19
set_default_nan_mode(1, &env->fp_status);
20
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
21
+ /* Default NaN value: sign bit set, all frac bits set */
22
+ set_float_default_nan_pattern(0b11111111, &env->fp_status);
20
}
23
}
21
24
22
static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
25
static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
23
- bool is_user)
26
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
24
+ bool is_secure, bool is_user)
27
index XXXXXXX..XXXXXXX 100644
25
{
28
--- a/fpu/softfloat-specialize.c.inc
26
/*
29
+++ b/fpu/softfloat-specialize.c.inc
27
* Return true if we should use the default memory map as a
30
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
28
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
31
uint8_t dnan_pattern = status->default_nan_pattern;
32
33
if (dnan_pattern == 0) {
34
-#if defined(TARGET_HEXAGON)
35
- /* Sign bit set, all frac bits set. */
36
- dnan_pattern = 0b11111111;
37
-#else
38
/*
39
* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
40
* S390, SH4, TriCore, and Xtensa. Our other supported targets
41
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
42
/* sign bit clear, set frac msb */
43
dnan_pattern = 0b01000000;
44
}
45
-#endif
29
}
46
}
30
47
assert(dnan_pattern != 0);
31
if (arm_feature(env, ARM_FEATURE_M)) {
32
- return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)]
33
- & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
34
+ return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
35
} else {
36
return regime_sctlr(env, mmu_idx) & SCTLR_BR;
37
}
38
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
39
{
40
ARMCPU *cpu = env_archcpu(env);
41
int n;
42
+ bool secure = regime_is_secure(env, mmu_idx);
43
bool is_user = regime_is_user(env, mmu_idx);
44
45
result->phys = address;
46
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
47
}
48
49
if (n == -1) { /* no hits */
50
- if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
51
+ if (!pmsav7_use_background_region(cpu, mmu_idx, secure, is_user)) {
52
/* background fault */
53
fi->type = ARMFault_Background;
54
return true;
55
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
56
} else if (m_is_ppb_region(env, address)) {
57
hit = true;
58
} else {
59
- if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
60
+ if (pmsav7_use_background_region(cpu, mmu_idx, secure, is_user)) {
61
hit = true;
62
}
63
48
64
--
49
--
65
2.25.1
50
2.34.1
66
67
diff view generated by jsdifflib
[PULL 23/39] chardev/baum: Use definitions to avoid dynamic stack allocation
[PULL 58/72] target/riscv: Set default NaN pattern explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the default NaN pattern explicitly for riscv.
2
2
3
We know 'x * y' will be at most 'X_MAX * Y_MAX' (which is not
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
a big value, it is actually 84). Instead of having the compiler
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
use variable-length array, declare an array able to hold the
5
Message-id: 20241202131347.498124-53-peter.maydell@linaro.org
6
maximum 'x * y'.
6
---
7
target/riscv/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
7
9
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
9
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
10
Reviewed-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20220819153931.3147384-3-peter.maydell@linaro.org
13
---
14
chardev/baum.c | 8 ++++----
15
1 file changed, 4 insertions(+), 4 deletions(-)
16
17
diff --git a/chardev/baum.c b/chardev/baum.c
18
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
19
--- a/chardev/baum.c
12
--- a/target/riscv/cpu.c
20
+++ b/chardev/baum.c
13
+++ b/target/riscv/cpu.c
21
@@ -XXX,XX +XXX,XX @@ static int baum_eat_packet(BaumChardev *baum, const uint8_t *buf, int len)
14
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
22
switch (req) {
15
cs->exception_index = RISCV_EXCP_NONE;
23
case BAUM_REQ_DisplayData:
16
env->load_res = -1;
24
{
17
set_default_nan_mode(1, &env->fp_status);
25
- uint8_t cells[baum->x * baum->y], c;
18
+ /* Default NaN value: sign bit clear, frac msb set */
26
- uint8_t text[baum->x * baum->y];
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
27
- uint8_t zero[baum->x * baum->y];
20
env->vill = true;
28
+ uint8_t cells[X_MAX * Y_MAX], c;
21
29
+ uint8_t text[X_MAX * Y_MAX];
22
#ifndef CONFIG_USER_ONLY
30
+ uint8_t zero[X_MAX * Y_MAX];
31
int cursor = BRLAPI_CURSOR_OFF;
32
int i;
33
34
@@ -XXX,XX +XXX,XX @@ static int baum_eat_packet(BaumChardev *baum, const uint8_t *buf, int len)
35
}
36
timer_del(baum->cellCount_timer);
37
38
- memset(zero, 0, sizeof(zero));
39
+ memset(zero, 0, baum->x * baum->y);
40
41
brlapi_writeArguments_t wa = {
42
.displayNumber = BRLAPI_DISPLAY_DEFAULT,
43
--
23
--
44
2.25.1
24
2.34.1
45
46
diff view generated by jsdifflib
[PULL 26/39] hw/net/e1000e_core: Use definition to avoid dynamic stack allocation
[PULL 59/72] target/tricore: Set default NaN pattern explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the default NaN pattern explicitly for tricore.
2
2
3
The compiler isn't clever enough to figure 'min_buf_size'
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
is a constant, so help it by using a definitions instead.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-54-peter.maydell@linaro.org
6
---
7
target/tricore/helper.c | 2 ++
8
1 file changed, 2 insertions(+)
5
9
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
7
Acked-by: Jason Wang <jasowang@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20220819153931.3147384-6-peter.maydell@linaro.org
11
---
12
hw/net/e1000e_core.c | 7 ++++---
13
1 file changed, 4 insertions(+), 3 deletions(-)
14
15
diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c
16
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/net/e1000e_core.c
12
--- a/target/tricore/helper.c
18
+++ b/hw/net/e1000e_core.c
13
+++ b/target/tricore/helper.c
19
@@ -XXX,XX +XXX,XX @@ e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt)
14
@@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env)
20
}
15
set_flush_to_zero(1, &env->fp_status);
16
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
17
set_default_nan_mode(1, &env->fp_status);
18
+ /* Default NaN pattern: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
21
}
20
}
22
21
23
+/* Min. octets in an ethernet frame sans FCS */
22
uint32_t psw_read(CPUTriCoreState *env)
24
+#define MIN_BUF_SIZE 60
25
+
26
ssize_t
27
e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt)
28
{
29
static const int maximum_ethernet_hdr_len = (14 + 4);
30
- /* Min. octets in an ethernet frame sans FCS */
31
- static const int min_buf_size = 60;
32
33
uint32_t n = 0;
34
- uint8_t min_buf[min_buf_size];
35
+ uint8_t min_buf[MIN_BUF_SIZE];
36
struct iovec min_iov;
37
uint8_t *filter_buf;
38
size_t size, orig_size;
39
--
23
--
40
2.25.1
24
2.34.1
41
42
diff view generated by jsdifflib
[PULL 22/39] chardev/baum: Replace magic values by X_MAX / Y_MAX definitions
[PULL 60/72] fpu: Remove default handling for dnan_pattern
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Now that all our targets have bene converted to explicitly specify
2
their pattern for the default NaN value we can remove the remaining
3
fallback code in parts64_default_nan().
2
4
3
Replace '84' magic value by the X_MAX definition, and '1' by Y_MAX.
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-55-peter.maydell@linaro.org
8
---
9
fpu/softfloat-specialize.c.inc | 14 --------------
10
1 file changed, 14 deletions(-)
4
11
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
6
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
7
Reviewed-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220819153931.3147384-2-peter.maydell@linaro.org
10
---
11
chardev/baum.c | 11 +++++++----
12
1 file changed, 7 insertions(+), 4 deletions(-)
13
14
diff --git a/chardev/baum.c b/chardev/baum.c
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/chardev/baum.c
14
--- a/fpu/softfloat-specialize.c.inc
17
+++ b/chardev/baum.c
15
+++ b/fpu/softfloat-specialize.c.inc
18
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
19
17
uint64_t frac;
20
#define BUF_SIZE 256
18
uint8_t dnan_pattern = status->default_nan_pattern;
21
19
22
+#define X_MAX 84
20
- if (dnan_pattern == 0) {
23
+#define Y_MAX 1
21
- /*
24
+
22
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
25
struct BaumChardev {
23
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
26
Chardev parent;
24
- * do not have floating-point.
27
25
- */
28
@@ -XXX,XX +XXX,XX @@ static int baum_deferred_init(BaumChardev *baum)
26
- if (snan_bit_is_one(status)) {
29
brlapi_perror("baum: brlapi__getDisplaySize");
27
- /* sign bit clear, set all frac bits other than msb */
30
return 0;
28
- dnan_pattern = 0b00111111;
31
}
29
- } else {
32
- if (baum->y > 1) {
30
- /* sign bit clear, set frac msb */
33
- baum->y = 1;
31
- dnan_pattern = 0b01000000;
34
+ if (baum->y > Y_MAX) {
32
- }
35
+ baum->y = Y_MAX;
33
- }
36
}
34
assert(dnan_pattern != 0);
37
- if (baum->x > 84) {
35
38
- baum->x = 84;
36
sign = dnan_pattern >> 7;
39
+ if (baum->x > X_MAX) {
40
+ baum->x = X_MAX;
41
}
42
43
con = qemu_console_lookup_by_index(0);
44
--
37
--
45
2.25.1
38
2.34.1
46
47
diff view generated by jsdifflib
[PULL 06/39] target/arm: Use GetPhysAddrResult in get_phys_addr_v5
[PULL 61/72] softfloat: Inline pickNaNMulAdd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
Inline pickNaNMulAdd into its only caller. This makes
4
one assert redundant with the immediately preceding IF.
5
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20220822152741.1617527-6-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-3-richard.henderson@linaro.org
9
[PMM: keep comment from old code in new location]
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
11
---
9
target/arm/ptw.c | 25 +++++++++++--------------
12
fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++-
10
1 file changed, 11 insertions(+), 14 deletions(-)
13
fpu/softfloat-specialize.c.inc | 54 ----------------------------------
14
2 files changed, 40 insertions(+), 55 deletions(-)
11
15
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
13
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/ptw.c
18
--- a/fpu/softfloat-parts.c.inc
15
+++ b/target/arm/ptw.c
19
+++ b/fpu/softfloat-parts.c.inc
16
@@ -XXX,XX +XXX,XX @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
17
21
}
18
static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
22
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
23
if (s->default_nan_mode) {
20
- hwaddr *phys_ptr, int *prot,
24
+ /*
21
- target_ulong *page_size,
25
+ * We guarantee not to require the target to tell us how to
22
- ARMMMUFaultInfo *fi)
26
+ * pick a NaN if we're always returning the default NaN.
23
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
27
+ * But if we're not in default-NaN mode then the target must
24
{
28
+ * specify.
25
int level = 1;
29
+ */
26
uint32_t table;
30
which = 3;
27
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
31
+ } else if (infzero) {
28
/* 1Mb section. */
32
+ /*
29
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
33
+ * Inf * 0 + NaN -- some implementations return the
30
ap = (desc >> 10) & 3;
34
+ * default NaN here, and some return the input NaN.
31
- *page_size = 1024 * 1024;
35
+ */
32
+ result->page_size = 1024 * 1024;
36
+ switch (s->float_infzeronan_rule) {
37
+ case float_infzeronan_dnan_never:
38
+ which = 2;
39
+ break;
40
+ case float_infzeronan_dnan_always:
41
+ which = 3;
42
+ break;
43
+ case float_infzeronan_dnan_if_qnan:
44
+ which = is_qnan(c->cls) ? 3 : 2;
45
+ break;
46
+ default:
47
+ g_assert_not_reached();
48
+ }
33
} else {
49
} else {
34
/* Lookup l2 entry. */
50
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
35
if (type == 1) {
51
+ FloatClass cls[3] = { a->cls, b->cls, c->cls };
36
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
52
+ Float3NaNPropRule rule = s->float_3nan_prop_rule;
37
case 1: /* 64k page. */
53
+
38
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
54
+ assert(rule != float_3nan_prop_none);
39
ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
55
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
40
- *page_size = 0x10000;
56
+ /* We have at least one SNaN input and should prefer it */
41
+ result->page_size = 0x10000;
57
+ do {
42
break;
58
+ which = rule & R_3NAN_1ST_MASK;
43
case 2: /* 4k page. */
59
+ rule >>= R_3NAN_1ST_LENGTH;
44
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
60
+ } while (!is_snan(cls[which]));
45
ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
61
+ } else {
46
- *page_size = 0x1000;
62
+ do {
47
+ result->page_size = 0x1000;
63
+ which = rule & R_3NAN_1ST_MASK;
48
break;
64
+ rule >>= R_3NAN_1ST_LENGTH;
49
case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
65
+ } while (!is_nan(cls[which]));
50
if (type == 1) {
66
+ }
51
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
52
if (arm_feature(env, ARM_FEATURE_XSCALE)
53
|| arm_feature(env, ARM_FEATURE_V6)) {
54
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
55
- *page_size = 0x1000;
56
+ result->page_size = 0x1000;
57
} else {
58
/*
59
* UNPREDICTABLE in ARMv5; we choose to take a
60
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
61
}
62
} else {
63
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
64
- *page_size = 0x400;
65
+ result->page_size = 0x400;
66
}
67
ap = (desc >> 4) & 3;
68
break;
69
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
70
g_assert_not_reached();
71
}
72
}
67
}
73
- *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
68
74
- *prot |= *prot ? PAGE_EXEC : 0;
69
if (which == 3) {
75
- if (!(*prot & (1 << access_type))) {
70
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
76
+ result->prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
71
index XXXXXXX..XXXXXXX 100644
77
+ result->prot |= result->prot ? PAGE_EXEC : 0;
72
--- a/fpu/softfloat-specialize.c.inc
78
+ if (!(result->prot & (1 << access_type))) {
73
+++ b/fpu/softfloat-specialize.c.inc
79
/* Access permission fault. */
74
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
80
fi->type = ARMFault_Permission;
81
goto do_fault;
82
}
83
- *phys_ptr = phys_addr;
84
+ result->phys = phys_addr;
85
return false;
86
do_fault:
87
fi->domain = domain;
88
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
89
result, fi);
90
} else {
91
return get_phys_addr_v5(env, address, access_type, mmu_idx,
92
- &result->phys, &result->prot,
93
- &result->page_size, fi);
94
+ result, fi);
95
}
75
}
96
}
76
}
97
77
78
-/*----------------------------------------------------------------------------
79
-| Select which NaN to propagate for a three-input operation.
80
-| For the moment we assume that no CPU needs the 'larger significand'
81
-| information.
82
-| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
83
-*----------------------------------------------------------------------------*/
84
-static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
85
- bool infzero, bool have_snan, float_status *status)
86
-{
87
- FloatClass cls[3] = { a_cls, b_cls, c_cls };
88
- Float3NaNPropRule rule = status->float_3nan_prop_rule;
89
- int which;
90
-
91
- /*
92
- * We guarantee not to require the target to tell us how to
93
- * pick a NaN if we're always returning the default NaN.
94
- * But if we're not in default-NaN mode then the target must
95
- * specify.
96
- */
97
- assert(!status->default_nan_mode);
98
-
99
- if (infzero) {
100
- /*
101
- * Inf * 0 + NaN -- some implementations return the default NaN here,
102
- * and some return the input NaN.
103
- */
104
- switch (status->float_infzeronan_rule) {
105
- case float_infzeronan_dnan_never:
106
- return 2;
107
- case float_infzeronan_dnan_always:
108
- return 3;
109
- case float_infzeronan_dnan_if_qnan:
110
- return is_qnan(c_cls) ? 3 : 2;
111
- default:
112
- g_assert_not_reached();
113
- }
114
- }
115
-
116
- assert(rule != float_3nan_prop_none);
117
- if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
118
- /* We have at least one SNaN input and should prefer it */
119
- do {
120
- which = rule & R_3NAN_1ST_MASK;
121
- rule >>= R_3NAN_1ST_LENGTH;
122
- } while (!is_snan(cls[which]));
123
- } else {
124
- do {
125
- which = rule & R_3NAN_1ST_MASK;
126
- rule >>= R_3NAN_1ST_LENGTH;
127
- } while (!is_nan(cls[which]));
128
- }
129
- return which;
130
-}
131
-
132
/*----------------------------------------------------------------------------
133
| Returns 1 if the double-precision floating-point value `a' is a quiet
134
| NaN; otherwise returns 0.
98
--
135
--
99
2.25.1
136
2.34.1
100
137
101
138
diff view generated by jsdifflib
[PULL 05/39] target/arm: Use GetPhysAddrResult in get_phys_addr_v6
[PULL 62/72] softfloat: Use goto for default nan case in pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
Remove "3" as a special case for which and simply
4
branch to return the desired value.
5
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20220822152741.1617527-5-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-4-richard.henderson@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
10
---
9
target/arm/ptw.c | 30 ++++++++++++++----------------
11
fpu/softfloat-parts.c.inc | 20 ++++++++++----------
10
1 file changed, 14 insertions(+), 16 deletions(-)
12
1 file changed, 10 insertions(+), 10 deletions(-)
11
13
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
13
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/ptw.c
16
--- a/fpu/softfloat-parts.c.inc
15
+++ b/target/arm/ptw.c
17
+++ b/fpu/softfloat-parts.c.inc
16
@@ -XXX,XX +XXX,XX @@ do_fault:
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
17
19
* But if we're not in default-NaN mode then the target must
18
static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
20
* specify.
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
21
*/
20
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
22
- which = 3;
21
- target_ulong *page_size, ARMMMUFaultInfo *fi)
23
+ goto default_nan;
22
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
24
} else if (infzero) {
23
{
25
/*
24
ARMCPU *cpu = env_archcpu(env);
26
* Inf * 0 + NaN -- some implementations return the
25
int level = 1;
27
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
26
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
28
*/
27
phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
29
switch (s->float_infzeronan_rule) {
28
phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
30
case float_infzeronan_dnan_never:
29
phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
31
- which = 2;
30
- *page_size = 0x1000000;
31
+ result->page_size = 0x1000000;
32
} else {
33
/* Section. */
34
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
35
- *page_size = 0x100000;
36
+ result->page_size = 0x100000;
37
}
38
ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
39
xn = desc & (1 << 4);
40
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
41
case 1: /* 64k page. */
42
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
43
xn = desc & (1 << 15);
44
- *page_size = 0x10000;
45
+ result->page_size = 0x10000;
46
break;
32
break;
47
case 2: case 3: /* 4k page. */
33
case float_infzeronan_dnan_always:
48
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
34
- which = 3;
49
xn = desc & 1;
35
- break;
50
- *page_size = 0x1000;
36
+ goto default_nan;
51
+ result->page_size = 0x1000;
37
case float_infzeronan_dnan_if_qnan:
38
- which = is_qnan(c->cls) ? 3 : 2;
39
+ if (is_qnan(c->cls)) {
40
+ goto default_nan;
41
+ }
52
break;
42
break;
53
default:
43
default:
54
/* Never happens, but compiler isn't smart enough to tell. */
44
g_assert_not_reached();
55
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
45
}
46
+ which = 2;
47
} else {
48
FloatClass cls[3] = { a->cls, b->cls, c->cls };
49
Float3NaNPropRule rule = s->float_3nan_prop_rule;
50
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
56
}
51
}
57
}
52
}
58
if (domain_prot == 3) {
53
59
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
54
- if (which == 3) {
60
+ result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
55
- parts_default_nan(a, s);
61
} else {
56
- return a;
62
if (pxn && !regime_is_user(env, mmu_idx)) {
57
- }
63
xn = 1;
58
-
64
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
59
switch (which) {
65
fi->type = ARMFault_AccessFlag;
60
case 0:
66
goto do_fault;
61
break;
67
}
62
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
68
- *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
63
parts_silence_nan(a, s);
69
+ result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
70
} else {
71
- *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
72
+ result->prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
73
}
74
- if (*prot && !xn) {
75
- *prot |= PAGE_EXEC;
76
+ if (result->prot && !xn) {
77
+ result->prot |= PAGE_EXEC;
78
}
79
- if (!(*prot & (1 << access_type))) {
80
+ if (!(result->prot & (1 << access_type))) {
81
/* Access permission fault. */
82
fi->type = ARMFault_Permission;
83
goto do_fault;
84
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
85
* the CPU doesn't support TZ or this is a non-secure translation
86
* regime, because the attribute will already be non-secure.
87
*/
88
- attrs->secure = false;
89
+ result->attrs.secure = false;
90
}
64
}
91
- *phys_ptr = phys_addr;
65
return a;
92
+ result->phys = phys_addr;
66
+
93
return false;
67
+ default_nan:
94
do_fault:
68
+ parts_default_nan(a, s);
95
fi->domain = domain;
69
+ return a;
96
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
70
}
97
result, fi);
71
98
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
72
/*
99
return get_phys_addr_v6(env, address, access_type, mmu_idx,
100
- &result->phys, &result->attrs,
101
- &result->prot, &result->page_size, fi);
102
+ result, fi);
103
} else {
104
return get_phys_addr_v5(env, address, access_type, mmu_idx,
105
&result->phys, &result->prot,
106
--
73
--
107
2.25.1
74
2.34.1
108
75
109
76
diff view generated by jsdifflib
[PULL 13/39] target/arm: Add secure parameter to pmsav8_mpu_lookup
[PULL 63/72] softfloat: Remove which from parts_pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Remove the use of regime_is_secure from pmsav8_mpu_lookup,
3
Assign the pointer return value to 'a' directly,
4
passing the new parameter to the lookup instead.
4
rather than going through an intermediary index.
5
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-13-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-5-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/internals.h | 4 ++--
11
fpu/softfloat-parts.c.inc | 32 ++++++++++----------------------
13
target/arm/m_helper.c | 2 +-
12
1 file changed, 10 insertions(+), 22 deletions(-)
14
target/arm/ptw.c | 7 +++----
15
3 files changed, 6 insertions(+), 7 deletions(-)
16
13
17
diff --git a/target/arm/internals.h b/target/arm/internals.h
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/internals.h
16
--- a/fpu/softfloat-parts.c.inc
20
+++ b/target/arm/internals.h
17
+++ b/fpu/softfloat-parts.c.inc
21
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
22
19
FloatPartsN *c, float_status *s,
23
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
20
int ab_mask, int abc_mask)
24
MMUAccessType access_type, ARMMMUIdx mmu_idx,
25
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi,
26
- uint32_t *mregion);
27
+ bool is_secure, GetPhysAddrResult *result,
28
+ ARMMMUFaultInfo *fi, uint32_t *mregion);
29
30
void arm_log_exception(CPUState *cs);
31
32
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/m_helper.c
35
+++ b/target/arm/m_helper.c
36
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
37
ARMMMUFaultInfo fi = {};
38
39
/* We can ignore the return value as prot is always set */
40
- pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
41
+ pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, targetsec,
42
&res, &fi, &mregion);
43
if (mregion == -1) {
44
mrvalid = false;
45
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/ptw.c
48
+++ b/target/arm/ptw.c
49
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
50
51
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
52
MMUAccessType access_type, ARMMMUIdx mmu_idx,
53
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi,
54
- uint32_t *mregion)
55
+ bool secure, GetPhysAddrResult *result,
56
+ ARMMMUFaultInfo *fi, uint32_t *mregion)
57
{
21
{
58
/*
22
- int which;
59
* Perform a PMSAv8 MPU lookup (without also doing the SAU check
23
bool infzero = (ab_mask == float_cmask_infzero);
60
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
24
bool have_snan = (abc_mask & float_cmask_snan);
61
*/
25
+ FloatPartsN *ret;
62
ARMCPU *cpu = env_archcpu(env);
26
63
bool is_user = regime_is_user(env, mmu_idx);
27
if (unlikely(have_snan)) {
64
- uint32_t secure = regime_is_secure(env, mmu_idx);
28
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
65
int n;
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
66
int matchregion = -1;
30
default:
67
bool hit = false;
31
g_assert_not_reached();
68
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
32
}
33
- which = 2;
34
+ ret = c;
35
} else {
36
- FloatClass cls[3] = { a->cls, b->cls, c->cls };
37
+ FloatPartsN *val[3] = { a, b, c };
38
Float3NaNPropRule rule = s->float_3nan_prop_rule;
39
40
assert(rule != float_3nan_prop_none);
41
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
42
/* We have at least one SNaN input and should prefer it */
43
do {
44
- which = rule & R_3NAN_1ST_MASK;
45
+ ret = val[rule & R_3NAN_1ST_MASK];
46
rule >>= R_3NAN_1ST_LENGTH;
47
- } while (!is_snan(cls[which]));
48
+ } while (!is_snan(ret->cls));
49
} else {
50
do {
51
- which = rule & R_3NAN_1ST_MASK;
52
+ ret = val[rule & R_3NAN_1ST_MASK];
53
rule >>= R_3NAN_1ST_LENGTH;
54
- } while (!is_nan(cls[which]));
55
+ } while (!is_nan(ret->cls));
69
}
56
}
70
}
57
}
71
58
72
- ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx,
59
- switch (which) {
73
+ ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, secure,
60
- case 0:
74
result, fi, NULL);
61
- break;
75
if (sattrs.subpage) {
62
- case 1:
76
result->page_size = 1;
63
- a = b;
64
- break;
65
- case 2:
66
- a = c;
67
- break;
68
- default:
69
- g_assert_not_reached();
70
+ if (is_snan(ret->cls)) {
71
+ parts_silence_nan(ret, s);
72
}
73
- if (is_snan(a->cls)) {
74
- parts_silence_nan(a, s);
75
- }
76
- return a;
77
+ return ret;
78
79
default_nan:
80
parts_default_nan(a, s);
77
--
81
--
78
2.25.1
82
2.34.1
79
83
80
84
diff view generated by jsdifflib
[PULL 18/39] target/arm: Add secure parameter to get_phys_addr_pmsav7
[PULL 64/72] softfloat: Pad array size in pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Remove the use of regime_is_secure from get_phys_addr_pmsav7,
3
While all indices into val[] should be in [0-2], the mask
4
using the new parameter instead.
4
applied is two bits. To help static analysis see there is
5
no possibility of read beyond the end of the array, pad the
6
array to 4 entries, with the final being (implicitly) NULL.
5
7
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-19-richard.henderson@linaro.org
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20241203203949.483774-6-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
---
12
target/arm/ptw.c | 5 ++---
13
fpu/softfloat-parts.c.inc | 2 +-
13
1 file changed, 2 insertions(+), 3 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
15
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/ptw.c
18
--- a/fpu/softfloat-parts.c.inc
18
+++ b/target/arm/ptw.c
19
+++ b/fpu/softfloat-parts.c.inc
19
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
20
21
}
21
static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
22
ret = c;
22
MMUAccessType access_type, ARMMMUIdx mmu_idx,
23
} else {
23
- GetPhysAddrResult *result,
24
- FloatPartsN *val[3] = { a, b, c };
24
+ bool secure, GetPhysAddrResult *result,
25
+ FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c };
25
ARMMMUFaultInfo *fi)
26
Float3NaNPropRule rule = s->float_3nan_prop_rule;
26
{
27
27
ARMCPU *cpu = env_archcpu(env);
28
assert(rule != float_3nan_prop_none);
28
int n;
29
- bool secure = regime_is_secure(env, mmu_idx);
30
bool is_user = regime_is_user(env, mmu_idx);
31
32
result->phys = address;
33
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
34
} else if (arm_feature(env, ARM_FEATURE_V7)) {
35
/* PMSAv7 */
36
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
37
- result, fi);
38
+ is_secure, result, fi);
39
} else {
40
/* Pre-v7 MPU */
41
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
42
--
29
--
43
2.25.1
30
2.34.1
44
31
45
32
diff view generated by jsdifflib
[PULL 16/39] target/arm: Add secure parameter to get_phys_addr_pmsav8
[PULL 65/72] softfloat: Move propagateFloatx80NaN to softfloat.c
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Remove the use of regime_is_secure from get_phys_addr_pmsav8.
3
This function is part of the public interface and
4
Since we already had a local variable named secure, use that.
4
is not "specialized" to any target in any way.
5
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-16-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-7-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/ptw.c | 5 ++---
11
fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++
13
1 file changed, 2 insertions(+), 3 deletions(-)
12
fpu/softfloat-specialize.c.inc | 52 ----------------------------------
13
2 files changed, 52 insertions(+), 52 deletions(-)
14
14
15
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/ptw.c
17
--- a/fpu/softfloat.c
18
+++ b/target/arm/ptw.c
18
+++ b/fpu/softfloat.c
19
@@ -XXX,XX +XXX,XX @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
20
20
*zExpPtr = 1 - shiftCount;
21
static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
21
}
22
MMUAccessType access_type, ARMMMUIdx mmu_idx,
22
23
- GetPhysAddrResult *result,
23
+/*----------------------------------------------------------------------------
24
+ bool secure, GetPhysAddrResult *result,
24
+| Takes two extended double-precision floating-point values `a' and `b', one
25
ARMMMUFaultInfo *fi)
25
+| of which is a NaN, and returns the appropriate NaN result. If either `a' or
26
{
26
+| `b' is a signaling NaN, the invalid exception is raised.
27
- uint32_t secure = regime_is_secure(env, mmu_idx);
27
+*----------------------------------------------------------------------------*/
28
V8M_SAttributes sattrs = {};
28
+
29
bool ret;
29
+floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
30
30
+{
31
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
31
+ bool aIsLargerSignificand;
32
if (arm_feature(env, ARM_FEATURE_V8)) {
32
+ FloatClass a_cls, b_cls;
33
/* PMSAv8 */
33
+
34
ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
34
+ /* This is not complete, but is good enough for pickNaN. */
35
- result, fi);
35
+ a_cls = (!floatx80_is_any_nan(a)
36
+ is_secure, result, fi);
36
+ ? float_class_normal
37
} else if (arm_feature(env, ARM_FEATURE_V7)) {
37
+ : floatx80_is_signaling_nan(a, status)
38
/* PMSAv7 */
38
+ ? float_class_snan
39
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
39
+ : float_class_qnan);
40
+ b_cls = (!floatx80_is_any_nan(b)
41
+ ? float_class_normal
42
+ : floatx80_is_signaling_nan(b, status)
43
+ ? float_class_snan
44
+ : float_class_qnan);
45
+
46
+ if (is_snan(a_cls) || is_snan(b_cls)) {
47
+ float_raise(float_flag_invalid, status);
48
+ }
49
+
50
+ if (status->default_nan_mode) {
51
+ return floatx80_default_nan(status);
52
+ }
53
+
54
+ if (a.low < b.low) {
55
+ aIsLargerSignificand = 0;
56
+ } else if (b.low < a.low) {
57
+ aIsLargerSignificand = 1;
58
+ } else {
59
+ aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
60
+ }
61
+
62
+ if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
63
+ if (is_snan(b_cls)) {
64
+ return floatx80_silence_nan(b, status);
65
+ }
66
+ return b;
67
+ } else {
68
+ if (is_snan(a_cls)) {
69
+ return floatx80_silence_nan(a, status);
70
+ }
71
+ return a;
72
+ }
73
+}
74
+
75
/*----------------------------------------------------------------------------
76
| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
77
| and extended significand formed by the concatenation of `zSig0' and `zSig1',
78
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
79
index XXXXXXX..XXXXXXX 100644
80
--- a/fpu/softfloat-specialize.c.inc
81
+++ b/fpu/softfloat-specialize.c.inc
82
@@ -XXX,XX +XXX,XX @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
83
return a;
84
}
85
86
-/*----------------------------------------------------------------------------
87
-| Takes two extended double-precision floating-point values `a' and `b', one
88
-| of which is a NaN, and returns the appropriate NaN result. If either `a' or
89
-| `b' is a signaling NaN, the invalid exception is raised.
90
-*----------------------------------------------------------------------------*/
91
-
92
-floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
93
-{
94
- bool aIsLargerSignificand;
95
- FloatClass a_cls, b_cls;
96
-
97
- /* This is not complete, but is good enough for pickNaN. */
98
- a_cls = (!floatx80_is_any_nan(a)
99
- ? float_class_normal
100
- : floatx80_is_signaling_nan(a, status)
101
- ? float_class_snan
102
- : float_class_qnan);
103
- b_cls = (!floatx80_is_any_nan(b)
104
- ? float_class_normal
105
- : floatx80_is_signaling_nan(b, status)
106
- ? float_class_snan
107
- : float_class_qnan);
108
-
109
- if (is_snan(a_cls) || is_snan(b_cls)) {
110
- float_raise(float_flag_invalid, status);
111
- }
112
-
113
- if (status->default_nan_mode) {
114
- return floatx80_default_nan(status);
115
- }
116
-
117
- if (a.low < b.low) {
118
- aIsLargerSignificand = 0;
119
- } else if (b.low < a.low) {
120
- aIsLargerSignificand = 1;
121
- } else {
122
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
123
- }
124
-
125
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
126
- if (is_snan(b_cls)) {
127
- return floatx80_silence_nan(b, status);
128
- }
129
- return b;
130
- } else {
131
- if (is_snan(a_cls)) {
132
- return floatx80_silence_nan(a, status);
133
- }
134
- return a;
135
- }
136
-}
137
-
138
/*----------------------------------------------------------------------------
139
| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
140
| NaN; otherwise returns 0.
40
--
141
--
41
2.25.1
142
2.34.1
42
43
diff view generated by jsdifflib
[PULL 11/39] target/arm: Remove is_subpage argument to pmsav8_mpu_lookup
[PULL 66/72] softfloat: Use parts_pick_nan in propagateFloatx80NaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This can be made redundant with result->page_size, by moving the basic
3
Unpacking and repacking the parts may be slightly more work
4
set of page_size from get_phys_addr_pmsav8. We still need to overwrite
4
than we did before, but we get to reuse more code. For a
5
page_size when v8m_security_lookup signals a subpage.
5
code path handling exceptional values, this is an improvement.
6
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-11-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-8-richard.henderson@linaro.org
9
[PMM: Update a comment that used to refer to is_subpage]
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
11
---
13
target/arm/internals.h | 4 ++--
12
fpu/softfloat.c | 43 +++++--------------------------------------
14
target/arm/m_helper.c | 3 +--
13
1 file changed, 5 insertions(+), 38 deletions(-)
15
target/arm/ptw.c | 23 ++++++++++++-----------
16
3 files changed, 15 insertions(+), 15 deletions(-)
17
14
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/internals.h
17
--- a/fpu/softfloat.c
21
+++ b/target/arm/internals.h
18
+++ b/fpu/softfloat.c
22
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
23
20
24
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
21
floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
25
MMUAccessType access_type, ARMMMUIdx mmu_idx,
26
- GetPhysAddrResult *result, bool *is_subpage,
27
- ARMMMUFaultInfo *fi, uint32_t *mregion);
28
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi,
29
+ uint32_t *mregion);
30
31
void arm_log_exception(CPUState *cs);
32
33
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/m_helper.c
36
+++ b/target/arm/m_helper.c
37
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
38
if (arm_current_el(env) != 0 || alt) {
39
GetPhysAddrResult res = {};
40
ARMMMUFaultInfo fi = {};
41
- bool is_subpage;
42
43
/* We can ignore the return value as prot is always set */
44
pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
45
- &res, &is_subpage, &fi, &mregion);
46
+ &res, &fi, &mregion);
47
if (mregion == -1) {
48
mrvalid = false;
49
mregion = 0;
50
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/ptw.c
53
+++ b/target/arm/ptw.c
54
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
55
56
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
57
MMUAccessType access_type, ARMMMUIdx mmu_idx,
58
- GetPhysAddrResult *result, bool *is_subpage,
59
- ARMMMUFaultInfo *fi, uint32_t *mregion)
60
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi,
61
+ uint32_t *mregion)
62
{
22
{
63
/*
23
- bool aIsLargerSignificand;
64
* Perform a PMSAv8 MPU lookup (without also doing the SAU check
24
- FloatClass a_cls, b_cls;
65
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
25
+ FloatParts128 pa, pb, *pr;
66
* mregion is (if not NULL) set to the region number which matched,
26
67
* or -1 if no region number is returned (MPU off, address did not
27
- /* This is not complete, but is good enough for pickNaN. */
68
* hit a region, address hit in multiple regions).
28
- a_cls = (!floatx80_is_any_nan(a)
69
- * We set is_subpage to true if the region hit doesn't cover the
29
- ? float_class_normal
70
- * entire TARGET_PAGE the address is within.
30
- : floatx80_is_signaling_nan(a, status)
71
+ * If the region hit doesn't cover the entire TARGET_PAGE the address
31
- ? float_class_snan
72
+ * is within, then we set the result page_size to 1 to force the
32
- : float_class_qnan);
73
+ * memory system to use a subpage.
33
- b_cls = (!floatx80_is_any_nan(b)
74
*/
34
- ? float_class_normal
75
ARMCPU *cpu = env_archcpu(env);
35
- : floatx80_is_signaling_nan(b, status)
76
bool is_user = regime_is_user(env, mmu_idx);
36
- ? float_class_snan
77
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
37
- : float_class_qnan);
78
uint32_t addr_page_base = address & TARGET_PAGE_MASK;
38
-
79
uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
39
- if (is_snan(a_cls) || is_snan(b_cls)) {
80
40
- float_raise(float_flag_invalid, status);
81
- *is_subpage = false;
41
- }
82
+ result->page_size = TARGET_PAGE_SIZE;
42
-
83
result->phys = address;
43
- if (status->default_nan_mode) {
84
result->prot = 0;
44
+ if (!floatx80_unpack_canonical(&pa, a, status) ||
85
if (mregion) {
45
+ !floatx80_unpack_canonical(&pb, b, status)) {
86
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
46
return floatx80_default_nan(status);
87
ranges_overlap(base, limit - base + 1,
88
addr_page_base,
89
TARGET_PAGE_SIZE)) {
90
- *is_subpage = true;
91
+ result->page_size = 1;
92
}
93
continue;
94
}
95
96
if (base > addr_page_base || limit < addr_page_limit) {
97
- *is_subpage = true;
98
+ result->page_size = 1;
99
}
100
101
if (matchregion != -1) {
102
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
103
uint32_t secure = regime_is_secure(env, mmu_idx);
104
V8M_SAttributes sattrs = {};
105
bool ret;
106
- bool mpu_is_subpage;
107
108
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
109
v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs);
110
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
111
}
47
}
112
48
113
ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx,
49
- if (a.low < b.low) {
114
- result, &mpu_is_subpage, fi, NULL);
50
- aIsLargerSignificand = 0;
115
- result->page_size =
51
- } else if (b.low < a.low) {
116
- sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
52
- aIsLargerSignificand = 1;
117
+ result, fi, NULL);
53
- } else {
118
+ if (sattrs.subpage) {
54
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
119
+ result->page_size = 1;
55
- }
120
+ }
56
-
121
return ret;
57
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
58
- if (is_snan(b_cls)) {
59
- return floatx80_silence_nan(b, status);
60
- }
61
- return b;
62
- } else {
63
- if (is_snan(a_cls)) {
64
- return floatx80_silence_nan(a, status);
65
- }
66
- return a;
67
- }
68
+ pr = parts_pick_nan(&pa, &pb, status);
69
+ return floatx80_round_pack_canonical(pr, status);
122
}
70
}
123
71
72
/*----------------------------------------------------------------------------
124
--
73
--
125
2.25.1
74
2.34.1
diff view generated by jsdifflib
[PULL 03/39] target/arm: Create GetPhysAddrResult
[PULL 67/72] softfloat: Inline pickNaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Combine 5 output pointer arguments from get_phys_addr
3
Inline pickNaN into its only caller. This makes one assert
4
into a single struct. Adjust all callers.
4
redundant with the immediately preceding IF.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220822152741.1617527-2-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-9-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/internals.h | 13 ++++-
11
fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++----
12
target/arm/helper.c | 27 ++++-----
12
fpu/softfloat-specialize.c.inc | 96 ----------------------------------
13
target/arm/m_helper.c | 52 ++++++-----------
13
2 files changed, 73 insertions(+), 105 deletions(-)
14
target/arm/ptw.c | 120 +++++++++++++++++++++-------------------
14
15
target/arm/tlb_helper.c | 22 +++-----
15
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
16
5 files changed, 109 insertions(+), 125 deletions(-)
17
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/internals.h
17
--- a/fpu/softfloat-parts.c.inc
21
+++ b/target/arm/internals.h
18
+++ b/fpu/softfloat-parts.c.inc
22
@@ -XXX,XX +XXX,XX @@ typedef struct ARMCacheAttrs {
19
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
23
bool is_s2_format:1;
20
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
24
} ARMCacheAttrs;
21
float_status *s)
25
22
{
26
+/* Fields that are valid upon success. */
23
+ int cmp, which;
27
+typedef struct GetPhysAddrResult {
28
+ hwaddr phys;
29
+ target_ulong page_size;
30
+ int prot;
31
+ MemTxAttrs attrs;
32
+ ARMCacheAttrs cacheattrs;
33
+} GetPhysAddrResult;
34
+
24
+
35
bool get_phys_addr(CPUARMState *env, target_ulong address,
25
if (is_snan(a->cls) || is_snan(b->cls)) {
36
MMUAccessType access_type, ARMMMUIdx mmu_idx,
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
37
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
27
}
38
- target_ulong *page_size,
28
39
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
29
if (s->default_nan_mode) {
40
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
30
parts_default_nan(a, s);
41
__attribute__((nonnull));
31
- } else {
42
32
- int cmp = frac_cmp(a, b);
43
void arm_log_exception(CPUState *cs);
33
- if (cmp == 0) {
44
diff --git a/target/arm/helper.c b/target/arm/helper.c
34
- cmp = a->sign < b->sign;
35
- }
36
+ return a;
37
+ }
38
39
- if (pickNaN(a->cls, b->cls, cmp > 0, s)) {
40
- a = b;
41
- }
42
+ cmp = frac_cmp(a, b);
43
+ if (cmp == 0) {
44
+ cmp = a->sign < b->sign;
45
+ }
46
+
47
+ switch (s->float_2nan_prop_rule) {
48
+ case float_2nan_prop_s_ab:
49
if (is_snan(a->cls)) {
50
- parts_silence_nan(a, s);
51
+ which = 0;
52
+ } else if (is_snan(b->cls)) {
53
+ which = 1;
54
+ } else if (is_qnan(a->cls)) {
55
+ which = 0;
56
+ } else {
57
+ which = 1;
58
}
59
+ break;
60
+ case float_2nan_prop_s_ba:
61
+ if (is_snan(b->cls)) {
62
+ which = 1;
63
+ } else if (is_snan(a->cls)) {
64
+ which = 0;
65
+ } else if (is_qnan(b->cls)) {
66
+ which = 1;
67
+ } else {
68
+ which = 0;
69
+ }
70
+ break;
71
+ case float_2nan_prop_ab:
72
+ which = is_nan(a->cls) ? 0 : 1;
73
+ break;
74
+ case float_2nan_prop_ba:
75
+ which = is_nan(b->cls) ? 1 : 0;
76
+ break;
77
+ case float_2nan_prop_x87:
78
+ /*
79
+ * This implements x87 NaN propagation rules:
80
+ * SNaN + QNaN => return the QNaN
81
+ * two SNaNs => return the one with the larger significand, silenced
82
+ * two QNaNs => return the one with the larger significand
83
+ * SNaN and a non-NaN => return the SNaN, silenced
84
+ * QNaN and a non-NaN => return the QNaN
85
+ *
86
+ * If we get down to comparing significands and they are the same,
87
+ * return the NaN with the positive sign bit (if any).
88
+ */
89
+ if (is_snan(a->cls)) {
90
+ if (is_snan(b->cls)) {
91
+ which = cmp > 0 ? 0 : 1;
92
+ } else {
93
+ which = is_qnan(b->cls) ? 1 : 0;
94
+ }
95
+ } else if (is_qnan(a->cls)) {
96
+ if (is_snan(b->cls) || !is_qnan(b->cls)) {
97
+ which = 0;
98
+ } else {
99
+ which = cmp > 0 ? 0 : 1;
100
+ }
101
+ } else {
102
+ which = 1;
103
+ }
104
+ break;
105
+ default:
106
+ g_assert_not_reached();
107
+ }
108
+
109
+ if (which) {
110
+ a = b;
111
+ }
112
+ if (is_snan(a->cls)) {
113
+ parts_silence_nan(a, s);
114
}
115
return a;
116
}
117
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
45
index XXXXXXX..XXXXXXX 100644
118
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/helper.c
119
--- a/fpu/softfloat-specialize.c.inc
47
+++ b/target/arm/helper.c
120
+++ b/fpu/softfloat-specialize.c.inc
48
@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
121
@@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status)
49
static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
50
MMUAccessType access_type, ARMMMUIdx mmu_idx)
51
{
52
- hwaddr phys_addr;
53
- target_ulong page_size;
54
- int prot;
55
bool ret;
56
uint64_t par64;
57
bool format64 = false;
58
- MemTxAttrs attrs = {};
59
ARMMMUFaultInfo fi = {};
60
- ARMCacheAttrs cacheattrs = {};
61
+ GetPhysAddrResult res = {};
62
63
- ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs,
64
- &prot, &page_size, &fi, &cacheattrs);
65
+ ret = get_phys_addr(env, value, access_type, mmu_idx, &res, &fi);
66
67
/*
68
* ATS operations only do S1 or S1+S2 translations, so we never
69
* have to deal with the ARMCacheAttrs format for S2 only.
70
*/
71
- assert(!cacheattrs.is_s2_format);
72
+ assert(!res.cacheattrs.is_s2_format);
73
74
if (ret) {
75
/*
76
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
77
/* Create a 64-bit PAR */
78
par64 = (1 << 11); /* LPAE bit always set */
79
if (!ret) {
80
- par64 |= phys_addr & ~0xfffULL;
81
- if (!attrs.secure) {
82
+ par64 |= res.phys & ~0xfffULL;
83
+ if (!res.attrs.secure) {
84
par64 |= (1 << 9); /* NS */
85
}
86
- par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */
87
- par64 |= cacheattrs.shareability << 7; /* SH */
88
+ par64 |= (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */
89
+ par64 |= res.cacheattrs.shareability << 7; /* SH */
90
} else {
91
uint32_t fsr = arm_fi_to_lfsc(&fi);
92
93
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
94
*/
95
if (!ret) {
96
/* We do not set any attribute bits in the PAR */
97
- if (page_size == (1 << 24)
98
+ if (res.page_size == (1 << 24)
99
&& arm_feature(env, ARM_FEATURE_V7)) {
100
- par64 = (phys_addr & 0xff000000) | (1 << 1);
101
+ par64 = (res.phys & 0xff000000) | (1 << 1);
102
} else {
103
- par64 = phys_addr & 0xfffff000;
104
+ par64 = res.phys & 0xfffff000;
105
}
106
- if (!attrs.secure) {
107
+ if (!res.attrs.secure) {
108
par64 |= (1 << 9); /* NS */
109
}
110
} else {
111
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
112
index XXXXXXX..XXXXXXX 100644
113
--- a/target/arm/m_helper.c
114
+++ b/target/arm/m_helper.c
115
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
116
{
117
CPUState *cs = CPU(cpu);
118
CPUARMState *env = &cpu->env;
119
- MemTxAttrs attrs = {};
120
MemTxResult txres;
121
- target_ulong page_size;
122
- hwaddr physaddr;
123
- int prot;
124
+ GetPhysAddrResult res = {};
125
ARMMMUFaultInfo fi = {};
126
- ARMCacheAttrs cacheattrs = {};
127
bool secure = mmu_idx & ARM_MMU_IDX_M_S;
128
int exc;
129
bool exc_secure;
130
131
- if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &physaddr,
132
- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
133
+ if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &res, &fi)) {
134
/* MPU/SAU lookup failed */
135
if (fi.type == ARMFault_QEMU_SFault) {
136
if (mode == STACK_LAZYFP) {
137
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
138
}
139
goto pend_fault;
140
}
141
- address_space_stl_le(arm_addressspace(cs, attrs), physaddr, value,
142
- attrs, &txres);
143
+ address_space_stl_le(arm_addressspace(cs, res.attrs), res.phys, value,
144
+ res.attrs, &txres);
145
if (txres != MEMTX_OK) {
146
/* BusFault trying to write the data */
147
if (mode == STACK_LAZYFP) {
148
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
149
{
150
CPUState *cs = CPU(cpu);
151
CPUARMState *env = &cpu->env;
152
- MemTxAttrs attrs = {};
153
MemTxResult txres;
154
- target_ulong page_size;
155
- hwaddr physaddr;
156
- int prot;
157
+ GetPhysAddrResult res = {};
158
ARMMMUFaultInfo fi = {};
159
- ARMCacheAttrs cacheattrs = {};
160
bool secure = mmu_idx & ARM_MMU_IDX_M_S;
161
int exc;
162
bool exc_secure;
163
uint32_t value;
164
165
- if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr,
166
- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
167
+ if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) {
168
/* MPU/SAU lookup failed */
169
if (fi.type == ARMFault_QEMU_SFault) {
170
qemu_log_mask(CPU_LOG_INT,
171
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
172
goto pend_fault;
173
}
174
175
- value = address_space_ldl(arm_addressspace(cs, attrs), physaddr,
176
- attrs, &txres);
177
+ value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys,
178
+ res.attrs, &txres);
179
if (txres != MEMTX_OK) {
180
/* BusFault trying to read the data */
181
qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n");
182
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
183
CPUState *cs = CPU(cpu);
184
CPUARMState *env = &cpu->env;
185
V8M_SAttributes sattrs = {};
186
- MemTxAttrs attrs = {};
187
+ GetPhysAddrResult res = {};
188
ARMMMUFaultInfo fi = {};
189
- ARMCacheAttrs cacheattrs = {};
190
MemTxResult txres;
191
- target_ulong page_size;
192
- hwaddr physaddr;
193
- int prot;
194
195
v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
196
if (!sattrs.nsc || sattrs.ns) {
197
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
198
"...really SecureFault with SFSR.INVEP\n");
199
return false;
200
}
201
- if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &physaddr,
202
- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
203
+ if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &res, &fi)) {
204
/* the MPU lookup failed */
205
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK;
206
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure);
207
qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL\n");
208
return false;
209
}
210
- *insn = address_space_lduw_le(arm_addressspace(cs, attrs), physaddr,
211
- attrs, &txres);
212
+ *insn = address_space_lduw_le(arm_addressspace(cs, res.attrs), res.phys,
213
+ res.attrs, &txres);
214
if (txres != MEMTX_OK) {
215
env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK;
216
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
217
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
218
*/
219
CPUState *cs = CPU(cpu);
220
CPUARMState *env = &cpu->env;
221
- MemTxAttrs attrs = {};
222
MemTxResult txres;
223
- target_ulong page_size;
224
- hwaddr physaddr;
225
- int prot;
226
+ GetPhysAddrResult res = {};
227
ARMMMUFaultInfo fi = {};
228
- ARMCacheAttrs cacheattrs = {};
229
uint32_t value;
230
231
- if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr,
232
- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
233
+ if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) {
234
/* MPU/SAU lookup failed */
235
if (fi.type == ARMFault_QEMU_SFault) {
236
qemu_log_mask(CPU_LOG_INT,
237
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
238
}
239
return false;
240
}
241
- value = address_space_ldl(arm_addressspace(cs, attrs), physaddr,
242
- attrs, &txres);
243
+ value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys,
244
+ res.attrs, &txres);
245
if (txres != MEMTX_OK) {
246
/* BusFault trying to read the data */
247
qemu_log_mask(CPU_LOG_INT,
248
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
249
index XXXXXXX..XXXXXXX 100644
250
--- a/target/arm/ptw.c
251
+++ b/target/arm/ptw.c
252
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
253
* @address: virtual address to get physical address for
254
* @access_type: 0 for read, 1 for write, 2 for execute
255
* @mmu_idx: MMU index indicating required translation regime
256
- * @phys_ptr: set to the physical address corresponding to the virtual address
257
- * @attrs: set to the memory transaction attributes to use
258
- * @prot: set to the permissions for the page containing phys_ptr
259
- * @page_size: set to the size of the page containing phys_ptr
260
+ * @result: set on translation success.
261
* @fi: set to fault info if the translation fails
262
- * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
263
*/
264
bool get_phys_addr(CPUARMState *env, target_ulong address,
265
MMUAccessType access_type, ARMMMUIdx mmu_idx,
266
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
267
- target_ulong *page_size,
268
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
269
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
270
{
271
ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
272
273
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
274
*/
275
if (arm_feature(env, ARM_FEATURE_EL2)) {
276
hwaddr ipa;
277
- int s2_prot;
278
+ int s1_prot;
279
int ret;
280
bool ipa_secure;
281
- ARMCacheAttrs cacheattrs2 = {};
282
+ ARMCacheAttrs cacheattrs1;
283
ARMMMUIdx s2_mmu_idx;
284
bool is_el0;
285
286
- ret = get_phys_addr(env, address, access_type, s1_mmu_idx, &ipa,
287
- attrs, prot, page_size, fi, cacheattrs);
288
+ ret = get_phys_addr(env, address, access_type, s1_mmu_idx,
289
+ result, fi);
290
291
/* If S1 fails or S2 is disabled, return early. */
292
if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
293
- *phys_ptr = ipa;
294
return ret;
295
}
296
297
- ipa_secure = attrs->secure;
298
+ ipa = result->phys;
299
+ ipa_secure = result->attrs.secure;
300
if (arm_is_secure_below_el3(env)) {
301
if (ipa_secure) {
302
- attrs->secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
303
+ result->attrs.secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
304
} else {
305
- attrs->secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
306
+ result->attrs.secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
307
}
308
} else {
309
assert(!ipa_secure);
310
}
311
312
- s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
313
+ s2_mmu_idx = (result->attrs.secure
314
+ ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2);
315
is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0;
316
317
- /* S1 is done. Now do S2 translation. */
318
+ /*
319
+ * S1 is done, now do S2 translation.
320
+ * Save the stage1 results so that we may merge
321
+ * prot and cacheattrs later.
322
+ */
323
+ s1_prot = result->prot;
324
+ cacheattrs1 = result->cacheattrs;
325
+ memset(result, 0, sizeof(*result));
326
+
327
ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, is_el0,
328
- phys_ptr, attrs, &s2_prot,
329
- page_size, fi, &cacheattrs2);
330
+ &result->phys, &result->attrs,
331
+ &result->prot, &result->page_size,
332
+ fi, &result->cacheattrs);
333
fi->s2addr = ipa;
334
+
335
/* Combine the S1 and S2 perms. */
336
- *prot &= s2_prot;
337
+ result->prot &= s1_prot;
338
339
/* If S2 fails, return early. */
340
if (ret) {
341
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
342
* Outer Write-Back Read-Allocate Write-Allocate.
343
* Do not overwrite Tagged within attrs.
344
*/
345
- if (cacheattrs->attrs != 0xf0) {
346
- cacheattrs->attrs = 0xff;
347
+ if (cacheattrs1.attrs != 0xf0) {
348
+ cacheattrs1.attrs = 0xff;
349
}
350
- cacheattrs->shareability = 0;
351
+ cacheattrs1.shareability = 0;
352
}
353
- *cacheattrs = combine_cacheattrs(env, *cacheattrs, cacheattrs2);
354
+ result->cacheattrs = combine_cacheattrs(env, cacheattrs1,
355
+ result->cacheattrs);
356
357
/* Check if IPA translates to secure or non-secure PA space. */
358
if (arm_is_secure_below_el3(env)) {
359
if (ipa_secure) {
360
- attrs->secure =
361
+ result->attrs.secure =
362
!(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW));
363
} else {
364
- attrs->secure =
365
+ result->attrs.secure =
366
!((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))
367
|| (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)));
368
}
369
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
370
* cannot upgrade an non-secure translation regime's attributes
371
* to secure.
372
*/
373
- attrs->secure = regime_is_secure(env, mmu_idx);
374
- attrs->user = regime_is_user(env, mmu_idx);
375
+ result->attrs.secure = regime_is_secure(env, mmu_idx);
376
+ result->attrs.user = regime_is_user(env, mmu_idx);
377
378
/*
379
* Fast Context Switch Extension. This doesn't exist at all in v8.
380
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
381
382
if (arm_feature(env, ARM_FEATURE_PMSA)) {
383
bool ret;
384
- *page_size = TARGET_PAGE_SIZE;
385
+ result->page_size = TARGET_PAGE_SIZE;
386
387
if (arm_feature(env, ARM_FEATURE_V8)) {
388
/* PMSAv8 */
389
ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
390
- phys_ptr, attrs, prot, page_size, fi);
391
+ &result->phys, &result->attrs,
392
+ &result->prot, &result->page_size, fi);
393
} else if (arm_feature(env, ARM_FEATURE_V7)) {
394
/* PMSAv7 */
395
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
396
- phys_ptr, prot, page_size, fi);
397
+ &result->phys, &result->prot,
398
+ &result->page_size, fi);
399
} else {
400
/* Pre-v7 MPU */
401
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
402
- phys_ptr, prot, fi);
403
+ &result->phys, &result->prot, fi);
404
}
405
qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
406
" mmu_idx %u -> %s (prot %c%c%c)\n",
407
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
408
(access_type == MMU_DATA_STORE ? "writing" : "execute"),
409
(uint32_t)address, mmu_idx,
410
ret ? "Miss" : "Hit",
411
- *prot & PAGE_READ ? 'r' : '-',
412
- *prot & PAGE_WRITE ? 'w' : '-',
413
- *prot & PAGE_EXEC ? 'x' : '-');
414
+ result->prot & PAGE_READ ? 'r' : '-',
415
+ result->prot & PAGE_WRITE ? 'w' : '-',
416
+ result->prot & PAGE_EXEC ? 'x' : '-');
417
418
return ret;
419
}
420
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
421
address = extract64(address, 0, 52);
422
}
423
}
424
- *phys_ptr = address;
425
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
426
- *page_size = TARGET_PAGE_SIZE;
427
+ result->phys = address;
428
+ result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
429
+ result->page_size = TARGET_PAGE_SIZE;
430
431
/* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
432
hcr = arm_hcr_el2_eff(env);
433
- cacheattrs->shareability = 0;
434
- cacheattrs->is_s2_format = false;
435
+ result->cacheattrs.shareability = 0;
436
+ result->cacheattrs.is_s2_format = false;
437
if (hcr & HCR_DC) {
438
if (hcr & HCR_DCT) {
439
memattr = 0xf0; /* Tagged, Normal, WB, RWA */
440
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
441
} else {
442
memattr = 0x44; /* Normal, NC, No */
443
}
444
- cacheattrs->shareability = 2; /* outer sharable */
445
+ result->cacheattrs.shareability = 2; /* outer sharable */
446
} else {
447
memattr = 0x00; /* Device, nGnRnE */
448
}
449
- cacheattrs->attrs = memattr;
450
+ result->cacheattrs.attrs = memattr;
451
return 0;
452
}
453
454
if (regime_using_lpae_format(env, mmu_idx)) {
455
return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
456
- phys_ptr, attrs, prot, page_size,
457
- fi, cacheattrs);
458
+ &result->phys, &result->attrs,
459
+ &result->prot, &result->page_size,
460
+ fi, &result->cacheattrs);
461
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
462
return get_phys_addr_v6(env, address, access_type, mmu_idx,
463
- phys_ptr, attrs, prot, page_size, fi);
464
+ &result->phys, &result->attrs,
465
+ &result->prot, &result->page_size, fi);
466
} else {
467
return get_phys_addr_v5(env, address, access_type, mmu_idx,
468
- phys_ptr, prot, page_size, fi);
469
+ &result->phys, &result->prot,
470
+ &result->page_size, fi);
471
}
122
}
472
}
123
}
473
124
474
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
125
-/*----------------------------------------------------------------------------
475
{
126
-| Select which NaN to propagate for a two-input operation.
476
ARMCPU *cpu = ARM_CPU(cs);
127
-| IEEE754 doesn't specify all the details of this, so the
477
CPUARMState *env = &cpu->env;
128
-| algorithm is target-specific.
478
- hwaddr phys_addr;
129
-| The routine is passed various bits of information about the
479
- target_ulong page_size;
130
-| two NaNs and should return 0 to select NaN a and 1 for NaN b.
480
- int prot;
131
-| Note that signalling NaNs are always squashed to quiet NaNs
481
- bool ret;
132
-| by the caller, by calling floatXX_silence_nan() before
482
+ GetPhysAddrResult res = {};
133
-| returning them.
483
ARMMMUFaultInfo fi = {};
134
-|
484
ARMMMUIdx mmu_idx = arm_mmu_idx(env);
135
-| aIsLargerSignificand is only valid if both a and b are NaNs
485
- ARMCacheAttrs cacheattrs = {};
136
-| of some kind, and is true if a has the larger significand,
486
+ bool ret;
137
-| or if both a and b have the same significand but a is
487
138
-| positive but b is negative. It is only needed for the x87
488
- *attrs = (MemTxAttrs) {};
139
-| tie-break rule.
140
-*----------------------------------------------------------------------------*/
489
-
141
-
490
- ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr,
142
-static int pickNaN(FloatClass a_cls, FloatClass b_cls,
491
- attrs, &prot, &page_size, &fi, &cacheattrs);
143
- bool aIsLargerSignificand, float_status *status)
492
+ ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi);
144
-{
493
+ *attrs = res.attrs;
145
- /*
494
146
- * We guarantee not to require the target to tell us how to
495
if (ret) {
147
- * pick a NaN if we're always returning the default NaN.
496
return -1;
148
- * But if we're not in default-NaN mode then the target must
497
}
149
- * specify via set_float_2nan_prop_rule().
498
- return phys_addr;
150
- */
499
+ return res.phys;
151
- assert(!status->default_nan_mode);
500
}
152
-
501
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
153
- switch (status->float_2nan_prop_rule) {
502
index XXXXXXX..XXXXXXX 100644
154
- case float_2nan_prop_s_ab:
503
--- a/target/arm/tlb_helper.c
155
- if (is_snan(a_cls)) {
504
+++ b/target/arm/tlb_helper.c
156
- return 0;
505
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
157
- } else if (is_snan(b_cls)) {
506
{
158
- return 1;
507
ARMCPU *cpu = ARM_CPU(cs);
159
- } else if (is_qnan(a_cls)) {
508
ARMMMUFaultInfo fi = {};
160
- return 0;
509
- hwaddr phys_addr;
161
- } else {
510
- target_ulong page_size;
162
- return 1;
511
- int prot, ret;
163
- }
512
- MemTxAttrs attrs = {};
164
- break;
513
- ARMCacheAttrs cacheattrs = {};
165
- case float_2nan_prop_s_ba:
514
+ GetPhysAddrResult res = {};
166
- if (is_snan(b_cls)) {
515
+ int ret;
167
- return 1;
516
168
- } else if (is_snan(a_cls)) {
517
/*
169
- return 0;
518
* Walk the page table and (if the mapping exists) add the page
170
- } else if (is_qnan(b_cls)) {
519
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
171
- return 1;
520
*/
172
- } else {
521
ret = get_phys_addr(&cpu->env, address, access_type,
173
- return 0;
522
core_to_arm_mmu_idx(&cpu->env, mmu_idx),
174
- }
523
- &phys_addr, &attrs, &prot, &page_size,
175
- break;
524
- &fi, &cacheattrs);
176
- case float_2nan_prop_ab:
525
+ &res, &fi);
177
- if (is_nan(a_cls)) {
526
if (likely(!ret)) {
178
- return 0;
527
/*
179
- } else {
528
* Map a single [sub]page. Regions smaller than our declared
180
- return 1;
529
* target page size are handled specially, so for those we
181
- }
530
* pass in the exact addresses.
182
- break;
531
*/
183
- case float_2nan_prop_ba:
532
- if (page_size >= TARGET_PAGE_SIZE) {
184
- if (is_nan(b_cls)) {
533
- phys_addr &= TARGET_PAGE_MASK;
185
- return 1;
534
+ if (res.page_size >= TARGET_PAGE_SIZE) {
186
- } else {
535
+ res.phys &= TARGET_PAGE_MASK;
187
- return 0;
536
address &= TARGET_PAGE_MASK;
188
- }
537
}
189
- break;
538
/* Notice and record tagged memory. */
190
- case float_2nan_prop_x87:
539
- if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs == 0xf0) {
191
- /*
540
- arm_tlb_mte_tagged(&attrs) = true;
192
- * This implements x87 NaN propagation rules:
541
+ if (cpu_isar_feature(aa64_mte, cpu) && res.cacheattrs.attrs == 0xf0) {
193
- * SNaN + QNaN => return the QNaN
542
+ arm_tlb_mte_tagged(&res.attrs) = true;
194
- * two SNaNs => return the one with the larger significand, silenced
543
}
195
- * two QNaNs => return the one with the larger significand
544
196
- * SNaN and a non-NaN => return the SNaN, silenced
545
- tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
197
- * QNaN and a non-NaN => return the QNaN
546
- prot, mmu_idx, page_size);
198
- *
547
+ tlb_set_page_with_attrs(cs, address, res.phys, res.attrs,
199
- * If we get down to comparing significands and they are the same,
548
+ res.prot, mmu_idx, res.page_size);
200
- * return the NaN with the positive sign bit (if any).
549
return true;
201
- */
550
} else if (probe) {
202
- if (is_snan(a_cls)) {
551
return false;
203
- if (is_snan(b_cls)) {
204
- return aIsLargerSignificand ? 0 : 1;
205
- }
206
- return is_qnan(b_cls) ? 1 : 0;
207
- } else if (is_qnan(a_cls)) {
208
- if (is_snan(b_cls) || !is_qnan(b_cls)) {
209
- return 0;
210
- } else {
211
- return aIsLargerSignificand ? 0 : 1;
212
- }
213
- } else {
214
- return 1;
215
- }
216
- default:
217
- g_assert_not_reached();
218
- }
219
-}
220
-
221
/*----------------------------------------------------------------------------
222
| Returns 1 if the double-precision floating-point value `a' is a quiet
223
| NaN; otherwise returns 0.
552
--
224
--
553
2.25.1
225
2.34.1
226
227
diff view generated by jsdifflib
[PULL 15/39] target/arm: Add is_secure parameter to get_phys_addr_v6
[PULL 68/72] softfloat: Share code between parts_pick_nan cases
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Remove the use of regime_is_secure from get_phys_addr_v6,
3
Remember if there was an SNaN, and use that to simplify
4
passing the new parameter to the lookup instead.
4
float_2nan_prop_s_{ab,ba} to only the snan component.
5
Then, fall through to the corresponding
6
float_2nan_prop_{ab,ba} case to handle any remaining
7
nans, which must be quiet.
5
8
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-15-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20241203203949.483774-10-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
target/arm/ptw.c | 11 +++++------
14
fpu/softfloat-parts.c.inc | 32 ++++++++++++--------------------
13
1 file changed, 5 insertions(+), 6 deletions(-)
15
1 file changed, 12 insertions(+), 20 deletions(-)
14
16
15
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/ptw.c
19
--- a/fpu/softfloat-parts.c.inc
18
+++ b/target/arm/ptw.c
20
+++ b/fpu/softfloat-parts.c.inc
19
@@ -XXX,XX +XXX,XX @@ do_fault:
21
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
20
22
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
21
static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
23
float_status *s)
22
MMUAccessType access_type, ARMMMUIdx mmu_idx,
23
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
24
+ bool is_secure, GetPhysAddrResult *result,
25
+ ARMMMUFaultInfo *fi)
26
{
24
{
27
ARMCPU *cpu = env_archcpu(env);
25
+ bool have_snan = false;
28
int level = 1;
26
int cmp, which;
29
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
27
30
fi->type = ARMFault_Translation;
28
if (is_snan(a->cls) || is_snan(b->cls)) {
31
goto do_fault;
29
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
30
+ have_snan = true;
32
}
31
}
33
- desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx),
32
34
- mmu_idx, fi);
33
if (s->default_nan_mode) {
35
+ desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
34
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
36
if (fi->type != ARMFault_None) {
35
37
goto do_fault;
36
switch (s->float_2nan_prop_rule) {
38
}
37
case float_2nan_prop_s_ab:
39
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
38
- if (is_snan(a->cls)) {
40
ns = extract32(desc, 3, 1);
39
- which = 0;
41
/* Lookup l2 entry. */
40
- } else if (is_snan(b->cls)) {
42
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
41
- which = 1;
43
- desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx),
42
- } else if (is_qnan(a->cls)) {
44
- mmu_idx, fi);
43
- which = 0;
45
+ desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
44
- } else {
46
if (fi->type != ARMFault_None) {
45
- which = 1;
47
goto do_fault;
46
+ if (have_snan) {
47
+ which = is_snan(a->cls) ? 0 : 1;
48
+ break;
48
}
49
}
49
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
50
- break;
50
result, fi);
51
- case float_2nan_prop_s_ba:
51
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
52
- if (is_snan(b->cls)) {
52
return get_phys_addr_v6(env, address, access_type, mmu_idx,
53
- which = 1;
53
- result, fi);
54
- } else if (is_snan(a->cls)) {
54
+ is_secure, result, fi);
55
- which = 0;
55
} else {
56
- } else if (is_qnan(b->cls)) {
56
return get_phys_addr_v5(env, address, access_type, mmu_idx,
57
- which = 1;
57
is_secure, result, fi);
58
- } else {
59
- which = 0;
60
- }
61
- break;
62
+ /* fall through */
63
case float_2nan_prop_ab:
64
which = is_nan(a->cls) ? 0 : 1;
65
break;
66
+ case float_2nan_prop_s_ba:
67
+ if (have_snan) {
68
+ which = is_snan(b->cls) ? 1 : 0;
69
+ break;
70
+ }
71
+ /* fall through */
72
case float_2nan_prop_ba:
73
which = is_nan(b->cls) ? 1 : 0;
74
break;
58
--
75
--
59
2.25.1
76
2.34.1
60
61
diff view generated by jsdifflib
[PULL 07/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5
[PULL 69/72] softfloat: Sink frac_cmp in parts_pick_nan until needed
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
Move the fractional comparison to the end of the
4
float_2nan_prop_x87 case. This is not required for
5
any other 2nan propagation rule. Reorganize the
6
x87 case itself to break out of the switch when the
7
fractional comparison is not required.
8
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20220822152741.1617527-7-richard.henderson@linaro.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20241203203949.483774-11-richard.henderson@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
13
---
9
target/arm/ptw.c | 24 ++++++++++++------------
14
fpu/softfloat-parts.c.inc | 19 +++++++++----------
10
1 file changed, 12 insertions(+), 12 deletions(-)
15
1 file changed, 9 insertions(+), 10 deletions(-)
11
16
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
13
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/ptw.c
19
--- a/fpu/softfloat-parts.c.inc
15
+++ b/target/arm/ptw.c
20
+++ b/fpu/softfloat-parts.c.inc
16
@@ -XXX,XX +XXX,XX @@ do_fault:
21
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
17
22
return a;
18
static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
20
- hwaddr *phys_ptr, int *prot,
21
+ GetPhysAddrResult *result,
22
ARMMMUFaultInfo *fi)
23
{
24
int n;
25
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
26
27
if (regime_translation_disabled(env, mmu_idx)) {
28
/* MPU disabled. */
29
- *phys_ptr = address;
30
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
31
+ result->phys = address;
32
+ result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
33
return false;
34
}
23
}
35
24
36
- *phys_ptr = address;
25
- cmp = frac_cmp(a, b);
37
+ result->phys = address;
26
- if (cmp == 0) {
38
for (n = 7; n >= 0; n--) {
27
- cmp = a->sign < b->sign;
39
base = env->cp15.c6_region[n];
28
- }
40
if ((base & 1) == 0) {
29
-
41
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
30
switch (s->float_2nan_prop_rule) {
42
fi->level = 1;
31
case float_2nan_prop_s_ab:
43
return true;
32
if (have_snan) {
33
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
34
* return the NaN with the positive sign bit (if any).
35
*/
36
if (is_snan(a->cls)) {
37
- if (is_snan(b->cls)) {
38
- which = cmp > 0 ? 0 : 1;
39
- } else {
40
+ if (!is_snan(b->cls)) {
41
which = is_qnan(b->cls) ? 1 : 0;
42
+ break;
43
}
44
} else if (is_qnan(a->cls)) {
45
if (is_snan(b->cls) || !is_qnan(b->cls)) {
46
which = 0;
47
- } else {
48
- which = cmp > 0 ? 0 : 1;
49
+ break;
50
}
51
} else {
52
which = 1;
53
+ break;
44
}
54
}
45
- *prot = PAGE_READ | PAGE_WRITE;
55
+ cmp = frac_cmp(a, b);
46
+ result->prot = PAGE_READ | PAGE_WRITE;
56
+ if (cmp == 0) {
47
break;
57
+ cmp = a->sign < b->sign;
48
case 2:
58
+ }
49
- *prot = PAGE_READ;
59
+ which = cmp > 0 ? 0 : 1;
50
+ result->prot = PAGE_READ;
51
if (!is_user) {
52
- *prot |= PAGE_WRITE;
53
+ result->prot |= PAGE_WRITE;
54
}
55
break;
56
case 3:
57
- *prot = PAGE_READ | PAGE_WRITE;
58
+ result->prot = PAGE_READ | PAGE_WRITE;
59
break;
60
case 5:
61
if (is_user) {
62
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
63
fi->level = 1;
64
return true;
65
}
66
- *prot = PAGE_READ;
67
+ result->prot = PAGE_READ;
68
break;
69
case 6:
70
- *prot = PAGE_READ;
71
+ result->prot = PAGE_READ;
72
break;
60
break;
73
default:
61
default:
74
/* Bad permission. */
62
g_assert_not_reached();
75
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
76
fi->level = 1;
77
return true;
78
}
79
- *prot |= PAGE_EXEC;
80
+ result->prot |= PAGE_EXEC;
81
return false;
82
}
83
84
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
85
} else {
86
/* Pre-v7 MPU */
87
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
88
- &result->phys, &result->prot, fi);
89
+ result, fi);
90
}
91
qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
92
" mmu_idx %u -> %s (prot %c%c%c)\n",
93
--
63
--
94
2.25.1
64
2.34.1
95
96
diff view generated by jsdifflib
[PULL 08/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7
[PULL 70/72] softfloat: Replace WHICH with RET in parts_pick_nan
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
Replace the "index" selecting between A and B with a result variable
4
of the proper type. This improves clarity within the function.
5
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20220822152741.1617527-8-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-12-richard.henderson@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
10
---
9
target/arm/ptw.c | 36 +++++++++++++++++-------------------
11
fpu/softfloat-parts.c.inc | 28 +++++++++++++---------------
10
1 file changed, 17 insertions(+), 19 deletions(-)
12
1 file changed, 13 insertions(+), 15 deletions(-)
11
13
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
13
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/ptw.c
16
--- a/fpu/softfloat-parts.c.inc
15
+++ b/target/arm/ptw.c
17
+++ b/fpu/softfloat-parts.c.inc
16
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
17
19
float_status *s)
18
static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
20
- hwaddr *phys_ptr, int *prot,
21
- target_ulong *page_size,
22
+ GetPhysAddrResult *result,
23
ARMMMUFaultInfo *fi)
24
{
20
{
25
ARMCPU *cpu = env_archcpu(env);
21
bool have_snan = false;
26
int n;
22
- int cmp, which;
27
bool is_user = regime_is_user(env, mmu_idx);
23
+ FloatPartsN *ret;
28
24
+ int cmp;
29
- *phys_ptr = address;
25
30
- *page_size = TARGET_PAGE_SIZE;
26
if (is_snan(a->cls) || is_snan(b->cls)) {
31
- *prot = 0;
27
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
32
+ result->phys = address;
28
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
33
+ result->page_size = TARGET_PAGE_SIZE;
29
switch (s->float_2nan_prop_rule) {
34
+ result->prot = 0;
30
case float_2nan_prop_s_ab:
35
31
if (have_snan) {
36
if (regime_translation_disabled(env, mmu_idx) ||
32
- which = is_snan(a->cls) ? 0 : 1;
37
m_is_ppb_region(env, address)) {
33
+ ret = is_snan(a->cls) ? a : b;
38
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
39
* which always does a direct read using address_space_ldl(), rather
40
* than going via this function, so we don't need to check that here.
41
*/
42
- get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
43
+ get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
44
} else { /* MPU enabled */
45
for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
46
/* region search */
47
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
48
if (ranges_overlap(base, rmask,
49
address & TARGET_PAGE_MASK,
50
TARGET_PAGE_SIZE)) {
51
- *page_size = 1;
52
+ result->page_size = 1;
53
}
54
continue;
55
}
56
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
57
continue;
58
}
59
if (rsize < TARGET_PAGE_BITS) {
60
- *page_size = 1 << rsize;
61
+ result->page_size = 1 << rsize;
62
}
63
break;
34
break;
64
}
35
}
65
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
36
/* fall through */
66
fi->type = ARMFault_Background;
37
case float_2nan_prop_ab:
67
return true;
38
- which = is_nan(a->cls) ? 0 : 1;
39
+ ret = is_nan(a->cls) ? a : b;
40
break;
41
case float_2nan_prop_s_ba:
42
if (have_snan) {
43
- which = is_snan(b->cls) ? 1 : 0;
44
+ ret = is_snan(b->cls) ? b : a;
45
break;
46
}
47
/* fall through */
48
case float_2nan_prop_ba:
49
- which = is_nan(b->cls) ? 1 : 0;
50
+ ret = is_nan(b->cls) ? b : a;
51
break;
52
case float_2nan_prop_x87:
53
/*
54
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
55
*/
56
if (is_snan(a->cls)) {
57
if (!is_snan(b->cls)) {
58
- which = is_qnan(b->cls) ? 1 : 0;
59
+ ret = is_qnan(b->cls) ? b : a;
60
break;
68
}
61
}
69
- get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
62
} else if (is_qnan(a->cls)) {
70
+ get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
63
if (is_snan(b->cls) || !is_qnan(b->cls)) {
71
} else { /* a MPU hit! */
64
- which = 0;
72
uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
65
+ ret = a;
73
uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1);
66
break;
74
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
75
case 5:
76
break; /* no access */
77
case 3:
78
- *prot |= PAGE_WRITE;
79
+ result->prot |= PAGE_WRITE;
80
/* fall through */
81
case 2:
82
case 6:
83
- *prot |= PAGE_READ | PAGE_EXEC;
84
+ result->prot |= PAGE_READ | PAGE_EXEC;
85
break;
86
case 7:
87
/* for v7M, same as 6; for R profile a reserved value */
88
if (arm_feature(env, ARM_FEATURE_M)) {
89
- *prot |= PAGE_READ | PAGE_EXEC;
90
+ result->prot |= PAGE_READ | PAGE_EXEC;
91
break;
92
}
93
/* fall through */
94
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
95
case 1:
96
case 2:
97
case 3:
98
- *prot |= PAGE_WRITE;
99
+ result->prot |= PAGE_WRITE;
100
/* fall through */
101
case 5:
102
case 6:
103
- *prot |= PAGE_READ | PAGE_EXEC;
104
+ result->prot |= PAGE_READ | PAGE_EXEC;
105
break;
106
case 7:
107
/* for v7M, same as 6; for R profile a reserved value */
108
if (arm_feature(env, ARM_FEATURE_M)) {
109
- *prot |= PAGE_READ | PAGE_EXEC;
110
+ result->prot |= PAGE_READ | PAGE_EXEC;
111
break;
112
}
113
/* fall through */
114
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
115
116
/* execute never */
117
if (xn) {
118
- *prot &= ~PAGE_EXEC;
119
+ result->prot &= ~PAGE_EXEC;
120
}
67
}
68
} else {
69
- which = 1;
70
+ ret = b;
71
break;
121
}
72
}
73
cmp = frac_cmp(a, b);
74
if (cmp == 0) {
75
cmp = a->sign < b->sign;
76
}
77
- which = cmp > 0 ? 0 : 1;
78
+ ret = cmp > 0 ? a : b;
79
break;
80
default:
81
g_assert_not_reached();
122
}
82
}
123
83
124
fi->type = ARMFault_Permission;
84
- if (which) {
125
fi->level = 1;
85
- a = b;
126
- return !(*prot & (1 << access_type));
86
+ if (is_snan(ret->cls)) {
127
+ return !(result->prot & (1 << access_type));
87
+ parts_silence_nan(ret, s);
88
}
89
- if (is_snan(a->cls)) {
90
- parts_silence_nan(a, s);
91
- }
92
- return a;
93
+ return ret;
128
}
94
}
129
95
130
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
96
static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
131
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
132
} else if (arm_feature(env, ARM_FEATURE_V7)) {
133
/* PMSAv7 */
134
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
135
- &result->phys, &result->prot,
136
- &result->page_size, fi);
137
+ result, fi);
138
} else {
139
/* Pre-v7 MPU */
140
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
141
--
97
--
142
2.25.1
98
2.34.1
143
99
144
100
diff view generated by jsdifflib
[PULL 02/39] target/arm: Fix alignment for VLD4.32
[PULL 71/72] MAINTAINERS: update email address for Leif Lindholm
1
From: Clément Chigot <chigot@adacore.com>
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
2
2
3
When requested, the alignment for VLD4.32 is 8 and not 16.
3
I'm migrating to Qualcomm's new open source email infrastructure, so
4
update my email address, and update the mailmap to match.
4
5
5
See ARM documentation about VLD4 encoding:
6
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
6
ebytes = 1 << UInt(size);
7
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
7
if size == '10' then
8
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
8
alignment = if a == '0' then 1 else 8;
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
else
10
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
alignment = if a == '0' then 1 else 4*ebytes;
11
Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com
11
12
Signed-off-by: Clément Chigot <chigot@adacore.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20220914105058.2787404-1-chigot@adacore.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
13
---
17
target/arm/translate-neon.c | 6 +++++-
14
MAINTAINERS | 2 +-
18
1 file changed, 5 insertions(+), 1 deletion(-)
15
.mailmap | 5 +++--
16
2 files changed, 4 insertions(+), 3 deletions(-)
19
17
20
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
18
diff --git a/MAINTAINERS b/MAINTAINERS
21
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/translate-neon.c
20
--- a/MAINTAINERS
23
+++ b/target/arm/translate-neon.c
21
+++ b/MAINTAINERS
24
@@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
22
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
25
case 3:
23
SBSA-REF
26
return false;
24
M: Radoslaw Biernacki <rad@semihalf.com>
27
case 4:
25
M: Peter Maydell <peter.maydell@linaro.org>
28
- align = pow2_align(size + 2);
26
-R: Leif Lindholm <quic_llindhol@quicinc.com>
29
+ if (size == 2) {
27
+R: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
30
+ align = pow2_align(3);
28
R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
31
+ } else {
29
L: qemu-arm@nongnu.org
32
+ align = pow2_align(size + 2);
30
S: Maintained
33
+ }
31
diff --git a/.mailmap b/.mailmap
34
break;
32
index XXXXXXX..XXXXXXX 100644
35
default:
33
--- a/.mailmap
36
g_assert_not_reached();
34
+++ b/.mailmap
35
@@ -XXX,XX +XXX,XX @@ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
36
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
37
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
38
Juan Quintela <quintela@trasno.org> <quintela@redhat.com>
39
-Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
40
-Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
41
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <quic_llindhol@quicinc.com>
42
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif.lindholm@linaro.org>
43
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif@nuviainc.com>
44
Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr>
45
Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com>
46
Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu>
37
--
47
--
38
2.25.1
48
2.34.1
39
49
40
50
diff view generated by jsdifflib
[PULL 01/39] hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic
[PULL 72/72] MAINTAINERS: Add correct email address for Vikram Garhwal
1
From: Anton Kochkov <anton.kochkov@proton.me>
1
From: Vikram Garhwal <vikram.garhwal@bytedance.com>
2
2
3
For consistency, function "update_rx_fifo()" should use the RX FIFO
3
Previously, maintainer role was paused due to inactive email id. Commit id:
4
register field names, not the TX FIFO ones, even if they refer to the
4
c009d715721861984c4987bcc78b7ee183e86d75.
5
same bit positions in the register.
6
5
7
Signed-off-by: Anton Kochkov <anton.kochkov@proton.me>
6
Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com>
8
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
7
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
9
Message-id: 20220817141754.2105981-1-anton.kochkov@proton.me
8
Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1123
11
[PMM: tweaked commit message]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
hw/net/can/xlnx-zynqmp-can.c | 32 ++++++++++++++++----------------
11
MAINTAINERS | 2 ++
15
1 file changed, 16 insertions(+), 16 deletions(-)
12
1 file changed, 2 insertions(+)
16
13
17
diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c
14
diff --git a/MAINTAINERS b/MAINTAINERS
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/net/can/xlnx-zynqmp-can.c
16
--- a/MAINTAINERS
20
+++ b/hw/net/can/xlnx-zynqmp-can.c
17
+++ b/MAINTAINERS
21
@@ -XXX,XX +XXX,XX @@ static void update_rx_fifo(XlnxZynqMPCANState *s, const qemu_can_frame *frame)
18
@@ -XXX,XX +XXX,XX @@ F: tests/qtest/fuzz-sb16-test.c
22
timestamp));
19
23
20
Xilinx CAN
24
/* First 32 bit of the data. */
21
M: Francisco Iglesias <francisco.iglesias@amd.com>
25
- fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA1_DB3_SHIFT,
22
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
26
- R_TXFIFO_DATA1_DB3_LENGTH,
23
S: Maintained
27
+ fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA1_DB3_SHIFT,
24
F: hw/net/can/xlnx-*
28
+ R_RXFIFO_DATA1_DB3_LENGTH,
25
F: include/hw/net/xlnx-*
29
frame->data[0]) |
26
@@ -XXX,XX +XXX,XX @@ F: include/hw/rx/
30
- deposit32(0, R_TXFIFO_DATA1_DB2_SHIFT,
27
CAN bus subsystem and hardware
31
- R_TXFIFO_DATA1_DB2_LENGTH,
28
M: Pavel Pisa <pisa@cmp.felk.cvut.cz>
32
+ deposit32(0, R_RXFIFO_DATA1_DB2_SHIFT,
29
M: Francisco Iglesias <francisco.iglesias@amd.com>
33
+ R_RXFIFO_DATA1_DB2_LENGTH,
30
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
34
frame->data[1]) |
31
S: Maintained
35
- deposit32(0, R_TXFIFO_DATA1_DB1_SHIFT,
32
W: https://canbus.pages.fel.cvut.cz/
36
- R_TXFIFO_DATA1_DB1_LENGTH,
33
F: net/can/*
37
+ deposit32(0, R_RXFIFO_DATA1_DB1_SHIFT,
38
+ R_RXFIFO_DATA1_DB1_LENGTH,
39
frame->data[2]) |
40
- deposit32(0, R_TXFIFO_DATA1_DB0_SHIFT,
41
- R_TXFIFO_DATA1_DB0_LENGTH,
42
+ deposit32(0, R_RXFIFO_DATA1_DB0_SHIFT,
43
+ R_RXFIFO_DATA1_DB0_LENGTH,
44
frame->data[3]));
45
/* Last 32 bit of the data. */
46
- fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA2_DB7_SHIFT,
47
- R_TXFIFO_DATA2_DB7_LENGTH,
48
+ fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA2_DB7_SHIFT,
49
+ R_RXFIFO_DATA2_DB7_LENGTH,
50
frame->data[4]) |
51
- deposit32(0, R_TXFIFO_DATA2_DB6_SHIFT,
52
- R_TXFIFO_DATA2_DB6_LENGTH,
53
+ deposit32(0, R_RXFIFO_DATA2_DB6_SHIFT,
54
+ R_RXFIFO_DATA2_DB6_LENGTH,
55
frame->data[5]) |
56
- deposit32(0, R_TXFIFO_DATA2_DB5_SHIFT,
57
- R_TXFIFO_DATA2_DB5_LENGTH,
58
+ deposit32(0, R_RXFIFO_DATA2_DB5_SHIFT,
59
+ R_RXFIFO_DATA2_DB5_LENGTH,
60
frame->data[6]) |
61
- deposit32(0, R_TXFIFO_DATA2_DB4_SHIFT,
62
- R_TXFIFO_DATA2_DB4_LENGTH,
63
+ deposit32(0, R_RXFIFO_DATA2_DB4_SHIFT,
64
+ R_RXFIFO_DATA2_DB4_LENGTH,
65
frame->data[7]));
66
67
ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
68
--
34
--
69
2.25.1
35
2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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