1
Hi; this pullreq contains mainly a chunk of RTH's refactoring
1
Arm queue; not huge but I figured I might as well send it out since
2
of the Arm pagetable walk code, plus a series from me fixing
2
I've been doing code review today and there's no queue of unprocessed
3
configure checkpatch warnings, and some old patches to various
3
pullreqs...
4
files all over the tree getting rid of dynamic stack allocation.
5
4
6
thanks
5
thanks
7
-- PMM
6
-- PMM
8
7
9
The following changes since commit 6338c30111d596d955e6bc933a82184a0b910c43:
8
The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:
10
9
11
Merge tag 'm68k-for-7.2-pull-request' of https://github.com/vivier/qemu-m68k into staging (2022-09-21 13:12:36 -0400)
10
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000)
12
11
13
are available in the Git repository at:
12
are available in the Git repository at:
14
13
15
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220922
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112
16
15
17
for you to fetch changes up to b3b5472db0ab7a53499441c1fe1dedec05b1e285:
16
for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de:
18
17
19
configure: Avoid use of 'local' as it is non-POSIX (2022-09-22 16:38:29 +0100)
18
ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000)
20
19
21
----------------------------------------------------------------
20
----------------------------------------------------------------
22
target-arm queue:
21
target-arm queue:
23
* hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic
22
* arm: Support emulation of ARMv8.4-TTST extension
24
* Fix alignment for Neon VLD4.32
23
* arm: Update cpu.h ID register field definitions
25
* Refactoring of page-table-walk code
24
* arm: Fix breakage of XScale instruction emulation
26
* hw/acpi: Add ospm_status hook implementation for acpi-ged
25
* hw/net/lan9118: Fix RX Status FIFO PEEK value
27
* hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level
26
* npcm7xx: Add ADC and PWM emulation
28
* chardev/baum: avoid variable-length arrays
27
* ui/cocoa: Make "open docs" help menu entry work again when binary
29
* io/channel-websock: avoid variable-length arrays
28
is run from the build tree
30
* hw/net/e1000e_core: Use definition to avoid dynamic stack allocation
29
* ui/cocoa: Fix openFile: deprecation on Big Sur
31
* hw/ppc/pnv: Avoid dynamic stack allocation
30
* docs: Add qemu-storage-daemon(1) manpage to meson.build
32
* hw/intc/xics: Avoid dynamic stack allocation
31
* docs: Build and install all the docs in a single manual
33
* hw/i386/multiboot: Avoid dynamic stack allocation
34
* hw/usb/hcd-ohci: Use definition to avoid dynamic stack allocation
35
* ui/curses: Avoid dynamic stack allocation
36
* tests/unit/test-vmstate: Avoid dynamic stack allocation
37
* configure: fix various shellcheck-spotted issues and nits
38
32
39
----------------------------------------------------------------
33
----------------------------------------------------------------
40
Anton Kochkov (1):
34
Hao Wu (6):
41
hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic
35
hw/misc: Add clock converter in NPCM7XX CLK module
36
hw/timer: Refactor NPCM7XX Timer to use CLK clock
37
hw/adc: Add an ADC module for NPCM7XX
38
hw/misc: Add a PWM module for NPCM7XX
39
hw/misc: Add QTest for NPCM7XX PWM Module
40
hw/*: Use type casting for SysBusDevice in NPCM7XX
42
41
43
Clément Chigot (1):
42
Leif Lindholm (6):
44
target/arm: Fix alignment for VLD4.32
43
target/arm: fix typo in cpu.h ID_AA64PFR1 field name
44
target/arm: make ARMCPU.clidr 64-bit
45
target/arm: make ARMCPU.ctr 64-bit
46
target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
47
target/arm: add aarch64 ID register fields to cpu.h
48
target/arm: add aarch32 ID register fields to cpu.h
45
49
46
Keqian Zhu (1):
50
Peter Maydell (5):
47
hw/acpi: Add ospm_status hook implementation for acpi-ged
51
docs: Add qemu-storage-daemon(1) manpage to meson.build
52
docs: Build and install all the docs in a single manual
53
target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
54
hw/net/lan9118: Fix RX Status FIFO PEEK value
55
hw/net/lan9118: Add symbolic constants for register offsets
48
56
49
Lucas Dietrich (1):
57
Roman Bolshakov (2):
50
hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level
58
ui/cocoa: Update path to docs in build tree
59
ui/cocoa: Fix openFile: deprecation on Big Sur
51
60
52
Peter Maydell (7):
61
Rémi Denis-Courmont (2):
53
configure: Remove unused python_version variable
62
target/arm: ARMv8.4-TTST extension
54
configure: Remove unused meson_args variable
63
target/arm: enable Small Translation tables in max CPU
55
configure: Add missing quoting for some easy cases
56
configure: Add './' on front of glob of */config-devices.mak.d
57
configure: Remove use of backtick `...` syntax
58
configure: Check mkdir result directly, not via $?
59
configure: Avoid use of 'local' as it is non-POSIX
60
64
61
Philippe Mathieu-Daudé (11):
65
docs/conf.py | 46 ++-
62
chardev/baum: Replace magic values by X_MAX / Y_MAX definitions
66
docs/devel/conf.py | 15 -
63
chardev/baum: Use definitions to avoid dynamic stack allocation
67
docs/index.html.in | 17 -
64
chardev/baum: Avoid dynamic stack allocation
68
docs/interop/conf.py | 28 --
65
io/channel-websock: Replace strlen(const_str) by sizeof(const_str) - 1
69
docs/meson.build | 65 ++--
66
hw/net/e1000e_core: Use definition to avoid dynamic stack allocation
70
docs/specs/conf.py | 16 -
67
hw/ppc/pnv: Avoid dynamic stack allocation
71
docs/system/arm/nuvoton.rst | 4 +-
68
hw/intc/xics: Avoid dynamic stack allocation
72
docs/system/conf.py | 28 --
69
hw/i386/multiboot: Avoid dynamic stack allocation
73
docs/tools/conf.py | 37 --
70
hw/usb/hcd-ohci: Use definition to avoid dynamic stack allocation
74
docs/user/conf.py | 15 -
71
ui/curses: Avoid dynamic stack allocation
75
meson.build | 1 +
72
tests/unit/test-vmstate: Avoid dynamic stack allocation
76
hw/adc/trace.h | 1 +
77
include/hw/adc/npcm7xx_adc.h | 69 ++++
78
include/hw/arm/npcm7xx.h | 4 +
79
include/hw/misc/npcm7xx_clk.h | 146 ++++++-
80
include/hw/misc/npcm7xx_pwm.h | 105 +++++
81
include/hw/timer/npcm7xx_timer.h | 1 +
82
target/arm/cpu.h | 85 ++++-
83
hw/adc/npcm7xx_adc.c | 301 +++++++++++++++
84
hw/arm/npcm7xx.c | 55 ++-
85
hw/arm/npcm7xx_boards.c | 2 +-
86
hw/mem/npcm7xx_mc.c | 2 +-
87
hw/misc/npcm7xx_clk.c | 807 ++++++++++++++++++++++++++++++++++++++-
88
hw/misc/npcm7xx_gcr.c | 2 +-
89
hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++
90
hw/misc/npcm7xx_rng.c | 2 +-
91
hw/net/lan9118.c | 26 +-
92
hw/nvram/npcm7xx_otp.c | 2 +-
93
hw/ssi/npcm7xx_fiu.c | 2 +-
94
hw/timer/npcm7xx_timer.c | 39 +-
95
target/arm/cpu64.c | 1 +
96
target/arm/helper.c | 15 +-
97
target/arm/translate.c | 7 +
98
tests/qtest/npcm7xx_adc-test.c | 377 ++++++++++++++++++
99
tests/qtest/npcm7xx_pwm-test.c | 490 ++++++++++++++++++++++++
100
hw/adc/meson.build | 1 +
101
hw/adc/trace-events | 5 +
102
hw/misc/meson.build | 1 +
103
hw/misc/trace-events | 6 +
104
tests/qtest/meson.build | 4 +-
105
ui/cocoa.m | 7 +-
106
41 files changed, 3124 insertions(+), 263 deletions(-)
107
delete mode 100644 docs/devel/conf.py
108
delete mode 100644 docs/index.html.in
109
delete mode 100644 docs/interop/conf.py
110
delete mode 100644 docs/specs/conf.py
111
delete mode 100644 docs/system/conf.py
112
delete mode 100644 docs/tools/conf.py
113
delete mode 100644 docs/user/conf.py
114
create mode 100644 hw/adc/trace.h
115
create mode 100644 include/hw/adc/npcm7xx_adc.h
116
create mode 100644 include/hw/misc/npcm7xx_pwm.h
117
create mode 100644 hw/adc/npcm7xx_adc.c
118
create mode 100644 hw/misc/npcm7xx_pwm.c
119
create mode 100644 tests/qtest/npcm7xx_adc-test.c
120
create mode 100644 tests/qtest/npcm7xx_pwm-test.c
121
create mode 100644 hw/adc/trace-events
73
122
74
Richard Henderson (17):
75
target/arm: Create GetPhysAddrResult
76
target/arm: Use GetPhysAddrResult in get_phys_addr_lpae
77
target/arm: Use GetPhysAddrResult in get_phys_addr_v6
78
target/arm: Use GetPhysAddrResult in get_phys_addr_v5
79
target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5
80
target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7
81
target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8
82
target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup
83
target/arm: Remove is_subpage argument to pmsav8_mpu_lookup
84
target/arm: Add is_secure parameter to v8m_security_lookup
85
target/arm: Add secure parameter to pmsav8_mpu_lookup
86
target/arm: Add is_secure parameter to get_phys_addr_v5
87
target/arm: Add is_secure parameter to get_phys_addr_v6
88
target/arm: Add secure parameter to get_phys_addr_pmsav8
89
target/arm: Add is_secure parameter to pmsav7_use_background_region
90
target/arm: Add secure parameter to get_phys_addr_pmsav7
91
target/arm: Add is_secure parameter to get_phys_addr_pmsav5
92
93
configure | 82 +++++-----
94
target/arm/internals.h | 26 +--
95
chardev/baum.c | 22 ++-
96
hw/acpi/generic_event_device.c | 8 +
97
hw/i386/multiboot.c | 5 +-
98
hw/intc/xics.c | 2 +-
99
hw/net/can/xlnx-zynqmp-can.c | 32 ++--
100
hw/net/e1000e_core.c | 7 +-
101
hw/net/lan9118.c | 8 +
102
hw/ppc/pnv.c | 4 +-
103
hw/ppc/spapr.c | 8 +-
104
hw/ppc/spapr_pci_nvlink2.c | 2 +-
105
hw/usb/hcd-ohci.c | 7 +-
106
io/channel-websock.c | 2 +-
107
target/arm/helper.c | 27 ++-
108
target/arm/m_helper.c | 78 ++++-----
109
target/arm/ptw.c | 364 +++++++++++++++++++----------------------
110
target/arm/tlb_helper.c | 22 +--
111
target/arm/translate-neon.c | 6 +-
112
tests/unit/test-vmstate.c | 7 +-
113
ui/curses.c | 2 +-
114
21 files changed, 347 insertions(+), 374 deletions(-)
115
diff view generated by jsdifflib
Deleted patch
1
From: Anton Kochkov <anton.kochkov@proton.me>
2
1
3
For consistency, function "update_rx_fifo()" should use the RX FIFO
4
register field names, not the TX FIFO ones, even if they refer to the
5
same bit positions in the register.
6
7
Signed-off-by: Anton Kochkov <anton.kochkov@proton.me>
8
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
9
Message-id: 20220817141754.2105981-1-anton.kochkov@proton.me
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1123
11
[PMM: tweaked commit message]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/net/can/xlnx-zynqmp-can.c | 32 ++++++++++++++++----------------
15
1 file changed, 16 insertions(+), 16 deletions(-)
16
17
diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/net/can/xlnx-zynqmp-can.c
20
+++ b/hw/net/can/xlnx-zynqmp-can.c
21
@@ -XXX,XX +XXX,XX @@ static void update_rx_fifo(XlnxZynqMPCANState *s, const qemu_can_frame *frame)
22
timestamp));
23
24
/* First 32 bit of the data. */
25
- fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA1_DB3_SHIFT,
26
- R_TXFIFO_DATA1_DB3_LENGTH,
27
+ fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA1_DB3_SHIFT,
28
+ R_RXFIFO_DATA1_DB3_LENGTH,
29
frame->data[0]) |
30
- deposit32(0, R_TXFIFO_DATA1_DB2_SHIFT,
31
- R_TXFIFO_DATA1_DB2_LENGTH,
32
+ deposit32(0, R_RXFIFO_DATA1_DB2_SHIFT,
33
+ R_RXFIFO_DATA1_DB2_LENGTH,
34
frame->data[1]) |
35
- deposit32(0, R_TXFIFO_DATA1_DB1_SHIFT,
36
- R_TXFIFO_DATA1_DB1_LENGTH,
37
+ deposit32(0, R_RXFIFO_DATA1_DB1_SHIFT,
38
+ R_RXFIFO_DATA1_DB1_LENGTH,
39
frame->data[2]) |
40
- deposit32(0, R_TXFIFO_DATA1_DB0_SHIFT,
41
- R_TXFIFO_DATA1_DB0_LENGTH,
42
+ deposit32(0, R_RXFIFO_DATA1_DB0_SHIFT,
43
+ R_RXFIFO_DATA1_DB0_LENGTH,
44
frame->data[3]));
45
/* Last 32 bit of the data. */
46
- fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA2_DB7_SHIFT,
47
- R_TXFIFO_DATA2_DB7_LENGTH,
48
+ fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA2_DB7_SHIFT,
49
+ R_RXFIFO_DATA2_DB7_LENGTH,
50
frame->data[4]) |
51
- deposit32(0, R_TXFIFO_DATA2_DB6_SHIFT,
52
- R_TXFIFO_DATA2_DB6_LENGTH,
53
+ deposit32(0, R_RXFIFO_DATA2_DB6_SHIFT,
54
+ R_RXFIFO_DATA2_DB6_LENGTH,
55
frame->data[5]) |
56
- deposit32(0, R_TXFIFO_DATA2_DB5_SHIFT,
57
- R_TXFIFO_DATA2_DB5_LENGTH,
58
+ deposit32(0, R_RXFIFO_DATA2_DB5_SHIFT,
59
+ R_RXFIFO_DATA2_DB5_LENGTH,
60
frame->data[6]) |
61
- deposit32(0, R_TXFIFO_DATA2_DB4_SHIFT,
62
- R_TXFIFO_DATA2_DB4_LENGTH,
63
+ deposit32(0, R_RXFIFO_DATA2_DB4_SHIFT,
64
+ R_RXFIFO_DATA2_DB4_LENGTH,
65
frame->data[7]));
66
67
ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
68
--
69
2.25.1
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
2
2
3
The compiler isn't clever enough to figure 'width' is a constant,
3
This adds for the Small Translation tables extension in AArch64 state.
4
so help it by using a definitions instead.
5
4
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220819153931.3147384-10-peter.maydell@linaro.org
10
---
8
---
11
hw/usb/hcd-ohci.c | 7 ++++---
9
target/arm/cpu.h | 5 +++++
12
1 file changed, 4 insertions(+), 3 deletions(-)
10
target/arm/helper.c | 15 +++++++++++++--
11
2 files changed, 18 insertions(+), 2 deletions(-)
13
12
14
diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/usb/hcd-ohci.c
15
--- a/target/arm/cpu.h
17
+++ b/hw/usb/hcd-ohci.c
16
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed)
17
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
19
return 1;
18
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
20
}
19
}
21
20
22
+#define HEX_CHAR_PER_LINE 16
21
+static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
22
+{
23
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
24
+}
23
+
25
+
24
static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len)
26
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
25
{
27
{
26
bool print16;
28
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
27
bool printall;
29
diff --git a/target/arm/helper.c b/target/arm/helper.c
28
- const int width = 16;
30
index XXXXXXX..XXXXXXX 100644
29
int i;
31
--- a/target/arm/helper.c
30
- char tmp[3 * width + 1];
32
+++ b/target/arm/helper.c
31
+ char tmp[3 * HEX_CHAR_PER_LINE + 1];
33
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
32
char *p = tmp;
34
{
33
35
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
34
print16 = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_SHORT);
36
bool epd, hpd, using16k, using64k;
35
@@ -XXX,XX +XXX,XX @@ static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len)
37
- int select, tsz, tbi;
38
+ int select, tsz, tbi, max_tsz;
39
40
if (!regime_has_2_ranges(mmu_idx)) {
41
select = 0;
42
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
43
hpd = extract64(tcr, 42, 1);
44
}
36
}
45
}
37
46
- tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
38
for (i = 0; ; i++) {
47
+
39
- if (i && (!(i % width) || (i == len))) {
48
+ if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
40
+ if (i && (!(i % HEX_CHAR_PER_LINE) || (i == len))) {
49
+ max_tsz = 48 - using64k;
41
if (!printall) {
50
+ } else {
42
trace_usb_ohci_td_pkt_short(msg, tmp);
51
+ max_tsz = 39;
43
break;
52
+ }
53
+
54
+ tsz = MIN(tsz, max_tsz);
55
tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
56
57
/* Present TBI as a composite with TBID. */
58
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
59
if (!aarch64 || stride == 9) {
60
/* AArch32 or 4KB pages */
61
startlevel = 2 - sl0;
62
+
63
+ if (cpu_isar_feature(aa64_st, cpu)) {
64
+ startlevel &= 3;
65
+ }
66
} else {
67
/* 16KB or 64KB pages */
68
startlevel = 3 - sl0;
44
--
69
--
45
2.25.1
70
2.20.1
46
71
47
72
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
2
2
3
Use autofree heap allocation instead of variable-length
3
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
4
array on the stack.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220819153931.3147384-12-peter.maydell@linaro.org
10
---
6
---
11
tests/unit/test-vmstate.c | 7 +++----
7
target/arm/cpu64.c | 1 +
12
1 file changed, 3 insertions(+), 4 deletions(-)
8
1 file changed, 1 insertion(+)
13
9
14
diff --git a/tests/unit/test-vmstate.c b/tests/unit/test-vmstate.c
10
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
15
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
16
--- a/tests/unit/test-vmstate.c
12
--- a/target/arm/cpu64.c
17
+++ b/tests/unit/test-vmstate.c
13
+++ b/target/arm/cpu64.c
18
@@ -XXX,XX +XXX,XX @@ static void save_buffer(const uint8_t *buf, size_t buf_size)
14
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
19
static void compare_vmstate(const uint8_t *wire, size_t size)
15
t = cpu->isar.id_aa64mmfr2;
20
{
16
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
21
QEMUFile *f = open_test_file(false);
17
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
22
- uint8_t result[size];
18
+ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
23
+ g_autofree uint8_t *result = g_malloc(size);
19
cpu->isar.id_aa64mmfr2 = t;
24
20
25
/* read back as binary */
21
/* Replicate the same data to the 32-bit id registers. */
26
27
- g_assert_cmpint(qemu_get_buffer(f, result, sizeof(result)), ==,
28
- sizeof(result));
29
+ g_assert_cmpint(qemu_get_buffer(f, result, size), ==, size);
30
g_assert(!qemu_file_get_error(f));
31
32
/* Compare that what is on the file is the same that what we
33
expected to be there */
34
- SUCCESS(memcmp(result, wire, sizeof(result)));
35
+ SUCCESS(memcmp(result, wire, size));
36
37
/* Must reach EOF */
38
qemu_get_byte(f);
39
--
22
--
40
2.25.1
23
2.20.1
41
24
42
25
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
Remove the use of regime_is_secure from get_phys_addr_v5,
3
SBSS -> SSBS
4
passing the new parameter to the lookup instead.
5
4
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
[PMM: Folded in definition of local is_secure in get_phys_addr(),
9
since I dropped the earlier patch that would have provided it]
10
Message-id: 20220822152741.1617527-14-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
9
Message-id: 20210108185154.8108-2-leif@nuviainc.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
11
---
14
target/arm/ptw.c | 14 +++++++-------
12
target/arm/cpu.h | 2 +-
15
1 file changed, 7 insertions(+), 7 deletions(-)
13
1 file changed, 1 insertion(+), 1 deletion(-)
16
14
17
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/ptw.c
17
--- a/target/arm/cpu.h
20
+++ b/target/arm/ptw.c
18
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
19
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, RAS, 28, 4)
22
20
FIELD(ID_AA64PFR0, SVE, 32, 4)
23
static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
21
24
MMUAccessType access_type, ARMMMUIdx mmu_idx,
22
FIELD(ID_AA64PFR1, BT, 0, 4)
25
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
23
-FIELD(ID_AA64PFR1, SBSS, 4, 4)
26
+ bool is_secure, GetPhysAddrResult *result,
24
+FIELD(ID_AA64PFR1, SSBS, 4, 4)
27
+ ARMMMUFaultInfo *fi)
25
FIELD(ID_AA64PFR1, MTE, 8, 4)
28
{
26
FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
29
int level = 1;
30
uint32_t table;
31
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
32
fi->type = ARMFault_Translation;
33
goto do_fault;
34
}
35
- desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx),
36
- mmu_idx, fi);
37
+ desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
38
if (fi->type != ARMFault_None) {
39
goto do_fault;
40
}
41
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
42
/* Fine pagetable. */
43
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
44
}
45
- desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx),
46
- mmu_idx, fi);
47
+ desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
48
if (fi->type != ARMFault_None) {
49
goto do_fault;
50
}
51
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
52
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
53
{
54
ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
55
+ bool is_secure = regime_is_secure(env, mmu_idx);
56
57
if (mmu_idx != s1_mmu_idx) {
58
/*
59
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
60
* cannot upgrade an non-secure translation regime's attributes
61
* to secure.
62
*/
63
- result->attrs.secure = regime_is_secure(env, mmu_idx);
64
+ result->attrs.secure = is_secure;
65
result->attrs.user = regime_is_user(env, mmu_idx);
66
67
/*
68
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
69
result, fi);
70
} else {
71
return get_phys_addr_v5(env, address, access_type, mmu_idx,
72
- result, fi);
73
+ is_secure, result, fi);
74
}
75
}
76
27
77
--
28
--
78
2.25.1
29
2.20.1
79
30
80
31
diff view generated by jsdifflib
1
There's only one place in configure where we use `...` to execute a
1
From: Leif Lindholm <leif@nuviainc.com>
2
command and capture the result. Switch to $() to match the rest of
3
the script. This silences a shellcheck warning.
4
2
3
The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
4
32, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
5
Extend the clidr field to be able to hold this context.
6
7
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Message-id: 20210108185154.8108-3-leif@nuviainc.com
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20220825150703.4074125-6-peter.maydell@linaro.org
9
---
13
---
10
configure | 2 +-
14
target/arm/cpu.h | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
15
1 file changed, 1 insertion(+), 1 deletion(-)
12
16
13
diff --git a/configure b/configure
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100755
18
index XXXXXXX..XXXXXXX 100644
15
--- a/configure
19
--- a/target/arm/cpu.h
16
+++ b/configure
20
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ LINKS="$LINKS python"
21
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
18
LINKS="$LINKS contrib/plugins/Makefile "
22
uint32_t id_afr0;
19
for f in $LINKS ; do
23
uint64_t id_aa64afr0;
20
if [ -e "$source_path/$f" ]; then
24
uint64_t id_aa64afr1;
21
- mkdir -p `dirname ./$f`
25
- uint32_t clidr;
22
+ mkdir -p "$(dirname ./"$f")"
26
+ uint64_t clidr;
23
symlink "$source_path/$f" "$f"
27
uint64_t mp_affinity; /* MP ID without feature bits */
24
fi
28
/* The elements of this array are the CCSIDR values for each cache,
25
done
29
* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
26
--
30
--
27
2.25.1
31
2.20.1
28
32
29
33
diff view generated by jsdifflib
1
Shellcheck warns that in
1
From: Leif Lindholm <leif@nuviainc.com>
2
rm -f */config-devices.mak.d
3
the glob might expand to something with a '-' in it, which would
4
then be misinterpreted as an option to rm. Fix this by adding './'.
5
2
3
When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the
4
TminLine field in bits [37:32].
5
Extend the ctr field to be able to hold this context.
6
7
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
8
Reviewed-by: Hao Wu <wuhaotsh@google.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Message-id: 20210108185154.8108-4-leif@nuviainc.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20220825150703.4074125-5-peter.maydell@linaro.org
10
---
13
---
11
configure | 2 +-
14
target/arm/cpu.h | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
15
1 file changed, 1 insertion(+), 1 deletion(-)
13
16
14
diff --git a/configure b/configure
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100755
18
index XXXXXXX..XXXXXXX 100644
16
--- a/configure
19
--- a/target/arm/cpu.h
17
+++ b/configure
20
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ exit 0
21
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
19
fi
22
uint64_t midr;
20
23
uint32_t revidr;
21
# Remove old dependency files to make sure that they get properly regenerated
24
uint32_t reset_fpsid;
22
-rm -f */config-devices.mak.d
25
- uint32_t ctr;
23
+rm -f ./*/config-devices.mak.d
26
+ uint64_t ctr;
24
27
uint32_t reset_sctlr;
25
if test -z "$python"
28
uint64_t pmceid0;
26
then
29
uint64_t pmceid1;
27
--
30
--
28
2.25.1
31
2.20.1
29
32
30
33
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
Remove the use of regime_is_secure from get_phys_addr_pmsav5.
3
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
4
4
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Message-id: 20210108185154.8108-5-leif@nuviainc.com
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220822152741.1617527-21-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
7
---
11
target/arm/ptw.c | 4 ++--
8
target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++
12
1 file changed, 2 insertions(+), 2 deletions(-)
9
1 file changed, 31 insertions(+)
13
10
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
11
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/ptw.c
13
--- a/target/arm/cpu.h
17
+++ b/target/arm/ptw.c
14
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ do_fault:
15
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
19
16
/*
20
static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
17
* System register ID fields.
21
MMUAccessType access_type, ARMMMUIdx mmu_idx,
18
*/
22
- GetPhysAddrResult *result,
19
+FIELD(CLIDR_EL1, CTYPE1, 0, 3)
23
+ bool is_secure, GetPhysAddrResult *result,
20
+FIELD(CLIDR_EL1, CTYPE2, 3, 3)
24
ARMMMUFaultInfo *fi)
21
+FIELD(CLIDR_EL1, CTYPE3, 6, 3)
25
{
22
+FIELD(CLIDR_EL1, CTYPE4, 9, 3)
26
int n;
23
+FIELD(CLIDR_EL1, CTYPE5, 12, 3)
27
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
24
+FIELD(CLIDR_EL1, CTYPE6, 15, 3)
28
} else {
25
+FIELD(CLIDR_EL1, CTYPE7, 18, 3)
29
/* Pre-v7 MPU */
26
+FIELD(CLIDR_EL1, LOUIS, 21, 3)
30
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
27
+FIELD(CLIDR_EL1, LOC, 24, 3)
31
- result, fi);
28
+FIELD(CLIDR_EL1, LOUU, 27, 3)
32
+ is_secure, result, fi);
29
+FIELD(CLIDR_EL1, ICB, 30, 3)
33
}
30
+
34
qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
31
+/* When FEAT_CCIDX is implemented */
35
" mmu_idx %u -> %s (prot %c%c%c)\n",
32
+FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
33
+FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
34
+FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
35
+
36
+/* When FEAT_CCIDX is not implemented */
37
+FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
38
+FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
39
+FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
40
+
41
+FIELD(CTR_EL0, IMINLINE, 0, 4)
42
+FIELD(CTR_EL0, L1IP, 14, 2)
43
+FIELD(CTR_EL0, DMINLINE, 16, 4)
44
+FIELD(CTR_EL0, ERG, 20, 4)
45
+FIELD(CTR_EL0, CWG, 24, 4)
46
+FIELD(CTR_EL0, IDC, 28, 1)
47
+FIELD(CTR_EL0, DIC, 29, 1)
48
+FIELD(CTR_EL0, TMINLINE, 32, 6)
49
+
50
FIELD(MIDR_EL1, REVISION, 0, 4)
51
FIELD(MIDR_EL1, PARTNUM, 4, 12)
52
FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
36
--
53
--
37
2.25.1
54
2.20.1
38
55
39
56
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
Remove the use of regime_is_secure from pmsav8_mpu_lookup,
3
Add entries present in ARM DDI 0487F.c (August 2020).
4
passing the new parameter to the lookup instead.
5
4
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-13-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Message-id: 20210108185154.8108-6-leif@nuviainc.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/internals.h | 4 ++--
11
target/arm/cpu.h | 15 +++++++++++++++
13
target/arm/m_helper.c | 2 +-
12
1 file changed, 15 insertions(+)
14
target/arm/ptw.c | 7 +++----
15
3 files changed, 6 insertions(+), 7 deletions(-)
16
13
17
diff --git a/target/arm/internals.h b/target/arm/internals.h
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/internals.h
16
--- a/target/arm/cpu.h
20
+++ b/target/arm/internals.h
17
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
18
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
22
19
FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
23
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
20
FIELD(ID_AA64ISAR1, SB, 36, 4)
24
MMUAccessType access_type, ARMMMUIdx mmu_idx,
21
FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
25
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi,
22
+FIELD(ID_AA64ISAR1, BF16, 44, 4)
26
- uint32_t *mregion);
23
+FIELD(ID_AA64ISAR1, DGH, 48, 4)
27
+ bool is_secure, GetPhysAddrResult *result,
24
+FIELD(ID_AA64ISAR1, I8MM, 52, 4)
28
+ ARMMMUFaultInfo *fi, uint32_t *mregion);
25
29
26
FIELD(ID_AA64PFR0, EL0, 0, 4)
30
void arm_log_exception(CPUState *cs);
27
FIELD(ID_AA64PFR0, EL1, 4, 4)
31
28
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
32
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
29
FIELD(ID_AA64PFR0, GIC, 24, 4)
33
index XXXXXXX..XXXXXXX 100644
30
FIELD(ID_AA64PFR0, RAS, 28, 4)
34
--- a/target/arm/m_helper.c
31
FIELD(ID_AA64PFR0, SVE, 32, 4)
35
+++ b/target/arm/m_helper.c
32
+FIELD(ID_AA64PFR0, SEL2, 36, 4)
36
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
33
+FIELD(ID_AA64PFR0, MPAM, 40, 4)
37
ARMMMUFaultInfo fi = {};
34
+FIELD(ID_AA64PFR0, AMU, 44, 4)
38
35
+FIELD(ID_AA64PFR0, DIT, 48, 4)
39
/* We can ignore the return value as prot is always set */
36
+FIELD(ID_AA64PFR0, CSV2, 56, 4)
40
- pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
37
+FIELD(ID_AA64PFR0, CSV3, 60, 4)
41
+ pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, targetsec,
38
42
&res, &fi, &mregion);
39
FIELD(ID_AA64PFR1, BT, 0, 4)
43
if (mregion == -1) {
40
FIELD(ID_AA64PFR1, SSBS, 4, 4)
44
mrvalid = false;
41
FIELD(ID_AA64PFR1, MTE, 8, 4)
45
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
42
FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
46
index XXXXXXX..XXXXXXX 100644
43
+FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
47
--- a/target/arm/ptw.c
44
48
+++ b/target/arm/ptw.c
45
FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
49
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
46
FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
50
47
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
51
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
48
FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
52
MMUAccessType access_type, ARMMMUIdx mmu_idx,
49
FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
53
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi,
50
FIELD(ID_AA64MMFR0, EXS, 44, 4)
54
- uint32_t *mregion)
51
+FIELD(ID_AA64MMFR0, FGT, 56, 4)
55
+ bool secure, GetPhysAddrResult *result,
52
+FIELD(ID_AA64MMFR0, ECV, 60, 4)
56
+ ARMMMUFaultInfo *fi, uint32_t *mregion)
53
57
{
54
FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
58
/*
55
FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
59
* Perform a PMSAv8 MPU lookup (without also doing the SAU check
56
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
60
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
57
FIELD(ID_AA64MMFR1, PAN, 20, 4)
61
*/
58
FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
62
ARMCPU *cpu = env_archcpu(env);
59
FIELD(ID_AA64MMFR1, XNX, 28, 4)
63
bool is_user = regime_is_user(env, mmu_idx);
60
+FIELD(ID_AA64MMFR1, TWED, 32, 4)
64
- uint32_t secure = regime_is_secure(env, mmu_idx);
61
+FIELD(ID_AA64MMFR1, ETS, 36, 4)
65
int n;
62
66
int matchregion = -1;
63
FIELD(ID_AA64MMFR2, CNP, 0, 4)
67
bool hit = false;
64
FIELD(ID_AA64MMFR2, UAO, 4, 4)
68
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
65
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
69
}
66
FIELD(ID_AA64DFR0, PMSVER, 32, 4)
70
}
67
FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
71
68
FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
72
- ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx,
69
+FIELD(ID_AA64DFR0, MTPMU, 48, 4)
73
+ ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, secure,
70
74
result, fi, NULL);
71
FIELD(ID_DFR0, COPDBG, 0, 4)
75
if (sattrs.subpage) {
72
FIELD(ID_DFR0, COPSDBG, 4, 4)
76
result->page_size = 1;
77
--
73
--
78
2.25.1
74
2.20.1
79
75
80
76
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
Add entries present in ARM DDI 0487F.c (August 2020).
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
5
Message-id: 20220822152741.1617527-10-richard.henderson@linaro.org
5
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Message-id: 20210108185154.8108-7-leif@nuviainc.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
10
---
9
target/arm/internals.h | 11 +++++------
11
target/arm/cpu.h | 28 ++++++++++++++++++++++++++++
10
target/arm/m_helper.c | 16 +++++++---------
12
1 file changed, 28 insertions(+)
11
target/arm/ptw.c | 20 +++++++++-----------
12
3 files changed, 21 insertions(+), 26 deletions(-)
13
13
14
diff --git a/target/arm/internals.h b/target/arm/internals.h
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/internals.h
16
--- a/target/arm/cpu.h
17
+++ b/target/arm/internals.h
17
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
18
@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, DP, 4, 4)
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
19
FIELD(ID_ISAR6, FHM, 8, 4)
20
V8M_SAttributes *sattrs);
20
FIELD(ID_ISAR6, SB, 12, 4)
21
21
FIELD(ID_ISAR6, SPECRES, 16, 4)
22
-bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
22
+FIELD(ID_ISAR6, BF16, 20, 4)
23
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
23
+FIELD(ID_ISAR6, I8MM, 24, 4)
24
- hwaddr *phys_ptr, MemTxAttrs *txattrs,
24
25
- int *prot, bool *is_subpage,
25
FIELD(ID_MMFR0, VMSA, 0, 4)
26
- ARMMMUFaultInfo *fi, uint32_t *mregion);
26
FIELD(ID_MMFR0, PMSA, 4, 4)
27
-
27
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR0, AUXREG, 20, 4)
28
/* Cacheability and shareability attributes for a memory access */
28
FIELD(ID_MMFR0, FCSE, 24, 4)
29
typedef struct ARMCacheAttrs {
29
FIELD(ID_MMFR0, INNERSHR, 28, 4)
30
/*
30
31
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
31
+FIELD(ID_MMFR1, L1HVDVA, 0, 4)
32
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
32
+FIELD(ID_MMFR1, L1UNIVA, 4, 4)
33
__attribute__((nonnull));
33
+FIELD(ID_MMFR1, L1HVDSW, 8, 4)
34
34
+FIELD(ID_MMFR1, L1UNISW, 12, 4)
35
+bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
35
+FIELD(ID_MMFR1, L1HVD, 16, 4)
36
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
36
+FIELD(ID_MMFR1, L1UNI, 20, 4)
37
+ GetPhysAddrResult *result, bool *is_subpage,
37
+FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
38
+ ARMMMUFaultInfo *fi, uint32_t *mregion);
38
+FIELD(ID_MMFR1, BPRED, 28, 4)
39
+
39
+
40
void arm_log_exception(CPUState *cs);
40
+FIELD(ID_MMFR2, L1HVDFG, 0, 4)
41
41
+FIELD(ID_MMFR2, L1HVDBG, 4, 4)
42
#endif /* !CONFIG_USER_ONLY */
42
+FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
43
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
43
+FIELD(ID_MMFR2, HVDTLB, 12, 4)
44
index XXXXXXX..XXXXXXX 100644
44
+FIELD(ID_MMFR2, UNITLB, 16, 4)
45
--- a/target/arm/m_helper.c
45
+FIELD(ID_MMFR2, MEMBARR, 20, 4)
46
+++ b/target/arm/m_helper.c
46
+FIELD(ID_MMFR2, WFISTALL, 24, 4)
47
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
47
+FIELD(ID_MMFR2, HWACCFLG, 28, 4)
48
V8M_SAttributes sattrs = {};
49
uint32_t tt_resp;
50
bool r, rw, nsr, nsrw, mrvalid;
51
- int prot;
52
- ARMMMUFaultInfo fi = {};
53
- MemTxAttrs attrs = {};
54
- hwaddr phys_addr;
55
ARMMMUIdx mmu_idx;
56
uint32_t mregion;
57
bool targetpriv;
58
bool targetsec = env->v7m.secure;
59
- bool is_subpage;
60
61
/*
62
* Work out what the security state and privilege level we're
63
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
64
* inspecting the other MPU state.
65
*/
66
if (arm_current_el(env) != 0 || alt) {
67
+ GetPhysAddrResult res = {};
68
+ ARMMMUFaultInfo fi = {};
69
+ bool is_subpage;
70
+
48
+
71
/* We can ignore the return value as prot is always set */
49
FIELD(ID_MMFR3, CMAINTVA, 0, 4)
72
pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
50
FIELD(ID_MMFR3, CMAINTSW, 4, 4)
73
- &phys_addr, &attrs, &prot, &is_subpage,
51
FIELD(ID_MMFR3, BPMAINT, 8, 4)
74
- &fi, &mregion);
52
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
75
+ &res, &is_subpage, &fi, &mregion);
53
FIELD(ID_MMFR4, CCIDX, 24, 4)
76
if (mregion == -1) {
54
FIELD(ID_MMFR4, EVT, 28, 4)
77
mrvalid = false;
55
78
mregion = 0;
56
+FIELD(ID_MMFR5, ETS, 0, 4)
79
} else {
57
+
80
mrvalid = true;
58
FIELD(ID_PFR0, STATE0, 0, 4)
81
}
59
FIELD(ID_PFR0, STATE1, 4, 4)
82
- r = prot & PAGE_READ;
60
FIELD(ID_PFR0, STATE2, 8, 4)
83
- rw = prot & PAGE_WRITE;
61
@@ -XXX,XX +XXX,XX @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4)
84
+ r = res.prot & PAGE_READ;
62
FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
85
+ rw = res.prot & PAGE_WRITE;
63
FIELD(ID_PFR1, GIC, 28, 4)
86
} else {
64
87
r = false;
65
+FIELD(ID_PFR2, CSV3, 0, 4)
88
rw = false;
66
+FIELD(ID_PFR2, SSBS, 4, 4)
89
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
67
+FIELD(ID_PFR2, RAS_FRAC, 8, 4)
90
index XXXXXXX..XXXXXXX 100644
68
+
91
--- a/target/arm/ptw.c
69
FIELD(ID_AA64ISAR0, AES, 4, 4)
92
+++ b/target/arm/ptw.c
70
FIELD(ID_AA64ISAR0, SHA1, 8, 4)
93
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
71
FIELD(ID_AA64ISAR0, SHA2, 12, 4)
94
72
@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
95
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
73
FIELD(ID_DFR0, PERFMON, 24, 4)
96
MMUAccessType access_type, ARMMMUIdx mmu_idx,
74
FIELD(ID_DFR0, TRACEFILT, 28, 4)
97
- hwaddr *phys_ptr, MemTxAttrs *txattrs,
75
98
- int *prot, bool *is_subpage,
76
+FIELD(ID_DFR1, MTPMU, 0, 4)
99
+ GetPhysAddrResult *result, bool *is_subpage,
77
+
100
ARMMMUFaultInfo *fi, uint32_t *mregion)
78
FIELD(DBGDIDR, SE_IMP, 12, 1)
101
{
79
FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
102
/*
80
FIELD(DBGDIDR, VERSION, 16, 4)
103
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
104
uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
105
106
*is_subpage = false;
107
- *phys_ptr = address;
108
- *prot = 0;
109
+ result->phys = address;
110
+ result->prot = 0;
111
if (mregion) {
112
*mregion = -1;
113
}
114
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
115
116
if (matchregion == -1) {
117
/* hit using the background region */
118
- get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
119
+ get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
120
} else {
121
uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
122
uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
123
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
124
xn = 1;
125
}
126
127
- *prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
128
- if (*prot && !xn && !(pxn && !is_user)) {
129
- *prot |= PAGE_EXEC;
130
+ result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
131
+ if (result->prot && !xn && !(pxn && !is_user)) {
132
+ result->prot |= PAGE_EXEC;
133
}
134
/*
135
* We don't need to look the attribute up in the MAIR0/MAIR1
136
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
137
138
fi->type = ARMFault_Permission;
139
fi->level = 1;
140
- return !(*prot & (1 << access_type));
141
+ return !(result->prot & (1 << access_type));
142
}
143
144
static bool v8m_is_sau_exempt(CPUARMState *env,
145
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
146
}
147
148
ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx,
149
- &result->phys, &result->attrs, &result->prot,
150
- &mpu_is_subpage, fi, NULL);
151
+ result, &mpu_is_subpage, fi, NULL);
152
result->page_size =
153
sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
154
return ret;
155
--
81
--
156
2.25.1
82
2.20.1
157
83
158
84
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Roman Bolshakov <r.bolshakov@yadro.com>
2
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
QEMU documentation can't be opened if QEMU is run from build tree
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
because executables are placed in the top of build tree after conversion
5
Message-id: 20220822152741.1617527-9-richard.henderson@linaro.org
5
to meson.
6
7
Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
8
Reported-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
12
---
9
target/arm/ptw.c | 28 ++++++++++++++--------------
13
ui/cocoa.m | 2 +-
10
1 file changed, 14 insertions(+), 14 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
11
15
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
diff --git a/ui/cocoa.m b/ui/cocoa.m
13
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/ptw.c
18
--- a/ui/cocoa.m
15
+++ b/target/arm/ptw.c
19
+++ b/ui/cocoa.m
16
@@ -XXX,XX +XXX,XX @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
20
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
17
21
- (void) openDocumentation: (NSString *) filename
18
static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
20
- hwaddr *phys_ptr, MemTxAttrs *txattrs,
21
- int *prot, target_ulong *page_size,
22
+ GetPhysAddrResult *result,
23
ARMMMUFaultInfo *fi)
24
{
22
{
25
uint32_t secure = regime_is_secure(env, mmu_idx);
23
/* Where to look for local files */
26
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
24
- NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"../docs/"};
27
} else {
25
+ NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
28
fi->type = ARMFault_QEMU_SFault;
26
NSString *full_file_path;
29
}
27
30
- *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
28
/* iterate thru the possible paths until the file is found */
31
- *phys_ptr = address;
32
- *prot = 0;
33
+ result->page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
34
+ result->phys = address;
35
+ result->prot = 0;
36
return true;
37
}
38
} else {
39
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
40
* might downgrade a secure access to nonsecure.
41
*/
42
if (sattrs.ns) {
43
- txattrs->secure = false;
44
+ result->attrs.secure = false;
45
} else if (!secure) {
46
/*
47
* NS access to S memory must fault.
48
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
49
* for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
50
*/
51
fi->type = ARMFault_QEMU_SFault;
52
- *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
53
- *phys_ptr = address;
54
- *prot = 0;
55
+ result->page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
56
+ result->phys = address;
57
+ result->prot = 0;
58
return true;
59
}
60
}
61
}
62
63
- ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr,
64
- txattrs, prot, &mpu_is_subpage, fi, NULL);
65
- *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
66
+ ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx,
67
+ &result->phys, &result->attrs, &result->prot,
68
+ &mpu_is_subpage, fi, NULL);
69
+ result->page_size =
70
+ sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
71
return ret;
72
}
73
74
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
75
if (arm_feature(env, ARM_FEATURE_V8)) {
76
/* PMSAv8 */
77
ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
78
- &result->phys, &result->attrs,
79
- &result->prot, &result->page_size, fi);
80
+ result, fi);
81
} else if (arm_feature(env, ARM_FEATURE_V7)) {
82
/* PMSAv7 */
83
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
84
--
29
--
85
2.25.1
30
2.20.1
86
31
87
32
diff view generated by jsdifflib
1
We use the non-POSIX 'local' keyword in just two places in configure;
1
In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage.
2
rewrite to avoid it.
2
At the moment new manpages have to be listed both in the conf.py for
3
3
Sphinx and also in docs/meson.build for Meson. We forgot the second
4
In do_compiler(), just drop the 'local' keyword. The variable
4
of those -- correct the omission.
5
'compiler' is only used elsewhere in the do_compiler_werror()
6
function, which already uses the variable as a normal non-local one.
7
8
In probe_target_compiler(), $try and $t are both local; make them
9
normal variables and use a more obviously distinct variable name
10
for $t.
11
5
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Message-id: 20220825150703.4074125-8-peter.maydell@linaro.org
9
Message-id: 20210108161416.21129-2-peter.maydell@linaro.org
16
---
10
---
17
configure | 7 +++----
11
docs/meson.build | 1 +
18
1 file changed, 3 insertions(+), 4 deletions(-)
12
1 file changed, 1 insertion(+)
19
13
20
diff --git a/configure b/configure
14
diff --git a/docs/meson.build b/docs/meson.build
21
index XXXXXXX..XXXXXXX 100755
15
index XXXXXXX..XXXXXXX 100644
22
--- a/configure
16
--- a/docs/meson.build
23
+++ b/configure
17
+++ b/docs/meson.build
24
@@ -XXX,XX +XXX,XX @@ error_exit() {
18
@@ -XXX,XX +XXX,XX @@ if build_docs
25
do_compiler() {
19
'qemu-img.1': (have_tools ? 'man1' : ''),
26
# Run the compiler, capturing its output to the log. First argument
20
'qemu-nbd.8': (have_tools ? 'man8' : ''),
27
# is compiler binary to execute.
21
'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
28
- local compiler="$1"
22
+ 'qemu-storage-daemon.1': (have_tools ? 'man1' : ''),
29
+ compiler="$1"
23
'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
30
shift
24
'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
31
if test -n "$BASH_VERSION"; then eval '
25
'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
32
echo >>config.log "
33
@@ -XXX,XX +XXX,XX @@ probe_target_compiler() {
34
: ${container_cross_strip:=${container_cross_prefix}strip}
35
done
36
37
- local t try
38
try=cross
39
case "$target_arch:$cpu" in
40
aarch64_be:aarch64 | \
41
@@ -XXX,XX +XXX,XX @@ probe_target_compiler() {
42
try='native cross' ;;
43
esac
44
eval "target_cflags=\${cross_cc_cflags_$target_arch}"
45
- for t in $try; do
46
- case $t in
47
+ for thistry in $try; do
48
+ case $thistry in
49
native)
50
target_cc=$cc
51
target_ccas=$ccas
52
--
26
--
53
2.25.1
27
2.20.1
54
28
55
29
diff view generated by jsdifflib
1
Shellcheck warns that we have one place where we run a command and
1
When we first converted our documentation to Sphinx, we split it into
2
then check if it failed using $?; this is better written to simply
2
multiple manuals (system, interop, tools, etc), which are all built
3
check the command in the 'if' statement directly.
3
separately. The primary driver for this was wanting to be able to
4
avoid shipping the 'devel' manual to end-users. However, this is
5
working against the grain of the way Sphinx wants to be used and
6
causes some annoyances:
7
* Cross-references between documents become much harder or
8
possibly impossible
9
* There is no single index to the whole documentation
10
* Within one manual there's no links or table-of-contents info
11
that lets you easily navigate to the others
12
* The devel manual doesn't get published on the QEMU website
13
(it would be nice to able to refer to it there)
14
15
Merely hiding our developer documentation from end users seems like
16
it's not enough benefit for these costs. Combine all the
17
documentation into a single manual (the same way that the readthedocs
18
site builds it) and install the whole thing. The previous manual
19
divisions remain as the new top level sections in the manual.
20
21
* The per-manual conf.py files are no longer needed
22
* The man_pages[] specifications previously in each per-manual
23
conf.py move to the top level conf.py
24
* docs/meson.build logic is simplified as we now only need to run
25
Sphinx once for the HTML and then once for the manpages5B
26
* The old index.html.in that produced the top-level page with
27
links to each manual is no longer needed
28
29
Unfortunately this means that we now have to build the HTML
30
documentation into docs/manual in the build tree rather than directly
31
into docs/; otherwise it is too awkward to ensure we install only the
32
built manual and not also the dependency info, stamp file, etc. The
33
manual still ends up in the same place in the final installed
34
directory, but anybody who was consulting documentation from within
35
the build tree will have to adjust where they're looking.
4
36
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
38
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
39
Message-id: 20210108161416.21129-3-peter.maydell@linaro.org
8
Message-id: 20220825150703.4074125-7-peter.maydell@linaro.org
9
---
40
---
10
configure | 3 +--
41
docs/conf.py | 46 ++++++++++++++++++++++++++++++-
11
1 file changed, 1 insertion(+), 2 deletions(-)
42
docs/devel/conf.py | 15 -----------
12
43
docs/index.html.in | 17 ------------
13
diff --git a/configure b/configure
44
docs/interop/conf.py | 28 -------------------
14
index XXXXXXX..XXXXXXX 100755
45
docs/meson.build | 64 +++++++++++++++++---------------------------
15
--- a/configure
46
docs/specs/conf.py | 16 -----------
16
+++ b/configure
47
docs/system/conf.py | 28 -------------------
17
@@ -XXX,XX +XXX,XX @@ fi
48
docs/tools/conf.py | 37 -------------------------
18
# it when configure exits.)
49
docs/user/conf.py | 15 -----------
19
TMPDIR1="config-temp"
50
9 files changed, 70 insertions(+), 196 deletions(-)
20
rm -rf "${TMPDIR1}"
51
delete mode 100644 docs/devel/conf.py
21
-mkdir -p "${TMPDIR1}"
52
delete mode 100644 docs/index.html.in
22
-if [ $? -ne 0 ]; then
53
delete mode 100644 docs/interop/conf.py
23
+if ! mkdir -p "${TMPDIR1}"; then
54
delete mode 100644 docs/specs/conf.py
24
echo "ERROR: failed to create temporary directory"
55
delete mode 100644 docs/system/conf.py
25
exit 1
56
delete mode 100644 docs/tools/conf.py
26
fi
57
delete mode 100644 docs/user/conf.py
58
59
diff --git a/docs/conf.py b/docs/conf.py
60
index XXXXXXX..XXXXXXX 100644
61
--- a/docs/conf.py
62
+++ b/docs/conf.py
63
@@ -XXX,XX +XXX,XX @@ latex_documents = [
64
65
# -- Options for manual page output ---------------------------------------
66
# Individual manual/conf.py can override this to create man pages
67
-man_pages = []
68
+man_pages = [
69
+ ('interop/qemu-ga', 'qemu-ga',
70
+ 'QEMU Guest Agent',
71
+ ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
72
+ ('interop/qemu-ga-ref', 'qemu-ga-ref',
73
+ 'QEMU Guest Agent Protocol Reference',
74
+ [], 7),
75
+ ('interop/qemu-qmp-ref', 'qemu-qmp-ref',
76
+ 'QEMU QMP Reference Manual',
77
+ [], 7),
78
+ ('interop/qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
79
+ 'QEMU Storage Daemon QMP Reference Manual',
80
+ [], 7),
81
+ ('system/qemu-manpage', 'qemu',
82
+ 'QEMU User Documentation',
83
+ ['Fabrice Bellard'], 1),
84
+ ('system/qemu-block-drivers', 'qemu-block-drivers',
85
+ 'QEMU block drivers reference',
86
+ ['Fabrice Bellard and the QEMU Project developers'], 7),
87
+ ('system/qemu-cpu-models', 'qemu-cpu-models',
88
+ 'QEMU CPU Models',
89
+ ['The QEMU Project developers'], 7),
90
+ ('tools/qemu-img', 'qemu-img',
91
+ 'QEMU disk image utility',
92
+ ['Fabrice Bellard'], 1),
93
+ ('tools/qemu-nbd', 'qemu-nbd',
94
+ 'QEMU Disk Network Block Device Server',
95
+ ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
96
+ ('tools/qemu-pr-helper', 'qemu-pr-helper',
97
+ 'QEMU persistent reservation helper',
98
+ [], 8),
99
+ ('tools/qemu-storage-daemon', 'qemu-storage-daemon',
100
+ 'QEMU storage daemon',
101
+ [], 1),
102
+ ('tools/qemu-trace-stap', 'qemu-trace-stap',
103
+ 'QEMU SystemTap trace tool',
104
+ [], 1),
105
+ ('tools/virtfs-proxy-helper', 'virtfs-proxy-helper',
106
+ 'QEMU 9p virtfs proxy filesystem helper',
107
+ ['M. Mohan Kumar'], 1),
108
+ ('tools/virtiofsd', 'virtiofsd',
109
+ 'QEMU virtio-fs shared file system daemon',
110
+ ['Stefan Hajnoczi <stefanha@redhat.com>',
111
+ 'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
112
+]
113
114
# -- Options for Texinfo output -------------------------------------------
115
116
diff --git a/docs/devel/conf.py b/docs/devel/conf.py
117
deleted file mode 100644
118
index XXXXXXX..XXXXXXX
119
--- a/docs/devel/conf.py
120
+++ /dev/null
121
@@ -XXX,XX +XXX,XX @@
122
-# -*- coding: utf-8 -*-
123
-#
124
-# QEMU documentation build configuration file for the 'devel' manual.
125
-#
126
-# This includes the top level conf file and then makes any necessary tweaks.
127
-import sys
128
-import os
129
-
130
-qemu_docdir = os.path.abspath("..")
131
-parent_config = os.path.join(qemu_docdir, "conf.py")
132
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
133
-
134
-# This slightly misuses the 'description', but is the best way to get
135
-# the manual title to appear in the sidebar.
136
-html_theme_options['description'] = u'Developer''s Guide'
137
diff --git a/docs/index.html.in b/docs/index.html.in
138
deleted file mode 100644
139
index XXXXXXX..XXXXXXX
140
--- a/docs/index.html.in
141
+++ /dev/null
142
@@ -XXX,XX +XXX,XX @@
143
-<!DOCTYPE html>
144
-<html lang="en">
145
- <head>
146
- <meta charset="UTF-8">
147
- <title>QEMU @VERSION@ Documentation</title>
148
- </head>
149
- <body>
150
- <h1>QEMU @VERSION@ Documentation</h1>
151
- <ul>
152
- <li><a href="system/index.html">System Emulation User's Guide</a></li>
153
- <li><a href="user/index.html">User Mode Emulation User's Guide</a></li>
154
- <li><a href="tools/index.html">Tools Guide</a></li>
155
- <li><a href="interop/index.html">System Emulation Management and Interoperability Guide</a></li>
156
- <li><a href="specs/index.html">System Emulation Guest Hardware Specifications</a></li>
157
- </ul>
158
- </body>
159
-</html>
160
diff --git a/docs/interop/conf.py b/docs/interop/conf.py
161
deleted file mode 100644
162
index XXXXXXX..XXXXXXX
163
--- a/docs/interop/conf.py
164
+++ /dev/null
165
@@ -XXX,XX +XXX,XX @@
166
-# -*- coding: utf-8 -*-
167
-#
168
-# QEMU documentation build configuration file for the 'interop' manual.
169
-#
170
-# This includes the top level conf file and then makes any necessary tweaks.
171
-import sys
172
-import os
173
-
174
-qemu_docdir = os.path.abspath("..")
175
-parent_config = os.path.join(qemu_docdir, "conf.py")
176
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
177
-
178
-# This slightly misuses the 'description', but is the best way to get
179
-# the manual title to appear in the sidebar.
180
-html_theme_options['description'] = u'System Emulation Management and Interoperability Guide'
181
-
182
-# One entry per manual page. List of tuples
183
-# (source start file, name, description, authors, manual section).
184
-man_pages = [
185
- ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent',
186
- ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
187
- ('qemu-ga-ref', 'qemu-ga-ref', 'QEMU Guest Agent Protocol Reference',
188
- [], 7),
189
- ('qemu-qmp-ref', 'qemu-qmp-ref', 'QEMU QMP Reference Manual',
190
- [], 7),
191
- ('qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
192
- 'QEMU Storage Daemon QMP Reference Manual', [], 7),
193
-]
194
diff --git a/docs/meson.build b/docs/meson.build
195
index XXXXXXX..XXXXXXX 100644
196
--- a/docs/meson.build
197
+++ b/docs/meson.build
198
@@ -XXX,XX +XXX,XX @@ if build_docs
199
meson.source_root() / 'docs/sphinx/qmp_lexer.py',
200
qapi_gen_depends ]
201
202
- configure_file(output: 'index.html',
203
- input: files('index.html.in'),
204
- configuration: {'VERSION': meson.project_version()},
205
- install_dir: qemu_docdir)
206
- manuals = [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ]
207
man_pages = {
208
- 'interop' : {
209
'qemu-ga.8': (have_tools ? 'man8' : ''),
210
'qemu-ga-ref.7': 'man7',
211
'qemu-qmp-ref.7': 'man7',
212
'qemu-storage-daemon-qmp-ref.7': (have_tools ? 'man7' : ''),
213
- },
214
- 'tools': {
215
'qemu-img.1': (have_tools ? 'man1' : ''),
216
'qemu-nbd.8': (have_tools ? 'man8' : ''),
217
'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
218
@@ -XXX,XX +XXX,XX @@ if build_docs
219
'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
220
'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
221
'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
222
- },
223
- 'system': {
224
'qemu.1': 'man1',
225
'qemu-block-drivers.7': 'man7',
226
'qemu-cpu-models.7': 'man7'
227
- },
228
}
229
230
sphinxdocs = []
231
sphinxmans = []
232
- foreach manual : manuals
233
- private_dir = meson.current_build_dir() / (manual + '.p')
234
- output_dir = meson.current_build_dir() / manual
235
- input_dir = meson.current_source_dir() / manual
236
237
- this_manual = custom_target(manual + ' manual',
238
+ private_dir = meson.current_build_dir() / 'manual.p'
239
+ output_dir = meson.current_build_dir() / 'manual'
240
+ input_dir = meson.current_source_dir()
241
+
242
+ this_manual = custom_target('QEMU manual',
243
build_by_default: build_docs,
244
- output: [manual + '.stamp'],
245
- input: [files('conf.py'), files(manual / 'conf.py')],
246
- depfile: manual + '.d',
247
+ output: 'docs.stamp',
248
+ input: files('conf.py'),
249
+ depfile: 'docs.d',
250
depend_files: sphinx_extn_depends,
251
command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@',
252
'-Ddepfile_stamp=@OUTPUT0@',
253
'-b', 'html', '-d', private_dir,
254
input_dir, output_dir])
255
- sphinxdocs += this_manual
256
- if build_docs and manual != 'devel'
257
- install_subdir(output_dir, install_dir: qemu_docdir)
258
- endif
259
+ sphinxdocs += this_manual
260
+ install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: true)
261
262
- these_man_pages = []
263
- install_dirs = []
264
- foreach page, section : man_pages.get(manual, {})
265
- these_man_pages += page
266
- install_dirs += section == '' ? false : get_option('mandir') / section
267
- endforeach
268
- if these_man_pages.length() > 0
269
- sphinxmans += custom_target(manual + ' man pages',
270
- build_by_default: build_docs,
271
- output: these_man_pages,
272
- input: this_manual,
273
- install: build_docs,
274
- install_dir: install_dirs,
275
- command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
276
- input_dir, meson.current_build_dir()])
277
- endif
278
+ these_man_pages = []
279
+ install_dirs = []
280
+ foreach page, section : man_pages
281
+ these_man_pages += page
282
+ install_dirs += section == '' ? false : get_option('mandir') / section
283
endforeach
284
+
285
+ sphinxmans += custom_target('QEMU man pages',
286
+ build_by_default: build_docs,
287
+ output: these_man_pages,
288
+ input: this_manual,
289
+ install: build_docs,
290
+ install_dir: install_dirs,
291
+ command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
292
+ input_dir, meson.current_build_dir()])
293
+
294
alias_target('sphinxdocs', sphinxdocs)
295
alias_target('html', sphinxdocs)
296
alias_target('man', sphinxmans)
297
diff --git a/docs/specs/conf.py b/docs/specs/conf.py
298
deleted file mode 100644
299
index XXXXXXX..XXXXXXX
300
--- a/docs/specs/conf.py
301
+++ /dev/null
302
@@ -XXX,XX +XXX,XX @@
303
-# -*- coding: utf-8 -*-
304
-#
305
-# QEMU documentation build configuration file for the 'specs' manual.
306
-#
307
-# This includes the top level conf file and then makes any necessary tweaks.
308
-import sys
309
-import os
310
-
311
-qemu_docdir = os.path.abspath("..")
312
-parent_config = os.path.join(qemu_docdir, "conf.py")
313
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
314
-
315
-# This slightly misuses the 'description', but is the best way to get
316
-# the manual title to appear in the sidebar.
317
-html_theme_options['description'] = \
318
- u'System Emulation Guest Hardware Specifications'
319
diff --git a/docs/system/conf.py b/docs/system/conf.py
320
deleted file mode 100644
321
index XXXXXXX..XXXXXXX
322
--- a/docs/system/conf.py
323
+++ /dev/null
324
@@ -XXX,XX +XXX,XX @@
325
-# -*- coding: utf-8 -*-
326
-#
327
-# QEMU documentation build configuration file for the 'system' manual.
328
-#
329
-# This includes the top level conf file and then makes any necessary tweaks.
330
-import sys
331
-import os
332
-
333
-qemu_docdir = os.path.abspath("..")
334
-parent_config = os.path.join(qemu_docdir, "conf.py")
335
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
336
-
337
-# This slightly misuses the 'description', but is the best way to get
338
-# the manual title to appear in the sidebar.
339
-html_theme_options['description'] = u'System Emulation User''s Guide'
340
-
341
-# One entry per manual page. List of tuples
342
-# (source start file, name, description, authors, manual section).
343
-man_pages = [
344
- ('qemu-manpage', 'qemu', u'QEMU User Documentation',
345
- ['Fabrice Bellard'], 1),
346
- ('qemu-block-drivers', 'qemu-block-drivers',
347
- u'QEMU block drivers reference',
348
- ['Fabrice Bellard and the QEMU Project developers'], 7),
349
- ('qemu-cpu-models', 'qemu-cpu-models',
350
- u'QEMU CPU Models',
351
- ['The QEMU Project developers'], 7)
352
-]
353
diff --git a/docs/tools/conf.py b/docs/tools/conf.py
354
deleted file mode 100644
355
index XXXXXXX..XXXXXXX
356
--- a/docs/tools/conf.py
357
+++ /dev/null
358
@@ -XXX,XX +XXX,XX @@
359
-# -*- coding: utf-8 -*-
360
-#
361
-# QEMU documentation build configuration file for the 'tools' manual.
362
-#
363
-# This includes the top level conf file and then makes any necessary tweaks.
364
-import sys
365
-import os
366
-
367
-qemu_docdir = os.path.abspath("..")
368
-parent_config = os.path.join(qemu_docdir, "conf.py")
369
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
370
-
371
-# This slightly misuses the 'description', but is the best way to get
372
-# the manual title to appear in the sidebar.
373
-html_theme_options['description'] = \
374
- u'Tools Guide'
375
-
376
-# One entry per manual page. List of tuples
377
-# (source start file, name, description, authors, manual section).
378
-man_pages = [
379
- ('qemu-img', 'qemu-img', u'QEMU disk image utility',
380
- ['Fabrice Bellard'], 1),
381
- ('qemu-storage-daemon', 'qemu-storage-daemon', u'QEMU storage daemon',
382
- [], 1),
383
- ('qemu-nbd', 'qemu-nbd', u'QEMU Disk Network Block Device Server',
384
- ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
385
- ('qemu-pr-helper', 'qemu-pr-helper', 'QEMU persistent reservation helper',
386
- [], 8),
387
- ('qemu-trace-stap', 'qemu-trace-stap', u'QEMU SystemTap trace tool',
388
- [], 1),
389
- ('virtfs-proxy-helper', 'virtfs-proxy-helper',
390
- u'QEMU 9p virtfs proxy filesystem helper',
391
- ['M. Mohan Kumar'], 1),
392
- ('virtiofsd', 'virtiofsd', u'QEMU virtio-fs shared file system daemon',
393
- ['Stefan Hajnoczi <stefanha@redhat.com>',
394
- 'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
395
-]
396
diff --git a/docs/user/conf.py b/docs/user/conf.py
397
deleted file mode 100644
398
index XXXXXXX..XXXXXXX
399
--- a/docs/user/conf.py
400
+++ /dev/null
401
@@ -XXX,XX +XXX,XX @@
402
-# -*- coding: utf-8 -*-
403
-#
404
-# QEMU documentation build configuration file for the 'user' manual.
405
-#
406
-# This includes the top level conf file and then makes any necessary tweaks.
407
-import sys
408
-import os
409
-
410
-qemu_docdir = os.path.abspath("..")
411
-parent_config = os.path.join(qemu_docdir, "conf.py")
412
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
413
-
414
-# This slightly misuses the 'description', but is the best way to get
415
-# the manual title to appear in the sidebar.
416
-html_theme_options['description'] = u'User Mode Emulation User''s Guide'
27
--
417
--
28
2.25.1
418
2.20.1
29
419
30
420
diff view generated by jsdifflib
1
This commit adds quotes in some places which:
1
In commit cd8be50e58f63413c0 we converted the A32 coprocessor
2
* are spotted by shellcheck
2
insns to decodetree. This accidentally broke XScale/iWMMXt insns,
3
* are obviously incorrect
3
because it moved the handling of "cp insns which are handled
4
* are easy to fix just by adding the quotes
4
by looking up the cp register in the hashtable" from after the
5
call to the legacy disas_xscale_insn() decode to before it,
6
with the result that all XScale/iWMMXt insns now UNDEF.
5
7
6
It doesn't attempt fix all of the places shellcheck finds errors,
8
Update valid_cp() so that it knows that on XScale cp 0 and 1
7
or even all the ones which are easy to fix. It's just a random
9
are not standard coprocessor instructions; this will cause
8
sampling which is hopefully easy to review and which cuts
10
the decodetree trans_ functions to ignore them, so that
9
down the size of the problem for next time somebody wants to
11
execution will correctly get through to the legacy decode again.
10
try to look at shellcheck errors.
11
12
13
Cc: qemu-stable@nongnu.org
14
Reported-by: Guenter Roeck <linux@roeck-us.net>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Tested-by: Guenter Roeck <linux@roeck-us.net>
15
Message-id: 20220825150703.4074125-4-peter.maydell@linaro.org
18
Message-id: 20210108195157.32067-1-peter.maydell@linaro.org
16
---
19
---
17
configure | 64 +++++++++++++++++++++++++++----------------------------
20
target/arm/translate.c | 7 +++++++
18
1 file changed, 32 insertions(+), 32 deletions(-)
21
1 file changed, 7 insertions(+)
19
22
20
diff --git a/configure b/configure
23
diff --git a/target/arm/translate.c b/target/arm/translate.c
21
index XXXXXXX..XXXXXXX 100755
24
index XXXXXXX..XXXXXXX 100644
22
--- a/configure
25
--- a/target/arm/translate.c
23
+++ b/configure
26
+++ b/target/arm/translate.c
24
@@ -XXX,XX +XXX,XX @@ GNUmakefile: ;
27
@@ -XXX,XX +XXX,XX @@ static bool valid_cp(DisasContext *s, int cp)
25
28
* only cp14 and cp15 are valid, and other values aren't considered
26
EOF
29
* to be in the coprocessor-instruction space at all. v8M still
27
cd build
30
* permits coprocessors 0..7.
28
- exec $source_path/configure "$@"
31
+ * For XScale, we must not decode the XScale cp0, cp1 space as
29
+ exec "$source_path/configure" "$@"
32
+ * a standard coprocessor insn, because we want to fall through to
30
fi
33
+ * the legacy disas_xscale_insn() decoder after decodetree is done.
31
34
*/
32
# Temporary directory used for files created while
35
+ if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) {
33
@@ -XXX,XX +XXX,XX @@ meson_option_build_array() {
36
+ return false;
34
printf ']\n'
37
+ }
35
}
38
+
36
39
if (arm_dc_feature(s, ARM_FEATURE_V8) &&
37
-. $source_path/scripts/meson-buildoptions.sh
40
!arm_dc_feature(s, ARM_FEATURE_M)) {
38
+. "$source_path/scripts/meson-buildoptions.sh"
41
return cp >= 14;
39
40
meson_options=
41
meson_option_add() {
42
@@ -XXX,XX +XXX,XX @@ for opt do
43
case "$opt" in
44
--help|-h) show_help=yes
45
;;
46
- --version|-V) exec cat $source_path/VERSION
47
+ --version|-V) exec cat "$source_path/VERSION"
48
;;
49
--prefix=*) prefix="$optarg"
50
;;
51
@@ -XXX,XX +XXX,XX @@ default_target_list=""
52
mak_wilds=""
53
54
if [ "$linux_user" != no ]; then
55
- if [ "$targetos" = linux ] && [ -d $source_path/linux-user/include/host/$cpu ]; then
56
+ if [ "$targetos" = linux ] && [ -d "$source_path/linux-user/include/host/$cpu" ]; then
57
linux_user=yes
58
elif [ "$linux_user" = yes ]; then
59
error_exit "linux-user not supported on this architecture"
60
@@ -XXX,XX +XXX,XX @@ if [ "$bsd_user" != no ]; then
61
if [ "$bsd_user" = "" ]; then
62
test $targetos = freebsd && bsd_user=yes
63
fi
64
- if [ "$bsd_user" = yes ] && ! [ -d $source_path/bsd-user/$targetos ]; then
65
+ if [ "$bsd_user" = yes ] && ! [ -d "$source_path/bsd-user/$targetos" ]; then
66
error_exit "bsd-user not supported on this host OS"
67
fi
68
fi
69
@@ -XXX,XX +XXX,XX @@ python="$python -B"
70
if test -z "$meson"; then
71
if test "$explicit_python" = no && has meson && version_ge "$(meson --version)" 0.59.3; then
72
meson=meson
73
- elif test $git_submodules_action != 'ignore' ; then
74
+ elif test "$git_submodules_action" != 'ignore' ; then
75
meson=git
76
elif test -e "${source_path}/meson/meson.py" ; then
77
meson=internal
78
@@ -XXX,XX +XXX,XX @@ esac
79
container="no"
80
if test $use_containers = "yes"; then
81
if has "docker" || has "podman"; then
82
- container=$($python $source_path/tests/docker/docker.py probe)
83
+ container=$($python "$source_path"/tests/docker/docker.py probe)
84
fi
85
fi
86
87
@@ -XXX,XX +XXX,XX @@ if test "$QEMU_GA_DISTRO" = ""; then
88
QEMU_GA_DISTRO=Linux
89
fi
90
if test "$QEMU_GA_VERSION" = ""; then
91
- QEMU_GA_VERSION=$(cat $source_path/VERSION)
92
+ QEMU_GA_VERSION=$(cat "$source_path"/VERSION)
93
fi
94
95
96
@@ -XXX,XX +XXX,XX @@ fi
97
for target in $target_list; do
98
target_dir="$target"
99
target_name=$(echo $target | cut -d '-' -f 1)$EXESUF
100
- mkdir -p $target_dir
101
+ mkdir -p "$target_dir"
102
case $target in
103
*-user) symlink "../qemu-$target_name" "$target_dir/qemu-$target_name" ;;
104
*) symlink "../qemu-system-$target_name" "$target_dir/qemu-system-$target_name" ;;
105
@@ -XXX,XX +XXX,XX @@ for target in $target_list; do
106
config_target_mak=tests/tcg/config-$target.mak
107
108
echo "# Automatically generated by configure - do not modify" > $config_target_mak
109
- echo "TARGET_NAME=$arch" >> $config_target_mak
110
+ echo "TARGET_NAME=$arch" >> "$config_target_mak"
111
case $target in
112
xtensa*-linux-user)
113
# the toolchain is not complete with headers, only build softmmu tests
114
continue
115
;;
116
*-softmmu)
117
- test -f $source_path/tests/tcg/$arch/Makefile.softmmu-target || continue
118
+ test -f "$source_path/tests/tcg/$arch/Makefile.softmmu-target" || continue
119
qemu="qemu-system-$arch"
120
;;
121
*-linux-user|*-bsd-user)
122
@@ -XXX,XX +XXX,XX @@ for target in $target_list; do
123
# compilers is a requirememt for adding a new test that needs a
124
# compiler feature.
125
126
- echo "BUILD_STATIC=$build_static" >> $config_target_mak
127
- write_target_makefile >> $config_target_mak
128
+ echo "BUILD_STATIC=$build_static" >> "$config_target_mak"
129
+ write_target_makefile >> "$config_target_mak"
130
case $target in
131
aarch64-*)
132
if do_compiler "$target_cc" $target_cflags \
133
-march=armv8.1-a+sve -o $TMPE $TMPC; then
134
- echo "CROSS_CC_HAS_SVE=y" >> $config_target_mak
135
+ echo "CROSS_CC_HAS_SVE=y" >> "$config_target_mak"
136
fi
137
if do_compiler "$target_cc" $target_cflags \
138
-march=armv8.1-a+sve2 -o $TMPE $TMPC; then
139
- echo "CROSS_CC_HAS_SVE2=y" >> $config_target_mak
140
+ echo "CROSS_CC_HAS_SVE2=y" >> "$config_target_mak"
141
fi
142
if do_compiler "$target_cc" $target_cflags \
143
-march=armv8.3-a -o $TMPE $TMPC; then
144
- echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak
145
+ echo "CROSS_CC_HAS_ARMV8_3=y" >> "$config_target_mak"
146
fi
147
if do_compiler "$target_cc" $target_cflags \
148
-mbranch-protection=standard -o $TMPE $TMPC; then
149
- echo "CROSS_CC_HAS_ARMV8_BTI=y" >> $config_target_mak
150
+ echo "CROSS_CC_HAS_ARMV8_BTI=y" >> "$config_target_mak"
151
fi
152
if do_compiler "$target_cc" $target_cflags \
153
-march=armv8.5-a+memtag -o $TMPE $TMPC; then
154
- echo "CROSS_CC_HAS_ARMV8_MTE=y" >> $config_target_mak
155
+ echo "CROSS_CC_HAS_ARMV8_MTE=y" >> "$config_target_mak"
156
fi
157
;;
158
ppc*)
159
if do_compiler "$target_cc" $target_cflags \
160
-mpower8-vector -o $TMPE $TMPC; then
161
- echo "CROSS_CC_HAS_POWER8_VECTOR=y" >> $config_target_mak
162
+ echo "CROSS_CC_HAS_POWER8_VECTOR=y" >> "$config_target_mak"
163
fi
164
if do_compiler "$target_cc" $target_cflags \
165
-mpower10 -o $TMPE $TMPC; then
166
- echo "CROSS_CC_HAS_POWER10=y" >> $config_target_mak
167
+ echo "CROSS_CC_HAS_POWER10=y" >> "$config_target_mak"
168
fi
169
;;
170
i386-linux-user)
171
if do_compiler "$target_cc" $target_cflags \
172
-Werror -fno-pie -o $TMPE $TMPC; then
173
- echo "CROSS_CC_HAS_I386_NOPIE=y" >> $config_target_mak
174
+ echo "CROSS_CC_HAS_I386_NOPIE=y" >> "$config_target_mak"
175
fi
176
;;
177
esac
178
elif test -n "$container_image"; then
179
echo "build-tcg-tests-$target: docker-image-$container_image" >> $makefile
180
- echo "BUILD_STATIC=y" >> $config_target_mak
181
- write_container_target_makefile >> $config_target_mak
182
+ echo "BUILD_STATIC=y" >> "$config_target_mak"
183
+ write_container_target_makefile >> "$config_target_mak"
184
case $target in
185
aarch64-*)
186
- echo "CROSS_CC_HAS_SVE=y" >> $config_target_mak
187
- echo "CROSS_CC_HAS_SVE2=y" >> $config_target_mak
188
- echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak
189
- echo "CROSS_CC_HAS_ARMV8_BTI=y" >> $config_target_mak
190
- echo "CROSS_CC_HAS_ARMV8_MTE=y" >> $config_target_mak
191
+ echo "CROSS_CC_HAS_SVE=y" >> "$config_target_mak"
192
+ echo "CROSS_CC_HAS_SVE2=y" >> "$config_target_mak"
193
+ echo "CROSS_CC_HAS_ARMV8_3=y" >> "$config_target_mak"
194
+ echo "CROSS_CC_HAS_ARMV8_BTI=y" >> "$config_target_mak"
195
+ echo "CROSS_CC_HAS_ARMV8_MTE=y" >> "$config_target_mak"
196
;;
197
ppc*)
198
- echo "CROSS_CC_HAS_POWER8_VECTOR=y" >> $config_target_mak
199
- echo "CROSS_CC_HAS_POWER10=y" >> $config_target_mak
200
+ echo "CROSS_CC_HAS_POWER8_VECTOR=y" >> "$config_target_mak"
201
+ echo "CROSS_CC_HAS_POWER10=y" >> "$config_target_mak"
202
;;
203
i386-linux-user)
204
- echo "CROSS_CC_HAS_I386_NOPIE=y" >> $config_target_mak
205
+ echo "CROSS_CC_HAS_I386_NOPIE=y" >> "$config_target_mak"
206
;;
207
esac
208
got_cross_cc=yes
209
fi
210
if test $got_cross_cc = yes; then
211
mkdir -p tests/tcg/$target
212
- echo "QEMU=$PWD/$qemu" >> $config_target_mak
213
+ echo "QEMU=$PWD/$qemu" >> "$config_target_mak"
214
echo "run-tcg-tests-$target: $qemu\$(EXESUF)" >> $makefile
215
tcg_tests_targets="$tcg_tests_targets $target"
216
fi
217
--
42
--
218
2.25.1
43
2.20.1
219
44
220
45
diff view generated by jsdifflib
1
From: Lucas Dietrich <ld.adecy@gmail.com>
1
A copy-and-paste error meant that the return value for register offset 0x44
2
(the RX Status FIFO PEEK register) returned a byte from a bogus offset in
3
the rx status FIFO. Fix the typo.
2
4
3
The LAN9118 allows the guest to specify a level for both the TX and
5
Cc: qemu-stable@nongnu.org
4
RX FIFOs at which an interrupt will be generated. We implement the
6
Fixes: https://bugs.launchpad.net/qemu/+bug/1904954
5
RSFL_INT interrupt for the RX FIFO but are missing the handling of
6
the equivalent TSFL_INT for the TX FIFO. Add the missing test to set
7
the interrupt if the TX FIFO has exceeded the guest-specified level.
8
9
This flag is required for Micrium lan911x ethernet driver to work.
10
11
Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com>
12
[PMM: Tweaked commit message and comment]
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20210108180401.2263-2-peter.maydell@linaro.org
15
---
10
---
16
hw/net/lan9118.c | 8 ++++++++
11
hw/net/lan9118.c | 2 +-
17
1 file changed, 8 insertions(+)
12
1 file changed, 1 insertion(+), 1 deletion(-)
18
13
19
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
14
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
20
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/net/lan9118.c
16
--- a/hw/net/lan9118.c
22
+++ b/hw/net/lan9118.c
17
+++ b/hw/net/lan9118.c
23
@@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s)
18
@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
24
n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511;
19
case 0x40:
25
s->tx_status_fifo[n] = status;
20
return rx_status_fifo_pop(s);
26
s->tx_status_fifo_used++;
21
case 0x44:
27
+
22
- return s->rx_status_fifo[s->tx_status_fifo_head];
28
+ /*
23
+ return s->rx_status_fifo[s->rx_status_fifo_head];
29
+ * Generate TSFL interrupt if TX FIFO level exceeds the level
24
case 0x48:
30
+ * specified in the FIFO_INT TX Status Level field.
25
return tx_status_fifo_pop(s);
31
+ */
26
case 0x4c:
32
+ if (s->tx_status_fifo_used > ((s->fifo_int >> 16) & 0xff)) {
33
+ s->int_sts |= TSFL_INT;
34
+ }
35
if (s->tx_status_fifo_used == 512) {
36
s->int_sts |= TSFF_INT;
37
/* TODO: Stop transmission. */
38
--
27
--
39
2.25.1
28
2.20.1
29
30
diff view generated by jsdifflib
1
The meson_args variable was added in commit 3b4da13293482134b, but
1
The lan9118 code mostly uses symbolic constants for register offsets;
2
was not used in that commit and isn't used today. Delete the
2
the exceptions are those which the datasheet doesn't give an official
3
unnecessary assignment.
3
symbolic name to.
4
5
Add some names for the registers which don't already have them, based
6
on the longer names they are given in the memory map.
4
7
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20220825150703.4074125-3-peter.maydell@linaro.org
10
Message-id: 20210108180401.2263-3-peter.maydell@linaro.org
9
---
11
---
10
configure | 1 -
12
hw/net/lan9118.c | 24 ++++++++++++++++++------
11
1 file changed, 1 deletion(-)
13
1 file changed, 18 insertions(+), 6 deletions(-)
12
14
13
diff --git a/configure b/configure
15
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
14
index XXXXXXX..XXXXXXX 100755
16
index XXXXXXX..XXXXXXX 100644
15
--- a/configure
17
--- a/hw/net/lan9118.c
16
+++ b/configure
18
+++ b/hw/net/lan9118.c
17
@@ -XXX,XX +XXX,XX @@ pie=""
19
@@ -XXX,XX +XXX,XX @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
18
coroutine=""
20
do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
19
plugins="$default_feature"
21
#endif
20
meson=""
22
21
-meson_args=""
23
+/* The tx and rx fifo ports are a range of aliased 32-bit registers */
22
ninja=""
24
+#define RX_DATA_FIFO_PORT_FIRST 0x00
23
bindir="bin"
25
+#define RX_DATA_FIFO_PORT_LAST 0x1f
24
skip_meson=no
26
+#define TX_DATA_FIFO_PORT_FIRST 0x20
27
+#define TX_DATA_FIFO_PORT_LAST 0x3f
28
+
29
+#define RX_STATUS_FIFO_PORT 0x40
30
+#define RX_STATUS_FIFO_PEEK 0x44
31
+#define TX_STATUS_FIFO_PORT 0x48
32
+#define TX_STATUS_FIFO_PEEK 0x4c
33
+
34
#define CSR_ID_REV 0x50
35
#define CSR_IRQ_CFG 0x54
36
#define CSR_INT_STS 0x58
37
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
38
offset &= 0xff;
39
40
//DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
41
- if (offset >= 0x20 && offset < 0x40) {
42
+ if (offset >= TX_DATA_FIFO_PORT_FIRST &&
43
+ offset <= TX_DATA_FIFO_PORT_LAST) {
44
/* TX FIFO */
45
tx_fifo_push(s, val);
46
return;
47
@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
48
lan9118_state *s = (lan9118_state *)opaque;
49
50
//DPRINTF("Read reg 0x%02x\n", (int)offset);
51
- if (offset < 0x20) {
52
+ if (offset <= RX_DATA_FIFO_PORT_LAST) {
53
/* RX FIFO */
54
return rx_fifo_pop(s);
55
}
56
switch (offset) {
57
- case 0x40:
58
+ case RX_STATUS_FIFO_PORT:
59
return rx_status_fifo_pop(s);
60
- case 0x44:
61
+ case RX_STATUS_FIFO_PEEK:
62
return s->rx_status_fifo[s->rx_status_fifo_head];
63
- case 0x48:
64
+ case TX_STATUS_FIFO_PORT:
65
return tx_status_fifo_pop(s);
66
- case 0x4c:
67
+ case TX_STATUS_FIFO_PEEK:
68
return s->tx_status_fifo[s->tx_status_fifo_head];
69
case CSR_ID_REV:
70
return 0x01180001;
25
--
71
--
26
2.25.1
72
2.20.1
27
73
28
74
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
This patch allows NPCM7XX CLK module to compute clocks that are used by
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
other NPCM7XX modules.
5
Message-id: 20220822152741.1617527-8-richard.henderson@linaro.org
5
6
Add a new struct NPCM7xxClockConverterState which represents a
7
single converter. Each clock converter in CLK module represents one
8
converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
9
takes one or more input clocks and converts them into one output clock.
10
They form a clock hierarchy in the CLK module and are responsible for
11
outputing clocks for various other modules in an NPCM7XX SoC.
12
13
Each converter has a function pointer called "convert" which represents
14
the unique logic for that converter.
15
16
The clock contains two initialization information: ConverterInitInfo and
17
ConverterConnectionInfo. They represent the vertices and edges in the
18
clock diagram respectively.
19
20
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
21
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
22
Signed-off-by: Hao Wu <wuhaotsh@google.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Message-id: 20210108190945.949196-2-wuhaotsh@google.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
26
---
9
target/arm/ptw.c | 36 +++++++++++++++++-------------------
27
include/hw/misc/npcm7xx_clk.h | 140 +++++-
10
1 file changed, 17 insertions(+), 19 deletions(-)
28
hw/misc/npcm7xx_clk.c | 805 +++++++++++++++++++++++++++++++++-
29
2 files changed, 932 insertions(+), 13 deletions(-)
11
30
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
31
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
13
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/ptw.c
33
--- a/include/hw/misc/npcm7xx_clk.h
15
+++ b/target/arm/ptw.c
34
+++ b/include/hw/misc/npcm7xx_clk.h
16
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
35
@@ -XXX,XX +XXX,XX @@
17
36
#define NPCM7XX_CLK_H
18
static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
37
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
38
#include "exec/memory.h"
20
- hwaddr *phys_ptr, int *prot,
39
+#include "hw/clock.h"
21
- target_ulong *page_size,
40
#include "hw/sysbus.h"
22
+ GetPhysAddrResult *result,
41
23
ARMMMUFaultInfo *fi)
42
/*
43
@@ -XXX,XX +XXX,XX @@
44
45
#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
46
47
-typedef struct NPCM7xxCLKState {
48
+/* Maximum amount of clock inputs in a SEL module. */
49
+#define NPCM7XX_CLK_SEL_MAX_INPUT 5
50
+
51
+/* PLLs in CLK module. */
52
+typedef enum NPCM7xxClockPLL {
53
+ NPCM7XX_CLOCK_PLL0,
54
+ NPCM7XX_CLOCK_PLL1,
55
+ NPCM7XX_CLOCK_PLL2,
56
+ NPCM7XX_CLOCK_PLLG,
57
+ NPCM7XX_CLOCK_NR_PLLS,
58
+} NPCM7xxClockPLL;
59
+
60
+/* SEL/MUX in CLK module. */
61
+typedef enum NPCM7xxClockSEL {
62
+ NPCM7XX_CLOCK_PIXCKSEL,
63
+ NPCM7XX_CLOCK_MCCKSEL,
64
+ NPCM7XX_CLOCK_CPUCKSEL,
65
+ NPCM7XX_CLOCK_CLKOUTSEL,
66
+ NPCM7XX_CLOCK_UARTCKSEL,
67
+ NPCM7XX_CLOCK_TIMCKSEL,
68
+ NPCM7XX_CLOCK_SDCKSEL,
69
+ NPCM7XX_CLOCK_GFXMSEL,
70
+ NPCM7XX_CLOCK_SUCKSEL,
71
+ NPCM7XX_CLOCK_NR_SELS,
72
+} NPCM7xxClockSEL;
73
+
74
+/* Dividers in CLK module. */
75
+typedef enum NPCM7xxClockDivider {
76
+ NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */
77
+ NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */
78
+ NPCM7XX_CLOCK_MC_DIVIDER,
79
+ NPCM7XX_CLOCK_AXI_DIVIDER,
80
+ NPCM7XX_CLOCK_AHB_DIVIDER,
81
+ NPCM7XX_CLOCK_AHB3_DIVIDER,
82
+ NPCM7XX_CLOCK_SPI0_DIVIDER,
83
+ NPCM7XX_CLOCK_SPIX_DIVIDER,
84
+ NPCM7XX_CLOCK_APB1_DIVIDER,
85
+ NPCM7XX_CLOCK_APB2_DIVIDER,
86
+ NPCM7XX_CLOCK_APB3_DIVIDER,
87
+ NPCM7XX_CLOCK_APB4_DIVIDER,
88
+ NPCM7XX_CLOCK_APB5_DIVIDER,
89
+ NPCM7XX_CLOCK_CLKOUT_DIVIDER,
90
+ NPCM7XX_CLOCK_UART_DIVIDER,
91
+ NPCM7XX_CLOCK_TIMER_DIVIDER,
92
+ NPCM7XX_CLOCK_ADC_DIVIDER,
93
+ NPCM7XX_CLOCK_MMC_DIVIDER,
94
+ NPCM7XX_CLOCK_SDHC_DIVIDER,
95
+ NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */
96
+ NPCM7XX_CLOCK_UTMI_DIVIDER,
97
+ NPCM7XX_CLOCK_NR_DIVIDERS,
98
+} NPCM7xxClockConverter;
99
+
100
+typedef struct NPCM7xxCLKState NPCM7xxCLKState;
101
+
102
+/**
103
+ * struct NPCM7xxClockPLLState - A PLL module in CLK module.
104
+ * @name: The name of the module.
105
+ * @clk: The CLK module that owns this module.
106
+ * @clock_in: The input clock of this module.
107
+ * @clock_out: The output clock of this module.
108
+ * @reg: The control registers for this PLL module.
109
+ */
110
+typedef struct NPCM7xxClockPLLState {
111
+ DeviceState parent;
112
+
113
+ const char *name;
114
+ NPCM7xxCLKState *clk;
115
+ Clock *clock_in;
116
+ Clock *clock_out;
117
+
118
+ int reg;
119
+} NPCM7xxClockPLLState;
120
+
121
+/**
122
+ * struct NPCM7xxClockSELState - A SEL module in CLK module.
123
+ * @name: The name of the module.
124
+ * @clk: The CLK module that owns this module.
125
+ * @input_size: The size of inputs of this module.
126
+ * @clock_in: The input clocks of this module.
127
+ * @clock_out: The output clocks of this module.
128
+ * @offset: The offset of this module in the control register.
129
+ * @len: The length of this module in the control register.
130
+ */
131
+typedef struct NPCM7xxClockSELState {
132
+ DeviceState parent;
133
+
134
+ const char *name;
135
+ NPCM7xxCLKState *clk;
136
+ uint8_t input_size;
137
+ Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
138
+ Clock *clock_out;
139
+
140
+ int offset;
141
+ int len;
142
+} NPCM7xxClockSELState;
143
+
144
+/**
145
+ * struct NPCM7xxClockDividerState - A Divider module in CLK module.
146
+ * @name: The name of the module.
147
+ * @clk: The CLK module that owns this module.
148
+ * @clock_in: The input clock of this module.
149
+ * @clock_out: The output clock of this module.
150
+ * @divide: The function the divider uses to divide the input.
151
+ * @reg: The index of the control register that contains the divisor.
152
+ * @offset: The offset of the divisor in the control register.
153
+ * @len: The length of the divisor in the control register.
154
+ * @divisor: The divisor for a constant divisor
155
+ */
156
+typedef struct NPCM7xxClockDividerState {
157
+ DeviceState parent;
158
+
159
+ const char *name;
160
+ NPCM7xxCLKState *clk;
161
+ Clock *clock_in;
162
+ Clock *clock_out;
163
+
164
+ uint32_t (*divide)(struct NPCM7xxClockDividerState *s);
165
+ union {
166
+ struct {
167
+ int reg;
168
+ int offset;
169
+ int len;
170
+ };
171
+ int divisor;
172
+ };
173
+} NPCM7xxClockDividerState;
174
+
175
+struct NPCM7xxCLKState {
176
SysBusDevice parent;
177
178
MemoryRegion iomem;
179
180
+ /* Clock converters */
181
+ NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS];
182
+ NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
183
+ NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
184
+
185
uint32_t regs[NPCM7XX_CLK_NR_REGS];
186
187
/* Time reference for SECCNT and CNTR25M, initialized by power on reset */
188
int64_t ref_ns;
189
-} NPCM7xxCLKState;
190
+
191
+ /* The incoming reference clock. */
192
+ Clock *clkref;
193
+};
194
195
#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
196
#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
197
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
198
index XXXXXXX..XXXXXXX 100644
199
--- a/hw/misc/npcm7xx_clk.c
200
+++ b/hw/misc/npcm7xx_clk.c
201
@@ -XXX,XX +XXX,XX @@
202
203
#include "hw/misc/npcm7xx_clk.h"
204
#include "hw/timer/npcm7xx_timer.h"
205
+#include "hw/qdev-clock.h"
206
#include "migration/vmstate.h"
207
#include "qemu/error-report.h"
208
#include "qemu/log.h"
209
@@ -XXX,XX +XXX,XX @@
210
#include "trace.h"
211
#include "sysemu/watchdog.h"
212
213
+/*
214
+ * The reference clock hz, and the SECCNT and CNTR25M registers in this module,
215
+ * is always 25 MHz.
216
+ */
217
+#define NPCM7XX_CLOCK_REF_HZ (25000000)
218
+
219
+/* Register Field Definitions */
220
+#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */
221
+
222
#define PLLCON_LOKI BIT(31)
223
#define PLLCON_LOKS BIT(30)
224
#define PLLCON_PWDEN BIT(12)
225
+#define PLLCON_FBDV(con) extract32((con), 16, 12)
226
+#define PLLCON_OTDV2(con) extract32((con), 13, 3)
227
+#define PLLCON_OTDV1(con) extract32((con), 8, 3)
228
+#define PLLCON_INDV(con) extract32((con), 0, 6)
229
230
enum NPCM7xxCLKRegisters {
231
NPCM7XX_CLK_CLKEN1,
232
@@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
233
[NPCM7XX_CLK_AHBCKFI] = 0x000000c8,
234
};
235
236
-/* Register Field Definitions */
237
-#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */
238
-
239
/* The number of watchdogs that can trigger a reset. */
240
#define NPCM7XX_NR_WATCHDOGS (3)
241
242
+/* Clock converter functions */
243
+
244
+#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
245
+#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \
246
+ (obj), TYPE_NPCM7XX_CLOCK_PLL)
247
+#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
248
+#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \
249
+ (obj), TYPE_NPCM7XX_CLOCK_SEL)
250
+#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
251
+#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \
252
+ (obj), TYPE_NPCM7XX_CLOCK_DIVIDER)
253
+
254
+static void npcm7xx_clk_update_pll(void *opaque)
255
+{
256
+ NPCM7xxClockPLLState *s = opaque;
257
+ uint32_t con = s->clk->regs[s->reg];
258
+ uint64_t freq;
259
+
260
+ /* The PLL is grounded if it is not locked yet. */
261
+ if (con & PLLCON_LOKI) {
262
+ freq = clock_get_hz(s->clock_in);
263
+ freq *= PLLCON_FBDV(con);
264
+ freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con);
265
+ } else {
266
+ freq = 0;
267
+ }
268
+
269
+ clock_update_hz(s->clock_out, freq);
270
+}
271
+
272
+static void npcm7xx_clk_update_sel(void *opaque)
273
+{
274
+ NPCM7xxClockSELState *s = opaque;
275
+ uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset,
276
+ s->len);
277
+
278
+ if (index >= s->input_size) {
279
+ qemu_log_mask(LOG_GUEST_ERROR,
280
+ "%s: SEL index: %u out of range\n",
281
+ __func__, index);
282
+ index = 0;
283
+ }
284
+ clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index]));
285
+}
286
+
287
+static void npcm7xx_clk_update_divider(void *opaque)
288
+{
289
+ NPCM7xxClockDividerState *s = opaque;
290
+ uint32_t freq;
291
+
292
+ freq = s->divide(s);
293
+ clock_update_hz(s->clock_out, freq);
294
+}
295
+
296
+static uint32_t divide_by_constant(NPCM7xxClockDividerState *s)
297
+{
298
+ return clock_get_hz(s->clock_in) / s->divisor;
299
+}
300
+
301
+static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s)
302
+{
303
+ return clock_get_hz(s->clock_in) /
304
+ (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);
305
+}
306
+
307
+static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s)
308
+{
309
+ return divide_by_reg_divisor(s) / 2;
310
+}
311
+
312
+static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s)
313
+{
314
+ return clock_get_hz(s->clock_in) >>
315
+ extract32(s->clk->regs[s->reg], s->offset, s->len);
316
+}
317
+
318
+static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)
319
+{
320
+ switch (reg) {
321
+ case NPCM7XX_CLK_PLLCON0:
322
+ return NPCM7XX_CLOCK_PLL0;
323
+ case NPCM7XX_CLK_PLLCON1:
324
+ return NPCM7XX_CLOCK_PLL1;
325
+ case NPCM7XX_CLK_PLLCON2:
326
+ return NPCM7XX_CLOCK_PLL2;
327
+ case NPCM7XX_CLK_PLLCONG:
328
+ return NPCM7XX_CLOCK_PLLG;
329
+ default:
330
+ g_assert_not_reached();
331
+ }
332
+}
333
+
334
+static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
335
+{
336
+ int i;
337
+
338
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
339
+ npcm7xx_clk_update_pll(&clk->plls[i]);
340
+ }
341
+}
342
+
343
+static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
344
+{
345
+ int i;
346
+
347
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
348
+ npcm7xx_clk_update_sel(&clk->sels[i]);
349
+ }
350
+}
351
+
352
+static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
353
+{
354
+ int i;
355
+
356
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
357
+ npcm7xx_clk_update_divider(&clk->dividers[i]);
358
+ }
359
+}
360
+
361
+static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)
362
+{
363
+ clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);
364
+ npcm7xx_clk_update_all_plls(clk);
365
+ npcm7xx_clk_update_all_sels(clk);
366
+ npcm7xx_clk_update_all_dividers(clk);
367
+}
368
+
369
+/* Types of clock sources. */
370
+typedef enum ClockSrcType {
371
+ CLKSRC_REF,
372
+ CLKSRC_PLL,
373
+ CLKSRC_SEL,
374
+ CLKSRC_DIV,
375
+} ClockSrcType;
376
+
377
+typedef struct PLLInitInfo {
378
+ const char *name;
379
+ ClockSrcType src_type;
380
+ int src_index;
381
+ int reg;
382
+ const char *public_name;
383
+} PLLInitInfo;
384
+
385
+typedef struct SELInitInfo {
386
+ const char *name;
387
+ uint8_t input_size;
388
+ ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT];
389
+ int src_index[NPCM7XX_CLK_SEL_MAX_INPUT];
390
+ int offset;
391
+ int len;
392
+ const char *public_name;
393
+} SELInitInfo;
394
+
395
+typedef struct DividerInitInfo {
396
+ const char *name;
397
+ ClockSrcType src_type;
398
+ int src_index;
399
+ uint32_t (*divide)(NPCM7xxClockDividerState *s);
400
+ int reg; /* not used when type == CONSTANT */
401
+ int offset; /* not used when type == CONSTANT */
402
+ int len; /* not used when type == CONSTANT */
403
+ int divisor; /* used only when type == CONSTANT */
404
+ const char *public_name;
405
+} DividerInitInfo;
406
+
407
+static const PLLInitInfo pll_init_info_list[] = {
408
+ [NPCM7XX_CLOCK_PLL0] = {
409
+ .name = "pll0",
410
+ .src_type = CLKSRC_REF,
411
+ .reg = NPCM7XX_CLK_PLLCON0,
412
+ },
413
+ [NPCM7XX_CLOCK_PLL1] = {
414
+ .name = "pll1",
415
+ .src_type = CLKSRC_REF,
416
+ .reg = NPCM7XX_CLK_PLLCON1,
417
+ },
418
+ [NPCM7XX_CLOCK_PLL2] = {
419
+ .name = "pll2",
420
+ .src_type = CLKSRC_REF,
421
+ .reg = NPCM7XX_CLK_PLLCON2,
422
+ },
423
+ [NPCM7XX_CLOCK_PLLG] = {
424
+ .name = "pllg",
425
+ .src_type = CLKSRC_REF,
426
+ .reg = NPCM7XX_CLK_PLLCONG,
427
+ },
428
+};
429
+
430
+static const SELInitInfo sel_init_info_list[] = {
431
+ [NPCM7XX_CLOCK_PIXCKSEL] = {
432
+ .name = "pixcksel",
433
+ .input_size = 2,
434
+ .src_type = {CLKSRC_PLL, CLKSRC_REF},
435
+ .src_index = {NPCM7XX_CLOCK_PLLG, 0},
436
+ .offset = 5,
437
+ .len = 1,
438
+ .public_name = "pixel-clock",
439
+ },
440
+ [NPCM7XX_CLOCK_MCCKSEL] = {
441
+ .name = "mccksel",
442
+ .input_size = 4,
443
+ .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF,
444
+ /*MCBPCK, shouldn't be used in normal operation*/
445
+ CLKSRC_REF},
446
+ .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0},
447
+ .offset = 12,
448
+ .len = 2,
449
+ .public_name = "mc-phy-clock",
450
+ },
451
+ [NPCM7XX_CLOCK_CPUCKSEL] = {
452
+ .name = "cpucksel",
453
+ .input_size = 4,
454
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
455
+ /*SYSBPCK, shouldn't be used in normal operation*/
456
+ CLKSRC_REF},
457
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0},
458
+ .offset = 0,
459
+ .len = 2,
460
+ .public_name = "system-clock",
461
+ },
462
+ [NPCM7XX_CLOCK_CLKOUTSEL] = {
463
+ .name = "clkoutsel",
464
+ .input_size = 5,
465
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
466
+ CLKSRC_PLL, CLKSRC_DIV},
467
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
468
+ NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2},
469
+ .offset = 18,
470
+ .len = 3,
471
+ .public_name = "tock",
472
+ },
473
+ [NPCM7XX_CLOCK_UARTCKSEL] = {
474
+ .name = "uartcksel",
475
+ .input_size = 4,
476
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
477
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
478
+ NPCM7XX_CLOCK_PLL2D2},
479
+ .offset = 8,
480
+ .len = 2,
481
+ },
482
+ [NPCM7XX_CLOCK_TIMCKSEL] = {
483
+ .name = "timcksel",
484
+ .input_size = 4,
485
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
486
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
487
+ NPCM7XX_CLOCK_PLL2D2},
488
+ .offset = 14,
489
+ .len = 2,
490
+ },
491
+ [NPCM7XX_CLOCK_SDCKSEL] = {
492
+ .name = "sdcksel",
493
+ .input_size = 4,
494
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
495
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
496
+ NPCM7XX_CLOCK_PLL2D2},
497
+ .offset = 6,
498
+ .len = 2,
499
+ },
500
+ [NPCM7XX_CLOCK_GFXMSEL] = {
501
+ .name = "gfxmksel",
502
+ .input_size = 2,
503
+ .src_type = {CLKSRC_REF, CLKSRC_PLL},
504
+ .src_index = {0, NPCM7XX_CLOCK_PLL2},
505
+ .offset = 21,
506
+ .len = 1,
507
+ },
508
+ [NPCM7XX_CLOCK_SUCKSEL] = {
509
+ .name = "sucksel",
510
+ .input_size = 4,
511
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
512
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
513
+ NPCM7XX_CLOCK_PLL2D2},
514
+ .offset = 10,
515
+ .len = 2,
516
+ },
517
+};
518
+
519
+static const DividerInitInfo divider_init_info_list[] = {
520
+ [NPCM7XX_CLOCK_PLL1D2] = {
521
+ .name = "pll1d2",
522
+ .src_type = CLKSRC_PLL,
523
+ .src_index = NPCM7XX_CLOCK_PLL1,
524
+ .divide = divide_by_constant,
525
+ .divisor = 2,
526
+ },
527
+ [NPCM7XX_CLOCK_PLL2D2] = {
528
+ .name = "pll2d2",
529
+ .src_type = CLKSRC_PLL,
530
+ .src_index = NPCM7XX_CLOCK_PLL2,
531
+ .divide = divide_by_constant,
532
+ .divisor = 2,
533
+ },
534
+ [NPCM7XX_CLOCK_MC_DIVIDER] = {
535
+ .name = "mc-divider",
536
+ .src_type = CLKSRC_SEL,
537
+ .src_index = NPCM7XX_CLOCK_MCCKSEL,
538
+ .divide = divide_by_constant,
539
+ .divisor = 2,
540
+ .public_name = "mc-clock"
541
+ },
542
+ [NPCM7XX_CLOCK_AXI_DIVIDER] = {
543
+ .name = "axi-divider",
544
+ .src_type = CLKSRC_SEL,
545
+ .src_index = NPCM7XX_CLOCK_CPUCKSEL,
546
+ .divide = shift_by_reg_divisor,
547
+ .reg = NPCM7XX_CLK_CLKDIV1,
548
+ .offset = 0,
549
+ .len = 1,
550
+ .public_name = "clk2"
551
+ },
552
+ [NPCM7XX_CLOCK_AHB_DIVIDER] = {
553
+ .name = "ahb-divider",
554
+ .src_type = CLKSRC_DIV,
555
+ .src_index = NPCM7XX_CLOCK_AXI_DIVIDER,
556
+ .divide = divide_by_reg_divisor,
557
+ .reg = NPCM7XX_CLK_CLKDIV1,
558
+ .offset = 26,
559
+ .len = 2,
560
+ .public_name = "clk4"
561
+ },
562
+ [NPCM7XX_CLOCK_AHB3_DIVIDER] = {
563
+ .name = "ahb3-divider",
564
+ .src_type = CLKSRC_DIV,
565
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
566
+ .divide = divide_by_reg_divisor,
567
+ .reg = NPCM7XX_CLK_CLKDIV1,
568
+ .offset = 6,
569
+ .len = 5,
570
+ .public_name = "ahb3-spi3-clock"
571
+ },
572
+ [NPCM7XX_CLOCK_SPI0_DIVIDER] = {
573
+ .name = "spi0-divider",
574
+ .src_type = CLKSRC_DIV,
575
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
576
+ .divide = divide_by_reg_divisor,
577
+ .reg = NPCM7XX_CLK_CLKDIV3,
578
+ .offset = 6,
579
+ .len = 5,
580
+ .public_name = "spi0-clock",
581
+ },
582
+ [NPCM7XX_CLOCK_SPIX_DIVIDER] = {
583
+ .name = "spix-divider",
584
+ .src_type = CLKSRC_DIV,
585
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
586
+ .divide = divide_by_reg_divisor,
587
+ .reg = NPCM7XX_CLK_CLKDIV3,
588
+ .offset = 1,
589
+ .len = 5,
590
+ .public_name = "spix-clock",
591
+ },
592
+ [NPCM7XX_CLOCK_APB1_DIVIDER] = {
593
+ .name = "apb1-divider",
594
+ .src_type = CLKSRC_DIV,
595
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
596
+ .divide = shift_by_reg_divisor,
597
+ .reg = NPCM7XX_CLK_CLKDIV2,
598
+ .offset = 24,
599
+ .len = 2,
600
+ .public_name = "apb1-clock",
601
+ },
602
+ [NPCM7XX_CLOCK_APB2_DIVIDER] = {
603
+ .name = "apb2-divider",
604
+ .src_type = CLKSRC_DIV,
605
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
606
+ .divide = shift_by_reg_divisor,
607
+ .reg = NPCM7XX_CLK_CLKDIV2,
608
+ .offset = 26,
609
+ .len = 2,
610
+ .public_name = "apb2-clock",
611
+ },
612
+ [NPCM7XX_CLOCK_APB3_DIVIDER] = {
613
+ .name = "apb3-divider",
614
+ .src_type = CLKSRC_DIV,
615
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
616
+ .divide = shift_by_reg_divisor,
617
+ .reg = NPCM7XX_CLK_CLKDIV2,
618
+ .offset = 28,
619
+ .len = 2,
620
+ .public_name = "apb3-clock",
621
+ },
622
+ [NPCM7XX_CLOCK_APB4_DIVIDER] = {
623
+ .name = "apb4-divider",
624
+ .src_type = CLKSRC_DIV,
625
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
626
+ .divide = shift_by_reg_divisor,
627
+ .reg = NPCM7XX_CLK_CLKDIV2,
628
+ .offset = 30,
629
+ .len = 2,
630
+ .public_name = "apb4-clock",
631
+ },
632
+ [NPCM7XX_CLOCK_APB5_DIVIDER] = {
633
+ .name = "apb5-divider",
634
+ .src_type = CLKSRC_DIV,
635
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
636
+ .divide = shift_by_reg_divisor,
637
+ .reg = NPCM7XX_CLK_CLKDIV2,
638
+ .offset = 22,
639
+ .len = 2,
640
+ .public_name = "apb5-clock",
641
+ },
642
+ [NPCM7XX_CLOCK_CLKOUT_DIVIDER] = {
643
+ .name = "clkout-divider",
644
+ .src_type = CLKSRC_SEL,
645
+ .src_index = NPCM7XX_CLOCK_CLKOUTSEL,
646
+ .divide = divide_by_reg_divisor,
647
+ .reg = NPCM7XX_CLK_CLKDIV2,
648
+ .offset = 16,
649
+ .len = 5,
650
+ .public_name = "clkout",
651
+ },
652
+ [NPCM7XX_CLOCK_UART_DIVIDER] = {
653
+ .name = "uart-divider",
654
+ .src_type = CLKSRC_SEL,
655
+ .src_index = NPCM7XX_CLOCK_UARTCKSEL,
656
+ .divide = divide_by_reg_divisor,
657
+ .reg = NPCM7XX_CLK_CLKDIV1,
658
+ .offset = 16,
659
+ .len = 5,
660
+ .public_name = "uart-clock",
661
+ },
662
+ [NPCM7XX_CLOCK_TIMER_DIVIDER] = {
663
+ .name = "timer-divider",
664
+ .src_type = CLKSRC_SEL,
665
+ .src_index = NPCM7XX_CLOCK_TIMCKSEL,
666
+ .divide = divide_by_reg_divisor,
667
+ .reg = NPCM7XX_CLK_CLKDIV1,
668
+ .offset = 21,
669
+ .len = 5,
670
+ .public_name = "timer-clock",
671
+ },
672
+ [NPCM7XX_CLOCK_ADC_DIVIDER] = {
673
+ .name = "adc-divider",
674
+ .src_type = CLKSRC_DIV,
675
+ .src_index = NPCM7XX_CLOCK_TIMER_DIVIDER,
676
+ .divide = shift_by_reg_divisor,
677
+ .reg = NPCM7XX_CLK_CLKDIV1,
678
+ .offset = 28,
679
+ .len = 3,
680
+ .public_name = "adc-clock",
681
+ },
682
+ [NPCM7XX_CLOCK_MMC_DIVIDER] = {
683
+ .name = "mmc-divider",
684
+ .src_type = CLKSRC_SEL,
685
+ .src_index = NPCM7XX_CLOCK_SDCKSEL,
686
+ .divide = divide_by_reg_divisor,
687
+ .reg = NPCM7XX_CLK_CLKDIV1,
688
+ .offset = 11,
689
+ .len = 5,
690
+ .public_name = "mmc-clock",
691
+ },
692
+ [NPCM7XX_CLOCK_SDHC_DIVIDER] = {
693
+ .name = "sdhc-divider",
694
+ .src_type = CLKSRC_SEL,
695
+ .src_index = NPCM7XX_CLOCK_SDCKSEL,
696
+ .divide = divide_by_reg_divisor_times_2,
697
+ .reg = NPCM7XX_CLK_CLKDIV2,
698
+ .offset = 0,
699
+ .len = 4,
700
+ .public_name = "sdhc-clock",
701
+ },
702
+ [NPCM7XX_CLOCK_GFXM_DIVIDER] = {
703
+ .name = "gfxm-divider",
704
+ .src_type = CLKSRC_SEL,
705
+ .src_index = NPCM7XX_CLOCK_GFXMSEL,
706
+ .divide = divide_by_constant,
707
+ .divisor = 3,
708
+ .public_name = "gfxm-clock",
709
+ },
710
+ [NPCM7XX_CLOCK_UTMI_DIVIDER] = {
711
+ .name = "utmi-divider",
712
+ .src_type = CLKSRC_SEL,
713
+ .src_index = NPCM7XX_CLOCK_SUCKSEL,
714
+ .divide = divide_by_reg_divisor,
715
+ .reg = NPCM7XX_CLK_CLKDIV2,
716
+ .offset = 8,
717
+ .len = 5,
718
+ .public_name = "utmi-clock",
719
+ },
720
+};
721
+
722
+static void npcm7xx_clk_pll_init(Object *obj)
723
+{
724
+ NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj);
725
+
726
+ pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in",
727
+ npcm7xx_clk_update_pll, pll);
728
+ pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out");
729
+}
730
+
731
+static void npcm7xx_clk_sel_init(Object *obj)
732
+{
733
+ int i;
734
+ NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj);
735
+
736
+ for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) {
737
+ sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel),
738
+ g_strdup_printf("clock-in[%d]", i),
739
+ npcm7xx_clk_update_sel, sel);
740
+ }
741
+ sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out");
742
+}
743
+static void npcm7xx_clk_divider_init(Object *obj)
744
+{
745
+ NPCM7xxClockDividerState *div = NPCM7XX_CLOCK_DIVIDER(obj);
746
+
747
+ div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in",
748
+ npcm7xx_clk_update_divider, div);
749
+ div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out");
750
+}
751
+
752
+static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
753
+ NPCM7xxCLKState *clk, const PLLInitInfo *init_info)
754
+{
755
+ pll->name = init_info->name;
756
+ pll->clk = clk;
757
+ pll->reg = init_info->reg;
758
+ if (init_info->public_name != NULL) {
759
+ qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk),
760
+ init_info->public_name);
761
+ }
762
+}
763
+
764
+static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
765
+ NPCM7xxCLKState *clk, const SELInitInfo *init_info)
766
+{
767
+ int input_size = init_info->input_size;
768
+
769
+ sel->name = init_info->name;
770
+ sel->clk = clk;
771
+ sel->input_size = init_info->input_size;
772
+ g_assert(input_size <= NPCM7XX_CLK_SEL_MAX_INPUT);
773
+ sel->offset = init_info->offset;
774
+ sel->len = init_info->len;
775
+ if (init_info->public_name != NULL) {
776
+ qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk),
777
+ init_info->public_name);
778
+ }
779
+}
780
+
781
+static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
782
+ NPCM7xxCLKState *clk, const DividerInitInfo *init_info)
783
+{
784
+ div->name = init_info->name;
785
+ div->clk = clk;
786
+
787
+ div->divide = init_info->divide;
788
+ if (div->divide == divide_by_constant) {
789
+ div->divisor = init_info->divisor;
790
+ } else {
791
+ div->reg = init_info->reg;
792
+ div->offset = init_info->offset;
793
+ div->len = init_info->len;
794
+ }
795
+ if (init_info->public_name != NULL) {
796
+ qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk),
797
+ init_info->public_name);
798
+ }
799
+}
800
+
801
+static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
802
+ int index)
803
+{
804
+ switch (type) {
805
+ case CLKSRC_REF:
806
+ return clk->clkref;
807
+ case CLKSRC_PLL:
808
+ return clk->plls[index].clock_out;
809
+ case CLKSRC_SEL:
810
+ return clk->sels[index].clock_out;
811
+ case CLKSRC_DIV:
812
+ return clk->dividers[index].clock_out;
813
+ default:
814
+ g_assert_not_reached();
815
+ }
816
+}
817
+
818
+static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
819
+{
820
+ int i, j;
821
+ Clock *src;
822
+
823
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
824
+ src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type,
825
+ pll_init_info_list[i].src_index);
826
+ clock_set_source(clk->plls[i].clock_in, src);
827
+ }
828
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
829
+ for (j = 0; j < sel_init_info_list[i].input_size; ++j) {
830
+ src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j],
831
+ sel_init_info_list[i].src_index[j]);
832
+ clock_set_source(clk->sels[i].clock_in[j], src);
833
+ }
834
+ }
835
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
836
+ src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type,
837
+ divider_init_info_list[i].src_index);
838
+ clock_set_source(clk->dividers[i].clock_in, src);
839
+ }
840
+}
841
+
842
static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
24
{
843
{
25
ARMCPU *cpu = env_archcpu(env);
844
uint32_t reg = offset / sizeof(uint32_t);
26
int n;
845
@@ -XXX,XX +XXX,XX @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
27
bool is_user = regime_is_user(env, mmu_idx);
846
*
28
847
* The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000.
29
- *phys_ptr = address;
30
- *page_size = TARGET_PAGE_SIZE;
31
- *prot = 0;
32
+ result->phys = address;
33
+ result->page_size = TARGET_PAGE_SIZE;
34
+ result->prot = 0;
35
36
if (regime_translation_disabled(env, mmu_idx) ||
37
m_is_ppb_region(env, address)) {
38
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
39
* which always does a direct read using address_space_ldl(), rather
40
* than going via this function, so we don't need to check that here.
41
*/
848
*/
42
- get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
849
- value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ;
43
+ get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
850
+ value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ;
44
} else { /* MPU enabled */
851
break;
45
for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
852
46
/* region search */
853
default:
47
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
854
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
48
if (ranges_overlap(base, rmask,
855
value |= (value & PLLCON_LOKS);
49
address & TARGET_PAGE_MASK,
50
TARGET_PAGE_SIZE)) {
51
- *page_size = 1;
52
+ result->page_size = 1;
53
}
54
continue;
55
}
56
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
57
continue;
58
}
59
if (rsize < TARGET_PAGE_BITS) {
60
- *page_size = 1 << rsize;
61
+ result->page_size = 1 << rsize;
62
}
63
break;
64
}
65
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
66
fi->type = ARMFault_Background;
67
return true;
68
}
69
- get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
70
+ get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
71
} else { /* a MPU hit! */
72
uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
73
uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1);
74
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
75
case 5:
76
break; /* no access */
77
case 3:
78
- *prot |= PAGE_WRITE;
79
+ result->prot |= PAGE_WRITE;
80
/* fall through */
81
case 2:
82
case 6:
83
- *prot |= PAGE_READ | PAGE_EXEC;
84
+ result->prot |= PAGE_READ | PAGE_EXEC;
85
break;
86
case 7:
87
/* for v7M, same as 6; for R profile a reserved value */
88
if (arm_feature(env, ARM_FEATURE_M)) {
89
- *prot |= PAGE_READ | PAGE_EXEC;
90
+ result->prot |= PAGE_READ | PAGE_EXEC;
91
break;
92
}
93
/* fall through */
94
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
95
case 1:
96
case 2:
97
case 3:
98
- *prot |= PAGE_WRITE;
99
+ result->prot |= PAGE_WRITE;
100
/* fall through */
101
case 5:
102
case 6:
103
- *prot |= PAGE_READ | PAGE_EXEC;
104
+ result->prot |= PAGE_READ | PAGE_EXEC;
105
break;
106
case 7:
107
/* for v7M, same as 6; for R profile a reserved value */
108
if (arm_feature(env, ARM_FEATURE_M)) {
109
- *prot |= PAGE_READ | PAGE_EXEC;
110
+ result->prot |= PAGE_READ | PAGE_EXEC;
111
break;
112
}
113
/* fall through */
114
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
115
116
/* execute never */
117
if (xn) {
118
- *prot &= ~PAGE_EXEC;
119
+ result->prot &= ~PAGE_EXEC;
120
}
856
}
121
}
857
}
858
+ /* Only update PLL when it is locked. */
859
+ if (value & PLLCON_LOKI) {
860
+ npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]);
861
+ }
862
+ break;
863
+
864
+ case NPCM7XX_CLK_CLKSEL:
865
+ npcm7xx_clk_update_all_sels(s);
866
+ break;
867
+
868
+ case NPCM7XX_CLK_CLKDIV1:
869
+ case NPCM7XX_CLK_CLKDIV2:
870
+ case NPCM7XX_CLK_CLKDIV3:
871
+ npcm7xx_clk_update_all_dividers(s);
872
break;
873
874
case NPCM7XX_CLK_CNTR25M:
875
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
876
case RESET_TYPE_COLD:
877
memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
878
s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
879
+ npcm7xx_clk_update_all_clocks(s);
880
return;
122
}
881
}
123
882
124
fi->type = ARMFault_Permission;
883
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
125
fi->level = 1;
884
__func__, type);
126
- return !(*prot & (1 << access_type));
127
+ return !(result->prot & (1 << access_type));
128
}
885
}
129
886
130
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
887
+static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
131
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
888
+{
132
} else if (arm_feature(env, ARM_FEATURE_V7)) {
889
+ int i;
133
/* PMSAv7 */
890
+
134
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
891
+ s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL);
135
- &result->phys, &result->prot,
892
+
136
- &result->page_size, fi);
893
+ /* First pass: init all converter modules */
137
+ result, fi);
894
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) != NPCM7XX_CLOCK_NR_PLLS);
138
} else {
895
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) != NPCM7XX_CLOCK_NR_SELS);
139
/* Pre-v7 MPU */
896
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list)
140
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
897
+ != NPCM7XX_CLOCK_NR_DIVIDERS);
898
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
899
+ object_initialize_child(OBJECT(s), pll_init_info_list[i].name,
900
+ &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL);
901
+ npcm7xx_init_clock_pll(&s->plls[i], s,
902
+ &pll_init_info_list[i]);
903
+ }
904
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
905
+ object_initialize_child(OBJECT(s), sel_init_info_list[i].name,
906
+ &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL);
907
+ npcm7xx_init_clock_sel(&s->sels[i], s,
908
+ &sel_init_info_list[i]);
909
+ }
910
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
911
+ object_initialize_child(OBJECT(s), divider_init_info_list[i].name,
912
+ &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER);
913
+ npcm7xx_init_clock_divider(&s->dividers[i], s,
914
+ &divider_init_info_list[i]);
915
+ }
916
+
917
+ /* Second pass: connect converter modules */
918
+ npcm7xx_connect_clocks(s);
919
+
920
+ clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
921
+}
922
+
923
static void npcm7xx_clk_init(Object *obj)
924
{
925
NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
926
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
927
memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
928
TYPE_NPCM7XX_CLK, 4 * KiB);
929
sysbus_init_mmio(&s->parent, &s->iomem);
930
- qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
931
- NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
932
}
933
934
-static const VMStateDescription vmstate_npcm7xx_clk = {
935
- .name = "npcm7xx-clk",
936
+static int npcm7xx_clk_post_load(void *opaque, int version_id)
937
+{
938
+ if (version_id >= 1) {
939
+ NPCM7xxCLKState *clk = opaque;
940
+
941
+ npcm7xx_clk_update_all_clocks(clk);
942
+ }
943
+
944
+ return 0;
945
+}
946
+
947
+static void npcm7xx_clk_realize(DeviceState *dev, Error **errp)
948
+{
949
+ int i;
950
+ NPCM7xxCLKState *s = NPCM7XX_CLK(dev);
951
+
952
+ qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
953
+ NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
954
+ npcm7xx_clk_init_clock_hierarchy(s);
955
+
956
+ /* Realize child devices */
957
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
958
+ if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) {
959
+ return;
960
+ }
961
+ }
962
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
963
+ if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) {
964
+ return;
965
+ }
966
+ }
967
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
968
+ if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) {
969
+ return;
970
+ }
971
+ }
972
+}
973
+
974
+static const VMStateDescription vmstate_npcm7xx_clk_pll = {
975
+ .name = "npcm7xx-clock-pll",
976
.version_id = 0,
977
.minimum_version_id = 0,
978
- .fields = (VMStateField[]) {
979
- VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
980
- VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
981
+ .fields = (VMStateField[]) {
982
+ VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState),
983
VMSTATE_END_OF_LIST(),
984
},
985
};
986
987
+static const VMStateDescription vmstate_npcm7xx_clk_sel = {
988
+ .name = "npcm7xx-clock-sel",
989
+ .version_id = 0,
990
+ .minimum_version_id = 0,
991
+ .fields = (VMStateField[]) {
992
+ VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState,
993
+ NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock),
994
+ VMSTATE_END_OF_LIST(),
995
+ },
996
+};
997
+
998
+static const VMStateDescription vmstate_npcm7xx_clk_divider = {
999
+ .name = "npcm7xx-clock-divider",
1000
+ .version_id = 0,
1001
+ .minimum_version_id = 0,
1002
+ .fields = (VMStateField[]) {
1003
+ VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState),
1004
+ VMSTATE_END_OF_LIST(),
1005
+ },
1006
+};
1007
+
1008
+static const VMStateDescription vmstate_npcm7xx_clk = {
1009
+ .name = "npcm7xx-clk",
1010
+ .version_id = 1,
1011
+ .minimum_version_id = 1,
1012
+ .post_load = npcm7xx_clk_post_load,
1013
+ .fields = (VMStateField[]) {
1014
+ VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
1015
+ VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
1016
+ VMSTATE_CLOCK(clkref, NPCM7xxCLKState),
1017
+ VMSTATE_END_OF_LIST(),
1018
+ },
1019
+};
1020
+
1021
+static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data)
1022
+{
1023
+ DeviceClass *dc = DEVICE_CLASS(klass);
1024
+
1025
+ dc->desc = "NPCM7xx Clock PLL Module";
1026
+ dc->vmsd = &vmstate_npcm7xx_clk_pll;
1027
+}
1028
+
1029
+static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data)
1030
+{
1031
+ DeviceClass *dc = DEVICE_CLASS(klass);
1032
+
1033
+ dc->desc = "NPCM7xx Clock SEL Module";
1034
+ dc->vmsd = &vmstate_npcm7xx_clk_sel;
1035
+}
1036
+
1037
+static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
1038
+{
1039
+ DeviceClass *dc = DEVICE_CLASS(klass);
1040
+
1041
+ dc->desc = "NPCM7xx Clock Divider Module";
1042
+ dc->vmsd = &vmstate_npcm7xx_clk_divider;
1043
+}
1044
+
1045
static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
1046
{
1047
ResettableClass *rc = RESETTABLE_CLASS(klass);
1048
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
1049
1050
dc->desc = "NPCM7xx Clock Control Registers";
1051
dc->vmsd = &vmstate_npcm7xx_clk;
1052
+ dc->realize = npcm7xx_clk_realize;
1053
rc->phases.enter = npcm7xx_clk_enter_reset;
1054
}
1055
1056
+static const TypeInfo npcm7xx_clk_pll_info = {
1057
+ .name = TYPE_NPCM7XX_CLOCK_PLL,
1058
+ .parent = TYPE_DEVICE,
1059
+ .instance_size = sizeof(NPCM7xxClockPLLState),
1060
+ .instance_init = npcm7xx_clk_pll_init,
1061
+ .class_init = npcm7xx_clk_pll_class_init,
1062
+};
1063
+
1064
+static const TypeInfo npcm7xx_clk_sel_info = {
1065
+ .name = TYPE_NPCM7XX_CLOCK_SEL,
1066
+ .parent = TYPE_DEVICE,
1067
+ .instance_size = sizeof(NPCM7xxClockSELState),
1068
+ .instance_init = npcm7xx_clk_sel_init,
1069
+ .class_init = npcm7xx_clk_sel_class_init,
1070
+};
1071
+
1072
+static const TypeInfo npcm7xx_clk_divider_info = {
1073
+ .name = TYPE_NPCM7XX_CLOCK_DIVIDER,
1074
+ .parent = TYPE_DEVICE,
1075
+ .instance_size = sizeof(NPCM7xxClockDividerState),
1076
+ .instance_init = npcm7xx_clk_divider_init,
1077
+ .class_init = npcm7xx_clk_divider_class_init,
1078
+};
1079
+
1080
static const TypeInfo npcm7xx_clk_info = {
1081
.name = TYPE_NPCM7XX_CLK,
1082
.parent = TYPE_SYS_BUS_DEVICE,
1083
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_clk_info = {
1084
1085
static void npcm7xx_clk_register_type(void)
1086
{
1087
+ type_register_static(&npcm7xx_clk_pll_info);
1088
+ type_register_static(&npcm7xx_clk_sel_info);
1089
+ type_register_static(&npcm7xx_clk_divider_info);
1090
type_register_static(&npcm7xx_clk_info);
1091
}
1092
type_init(npcm7xx_clk_register_type);
141
--
1093
--
142
2.25.1
1094
2.20.1
143
1095
144
1096
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
This patch makes NPCM7XX Timer to use a the timer clock generated by the
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
CLK module instead of the magic number TIMER_REF_HZ.
5
Message-id: 20220822152741.1617527-4-richard.henderson@linaro.org
5
6
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
7
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
8
Signed-off-by: Hao Wu <wuhaotsh@google.com>
9
Message-id: 20210108190945.949196-3-wuhaotsh@google.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
12
---
9
target/arm/ptw.c | 69 ++++++++++++++++++------------------------------
13
include/hw/misc/npcm7xx_clk.h | 6 -----
10
1 file changed, 26 insertions(+), 43 deletions(-)
14
include/hw/timer/npcm7xx_timer.h | 1 +
15
hw/arm/npcm7xx.c | 5 ++++
16
hw/timer/npcm7xx_timer.c | 39 +++++++++++++++-----------------
17
4 files changed, 24 insertions(+), 27 deletions(-)
11
18
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
19
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
13
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/ptw.c
21
--- a/include/hw/misc/npcm7xx_clk.h
15
+++ b/target/arm/ptw.c
22
+++ b/include/hw/misc/npcm7xx_clk.h
16
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@
17
24
#include "hw/clock.h"
18
static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
25
#include "hw/sysbus.h"
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
26
20
- bool s1_is_el0, hwaddr *phys_ptr,
27
-/*
21
- MemTxAttrs *txattrs, int *prot,
28
- * The reference clock frequency for the timer modules, and the SECCNT and
22
- target_ulong *page_size_ptr,
29
- * CNTR25M registers in this module, is always 25 MHz.
23
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
30
- */
24
+ bool s1_is_el0, GetPhysAddrResult *result,
31
-#define NPCM7XX_TIMER_REF_HZ (25000000)
25
+ ARMMMUFaultInfo *fi)
32
-
26
__attribute__((nonnull));
33
/*
27
34
* Number of registers in our device state structure. Don't change this without
28
/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
35
* incrementing the version_id in the vmstate.
29
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
36
diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/timer/npcm7xx_timer.h
39
+++ b/include/hw/timer/npcm7xx_timer.h
40
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState {
41
42
uint32_t tisr;
43
44
+ Clock *clock;
45
NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
46
NPCM7xxWatchdogTimer watchdog_timer;
47
};
48
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/arm/npcm7xx.c
51
+++ b/hw/arm/npcm7xx.c
52
@@ -XXX,XX +XXX,XX @@
53
#include "hw/char/serial.h"
54
#include "hw/loader.h"
55
#include "hw/misc/unimp.h"
56
+#include "hw/qdev-clock.h"
57
#include "hw/qdev-properties.h"
58
#include "qapi/error.h"
59
#include "qemu/units.h"
60
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
61
int first_irq;
62
int j;
63
64
+ /* Connect the timer clock. */
65
+ qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
66
+ DEVICE(&s->clk), "timer-clock"));
67
+
68
sysbus_realize(sbd, &error_abort);
69
sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
70
71
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/hw/timer/npcm7xx_timer.c
74
+++ b/hw/timer/npcm7xx_timer.c
75
@@ -XXX,XX +XXX,XX @@
76
#include "qemu/osdep.h"
77
78
#include "hw/irq.h"
79
+#include "hw/qdev-clock.h"
80
#include "hw/qdev-properties.h"
81
-#include "hw/misc/npcm7xx_clk.h"
82
#include "hw/timer/npcm7xx_timer.h"
83
#include "migration/vmstate.h"
84
#include "qemu/bitops.h"
85
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
86
/* Convert a timer cycle count to a time interval in nanoseconds. */
87
static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
30
{
88
{
31
if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
89
- int64_t ns = count;
32
!regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
90
+ int64_t ticks = count;
33
- target_ulong s2size;
91
34
- hwaddr s2pa;
92
- ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
35
- int s2prot;
93
- ns *= npcm7xx_tcsr_prescaler(t->tcsr);
36
- int ret;
94
+ ticks *= npcm7xx_tcsr_prescaler(t->tcsr);
37
ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S
95
38
: ARMMMUIdx_Stage2;
96
- return ns;
39
- ARMCacheAttrs cacheattrs = {};
97
+ return clock_ticks_to_ns(t->ctrl->clock, ticks);
40
- MemTxAttrs txattrs = {};
41
+ GetPhysAddrResult s2 = {};
42
+ int ret;
43
44
ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false,
45
- &s2pa, &txattrs, &s2prot, &s2size, fi,
46
- &cacheattrs);
47
+ &s2, fi);
48
if (ret) {
49
assert(fi->type != ARMFault_None);
50
fi->s2addr = addr;
51
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
52
return ~0;
53
}
54
if ((arm_hcr_el2_eff(env) & HCR_PTW) &&
55
- ptw_attrs_are_device(env, cacheattrs)) {
56
+ ptw_attrs_are_device(env, s2.cacheattrs)) {
57
/*
58
* PTW set and S1 walk touched S2 Device memory:
59
* generate Permission fault.
60
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
61
assert(!*is_secure);
62
}
63
64
- addr = s2pa;
65
+ addr = s2.phys;
66
}
67
return addr;
68
}
98
}
69
@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
99
70
* table walk), must be true if this is stage 2 of a stage 1+2
100
/* Convert a time interval in nanoseconds to a timer cycle count. */
71
* walk for an EL0 access. If @mmu_idx is anything else,
101
static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
72
* @s1_is_el0 is ignored.
73
- * @phys_ptr: set to the physical address corresponding to the virtual address
74
- * @attrs: set to the memory transaction attributes to use
75
- * @prot: set to the permissions for the page containing phys_ptr
76
- * @page_size_ptr: set to the size of the page containing phys_ptr
77
+ * @result: set on translation success,
78
* @fi: set to fault info if the translation fails
79
- * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
80
*/
81
static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
82
MMUAccessType access_type, ARMMMUIdx mmu_idx,
83
- bool s1_is_el0, hwaddr *phys_ptr,
84
- MemTxAttrs *txattrs, int *prot,
85
- target_ulong *page_size_ptr,
86
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
87
+ bool s1_is_el0, GetPhysAddrResult *result,
88
+ ARMMMUFaultInfo *fi)
89
{
102
{
90
ARMCPU *cpu = env_archcpu(env);
103
- int64_t count;
91
/* Read an LPAE long-descriptor translation table. */
104
-
92
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
105
- count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
93
if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
106
- count /= npcm7xx_tcsr_prescaler(t->tcsr);
94
ns = mmu_idx == ARMMMUIdx_Stage2;
107
-
95
xn = extract32(attrs, 11, 2);
108
- return count;
96
- *prot = get_S2prot(env, ap, xn, s1_is_el0);
109
+ return ns / clock_ticks_to_ns(t->ctrl->clock,
97
+ result->prot = get_S2prot(env, ap, xn, s1_is_el0);
110
+ npcm7xx_tcsr_prescaler(t->tcsr));
98
} else {
111
}
99
ns = extract32(attrs, 3, 1);
112
100
xn = extract32(attrs, 12, 1);
113
static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
101
pxn = extract32(attrs, 11, 1);
114
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
102
- *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
115
static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
103
+ result->prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
116
int64_t cycles)
104
}
117
{
105
118
- uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
106
fault_type = ARMFault_Permission;
119
- int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
107
- if (!(*prot & (1 << access_type))) {
120
+ int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t);
108
+ if (!(result->prot & (1 << access_type))) {
121
+ int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks);
109
goto do_fault;
110
}
111
112
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
113
* the CPU doesn't support TZ or this is a non-secure translation
114
* regime, because the attribute will already be non-secure.
115
*/
116
- txattrs->secure = false;
117
+ result->attrs.secure = false;
118
}
119
/* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
120
if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
121
- arm_tlb_bti_gp(txattrs) = true;
122
+ arm_tlb_bti_gp(&result->attrs) = true;
123
}
124
125
if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
126
- cacheattrs->is_s2_format = true;
127
- cacheattrs->attrs = extract32(attrs, 0, 4);
128
+ result->cacheattrs.is_s2_format = true;
129
+ result->cacheattrs.attrs = extract32(attrs, 0, 4);
130
} else {
131
/* Index into MAIR registers for cache attributes */
132
uint8_t attrindx = extract32(attrs, 0, 3);
133
uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
134
assert(attrindx <= 7);
135
- cacheattrs->is_s2_format = false;
136
- cacheattrs->attrs = extract64(mair, attrindx * 8, 8);
137
+ result->cacheattrs.is_s2_format = false;
138
+ result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
139
}
140
122
141
/*
123
/*
142
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
124
* The reset function always clears the current timer. The caller of the
143
* that case comes from TCR_ELx, which we extracted earlier.
125
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
144
*/
126
*/
145
if (param.ds) {
127
npcm7xx_timer_clear(&t->base_timer);
146
- cacheattrs->shareability = param.sh;
128
147
+ result->cacheattrs.shareability = param.sh;
129
- ns *= prescaler;
148
} else {
130
t->base_timer.remaining_ns = ns;
149
- cacheattrs->shareability = extract32(attrs, 6, 2);
131
}
150
+ result->cacheattrs.shareability = extract32(attrs, 6, 2);
132
151
}
133
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj)
152
134
qemu_irq_lower(s->watchdog_timer.irq);
153
- *phys_ptr = descaddr;
135
}
154
- *page_size_ptr = page_size;
136
155
+ result->phys = descaddr;
137
-static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
156
+ result->page_size = page_size;
138
+static void npcm7xx_timer_init(Object *obj)
157
return false;
139
{
158
140
- NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
159
do_fault:
141
- SysBusDevice *sbd = &s->parent;
160
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
142
+ NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
161
cacheattrs1 = result->cacheattrs;
143
+ DeviceState *dev = DEVICE(obj);
162
memset(result, 0, sizeof(*result));
144
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
163
145
int i;
164
- ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, is_el0,
146
NPCM7xxWatchdogTimer *w;
165
- &result->phys, &result->attrs,
147
166
- &result->prot, &result->page_size,
148
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
167
- fi, &result->cacheattrs);
149
npcm7xx_watchdog_timer_expired, w);
168
+ ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx,
150
sysbus_init_irq(sbd, &w->irq);
169
+ is_el0, result, fi);
151
170
fi->s2addr = ipa;
152
- memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
171
153
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s,
172
/* Combine the S1 and S2 perms. */
154
TYPE_NPCM7XX_TIMER, 4 * KiB);
173
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
155
sysbus_init_mmio(sbd, &s->iomem);
174
156
qdev_init_gpio_out_named(dev, &w->reset_signal,
175
if (regime_using_lpae_format(env, mmu_idx)) {
157
NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
176
return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
158
+ s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL);
177
- &result->phys, &result->attrs,
159
}
178
- &result->prot, &result->page_size,
160
179
- fi, &result->cacheattrs);
161
static const VMStateDescription vmstate_npcm7xx_base_timer = {
180
+ result, fi);
162
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
181
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
163
182
return get_phys_addr_v6(env, address, access_type, mmu_idx,
164
static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
183
&result->phys, &result->attrs,
165
.name = "npcm7xx-timer-ctrl",
166
- .version_id = 1,
167
- .minimum_version_id = 1,
168
+ .version_id = 2,
169
+ .minimum_version_id = 2,
170
.fields = (VMStateField[]) {
171
VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
172
+ VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),
173
VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
174
NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
175
NPCM7xxTimer),
176
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
177
QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
178
179
dc->desc = "NPCM7xx Timer Controller";
180
- dc->realize = npcm7xx_timer_realize;
181
dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
182
rc->phases.enter = npcm7xx_timer_enter_reset;
183
rc->phases.hold = npcm7xx_timer_hold_reset;
184
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = {
185
.parent = TYPE_SYS_BUS_DEVICE,
186
.instance_size = sizeof(NPCM7xxTimerCtrlState),
187
.class_init = npcm7xx_timer_class_init,
188
+ .instance_init = npcm7xx_timer_init,
189
};
190
191
static void npcm7xx_timer_register_type(void)
184
--
192
--
185
2.25.1
193
2.20.1
186
194
187
195
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
Remove the use of regime_is_secure from v8m_security_lookup,
3
The ADC is part of NPCM7XX Module. Its behavior is controled by the
4
passing the new parameter to the lookup instead.
4
ADC_CON register. It converts one of the eight analog inputs into a
5
digital input and stores it in the ADC_DATA register when enabled.
5
6
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Users can alter input value by using qom-set QMP command.
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
8
Message-id: 20220822152741.1617527-12-richard.henderson@linaro.org
9
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
10
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
11
Signed-off-by: Hao Wu <wuhaotsh@google.com>
12
Message-id: 20210108190945.949196-4-wuhaotsh@google.com
13
[PMM: Added missing hw/adc/trace.h file]
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
16
---
12
target/arm/internals.h | 2 +-
17
docs/system/arm/nuvoton.rst | 2 +-
13
target/arm/m_helper.c | 9 ++++++---
18
meson.build | 1 +
14
target/arm/ptw.c | 9 +++++----
19
hw/adc/trace.h | 1 +
15
3 files changed, 12 insertions(+), 8 deletions(-)
20
include/hw/adc/npcm7xx_adc.h | 69 ++++++
21
include/hw/arm/npcm7xx.h | 2 +
22
hw/adc/npcm7xx_adc.c | 301 ++++++++++++++++++++++++++
23
hw/arm/npcm7xx.c | 24 ++-
24
tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++
25
hw/adc/meson.build | 1 +
26
hw/adc/trace-events | 5 +
27
tests/qtest/meson.build | 3 +-
28
11 files changed, 783 insertions(+), 3 deletions(-)
29
create mode 100644 hw/adc/trace.h
30
create mode 100644 include/hw/adc/npcm7xx_adc.h
31
create mode 100644 hw/adc/npcm7xx_adc.c
32
create mode 100644 tests/qtest/npcm7xx_adc-test.c
33
create mode 100644 hw/adc/trace-events
16
34
17
diff --git a/target/arm/internals.h b/target/arm/internals.h
35
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
18
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/internals.h
37
--- a/docs/system/arm/nuvoton.rst
20
+++ b/target/arm/internals.h
38
+++ b/docs/system/arm/nuvoton.rst
21
@@ -XXX,XX +XXX,XX @@ typedef struct V8M_SAttributes {
39
@@ -XXX,XX +XXX,XX @@ Supported devices
22
40
* Random Number Generator (RNG)
23
void v8m_security_lookup(CPUARMState *env, uint32_t address,
41
* USB host (USBH)
24
MMUAccessType access_type, ARMMMUIdx mmu_idx,
42
* GPIO controller
25
- V8M_SAttributes *sattrs);
43
+ * Analog to Digital Converter (ADC)
26
+ bool secure, V8M_SAttributes *sattrs);
44
27
45
Missing devices
28
/* Cacheability and shareability attributes for a memory access */
46
---------------
29
typedef struct ARMCacheAttrs {
47
@@ -XXX,XX +XXX,XX @@ Missing devices
30
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
48
* USB device (USBD)
49
* SMBus controller (SMBF)
50
* Peripheral SPI controller (PSPI)
51
- * Analog to Digital Converter (ADC)
52
* SD/MMC host
53
* PECI interface
54
* Pulse Width Modulation (PWM)
55
diff --git a/meson.build b/meson.build
31
index XXXXXXX..XXXXXXX 100644
56
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/m_helper.c
57
--- a/meson.build
33
+++ b/target/arm/m_helper.c
58
+++ b/meson.build
34
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
59
@@ -XXX,XX +XXX,XX @@ if have_system
35
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
60
'chardev',
36
V8M_SAttributes sattrs = {};
61
'hw/9pfs',
37
62
'hw/acpi',
38
- v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs);
63
+ 'hw/adc',
39
+ v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
64
'hw/alpha',
40
+ targets_secure, &sattrs);
65
'hw/arm',
41
if (sattrs.ns) {
66
'hw/audio',
42
attrs.secure = false;
67
diff --git a/hw/adc/trace.h b/hw/adc/trace.h
43
} else if (!targets_secure) {
68
new file mode 100644
44
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
69
index XXXXXXX..XXXXXXX
45
ARMMMUFaultInfo fi = {};
70
--- /dev/null
46
MemTxResult txres;
71
+++ b/hw/adc/trace.h
47
72
@@ -0,0 +1 @@
48
- v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
73
+#include "trace/trace-hw_adc.h"
49
+ v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx,
74
diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h
50
+ regime_is_secure(env, mmu_idx), &sattrs);
75
new file mode 100644
51
if (!sattrs.nsc || sattrs.ns) {
76
index XXXXXXX..XXXXXXX
52
/*
77
--- /dev/null
53
* This must be the second half of the insn, and it straddles a
78
+++ b/include/hw/adc/npcm7xx_adc.h
54
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
79
@@ -XXX,XX +XXX,XX @@
55
}
80
+/*
56
81
+ * Nuvoton NPCM7xx ADC Module
57
if (env->v7m.secure) {
82
+ *
58
- v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs);
83
+ * Copyright 2020 Google LLC
59
+ v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
84
+ *
60
+ targetsec, &sattrs);
85
+ * This program is free software; you can redistribute it and/or modify it
61
nsr = sattrs.ns && r;
86
+ * under the terms of the GNU General Public License as published by the
62
nsrw = sattrs.ns && rw;
87
+ * Free Software Foundation; either version 2 of the License, or
63
} else {
88
+ * (at your option) any later version.
64
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
89
+ *
90
+ * This program is distributed in the hope that it will be useful, but WITHOUT
91
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
92
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
93
+ * for more details.
94
+ */
95
+#ifndef NPCM7XX_ADC_H
96
+#define NPCM7XX_ADC_H
97
+
98
+#include "hw/clock.h"
99
+#include "hw/irq.h"
100
+#include "hw/sysbus.h"
101
+#include "qemu/timer.h"
102
+
103
+#define NPCM7XX_ADC_NUM_INPUTS 8
104
+/**
105
+ * This value should not be changed unless write_adc_calibration function in
106
+ * hw/arm/npcm7xx.c is also changed.
107
+ */
108
+#define NPCM7XX_ADC_NUM_CALIB 2
109
+
110
+/**
111
+ * struct NPCM7xxADCState - Analog to Digital Converter Module device state.
112
+ * @parent: System bus device.
113
+ * @iomem: Memory region through which registers are accessed.
114
+ * @conv_timer: The timer counts down remaining cycles for the conversion.
115
+ * @irq: GIC interrupt line to fire on expiration (if enabled).
116
+ * @con: The Control Register.
117
+ * @data: The Data Buffer.
118
+ * @clock: The ADC Clock.
119
+ * @adci: The input voltage in units of uV. 1uv = 1e-6V.
120
+ * @vref: The external reference voltage.
121
+ * @iref: The internal reference voltage, initialized at launch time.
122
+ * @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
123
+ */
124
+typedef struct {
125
+ SysBusDevice parent;
126
+
127
+ MemoryRegion iomem;
128
+
129
+ QEMUTimer conv_timer;
130
+
131
+ qemu_irq irq;
132
+ uint32_t con;
133
+ uint32_t data;
134
+ Clock *clock;
135
+
136
+ /* Voltages are in unit of uV. 1V = 1000000uV. */
137
+ uint32_t adci[NPCM7XX_ADC_NUM_INPUTS];
138
+ uint32_t vref;
139
+ uint32_t iref;
140
+
141
+ uint16_t calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
142
+} NPCM7xxADCState;
143
+
144
+#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
145
+#define NPCM7XX_ADC(obj) \
146
+ OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
147
+
148
+#endif /* NPCM7XX_ADC_H */
149
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
65
index XXXXXXX..XXXXXXX 100644
150
index XXXXXXX..XXXXXXX 100644
66
--- a/target/arm/ptw.c
151
--- a/include/hw/arm/npcm7xx.h
67
+++ b/target/arm/ptw.c
152
+++ b/include/hw/arm/npcm7xx.h
68
@@ -XXX,XX +XXX,XX @@ static bool v8m_is_sau_exempt(CPUARMState *env,
153
@@ -XXX,XX +XXX,XX @@
154
#define NPCM7XX_H
155
156
#include "hw/boards.h"
157
+#include "hw/adc/npcm7xx_adc.h"
158
#include "hw/cpu/a9mpcore.h"
159
#include "hw/gpio/npcm7xx_gpio.h"
160
#include "hw/mem/npcm7xx_mc.h"
161
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
162
NPCM7xxGCRState gcr;
163
NPCM7xxCLKState clk;
164
NPCM7xxTimerCtrlState tim[3];
165
+ NPCM7xxADCState adc;
166
NPCM7xxOTPState key_storage;
167
NPCM7xxOTPState fuse_array;
168
NPCM7xxMCState mc;
169
diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
170
new file mode 100644
171
index XXXXXXX..XXXXXXX
172
--- /dev/null
173
+++ b/hw/adc/npcm7xx_adc.c
174
@@ -XXX,XX +XXX,XX @@
175
+/*
176
+ * Nuvoton NPCM7xx ADC Module
177
+ *
178
+ * Copyright 2020 Google LLC
179
+ *
180
+ * This program is free software; you can redistribute it and/or modify it
181
+ * under the terms of the GNU General Public License as published by the
182
+ * Free Software Foundation; either version 2 of the License, or
183
+ * (at your option) any later version.
184
+ *
185
+ * This program is distributed in the hope that it will be useful, but WITHOUT
186
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
187
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
188
+ * for more details.
189
+ */
190
+
191
+#include "qemu/osdep.h"
192
+#include "hw/adc/npcm7xx_adc.h"
193
+#include "hw/qdev-clock.h"
194
+#include "hw/qdev-properties.h"
195
+#include "hw/registerfields.h"
196
+#include "migration/vmstate.h"
197
+#include "qemu/log.h"
198
+#include "qemu/module.h"
199
+#include "qemu/timer.h"
200
+#include "qemu/units.h"
201
+#include "trace.h"
202
+
203
+REG32(NPCM7XX_ADC_CON, 0x0)
204
+REG32(NPCM7XX_ADC_DATA, 0x4)
205
+
206
+/* Register field definitions. */
207
+#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
208
+#define NPCM7XX_ADC_CON_INT_EN BIT(21)
209
+#define NPCM7XX_ADC_CON_REFSEL BIT(19)
210
+#define NPCM7XX_ADC_CON_INT BIT(18)
211
+#define NPCM7XX_ADC_CON_EN BIT(17)
212
+#define NPCM7XX_ADC_CON_RST BIT(16)
213
+#define NPCM7XX_ADC_CON_CONV BIT(14)
214
+#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
215
+
216
+#define NPCM7XX_ADC_MAX_RESULT 1023
217
+#define NPCM7XX_ADC_DEFAULT_IREF 2000000
218
+#define NPCM7XX_ADC_CONV_CYCLES 20
219
+#define NPCM7XX_ADC_RESET_CYCLES 10
220
+#define NPCM7XX_ADC_R0_INPUT 500000
221
+#define NPCM7XX_ADC_R1_INPUT 1500000
222
+
223
+static void npcm7xx_adc_reset(NPCM7xxADCState *s)
224
+{
225
+ timer_del(&s->conv_timer);
226
+ s->con = 0x000c0001;
227
+ s->data = 0x00000000;
228
+}
229
+
230
+static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
231
+{
232
+ uint32_t result;
233
+
234
+ result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;
235
+ if (result > NPCM7XX_ADC_MAX_RESULT) {
236
+ result = NPCM7XX_ADC_MAX_RESULT;
237
+ }
238
+
239
+ return result;
240
+}
241
+
242
+static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
243
+{
244
+ return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
245
+}
246
+
247
+static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
248
+ uint32_t cycles, uint32_t prescaler)
249
+{
250
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
251
+ int64_t ticks = cycles;
252
+ int64_t ns;
253
+
254
+ ticks *= prescaler;
255
+ ns = clock_ticks_to_ns(clk, ticks);
256
+ ns += now;
257
+ timer_mod(timer, ns);
258
+}
259
+
260
+static void npcm7xx_adc_start_convert(NPCM7xxADCState *s)
261
+{
262
+ uint32_t prescaler = npcm7xx_adc_prescaler(s);
263
+
264
+ npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES,
265
+ prescaler);
266
+}
267
+
268
+static void npcm7xx_adc_convert_done(void *opaque)
269
+{
270
+ NPCM7xxADCState *s = opaque;
271
+ uint32_t input = NPCM7XX_ADC_CON_MUX(s->con);
272
+ uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL)
273
+ ? s->iref : s->vref;
274
+
275
+ if (input >= NPCM7XX_ADC_NUM_INPUTS) {
276
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n",
277
+ __func__, input);
278
+ return;
279
+ }
280
+ s->data = npcm7xx_adc_convert(s->adci[input], ref);
281
+ if (s->con & NPCM7XX_ADC_CON_INT_EN) {
282
+ s->con |= NPCM7XX_ADC_CON_INT;
283
+ qemu_irq_raise(s->irq);
284
+ }
285
+ s->con &= ~NPCM7XX_ADC_CON_CONV;
286
+}
287
+
288
+static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc)
289
+{
290
+ adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT,
291
+ adc->iref);
292
+ adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT,
293
+ adc->iref);
294
+}
295
+
296
+static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con)
297
+{
298
+ uint32_t old_con = s->con;
299
+
300
+ /* Write ADC_INT to 1 to clear it */
301
+ if (new_con & NPCM7XX_ADC_CON_INT) {
302
+ new_con &= ~NPCM7XX_ADC_CON_INT;
303
+ qemu_irq_lower(s->irq);
304
+ } else if (old_con & NPCM7XX_ADC_CON_INT) {
305
+ new_con |= NPCM7XX_ADC_CON_INT;
306
+ }
307
+
308
+ s->con = new_con;
309
+
310
+ if (s->con & NPCM7XX_ADC_CON_RST) {
311
+ npcm7xx_adc_reset(s);
312
+ return;
313
+ }
314
+
315
+ if ((s->con & NPCM7XX_ADC_CON_EN)) {
316
+ if (s->con & NPCM7XX_ADC_CON_CONV) {
317
+ if (!(old_con & NPCM7XX_ADC_CON_CONV)) {
318
+ npcm7xx_adc_start_convert(s);
319
+ }
320
+ } else {
321
+ timer_del(&s->conv_timer);
322
+ }
323
+ }
324
+}
325
+
326
+static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size)
327
+{
328
+ uint64_t value = 0;
329
+ NPCM7xxADCState *s = opaque;
330
+
331
+ switch (offset) {
332
+ case A_NPCM7XX_ADC_CON:
333
+ value = s->con;
334
+ break;
335
+
336
+ case A_NPCM7XX_ADC_DATA:
337
+ value = s->data;
338
+ break;
339
+
340
+ default:
341
+ qemu_log_mask(LOG_GUEST_ERROR,
342
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
343
+ __func__, offset);
344
+ break;
345
+ }
346
+
347
+ trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value);
348
+ return value;
349
+}
350
+
351
+static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v,
352
+ unsigned size)
353
+{
354
+ NPCM7xxADCState *s = opaque;
355
+
356
+ trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v);
357
+ switch (offset) {
358
+ case A_NPCM7XX_ADC_CON:
359
+ npcm7xx_adc_write_con(s, v);
360
+ break;
361
+
362
+ case A_NPCM7XX_ADC_DATA:
363
+ qemu_log_mask(LOG_GUEST_ERROR,
364
+ "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
365
+ __func__, offset);
366
+ break;
367
+
368
+ default:
369
+ qemu_log_mask(LOG_GUEST_ERROR,
370
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
371
+ __func__, offset);
372
+ break;
373
+ }
374
+
375
+}
376
+
377
+static const struct MemoryRegionOps npcm7xx_adc_ops = {
378
+ .read = npcm7xx_adc_read,
379
+ .write = npcm7xx_adc_write,
380
+ .endianness = DEVICE_LITTLE_ENDIAN,
381
+ .valid = {
382
+ .min_access_size = 4,
383
+ .max_access_size = 4,
384
+ .unaligned = false,
385
+ },
386
+};
387
+
388
+static void npcm7xx_adc_enter_reset(Object *obj, ResetType type)
389
+{
390
+ NPCM7xxADCState *s = NPCM7XX_ADC(obj);
391
+
392
+ npcm7xx_adc_reset(s);
393
+}
394
+
395
+static void npcm7xx_adc_hold_reset(Object *obj)
396
+{
397
+ NPCM7xxADCState *s = NPCM7XX_ADC(obj);
398
+
399
+ qemu_irq_lower(s->irq);
400
+}
401
+
402
+static void npcm7xx_adc_init(Object *obj)
403
+{
404
+ NPCM7xxADCState *s = NPCM7XX_ADC(obj);
405
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
406
+ int i;
407
+
408
+ sysbus_init_irq(sbd, &s->irq);
409
+
410
+ timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL,
411
+ npcm7xx_adc_convert_done, s);
412
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s,
413
+ TYPE_NPCM7XX_ADC, 4 * KiB);
414
+ sysbus_init_mmio(sbd, &s->iomem);
415
+ s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
416
+
417
+ for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) {
418
+ object_property_add_uint32_ptr(obj, "adci[*]",
419
+ &s->adci[i], OBJ_PROP_FLAG_WRITE);
420
+ }
421
+ object_property_add_uint32_ptr(obj, "vref",
422
+ &s->vref, OBJ_PROP_FLAG_WRITE);
423
+ npcm7xx_adc_calibrate(s);
424
+}
425
+
426
+static const VMStateDescription vmstate_npcm7xx_adc = {
427
+ .name = "npcm7xx-adc",
428
+ .version_id = 0,
429
+ .minimum_version_id = 0,
430
+ .fields = (VMStateField[]) {
431
+ VMSTATE_TIMER(conv_timer, NPCM7xxADCState),
432
+ VMSTATE_UINT32(con, NPCM7xxADCState),
433
+ VMSTATE_UINT32(data, NPCM7xxADCState),
434
+ VMSTATE_CLOCK(clock, NPCM7xxADCState),
435
+ VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS),
436
+ VMSTATE_UINT32(vref, NPCM7xxADCState),
437
+ VMSTATE_UINT32(iref, NPCM7xxADCState),
438
+ VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState,
439
+ NPCM7XX_ADC_NUM_CALIB),
440
+ VMSTATE_END_OF_LIST(),
441
+ },
442
+};
443
+
444
+static Property npcm7xx_timer_properties[] = {
445
+ DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF),
446
+ DEFINE_PROP_END_OF_LIST(),
447
+};
448
+
449
+static void npcm7xx_adc_class_init(ObjectClass *klass, void *data)
450
+{
451
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
452
+ DeviceClass *dc = DEVICE_CLASS(klass);
453
+
454
+ dc->desc = "NPCM7xx ADC Module";
455
+ dc->vmsd = &vmstate_npcm7xx_adc;
456
+ rc->phases.enter = npcm7xx_adc_enter_reset;
457
+ rc->phases.hold = npcm7xx_adc_hold_reset;
458
+
459
+ device_class_set_props(dc, npcm7xx_timer_properties);
460
+}
461
+
462
+static const TypeInfo npcm7xx_adc_info = {
463
+ .name = TYPE_NPCM7XX_ADC,
464
+ .parent = TYPE_SYS_BUS_DEVICE,
465
+ .instance_size = sizeof(NPCM7xxADCState),
466
+ .class_init = npcm7xx_adc_class_init,
467
+ .instance_init = npcm7xx_adc_init,
468
+};
469
+
470
+static void npcm7xx_adc_register_types(void)
471
+{
472
+ type_register_static(&npcm7xx_adc_info);
473
+}
474
+
475
+type_init(npcm7xx_adc_register_types);
476
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
477
index XXXXXXX..XXXXXXX 100644
478
--- a/hw/arm/npcm7xx.c
479
+++ b/hw/arm/npcm7xx.c
480
@@ -XXX,XX +XXX,XX @@
481
#define NPCM7XX_EHCI_BA (0xf0806000)
482
#define NPCM7XX_OHCI_BA (0xf0807000)
483
484
+/* ADC Module */
485
+#define NPCM7XX_ADC_BA (0xf000c000)
486
+
487
/* Internal AHB SRAM */
488
#define NPCM7XX_RAM3_BA (0xc0008000)
489
#define NPCM7XX_RAM3_SZ (4 * KiB)
490
@@ -XXX,XX +XXX,XX @@
491
#define NPCM7XX_ROM_BA (0xffff0000)
492
#define NPCM7XX_ROM_SZ (64 * KiB)
493
494
+
495
/* Clock configuration values to be fixed up when bypassing bootloader */
496
497
/* Run PLL1 at 1600 MHz */
498
@@ -XXX,XX +XXX,XX @@
499
* interrupts.
500
*/
501
enum NPCM7xxInterrupt {
502
+ NPCM7XX_ADC_IRQ = 0,
503
NPCM7XX_UART0_IRQ = 2,
504
NPCM7XX_UART1_IRQ,
505
NPCM7XX_UART2_IRQ,
506
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
507
sizeof(value));
69
}
508
}
70
509
71
void v8m_security_lookup(CPUARMState *env, uint32_t address,
510
+static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
72
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
511
+{
73
- V8M_SAttributes *sattrs)
512
+ /* Both ADC and the fuse array must have realized. */
74
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
513
+ QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
75
+ bool is_secure, V8M_SAttributes *sattrs)
514
+ npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
515
+ NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
516
+}
517
+
518
static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
76
{
519
{
77
/*
520
return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
78
* Look up the security attributes for this address. Compare the
521
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
79
@@ -XXX,XX +XXX,XX @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
522
TYPE_NPCM7XX_FUSE_ARRAY);
80
}
523
object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
81
524
object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
82
if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) {
525
+ object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
83
- sattrs->ns = !regime_is_secure(env, mmu_idx);
526
84
+ sattrs->ns = !is_secure;
527
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
85
return;
528
object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
86
}
529
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
87
530
sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
88
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
531
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
89
bool ret;
532
90
533
+ /* ADC Modules. Cannot fail. */
91
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
534
+ qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
92
- v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs);
535
+ DEVICE(&s->clk), "adc-clock"));
93
+ v8m_security_lookup(env, address, access_type, mmu_idx,
536
+ sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
94
+ secure, &sattrs);
537
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
95
if (access_type == MMU_INST_FETCH) {
538
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
96
/*
539
+ npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
97
* Instruction fetches always use the MMU bank and the
540
+ npcm7xx_write_adc_calibration(s);
541
+
542
/* Timer Modules (TIM). Cannot fail. */
543
QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
544
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
545
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
546
create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
547
create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
548
create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
549
- create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB);
550
create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB);
551
create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB);
552
create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB);
553
diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c
554
new file mode 100644
555
index XXXXXXX..XXXXXXX
556
--- /dev/null
557
+++ b/tests/qtest/npcm7xx_adc-test.c
558
@@ -XXX,XX +XXX,XX @@
559
+/*
560
+ * QTests for Nuvoton NPCM7xx ADCModules.
561
+ *
562
+ * Copyright 2020 Google LLC
563
+ *
564
+ * This program is free software; you can redistribute it and/or modify it
565
+ * under the terms of the GNU General Public License as published by the
566
+ * Free Software Foundation; either version 2 of the License, or
567
+ * (at your option) any later version.
568
+ *
569
+ * This program is distributed in the hope that it will be useful, but WITHOUT
570
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
571
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
572
+ * for more details.
573
+ */
574
+
575
+#include "qemu/osdep.h"
576
+#include "qemu/bitops.h"
577
+#include "qemu/timer.h"
578
+#include "libqos/libqtest.h"
579
+#include "qapi/qmp/qdict.h"
580
+
581
+#define REF_HZ (25000000)
582
+
583
+#define CON_OFFSET 0x0
584
+#define DATA_OFFSET 0x4
585
+
586
+#define NUM_INPUTS 8
587
+#define DEFAULT_IREF 2000000
588
+#define CONV_CYCLES 20
589
+#define RESET_CYCLES 10
590
+#define R0_INPUT 500000
591
+#define R1_INPUT 1500000
592
+#define MAX_RESULT 1023
593
+
594
+#define DEFAULT_CLKDIV 5
595
+
596
+#define FUSE_ARRAY_BA 0xf018a000
597
+#define FCTL_OFFSET 0x14
598
+#define FST_OFFSET 0x0
599
+#define FADDR_OFFSET 0x4
600
+#define FDATA_OFFSET 0x8
601
+#define ADC_CALIB_ADDR 24
602
+#define FUSE_READ 0x2
603
+
604
+/* Register field definitions. */
605
+#define CON_MUX(rv) ((rv) << 24)
606
+#define CON_INT_EN BIT(21)
607
+#define CON_REFSEL BIT(19)
608
+#define CON_INT BIT(18)
609
+#define CON_EN BIT(17)
610
+#define CON_RST BIT(16)
611
+#define CON_CONV BIT(14)
612
+#define CON_DIV(rv) extract32(rv, 1, 8)
613
+
614
+#define FST_RDST BIT(1)
615
+#define FDATA_MASK 0xff
616
+
617
+#define MAX_ERROR 10000
618
+#define MIN_CALIB_INPUT 100000
619
+#define MAX_CALIB_INPUT 1800000
620
+
621
+static const uint32_t input_list[] = {
622
+ 100000,
623
+ 500000,
624
+ 1000000,
625
+ 1500000,
626
+ 1800000,
627
+ 2000000,
628
+};
629
+
630
+static const uint32_t vref_list[] = {
631
+ 2000000,
632
+ 2200000,
633
+ 2500000,
634
+};
635
+
636
+static const uint32_t iref_list[] = {
637
+ 1800000,
638
+ 1900000,
639
+ 2000000,
640
+ 2100000,
641
+ 2200000,
642
+};
643
+
644
+static const uint32_t div_list[] = {0, 1, 3, 7, 15};
645
+
646
+typedef struct ADC {
647
+ int irq;
648
+ uint64_t base_addr;
649
+} ADC;
650
+
651
+ADC adc = {
652
+ .irq = 0,
653
+ .base_addr = 0xf000c000
654
+};
655
+
656
+static uint32_t adc_read_con(QTestState *qts, const ADC *adc)
657
+{
658
+ return qtest_readl(qts, adc->base_addr + CON_OFFSET);
659
+}
660
+
661
+static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value)
662
+{
663
+ qtest_writel(qts, adc->base_addr + CON_OFFSET, value);
664
+}
665
+
666
+static uint32_t adc_read_data(QTestState *qts, const ADC *adc)
667
+{
668
+ return qtest_readl(qts, adc->base_addr + DATA_OFFSET);
669
+}
670
+
671
+static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv)
672
+{
673
+ return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0])
674
+ / (int32_t)(rv[1] - rv[0]);
675
+}
676
+
677
+static void adc_qom_set(QTestState *qts, const ADC *adc,
678
+ const char *name, uint32_t value)
679
+{
680
+ QDict *response;
681
+ const char *path = "/machine/soc/adc";
682
+
683
+ g_test_message("Setting properties %s of %s with value %u",
684
+ name, path, value);
685
+ response = qtest_qmp(qts, "{ 'execute': 'qom-set',"
686
+ " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}",
687
+ path, name, value);
688
+ /* The qom set message returns successfully. */
689
+ g_assert_true(qdict_haskey(response, "return"));
690
+}
691
+
692
+static void adc_write_input(QTestState *qts, const ADC *adc,
693
+ uint32_t index, uint32_t value)
694
+{
695
+ char name[100];
696
+
697
+ sprintf(name, "adci[%u]", index);
698
+ adc_qom_set(qts, adc, name, value);
699
+}
700
+
701
+static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value)
702
+{
703
+ adc_qom_set(qts, adc, "vref", value);
704
+}
705
+
706
+static uint32_t adc_calculate_output(uint32_t input, uint32_t ref)
707
+{
708
+ uint32_t output;
709
+
710
+ g_assert_cmpuint(input, <=, ref);
711
+ output = (input * (MAX_RESULT + 1)) / ref;
712
+ if (output > MAX_RESULT) {
713
+ output = MAX_RESULT;
714
+ }
715
+
716
+ return output;
717
+}
718
+
719
+static uint32_t adc_prescaler(QTestState *qts, const ADC *adc)
720
+{
721
+ uint32_t div = extract32(adc_read_con(qts, adc), 1, 8);
722
+
723
+ return 2 * (div + 1);
724
+}
725
+
726
+static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale,
727
+ uint32_t clkdiv)
728
+{
729
+ return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale;
730
+}
731
+
732
+static void adc_wait_conv_finished(QTestState *qts, const ADC *adc,
733
+ uint32_t clkdiv)
734
+{
735
+ uint32_t prescaler = adc_prescaler(qts, adc);
736
+
737
+ /*
738
+ * ADC should takes roughly 20 cycles to convert one sample. So we assert it
739
+ * should take 10~30 cycles here.
740
+ */
741
+ qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler,
742
+ clkdiv));
743
+ /* ADC is still converting. */
744
+ g_assert_true(adc_read_con(qts, adc) & CON_CONV);
745
+ qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv));
746
+ /* ADC has finished conversion. */
747
+ g_assert_false(adc_read_con(qts, adc) & CON_CONV);
748
+}
749
+
750
+/* Check ADC can be reset to default value. */
751
+static void test_init(gconstpointer adc_p)
752
+{
753
+ const ADC *adc = adc_p;
754
+
755
+ QTestState *qts = qtest_init("-machine quanta-gsj");
756
+ adc_write_con(qts, adc, CON_REFSEL | CON_INT);
757
+ g_assert_cmphex(adc_read_con(qts, adc), ==, CON_REFSEL);
758
+ qtest_quit(qts);
759
+}
760
+
761
+/* Check ADC can convert from an internal reference. */
762
+static void test_convert_internal(gconstpointer adc_p)
763
+{
764
+ const ADC *adc = adc_p;
765
+ uint32_t index, input, output, expected_output;
766
+ QTestState *qts = qtest_init("-machine quanta-gsj");
767
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
768
+
769
+ for (index = 0; index < NUM_INPUTS; ++index) {
770
+ for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
771
+ input = input_list[i];
772
+ expected_output = adc_calculate_output(input, DEFAULT_IREF);
773
+
774
+ adc_write_input(qts, adc, index, input);
775
+ adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
776
+ CON_EN | CON_CONV);
777
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
778
+ g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) |
779
+ CON_REFSEL | CON_EN);
780
+ g_assert_false(qtest_get_irq(qts, adc->irq));
781
+ output = adc_read_data(qts, adc);
782
+ g_assert_cmpuint(output, ==, expected_output);
783
+ }
784
+ }
785
+
786
+ qtest_quit(qts);
787
+}
788
+
789
+/* Check ADC can convert from an external reference. */
790
+static void test_convert_external(gconstpointer adc_p)
791
+{
792
+ const ADC *adc = adc_p;
793
+ uint32_t index, input, vref, output, expected_output;
794
+ QTestState *qts = qtest_init("-machine quanta-gsj");
795
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
796
+
797
+ for (index = 0; index < NUM_INPUTS; ++index) {
798
+ for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
799
+ for (size_t j = 0; j < ARRAY_SIZE(vref_list); ++j) {
800
+ input = input_list[i];
801
+ vref = vref_list[j];
802
+ expected_output = adc_calculate_output(input, vref);
803
+
804
+ adc_write_input(qts, adc, index, input);
805
+ adc_write_vref(qts, adc, vref);
806
+ adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN |
807
+ CON_CONV);
808
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
809
+ g_assert_cmphex(adc_read_con(qts, adc), ==,
810
+ CON_MUX(index) | CON_EN);
811
+ g_assert_false(qtest_get_irq(qts, adc->irq));
812
+ output = adc_read_data(qts, adc);
813
+ g_assert_cmpuint(output, ==, expected_output);
814
+ }
815
+ }
816
+ }
817
+
818
+ qtest_quit(qts);
819
+}
820
+
821
+/* Check ADC interrupt files if and only if CON_INT_EN is set. */
822
+static void test_interrupt(gconstpointer adc_p)
823
+{
824
+ const ADC *adc = adc_p;
825
+ uint32_t index, input, output, expected_output;
826
+ QTestState *qts = qtest_init("-machine quanta-gsj");
827
+
828
+ index = 1;
829
+ input = input_list[1];
830
+ expected_output = adc_calculate_output(input, DEFAULT_IREF);
831
+
832
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
833
+ adc_write_input(qts, adc, index, input);
834
+ g_assert_false(qtest_get_irq(qts, adc->irq));
835
+ adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON_INT
836
+ | CON_EN | CON_CONV);
837
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
838
+ g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | CON_INT_EN
839
+ | CON_REFSEL | CON_INT | CON_EN);
840
+ g_assert_true(qtest_get_irq(qts, adc->irq));
841
+ output = adc_read_data(qts, adc);
842
+ g_assert_cmpuint(output, ==, expected_output);
843
+
844
+ qtest_quit(qts);
845
+}
846
+
847
+/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */
848
+static void test_reset(gconstpointer adc_p)
849
+{
850
+ const ADC *adc = adc_p;
851
+ QTestState *qts = qtest_init("-machine quanta-gsj");
852
+
853
+ for (size_t i = 0; i < ARRAY_SIZE(div_list); ++i) {
854
+ uint32_t div = div_list[i];
855
+
856
+ adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div));
857
+ qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES,
858
+ adc_prescaler(qts, adc), DEFAULT_CLKDIV));
859
+ g_assert_false(adc_read_con(qts, adc) & CON_EN);
860
+ }
861
+ qtest_quit(qts);
862
+}
863
+
864
+/* Check ADC Calibration works as desired. */
865
+static void test_calibrate(gconstpointer adc_p)
866
+{
867
+ int i, j;
868
+ const ADC *adc = adc_p;
869
+
870
+ for (j = 0; j < ARRAY_SIZE(iref_list); ++j) {
871
+ uint32_t iref = iref_list[j];
872
+ uint32_t expected_rv[] = {
873
+ adc_calculate_output(R0_INPUT, iref),
874
+ adc_calculate_output(R1_INPUT, iref),
875
+ };
876
+ char buf[100];
877
+ QTestState *qts;
878
+
879
+ sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=%u", iref);
880
+ qts = qtest_init(buf);
881
+
882
+ /* Check the converted value is correct using the calibration value. */
883
+ for (i = 0; i < ARRAY_SIZE(input_list); ++i) {
884
+ uint32_t input;
885
+ uint32_t output;
886
+ uint32_t expected_output;
887
+ uint32_t calibrated_voltage;
888
+ uint32_t index = 0;
889
+
890
+ input = input_list[i];
891
+ /* Calibration only works for input range 0.1V ~ 1.8V. */
892
+ if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) {
893
+ continue;
894
+ }
895
+ expected_output = adc_calculate_output(input, iref);
896
+
897
+ adc_write_input(qts, adc, index, input);
898
+ adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
899
+ CON_EN | CON_CONV);
900
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
901
+ g_assert_cmphex(adc_read_con(qts, adc), ==,
902
+ CON_REFSEL | CON_MUX(index) | CON_EN);
903
+ output = adc_read_data(qts, adc);
904
+ g_assert_cmpuint(output, ==, expected_output);
905
+
906
+ calibrated_voltage = adc_calibrate(output, expected_rv);
907
+ g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR);
908
+ g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR);
909
+ }
910
+
911
+ qtest_quit(qts);
912
+ }
913
+}
914
+
915
+static void adc_add_test(const char *name, const ADC* wd,
916
+ GTestDataFunc fn)
917
+{
918
+ g_autofree char *full_name = g_strdup_printf("npcm7xx_adc/%s", name);
919
+ qtest_add_data_func(full_name, wd, fn);
920
+}
921
+#define add_test(name, td) adc_add_test(#name, td, test_##name)
922
+
923
+int main(int argc, char **argv)
924
+{
925
+ g_test_init(&argc, &argv, NULL);
926
+
927
+ add_test(init, &adc);
928
+ add_test(convert_internal, &adc);
929
+ add_test(convert_external, &adc);
930
+ add_test(interrupt, &adc);
931
+ add_test(reset, &adc);
932
+ add_test(calibrate, &adc);
933
+
934
+ return g_test_run();
935
+}
936
diff --git a/hw/adc/meson.build b/hw/adc/meson.build
937
index XXXXXXX..XXXXXXX 100644
938
--- a/hw/adc/meson.build
939
+++ b/hw/adc/meson.build
940
@@ -1 +1,2 @@
941
softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c'))
942
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c'))
943
diff --git a/hw/adc/trace-events b/hw/adc/trace-events
944
new file mode 100644
945
index XXXXXXX..XXXXXXX
946
--- /dev/null
947
+++ b/hw/adc/trace-events
948
@@ -XXX,XX +XXX,XX @@
949
+# See docs/devel/tracing.txt for syntax documentation.
950
+
951
+# npcm7xx_adc.c
952
+npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
953
+npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
954
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
955
index XXXXXXX..XXXXXXX 100644
956
--- a/tests/qtest/meson.build
957
+++ b/tests/qtest/meson.build
958
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
959
['prom-env-test', 'boot-serial-test']
960
961
qtests_npcm7xx = \
962
- ['npcm7xx_gpio-test',
963
+ ['npcm7xx_adc-test',
964
+ 'npcm7xx_gpio-test',
965
'npcm7xx_rng-test',
966
'npcm7xx_timer-test',
967
'npcm7xx_watchdog_timer-test']
98
--
968
--
99
2.25.1
969
2.20.1
100
970
101
971
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
identical PWM modules. Each module contains 4 PWM entries. Each PWM has
5
Message-id: 20220822152741.1617527-6-richard.henderson@linaro.org
5
two outputs: frequency and duty_cycle. Both are computed using inputs
6
from software side.
7
8
This module does not model detail pulse signals since it is expensive.
9
It also does not model interrupts and watchdogs that are dependant on
10
the detail models. The interfaces for these are left in the module so
11
that anyone in need for these functionalities can implement on their
12
own.
13
14
The user can read the duty cycle and frequency using qom-get command.
15
16
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
17
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
18
Signed-off-by: Hao Wu <wuhaotsh@google.com>
19
Message-id: 20210108190945.949196-5-wuhaotsh@google.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
22
---
9
target/arm/ptw.c | 25 +++++++++++--------------
23
docs/system/arm/nuvoton.rst | 2 +-
10
1 file changed, 11 insertions(+), 14 deletions(-)
24
include/hw/arm/npcm7xx.h | 2 +
25
include/hw/misc/npcm7xx_pwm.h | 105 +++++++
26
hw/arm/npcm7xx.c | 26 +-
27
hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++++++++++
28
hw/misc/meson.build | 1 +
29
hw/misc/trace-events | 6 +
30
7 files changed, 689 insertions(+), 3 deletions(-)
31
create mode 100644 include/hw/misc/npcm7xx_pwm.h
32
create mode 100644 hw/misc/npcm7xx_pwm.c
11
33
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
34
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
13
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/ptw.c
36
--- a/docs/system/arm/nuvoton.rst
15
+++ b/target/arm/ptw.c
37
+++ b/docs/system/arm/nuvoton.rst
16
@@ -XXX,XX +XXX,XX @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
38
@@ -XXX,XX +XXX,XX @@ Supported devices
17
39
* USB host (USBH)
18
static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
40
* GPIO controller
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
41
* Analog to Digital Converter (ADC)
20
- hwaddr *phys_ptr, int *prot,
42
+ * Pulse Width Modulation (PWM)
21
- target_ulong *page_size,
43
22
- ARMMMUFaultInfo *fi)
44
Missing devices
23
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
45
---------------
24
{
46
@@ -XXX,XX +XXX,XX @@ Missing devices
25
int level = 1;
47
* Peripheral SPI controller (PSPI)
26
uint32_t table;
48
* SD/MMC host
27
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
49
* PECI interface
28
/* 1Mb section. */
50
- * Pulse Width Modulation (PWM)
29
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
51
* Tachometer
30
ap = (desc >> 10) & 3;
52
* PCI and PCIe root complex and bridges
31
- *page_size = 1024 * 1024;
53
* VDM and MCTP support
32
+ result->page_size = 1024 * 1024;
54
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
33
} else {
55
index XXXXXXX..XXXXXXX 100644
34
/* Lookup l2 entry. */
56
--- a/include/hw/arm/npcm7xx.h
35
if (type == 1) {
57
+++ b/include/hw/arm/npcm7xx.h
36
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
58
@@ -XXX,XX +XXX,XX @@
37
case 1: /* 64k page. */
59
#include "hw/mem/npcm7xx_mc.h"
38
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
60
#include "hw/misc/npcm7xx_clk.h"
39
ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
61
#include "hw/misc/npcm7xx_gcr.h"
40
- *page_size = 0x10000;
62
+#include "hw/misc/npcm7xx_pwm.h"
41
+ result->page_size = 0x10000;
63
#include "hw/misc/npcm7xx_rng.h"
42
break;
64
#include "hw/nvram/npcm7xx_otp.h"
43
case 2: /* 4k page. */
65
#include "hw/timer/npcm7xx_timer.h"
44
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
66
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
45
ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
67
NPCM7xxCLKState clk;
46
- *page_size = 0x1000;
68
NPCM7xxTimerCtrlState tim[3];
47
+ result->page_size = 0x1000;
69
NPCM7xxADCState adc;
48
break;
70
+ NPCM7xxPWMState pwm[2];
49
case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
71
NPCM7xxOTPState key_storage;
50
if (type == 1) {
72
NPCM7xxOTPState fuse_array;
51
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
73
NPCM7xxMCState mc;
52
if (arm_feature(env, ARM_FEATURE_XSCALE)
74
diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
53
|| arm_feature(env, ARM_FEATURE_V6)) {
75
new file mode 100644
54
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
76
index XXXXXXX..XXXXXXX
55
- *page_size = 0x1000;
77
--- /dev/null
56
+ result->page_size = 0x1000;
78
+++ b/include/hw/misc/npcm7xx_pwm.h
57
} else {
79
@@ -XXX,XX +XXX,XX @@
58
/*
80
+/*
59
* UNPREDICTABLE in ARMv5; we choose to take a
81
+ * Nuvoton NPCM7xx PWM Module
60
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
82
+ *
61
}
83
+ * Copyright 2020 Google LLC
62
} else {
84
+ *
63
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
85
+ * This program is free software; you can redistribute it and/or modify it
64
- *page_size = 0x400;
86
+ * under the terms of the GNU General Public License as published by the
65
+ result->page_size = 0x400;
87
+ * Free Software Foundation; either version 2 of the License, or
66
}
88
+ * (at your option) any later version.
67
ap = (desc >> 4) & 3;
89
+ *
68
break;
90
+ * This program is distributed in the hope that it will be useful, but WITHOUT
69
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
91
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
70
g_assert_not_reached();
92
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
71
}
93
+ * for more details.
94
+ */
95
+#ifndef NPCM7XX_PWM_H
96
+#define NPCM7XX_PWM_H
97
+
98
+#include "hw/clock.h"
99
+#include "hw/sysbus.h"
100
+#include "hw/irq.h"
101
+
102
+/* Each PWM module holds 4 PWM channels. */
103
+#define NPCM7XX_PWM_PER_MODULE 4
104
+
105
+/*
106
+ * Number of registers in one pwm module. Don't change this without increasing
107
+ * the version_id in vmstate.
108
+ */
109
+#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t))
110
+
111
+/*
112
+ * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY
113
+ * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
114
+ * value of 100,000 the duty cycle for that PWM is 10%.
115
+ */
116
+#define NPCM7XX_PWM_MAX_DUTY 1000000
117
+
118
+typedef struct NPCM7xxPWMState NPCM7xxPWMState;
119
+
120
+/**
121
+ * struct NPCM7xxPWM - The state of a single PWM channel.
122
+ * @module: The PWM module that contains this channel.
123
+ * @irq: GIC interrupt line to fire on expiration if enabled.
124
+ * @running: Whether this PWM channel is generating output.
125
+ * @inverted: Whether this PWM channel is inverted.
126
+ * @index: The index of this PWM channel.
127
+ * @cnr: The counter register.
128
+ * @cmr: The comparator register.
129
+ * @pdr: The data register.
130
+ * @pwdr: The watchdog register.
131
+ * @freq: The frequency of this PWM channel.
132
+ * @duty: The duty cycle of this PWM channel. One unit represents
133
+ * 1/NPCM7XX_MAX_DUTY cycles.
134
+ */
135
+typedef struct NPCM7xxPWM {
136
+ NPCM7xxPWMState *module;
137
+
138
+ qemu_irq irq;
139
+
140
+ bool running;
141
+ bool inverted;
142
+
143
+ uint8_t index;
144
+ uint32_t cnr;
145
+ uint32_t cmr;
146
+ uint32_t pdr;
147
+ uint32_t pwdr;
148
+
149
+ uint32_t freq;
150
+ uint32_t duty;
151
+} NPCM7xxPWM;
152
+
153
+/**
154
+ * struct NPCM7xxPWMState - Pulse Width Modulation device state.
155
+ * @parent: System bus device.
156
+ * @iomem: Memory region through which registers are accessed.
157
+ * @clock: The PWM clock.
158
+ * @pwm: The PWM channels owned by this module.
159
+ * @ppr: The prescaler register.
160
+ * @csr: The clock selector register.
161
+ * @pcr: The control register.
162
+ * @pier: The interrupt enable register.
163
+ * @piir: The interrupt indication register.
164
+ */
165
+struct NPCM7xxPWMState {
166
+ SysBusDevice parent;
167
+
168
+ MemoryRegion iomem;
169
+
170
+ Clock *clock;
171
+ NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE];
172
+
173
+ uint32_t ppr;
174
+ uint32_t csr;
175
+ uint32_t pcr;
176
+ uint32_t pier;
177
+ uint32_t piir;
178
+};
179
+
180
+#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
181
+#define NPCM7XX_PWM(obj) \
182
+ OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
183
+
184
+#endif /* NPCM7XX_PWM_H */
185
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
186
index XXXXXXX..XXXXXXX 100644
187
--- a/hw/arm/npcm7xx.c
188
+++ b/hw/arm/npcm7xx.c
189
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
190
NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
191
NPCM7XX_EHCI_IRQ = 61,
192
NPCM7XX_OHCI_IRQ = 62,
193
+ NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */
194
+ NPCM7XX_PWM1_IRQ, /* PWM module 1 */
195
NPCM7XX_GPIO0_IRQ = 116,
196
NPCM7XX_GPIO1_IRQ,
197
NPCM7XX_GPIO2_IRQ,
198
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
199
0xb8000000, /* CS3 */
200
};
201
202
+/* Register base address for each PWM Module */
203
+static const hwaddr npcm7xx_pwm_addr[] = {
204
+ 0xf0103000,
205
+ 0xf0104000,
206
+};
207
+
208
static const struct {
209
hwaddr regs_addr;
210
uint32_t unconnected_pins;
211
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
212
object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
213
TYPE_NPCM7XX_FIU);
72
}
214
}
73
- *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
215
+
74
- *prot |= *prot ? PAGE_EXEC : 0;
216
+ for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
75
- if (!(*prot & (1 << access_type))) {
217
+ object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
76
+ result->prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
218
+ }
77
+ result->prot |= result->prot ? PAGE_EXEC : 0;
78
+ if (!(result->prot & (1 << access_type))) {
79
/* Access permission fault. */
80
fi->type = ARMFault_Permission;
81
goto do_fault;
82
}
83
- *phys_ptr = phys_addr;
84
+ result->phys = phys_addr;
85
return false;
86
do_fault:
87
fi->domain = domain;
88
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
89
result, fi);
90
} else {
91
return get_phys_addr_v5(env, address, access_type, mmu_idx,
92
- &result->phys, &result->prot,
93
- &result->page_size, fi);
94
+ result, fi);
95
}
96
}
219
}
97
220
221
static void npcm7xx_realize(DeviceState *dev, Error **errp)
222
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
223
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
224
npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
225
226
+ /* PWM Modules. Cannot fail. */
227
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
228
+ for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
229
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
230
+
231
+ qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
232
+ DEVICE(&s->clk), "apb3-clock"));
233
+ sysbus_realize(sbd, &error_abort);
234
+ sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
235
+ sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
236
+ }
237
+
238
/*
239
* Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
240
* specified, but this is a programming error.
241
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
242
create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB);
243
create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB);
244
create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);
245
- create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * KiB);
246
- create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * KiB);
247
create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB);
248
create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB);
249
create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB);
250
diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c
251
new file mode 100644
252
index XXXXXXX..XXXXXXX
253
--- /dev/null
254
+++ b/hw/misc/npcm7xx_pwm.c
255
@@ -XXX,XX +XXX,XX @@
256
+/*
257
+ * Nuvoton NPCM7xx PWM Module
258
+ *
259
+ * Copyright 2020 Google LLC
260
+ *
261
+ * This program is free software; you can redistribute it and/or modify it
262
+ * under the terms of the GNU General Public License as published by the
263
+ * Free Software Foundation; either version 2 of the License, or
264
+ * (at your option) any later version.
265
+ *
266
+ * This program is distributed in the hope that it will be useful, but WITHOUT
267
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
268
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
269
+ * for more details.
270
+ */
271
+
272
+#include "qemu/osdep.h"
273
+#include "hw/irq.h"
274
+#include "hw/qdev-clock.h"
275
+#include "hw/qdev-properties.h"
276
+#include "hw/misc/npcm7xx_pwm.h"
277
+#include "hw/registerfields.h"
278
+#include "migration/vmstate.h"
279
+#include "qemu/bitops.h"
280
+#include "qemu/error-report.h"
281
+#include "qemu/log.h"
282
+#include "qemu/module.h"
283
+#include "qemu/units.h"
284
+#include "trace.h"
285
+
286
+REG32(NPCM7XX_PWM_PPR, 0x00);
287
+REG32(NPCM7XX_PWM_CSR, 0x04);
288
+REG32(NPCM7XX_PWM_PCR, 0x08);
289
+REG32(NPCM7XX_PWM_CNR0, 0x0c);
290
+REG32(NPCM7XX_PWM_CMR0, 0x10);
291
+REG32(NPCM7XX_PWM_PDR0, 0x14);
292
+REG32(NPCM7XX_PWM_CNR1, 0x18);
293
+REG32(NPCM7XX_PWM_CMR1, 0x1c);
294
+REG32(NPCM7XX_PWM_PDR1, 0x20);
295
+REG32(NPCM7XX_PWM_CNR2, 0x24);
296
+REG32(NPCM7XX_PWM_CMR2, 0x28);
297
+REG32(NPCM7XX_PWM_PDR2, 0x2c);
298
+REG32(NPCM7XX_PWM_CNR3, 0x30);
299
+REG32(NPCM7XX_PWM_CMR3, 0x34);
300
+REG32(NPCM7XX_PWM_PDR3, 0x38);
301
+REG32(NPCM7XX_PWM_PIER, 0x3c);
302
+REG32(NPCM7XX_PWM_PIIR, 0x40);
303
+REG32(NPCM7XX_PWM_PWDR0, 0x44);
304
+REG32(NPCM7XX_PWM_PWDR1, 0x48);
305
+REG32(NPCM7XX_PWM_PWDR2, 0x4c);
306
+REG32(NPCM7XX_PWM_PWDR3, 0x50);
307
+
308
+/* Register field definitions. */
309
+#define NPCM7XX_PPR(rv, index) extract32((rv), npcm7xx_ppr_base[index], 8)
310
+#define NPCM7XX_CSR(rv, index) extract32((rv), npcm7xx_csr_base[index], 3)
311
+#define NPCM7XX_CH(rv, index) extract32((rv), npcm7xx_ch_base[index], 4)
312
+#define NPCM7XX_CH_EN BIT(0)
313
+#define NPCM7XX_CH_INV BIT(2)
314
+#define NPCM7XX_CH_MOD BIT(3)
315
+
316
+/* Offset of each PWM channel's prescaler in the PPR register. */
317
+static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 };
318
+/* Offset of each PWM channel's clock selector in the CSR register. */
319
+static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 };
320
+/* Offset of each PWM channel's control variable in the PCR register. */
321
+static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 };
322
+
323
+static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p)
324
+{
325
+ uint32_t ppr;
326
+ uint32_t csr;
327
+ uint32_t freq;
328
+
329
+ if (!p->running) {
330
+ return 0;
331
+ }
332
+
333
+ csr = NPCM7XX_CSR(p->module->csr, p->index);
334
+ ppr = NPCM7XX_PPR(p->module->ppr, p->index);
335
+ freq = clock_get_hz(p->module->clock);
336
+ freq /= ppr + 1;
337
+ /* csr can only be 0~4 */
338
+ if (csr > 4) {
339
+ qemu_log_mask(LOG_GUEST_ERROR,
340
+ "%s: invalid csr value %u\n",
341
+ __func__, csr);
342
+ csr = 4;
343
+ }
344
+ /* freq won't be changed if csr == 4. */
345
+ if (csr < 4) {
346
+ freq >>= csr + 1;
347
+ }
348
+
349
+ return freq / (p->cnr + 1);
350
+}
351
+
352
+static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
353
+{
354
+ uint64_t duty;
355
+
356
+ if (p->running) {
357
+ if (p->cnr == 0) {
358
+ duty = 0;
359
+ } else if (p->cmr >= p->cnr) {
360
+ duty = NPCM7XX_PWM_MAX_DUTY;
361
+ } else {
362
+ duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);
363
+ }
364
+ } else {
365
+ duty = 0;
366
+ }
367
+
368
+ if (p->inverted) {
369
+ duty = NPCM7XX_PWM_MAX_DUTY - duty;
370
+ }
371
+
372
+ return duty;
373
+}
374
+
375
+static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p)
376
+{
377
+ uint32_t freq = npcm7xx_pwm_calculate_freq(p);
378
+
379
+ if (freq != p->freq) {
380
+ trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path,
381
+ p->index, p->freq, freq);
382
+ p->freq = freq;
383
+ }
384
+}
385
+
386
+static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p)
387
+{
388
+ uint32_t duty = npcm7xx_pwm_calculate_duty(p);
389
+
390
+ if (duty != p->duty) {
391
+ trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path,
392
+ p->index, p->duty, duty);
393
+ p->duty = duty;
394
+ }
395
+}
396
+
397
+static void npcm7xx_pwm_update_output(NPCM7xxPWM *p)
398
+{
399
+ npcm7xx_pwm_update_freq(p);
400
+ npcm7xx_pwm_update_duty(p);
401
+}
402
+
403
+static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr)
404
+{
405
+ int i;
406
+ uint32_t old_ppr = s->ppr;
407
+
408
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE);
409
+ s->ppr = new_ppr;
410
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
411
+ if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) {
412
+ npcm7xx_pwm_update_freq(&s->pwm[i]);
413
+ }
414
+ }
415
+}
416
+
417
+static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr)
418
+{
419
+ int i;
420
+ uint32_t old_csr = s->csr;
421
+
422
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE);
423
+ s->csr = new_csr;
424
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
425
+ if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) {
426
+ npcm7xx_pwm_update_freq(&s->pwm[i]);
427
+ }
428
+ }
429
+}
430
+
431
+static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr)
432
+{
433
+ int i;
434
+ bool inverted;
435
+ uint32_t pcr;
436
+ NPCM7xxPWM *p;
437
+
438
+ s->pcr = new_pcr;
439
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE);
440
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
441
+ p = &s->pwm[i];
442
+ pcr = NPCM7XX_CH(new_pcr, i);
443
+ inverted = pcr & NPCM7XX_CH_INV;
444
+
445
+ /*
446
+ * We only run a PWM channel with toggle mode. Single-shot mode does not
447
+ * generate frequency and duty-cycle values.
448
+ */
449
+ if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) {
450
+ if (p->running) {
451
+ /* Re-run this PWM channel if inverted changed. */
452
+ if (p->inverted ^ inverted) {
453
+ p->inverted = inverted;
454
+ npcm7xx_pwm_update_duty(p);
455
+ }
456
+ } else {
457
+ /* Run this PWM channel. */
458
+ p->running = true;
459
+ p->inverted = inverted;
460
+ npcm7xx_pwm_update_output(p);
461
+ }
462
+ } else {
463
+ /* Clear this PWM channel. */
464
+ p->running = false;
465
+ p->inverted = inverted;
466
+ npcm7xx_pwm_update_output(p);
467
+ }
468
+ }
469
+
470
+}
471
+
472
+static hwaddr npcm7xx_cnr_index(hwaddr offset)
473
+{
474
+ switch (offset) {
475
+ case A_NPCM7XX_PWM_CNR0:
476
+ return 0;
477
+ case A_NPCM7XX_PWM_CNR1:
478
+ return 1;
479
+ case A_NPCM7XX_PWM_CNR2:
480
+ return 2;
481
+ case A_NPCM7XX_PWM_CNR3:
482
+ return 3;
483
+ default:
484
+ g_assert_not_reached();
485
+ }
486
+}
487
+
488
+static hwaddr npcm7xx_cmr_index(hwaddr offset)
489
+{
490
+ switch (offset) {
491
+ case A_NPCM7XX_PWM_CMR0:
492
+ return 0;
493
+ case A_NPCM7XX_PWM_CMR1:
494
+ return 1;
495
+ case A_NPCM7XX_PWM_CMR2:
496
+ return 2;
497
+ case A_NPCM7XX_PWM_CMR3:
498
+ return 3;
499
+ default:
500
+ g_assert_not_reached();
501
+ }
502
+}
503
+
504
+static hwaddr npcm7xx_pdr_index(hwaddr offset)
505
+{
506
+ switch (offset) {
507
+ case A_NPCM7XX_PWM_PDR0:
508
+ return 0;
509
+ case A_NPCM7XX_PWM_PDR1:
510
+ return 1;
511
+ case A_NPCM7XX_PWM_PDR2:
512
+ return 2;
513
+ case A_NPCM7XX_PWM_PDR3:
514
+ return 3;
515
+ default:
516
+ g_assert_not_reached();
517
+ }
518
+}
519
+
520
+static hwaddr npcm7xx_pwdr_index(hwaddr offset)
521
+{
522
+ switch (offset) {
523
+ case A_NPCM7XX_PWM_PWDR0:
524
+ return 0;
525
+ case A_NPCM7XX_PWM_PWDR1:
526
+ return 1;
527
+ case A_NPCM7XX_PWM_PWDR2:
528
+ return 2;
529
+ case A_NPCM7XX_PWM_PWDR3:
530
+ return 3;
531
+ default:
532
+ g_assert_not_reached();
533
+ }
534
+}
535
+
536
+static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size)
537
+{
538
+ NPCM7xxPWMState *s = opaque;
539
+ uint64_t value = 0;
540
+
541
+ switch (offset) {
542
+ case A_NPCM7XX_PWM_CNR0:
543
+ case A_NPCM7XX_PWM_CNR1:
544
+ case A_NPCM7XX_PWM_CNR2:
545
+ case A_NPCM7XX_PWM_CNR3:
546
+ value = s->pwm[npcm7xx_cnr_index(offset)].cnr;
547
+ break;
548
+
549
+ case A_NPCM7XX_PWM_CMR0:
550
+ case A_NPCM7XX_PWM_CMR1:
551
+ case A_NPCM7XX_PWM_CMR2:
552
+ case A_NPCM7XX_PWM_CMR3:
553
+ value = s->pwm[npcm7xx_cmr_index(offset)].cmr;
554
+ break;
555
+
556
+ case A_NPCM7XX_PWM_PDR0:
557
+ case A_NPCM7XX_PWM_PDR1:
558
+ case A_NPCM7XX_PWM_PDR2:
559
+ case A_NPCM7XX_PWM_PDR3:
560
+ value = s->pwm[npcm7xx_pdr_index(offset)].pdr;
561
+ break;
562
+
563
+ case A_NPCM7XX_PWM_PWDR0:
564
+ case A_NPCM7XX_PWM_PWDR1:
565
+ case A_NPCM7XX_PWM_PWDR2:
566
+ case A_NPCM7XX_PWM_PWDR3:
567
+ value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr;
568
+ break;
569
+
570
+ case A_NPCM7XX_PWM_PPR:
571
+ value = s->ppr;
572
+ break;
573
+
574
+ case A_NPCM7XX_PWM_CSR:
575
+ value = s->csr;
576
+ break;
577
+
578
+ case A_NPCM7XX_PWM_PCR:
579
+ value = s->pcr;
580
+ break;
581
+
582
+ case A_NPCM7XX_PWM_PIER:
583
+ value = s->pier;
584
+ break;
585
+
586
+ case A_NPCM7XX_PWM_PIIR:
587
+ value = s->piir;
588
+ break;
589
+
590
+ default:
591
+ qemu_log_mask(LOG_GUEST_ERROR,
592
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
593
+ __func__, offset);
594
+ break;
595
+ }
596
+
597
+ trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value);
598
+ return value;
599
+}
600
+
601
+static void npcm7xx_pwm_write(void *opaque, hwaddr offset,
602
+ uint64_t v, unsigned size)
603
+{
604
+ NPCM7xxPWMState *s = opaque;
605
+ NPCM7xxPWM *p;
606
+ uint32_t value = v;
607
+
608
+ trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value);
609
+ switch (offset) {
610
+ case A_NPCM7XX_PWM_CNR0:
611
+ case A_NPCM7XX_PWM_CNR1:
612
+ case A_NPCM7XX_PWM_CNR2:
613
+ case A_NPCM7XX_PWM_CNR3:
614
+ p = &s->pwm[npcm7xx_cnr_index(offset)];
615
+ p->cnr = value;
616
+ npcm7xx_pwm_update_output(p);
617
+ break;
618
+
619
+ case A_NPCM7XX_PWM_CMR0:
620
+ case A_NPCM7XX_PWM_CMR1:
621
+ case A_NPCM7XX_PWM_CMR2:
622
+ case A_NPCM7XX_PWM_CMR3:
623
+ p = &s->pwm[npcm7xx_cmr_index(offset)];
624
+ p->cmr = value;
625
+ npcm7xx_pwm_update_output(p);
626
+ break;
627
+
628
+ case A_NPCM7XX_PWM_PDR0:
629
+ case A_NPCM7XX_PWM_PDR1:
630
+ case A_NPCM7XX_PWM_PDR2:
631
+ case A_NPCM7XX_PWM_PDR3:
632
+ qemu_log_mask(LOG_GUEST_ERROR,
633
+ "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
634
+ __func__, offset);
635
+ break;
636
+
637
+ case A_NPCM7XX_PWM_PWDR0:
638
+ case A_NPCM7XX_PWM_PWDR1:
639
+ case A_NPCM7XX_PWM_PWDR2:
640
+ case A_NPCM7XX_PWM_PWDR3:
641
+ qemu_log_mask(LOG_UNIMP,
642
+ "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
643
+ __func__, offset);
644
+ break;
645
+
646
+ case A_NPCM7XX_PWM_PPR:
647
+ npcm7xx_pwm_write_ppr(s, value);
648
+ break;
649
+
650
+ case A_NPCM7XX_PWM_CSR:
651
+ npcm7xx_pwm_write_csr(s, value);
652
+ break;
653
+
654
+ case A_NPCM7XX_PWM_PCR:
655
+ npcm7xx_pwm_write_pcr(s, value);
656
+ break;
657
+
658
+ case A_NPCM7XX_PWM_PIER:
659
+ qemu_log_mask(LOG_UNIMP,
660
+ "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
661
+ __func__, offset);
662
+ break;
663
+
664
+ case A_NPCM7XX_PWM_PIIR:
665
+ qemu_log_mask(LOG_UNIMP,
666
+ "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
667
+ __func__, offset);
668
+ break;
669
+
670
+ default:
671
+ qemu_log_mask(LOG_GUEST_ERROR,
672
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
673
+ __func__, offset);
674
+ break;
675
+ }
676
+}
677
+
678
+static const struct MemoryRegionOps npcm7xx_pwm_ops = {
679
+ .read = npcm7xx_pwm_read,
680
+ .write = npcm7xx_pwm_write,
681
+ .endianness = DEVICE_LITTLE_ENDIAN,
682
+ .valid = {
683
+ .min_access_size = 4,
684
+ .max_access_size = 4,
685
+ .unaligned = false,
686
+ },
687
+};
688
+
689
+static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type)
690
+{
691
+ NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
692
+ int i;
693
+
694
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
695
+ NPCM7xxPWM *p = &s->pwm[i];
696
+
697
+ p->cnr = 0x00000000;
698
+ p->cmr = 0x00000000;
699
+ p->pdr = 0x00000000;
700
+ p->pwdr = 0x00000000;
701
+ }
702
+
703
+ s->ppr = 0x00000000;
704
+ s->csr = 0x00000000;
705
+ s->pcr = 0x00000000;
706
+ s->pier = 0x00000000;
707
+ s->piir = 0x00000000;
708
+}
709
+
710
+static void npcm7xx_pwm_hold_reset(Object *obj)
711
+{
712
+ NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
713
+ int i;
714
+
715
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
716
+ qemu_irq_lower(s->pwm[i].irq);
717
+ }
718
+}
719
+
720
+static void npcm7xx_pwm_init(Object *obj)
721
+{
722
+ NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
723
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
724
+ int i;
725
+
726
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
727
+ NPCM7xxPWM *p = &s->pwm[i];
728
+ p->module = s;
729
+ p->index = i;
730
+ sysbus_init_irq(sbd, &p->irq);
731
+ }
732
+
733
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s,
734
+ TYPE_NPCM7XX_PWM, 4 * KiB);
735
+ sysbus_init_mmio(sbd, &s->iomem);
736
+ s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
737
+
738
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
739
+ object_property_add_uint32_ptr(obj, "freq[*]",
740
+ &s->pwm[i].freq, OBJ_PROP_FLAG_READ);
741
+ object_property_add_uint32_ptr(obj, "duty[*]",
742
+ &s->pwm[i].duty, OBJ_PROP_FLAG_READ);
743
+ }
744
+}
745
+
746
+static const VMStateDescription vmstate_npcm7xx_pwm = {
747
+ .name = "npcm7xx-pwm",
748
+ .version_id = 0,
749
+ .minimum_version_id = 0,
750
+ .fields = (VMStateField[]) {
751
+ VMSTATE_BOOL(running, NPCM7xxPWM),
752
+ VMSTATE_BOOL(inverted, NPCM7xxPWM),
753
+ VMSTATE_UINT8(index, NPCM7xxPWM),
754
+ VMSTATE_UINT32(cnr, NPCM7xxPWM),
755
+ VMSTATE_UINT32(cmr, NPCM7xxPWM),
756
+ VMSTATE_UINT32(pdr, NPCM7xxPWM),
757
+ VMSTATE_UINT32(pwdr, NPCM7xxPWM),
758
+ VMSTATE_UINT32(freq, NPCM7xxPWM),
759
+ VMSTATE_UINT32(duty, NPCM7xxPWM),
760
+ VMSTATE_END_OF_LIST(),
761
+ },
762
+};
763
+
764
+static const VMStateDescription vmstate_npcm7xx_pwm_module = {
765
+ .name = "npcm7xx-pwm-module",
766
+ .version_id = 0,
767
+ .minimum_version_id = 0,
768
+ .fields = (VMStateField[]) {
769
+ VMSTATE_CLOCK(clock, NPCM7xxPWMState),
770
+ VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState,
771
+ NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pwm,
772
+ NPCM7xxPWM),
773
+ VMSTATE_UINT32(ppr, NPCM7xxPWMState),
774
+ VMSTATE_UINT32(csr, NPCM7xxPWMState),
775
+ VMSTATE_UINT32(pcr, NPCM7xxPWMState),
776
+ VMSTATE_UINT32(pier, NPCM7xxPWMState),
777
+ VMSTATE_UINT32(piir, NPCM7xxPWMState),
778
+ VMSTATE_END_OF_LIST(),
779
+ },
780
+};
781
+
782
+static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data)
783
+{
784
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
785
+ DeviceClass *dc = DEVICE_CLASS(klass);
786
+
787
+ dc->desc = "NPCM7xx PWM Controller";
788
+ dc->vmsd = &vmstate_npcm7xx_pwm_module;
789
+ rc->phases.enter = npcm7xx_pwm_enter_reset;
790
+ rc->phases.hold = npcm7xx_pwm_hold_reset;
791
+}
792
+
793
+static const TypeInfo npcm7xx_pwm_info = {
794
+ .name = TYPE_NPCM7XX_PWM,
795
+ .parent = TYPE_SYS_BUS_DEVICE,
796
+ .instance_size = sizeof(NPCM7xxPWMState),
797
+ .class_init = npcm7xx_pwm_class_init,
798
+ .instance_init = npcm7xx_pwm_init,
799
+};
800
+
801
+static void npcm7xx_pwm_register_type(void)
802
+{
803
+ type_register_static(&npcm7xx_pwm_info);
804
+}
805
+type_init(npcm7xx_pwm_register_type);
806
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
807
index XXXXXXX..XXXXXXX 100644
808
--- a/hw/misc/meson.build
809
+++ b/hw/misc/meson.build
810
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
811
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
812
'npcm7xx_clk.c',
813
'npcm7xx_gcr.c',
814
+ 'npcm7xx_pwm.c',
815
'npcm7xx_rng.c',
816
))
817
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
818
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
819
index XXXXXXX..XXXXXXX 100644
820
--- a/hw/misc/trace-events
821
+++ b/hw/misc/trace-events
822
@@ -XXX,XX +XXX,XX @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu
823
npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
824
npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
825
826
+# npcm7xx_pwm.c
827
+npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
828
+npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
829
+npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u"
830
+npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u"
831
+
832
# stm32f4xx_syscfg.c
833
stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
834
stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
98
--
835
--
99
2.25.1
836
2.20.1
100
837
101
838
diff view generated by jsdifflib
1
From: Clément Chigot <chigot@adacore.com>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
When requested, the alignment for VLD4.32 is 8 and not 16.
3
We add a qtest for the PWM in the previous patch. It proves it works as
4
expected.
4
5
5
See ARM documentation about VLD4 encoding:
6
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
6
ebytes = 1 << UInt(size);
7
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
7
if size == '10' then
8
Signed-off-by: Hao Wu <wuhaotsh@google.com>
8
alignment = if a == '0' then 1 else 8;
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
else
10
Message-id: 20210108190945.949196-6-wuhaotsh@google.com
10
alignment = if a == '0' then 1 else 4*ebytes;
11
12
Signed-off-by: Clément Chigot <chigot@adacore.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20220914105058.2787404-1-chigot@adacore.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
12
---
17
target/arm/translate-neon.c | 6 +++++-
13
tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++
18
1 file changed, 5 insertions(+), 1 deletion(-)
14
tests/qtest/meson.build | 1 +
15
2 files changed, 491 insertions(+)
16
create mode 100644 tests/qtest/npcm7xx_pwm-test.c
19
17
20
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
18
diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c
19
new file mode 100644
20
index XXXXXXX..XXXXXXX
21
--- /dev/null
22
+++ b/tests/qtest/npcm7xx_pwm-test.c
23
@@ -XXX,XX +XXX,XX @@
24
+/*
25
+ * QTests for Nuvoton NPCM7xx PWM Modules.
26
+ *
27
+ * Copyright 2020 Google LLC
28
+ *
29
+ * This program is free software; you can redistribute it and/or modify it
30
+ * under the terms of the GNU General Public License as published by the
31
+ * Free Software Foundation; either version 2 of the License, or
32
+ * (at your option) any later version.
33
+ *
34
+ * This program is distributed in the hope that it will be useful, but WITHOUT
35
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
36
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
37
+ * for more details.
38
+ */
39
+
40
+#include "qemu/osdep.h"
41
+#include "qemu/bitops.h"
42
+#include "libqos/libqtest.h"
43
+#include "qapi/qmp/qdict.h"
44
+#include "qapi/qmp/qnum.h"
45
+
46
+#define REF_HZ 25000000
47
+
48
+/* Register field definitions. */
49
+#define CH_EN BIT(0)
50
+#define CH_INV BIT(2)
51
+#define CH_MOD BIT(3)
52
+
53
+/* Registers shared between all PWMs in a module */
54
+#define PPR 0x00
55
+#define CSR 0x04
56
+#define PCR 0x08
57
+#define PIER 0x3c
58
+#define PIIR 0x40
59
+
60
+/* CLK module related */
61
+#define CLK_BA 0xf0801000
62
+#define CLKSEL 0x04
63
+#define CLKDIV1 0x08
64
+#define CLKDIV2 0x2c
65
+#define PLLCON0 0x0c
66
+#define PLLCON1 0x10
67
+#define PLL_INDV(rv) extract32((rv), 0, 6)
68
+#define PLL_FBDV(rv) extract32((rv), 16, 12)
69
+#define PLL_OTDV1(rv) extract32((rv), 8, 3)
70
+#define PLL_OTDV2(rv) extract32((rv), 13, 3)
71
+#define APB3CKDIV(rv) extract32((rv), 28, 2)
72
+#define CLK2CKDIV(rv) extract32((rv), 0, 1)
73
+#define CLK4CKDIV(rv) extract32((rv), 26, 2)
74
+#define CPUCKSEL(rv) extract32((rv), 0, 2)
75
+
76
+#define MAX_DUTY 1000000
77
+
78
+typedef struct PWMModule {
79
+ int irq;
80
+ uint64_t base_addr;
81
+} PWMModule;
82
+
83
+typedef struct PWM {
84
+ uint32_t cnr_offset;
85
+ uint32_t cmr_offset;
86
+ uint32_t pdr_offset;
87
+ uint32_t pwdr_offset;
88
+} PWM;
89
+
90
+typedef struct TestData {
91
+ const PWMModule *module;
92
+ const PWM *pwm;
93
+} TestData;
94
+
95
+static const PWMModule pwm_module_list[] = {
96
+ {
97
+ .irq = 93,
98
+ .base_addr = 0xf0103000
99
+ },
100
+ {
101
+ .irq = 94,
102
+ .base_addr = 0xf0104000
103
+ }
104
+};
105
+
106
+static const PWM pwm_list[] = {
107
+ {
108
+ .cnr_offset = 0x0c,
109
+ .cmr_offset = 0x10,
110
+ .pdr_offset = 0x14,
111
+ .pwdr_offset = 0x44,
112
+ },
113
+ {
114
+ .cnr_offset = 0x18,
115
+ .cmr_offset = 0x1c,
116
+ .pdr_offset = 0x20,
117
+ .pwdr_offset = 0x48,
118
+ },
119
+ {
120
+ .cnr_offset = 0x24,
121
+ .cmr_offset = 0x28,
122
+ .pdr_offset = 0x2c,
123
+ .pwdr_offset = 0x4c,
124
+ },
125
+ {
126
+ .cnr_offset = 0x30,
127
+ .cmr_offset = 0x34,
128
+ .pdr_offset = 0x38,
129
+ .pwdr_offset = 0x50,
130
+ },
131
+};
132
+
133
+static const int ppr_base[] = { 0, 0, 8, 8 };
134
+static const int csr_base[] = { 0, 4, 8, 12 };
135
+static const int pcr_base[] = { 0, 8, 12, 16 };
136
+
137
+static const uint32_t ppr_list[] = {
138
+ 0,
139
+ 1,
140
+ 10,
141
+ 100,
142
+ 255, /* Max possible value. */
143
+};
144
+
145
+static const uint32_t csr_list[] = {
146
+ 0,
147
+ 1,
148
+ 2,
149
+ 3,
150
+ 4, /* Max possible value. */
151
+};
152
+
153
+static const uint32_t cnr_list[] = {
154
+ 0,
155
+ 1,
156
+ 50,
157
+ 100,
158
+ 150,
159
+ 200,
160
+ 1000,
161
+ 10000,
162
+ 65535, /* Max possible value. */
163
+};
164
+
165
+static const uint32_t cmr_list[] = {
166
+ 0,
167
+ 1,
168
+ 10,
169
+ 50,
170
+ 100,
171
+ 150,
172
+ 200,
173
+ 1000,
174
+ 10000,
175
+ 65535, /* Max possible value. */
176
+};
177
+
178
+/* Returns the index of the PWM module. */
179
+static int pwm_module_index(const PWMModule *module)
180
+{
181
+ ptrdiff_t diff = module - pwm_module_list;
182
+
183
+ g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list));
184
+
185
+ return diff;
186
+}
187
+
188
+/* Returns the index of the PWM entry. */
189
+static int pwm_index(const PWM *pwm)
190
+{
191
+ ptrdiff_t diff = pwm - pwm_list;
192
+
193
+ g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list));
194
+
195
+ return diff;
196
+}
197
+
198
+static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name)
199
+{
200
+ QDict *response;
201
+
202
+ g_test_message("Getting properties %s from %s", name, path);
203
+ response = qtest_qmp(qts, "{ 'execute': 'qom-get',"
204
+ " 'arguments': { 'path': %s, 'property': %s}}",
205
+ path, name);
206
+ /* The qom set message returns successfully. */
207
+ g_assert_true(qdict_haskey(response, "return"));
208
+ return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return")));
209
+}
210
+
211
+static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index)
212
+{
213
+ char path[100];
214
+ char name[100];
215
+
216
+ sprintf(path, "/machine/soc/pwm[%d]", module_index);
217
+ sprintf(name, "freq[%d]", pwm_index);
218
+
219
+ return pwm_qom_get(qts, path, name);
220
+}
221
+
222
+static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index)
223
+{
224
+ char path[100];
225
+ char name[100];
226
+
227
+ sprintf(path, "/machine/soc/pwm[%d]", module_index);
228
+ sprintf(name, "duty[%d]", pwm_index);
229
+
230
+ return pwm_qom_get(qts, path, name);
231
+}
232
+
233
+static uint32_t get_pll(uint32_t con)
234
+{
235
+ return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con)
236
+ * PLL_OTDV2(con));
237
+}
238
+
239
+static uint64_t read_pclk(QTestState *qts)
240
+{
241
+ uint64_t freq = REF_HZ;
242
+ uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL);
243
+ uint32_t pllcon;
244
+ uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1);
245
+ uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2);
246
+
247
+ switch (CPUCKSEL(clksel)) {
248
+ case 0:
249
+ pllcon = qtest_readl(qts, CLK_BA + PLLCON0);
250
+ freq = get_pll(pllcon);
251
+ break;
252
+ case 1:
253
+ pllcon = qtest_readl(qts, CLK_BA + PLLCON1);
254
+ freq = get_pll(pllcon);
255
+ break;
256
+ case 2:
257
+ break;
258
+ case 3:
259
+ break;
260
+ default:
261
+ g_assert_not_reached();
262
+ }
263
+
264
+ freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2));
265
+
266
+ return freq;
267
+}
268
+
269
+static uint32_t pwm_selector(uint32_t csr)
270
+{
271
+ switch (csr) {
272
+ case 0:
273
+ return 2;
274
+ case 1:
275
+ return 4;
276
+ case 2:
277
+ return 8;
278
+ case 3:
279
+ return 16;
280
+ case 4:
281
+ return 1;
282
+ default:
283
+ g_assert_not_reached();
284
+ }
285
+}
286
+
287
+static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr,
288
+ uint32_t cnr)
289
+{
290
+ return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1));
291
+}
292
+
293
+static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
294
+{
295
+ uint64_t duty;
296
+
297
+ if (cnr == 0) {
298
+ /* PWM is stopped. */
299
+ duty = 0;
300
+ } else if (cmr >= cnr) {
301
+ duty = MAX_DUTY;
302
+ } else {
303
+ duty = MAX_DUTY * (cmr + 1) / (cnr + 1);
304
+ }
305
+
306
+ if (inverted) {
307
+ duty = MAX_DUTY - duty;
308
+ }
309
+
310
+ return duty;
311
+}
312
+
313
+static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset)
314
+{
315
+ return qtest_readl(qts, td->module->base_addr + offset);
316
+}
317
+
318
+static void pwm_write(QTestState *qts, const TestData *td, unsigned offset,
319
+ uint32_t value)
320
+{
321
+ qtest_writel(qts, td->module->base_addr + offset, value);
322
+}
323
+
324
+static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td)
325
+{
326
+ return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8);
327
+}
328
+
329
+static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value)
330
+{
331
+ pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]);
332
+}
333
+
334
+static uint32_t pwm_read_csr(QTestState *qts, const TestData *td)
335
+{
336
+ return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3);
337
+}
338
+
339
+static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value)
340
+{
341
+ pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]);
342
+}
343
+
344
+static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td)
345
+{
346
+ return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4);
347
+}
348
+
349
+static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value)
350
+{
351
+ pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]);
352
+}
353
+
354
+static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td)
355
+{
356
+ return pwm_read(qts, td, td->pwm->cnr_offset);
357
+}
358
+
359
+static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value)
360
+{
361
+ pwm_write(qts, td, td->pwm->cnr_offset, value);
362
+}
363
+
364
+static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td)
365
+{
366
+ return pwm_read(qts, td, td->pwm->cmr_offset);
367
+}
368
+
369
+static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value)
370
+{
371
+ pwm_write(qts, td, td->pwm->cmr_offset, value);
372
+}
373
+
374
+/* Check pwm registers can be reset to default value */
375
+static void test_init(gconstpointer test_data)
376
+{
377
+ const TestData *td = test_data;
378
+ QTestState *qts = qtest_init("-machine quanta-gsj");
379
+ int module = pwm_module_index(td->module);
380
+ int pwm = pwm_index(td->pwm);
381
+
382
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
383
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
384
+
385
+ qtest_quit(qts);
386
+}
387
+
388
+/* One-shot mode should not change frequency and duty cycle. */
389
+static void test_oneshot(gconstpointer test_data)
390
+{
391
+ const TestData *td = test_data;
392
+ QTestState *qts = qtest_init("-machine quanta-gsj");
393
+ int module = pwm_module_index(td->module);
394
+ int pwm = pwm_index(td->pwm);
395
+ uint32_t ppr, csr, pcr;
396
+ int i, j;
397
+
398
+ pcr = CH_EN;
399
+ for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
400
+ ppr = ppr_list[i];
401
+ pwm_write_ppr(qts, td, ppr);
402
+
403
+ for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
404
+ csr = csr_list[j];
405
+ pwm_write_csr(qts, td, csr);
406
+ pwm_write_pcr(qts, td, pcr);
407
+
408
+ g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
409
+ g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
410
+ g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
411
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
412
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
413
+ }
414
+ }
415
+
416
+ qtest_quit(qts);
417
+}
418
+
419
+/* In toggle mode, the PWM generates correct outputs. */
420
+static void test_toggle(gconstpointer test_data)
421
+{
422
+ const TestData *td = test_data;
423
+ QTestState *qts = qtest_init("-machine quanta-gsj");
424
+ int module = pwm_module_index(td->module);
425
+ int pwm = pwm_index(td->pwm);
426
+ uint32_t ppr, csr, pcr, cnr, cmr;
427
+ int i, j, k, l;
428
+ uint64_t expected_freq, expected_duty;
429
+
430
+ pcr = CH_EN | CH_MOD;
431
+ for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
432
+ ppr = ppr_list[i];
433
+ pwm_write_ppr(qts, td, ppr);
434
+
435
+ for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
436
+ csr = csr_list[j];
437
+ pwm_write_csr(qts, td, csr);
438
+
439
+ for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) {
440
+ cnr = cnr_list[k];
441
+ pwm_write_cnr(qts, td, cnr);
442
+
443
+ for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) {
444
+ cmr = cmr_list[l];
445
+ pwm_write_cmr(qts, td, cmr);
446
+ expected_freq = pwm_compute_freq(qts, ppr, csr, cnr);
447
+ expected_duty = pwm_compute_duty(cnr, cmr, false);
448
+
449
+ pwm_write_pcr(qts, td, pcr);
450
+ g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
451
+ g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
452
+ g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
453
+ g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr);
454
+ g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr);
455
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
456
+ ==, expected_duty);
457
+ if (expected_duty != 0 && expected_duty != 100) {
458
+ /* Duty cycle with 0 or 100 doesn't need frequency. */
459
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
460
+ ==, expected_freq);
461
+ }
462
+
463
+ /* Test inverted mode */
464
+ expected_duty = pwm_compute_duty(cnr, cmr, true);
465
+ pwm_write_pcr(qts, td, pcr | CH_INV);
466
+ g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV);
467
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
468
+ ==, expected_duty);
469
+ if (expected_duty != 0 && expected_duty != 100) {
470
+ /* Duty cycle with 0 or 100 doesn't need frequency. */
471
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
472
+ ==, expected_freq);
473
+ }
474
+
475
+ }
476
+ }
477
+ }
478
+ }
479
+
480
+ qtest_quit(qts);
481
+}
482
+
483
+static void pwm_add_test(const char *name, const TestData* td,
484
+ GTestDataFunc fn)
485
+{
486
+ g_autofree char *full_name = g_strdup_printf(
487
+ "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module),
488
+ pwm_index(td->pwm), name);
489
+ qtest_add_data_func(full_name, td, fn);
490
+}
491
+#define add_test(name, td) pwm_add_test(#name, td, test_##name)
492
+
493
+int main(int argc, char **argv)
494
+{
495
+ TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)];
496
+
497
+ g_test_init(&argc, &argv, NULL);
498
+
499
+ for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) {
500
+ for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) {
501
+ TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j];
502
+
503
+ td->module = &pwm_module_list[i];
504
+ td->pwm = &pwm_list[j];
505
+
506
+ add_test(init, td);
507
+ add_test(oneshot, td);
508
+ add_test(toggle, td);
509
+ }
510
+ }
511
+
512
+ return g_test_run();
513
+}
514
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
21
index XXXXXXX..XXXXXXX 100644
515
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/translate-neon.c
516
--- a/tests/qtest/meson.build
23
+++ b/target/arm/translate-neon.c
517
+++ b/tests/qtest/meson.build
24
@@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
518
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
25
case 3:
519
qtests_npcm7xx = \
26
return false;
520
['npcm7xx_adc-test',
27
case 4:
521
'npcm7xx_gpio-test',
28
- align = pow2_align(size + 2);
522
+ 'npcm7xx_pwm-test',
29
+ if (size == 2) {
523
'npcm7xx_rng-test',
30
+ align = pow2_align(3);
524
'npcm7xx_timer-test',
31
+ } else {
525
'npcm7xx_watchdog_timer-test']
32
+ align = pow2_align(size + 2);
33
+ }
34
break;
35
default:
36
g_assert_not_reached();
37
--
526
--
38
2.25.1
527
2.20.1
39
528
40
529
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Combine 5 output pointer arguments from get_phys_addr
4
into a single struct. Adjust all callers.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220822152741.1617527-2-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/internals.h | 13 ++++-
12
target/arm/helper.c | 27 ++++-----
13
target/arm/m_helper.c | 52 ++++++-----------
14
target/arm/ptw.c | 120 +++++++++++++++++++++-------------------
15
target/arm/tlb_helper.c | 22 +++-----
16
5 files changed, 109 insertions(+), 125 deletions(-)
17
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/internals.h
21
+++ b/target/arm/internals.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct ARMCacheAttrs {
23
bool is_s2_format:1;
24
} ARMCacheAttrs;
25
26
+/* Fields that are valid upon success. */
27
+typedef struct GetPhysAddrResult {
28
+ hwaddr phys;
29
+ target_ulong page_size;
30
+ int prot;
31
+ MemTxAttrs attrs;
32
+ ARMCacheAttrs cacheattrs;
33
+} GetPhysAddrResult;
34
+
35
bool get_phys_addr(CPUARMState *env, target_ulong address,
36
MMUAccessType access_type, ARMMMUIdx mmu_idx,
37
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
38
- target_ulong *page_size,
39
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
40
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
41
__attribute__((nonnull));
42
43
void arm_log_exception(CPUState *cs);
44
diff --git a/target/arm/helper.c b/target/arm/helper.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/helper.c
47
+++ b/target/arm/helper.c
48
@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
49
static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
50
MMUAccessType access_type, ARMMMUIdx mmu_idx)
51
{
52
- hwaddr phys_addr;
53
- target_ulong page_size;
54
- int prot;
55
bool ret;
56
uint64_t par64;
57
bool format64 = false;
58
- MemTxAttrs attrs = {};
59
ARMMMUFaultInfo fi = {};
60
- ARMCacheAttrs cacheattrs = {};
61
+ GetPhysAddrResult res = {};
62
63
- ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs,
64
- &prot, &page_size, &fi, &cacheattrs);
65
+ ret = get_phys_addr(env, value, access_type, mmu_idx, &res, &fi);
66
67
/*
68
* ATS operations only do S1 or S1+S2 translations, so we never
69
* have to deal with the ARMCacheAttrs format for S2 only.
70
*/
71
- assert(!cacheattrs.is_s2_format);
72
+ assert(!res.cacheattrs.is_s2_format);
73
74
if (ret) {
75
/*
76
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
77
/* Create a 64-bit PAR */
78
par64 = (1 << 11); /* LPAE bit always set */
79
if (!ret) {
80
- par64 |= phys_addr & ~0xfffULL;
81
- if (!attrs.secure) {
82
+ par64 |= res.phys & ~0xfffULL;
83
+ if (!res.attrs.secure) {
84
par64 |= (1 << 9); /* NS */
85
}
86
- par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */
87
- par64 |= cacheattrs.shareability << 7; /* SH */
88
+ par64 |= (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */
89
+ par64 |= res.cacheattrs.shareability << 7; /* SH */
90
} else {
91
uint32_t fsr = arm_fi_to_lfsc(&fi);
92
93
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
94
*/
95
if (!ret) {
96
/* We do not set any attribute bits in the PAR */
97
- if (page_size == (1 << 24)
98
+ if (res.page_size == (1 << 24)
99
&& arm_feature(env, ARM_FEATURE_V7)) {
100
- par64 = (phys_addr & 0xff000000) | (1 << 1);
101
+ par64 = (res.phys & 0xff000000) | (1 << 1);
102
} else {
103
- par64 = phys_addr & 0xfffff000;
104
+ par64 = res.phys & 0xfffff000;
105
}
106
- if (!attrs.secure) {
107
+ if (!res.attrs.secure) {
108
par64 |= (1 << 9); /* NS */
109
}
110
} else {
111
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
112
index XXXXXXX..XXXXXXX 100644
113
--- a/target/arm/m_helper.c
114
+++ b/target/arm/m_helper.c
115
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
116
{
117
CPUState *cs = CPU(cpu);
118
CPUARMState *env = &cpu->env;
119
- MemTxAttrs attrs = {};
120
MemTxResult txres;
121
- target_ulong page_size;
122
- hwaddr physaddr;
123
- int prot;
124
+ GetPhysAddrResult res = {};
125
ARMMMUFaultInfo fi = {};
126
- ARMCacheAttrs cacheattrs = {};
127
bool secure = mmu_idx & ARM_MMU_IDX_M_S;
128
int exc;
129
bool exc_secure;
130
131
- if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &physaddr,
132
- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
133
+ if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &res, &fi)) {
134
/* MPU/SAU lookup failed */
135
if (fi.type == ARMFault_QEMU_SFault) {
136
if (mode == STACK_LAZYFP) {
137
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
138
}
139
goto pend_fault;
140
}
141
- address_space_stl_le(arm_addressspace(cs, attrs), physaddr, value,
142
- attrs, &txres);
143
+ address_space_stl_le(arm_addressspace(cs, res.attrs), res.phys, value,
144
+ res.attrs, &txres);
145
if (txres != MEMTX_OK) {
146
/* BusFault trying to write the data */
147
if (mode == STACK_LAZYFP) {
148
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
149
{
150
CPUState *cs = CPU(cpu);
151
CPUARMState *env = &cpu->env;
152
- MemTxAttrs attrs = {};
153
MemTxResult txres;
154
- target_ulong page_size;
155
- hwaddr physaddr;
156
- int prot;
157
+ GetPhysAddrResult res = {};
158
ARMMMUFaultInfo fi = {};
159
- ARMCacheAttrs cacheattrs = {};
160
bool secure = mmu_idx & ARM_MMU_IDX_M_S;
161
int exc;
162
bool exc_secure;
163
uint32_t value;
164
165
- if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr,
166
- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
167
+ if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) {
168
/* MPU/SAU lookup failed */
169
if (fi.type == ARMFault_QEMU_SFault) {
170
qemu_log_mask(CPU_LOG_INT,
171
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
172
goto pend_fault;
173
}
174
175
- value = address_space_ldl(arm_addressspace(cs, attrs), physaddr,
176
- attrs, &txres);
177
+ value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys,
178
+ res.attrs, &txres);
179
if (txres != MEMTX_OK) {
180
/* BusFault trying to read the data */
181
qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n");
182
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
183
CPUState *cs = CPU(cpu);
184
CPUARMState *env = &cpu->env;
185
V8M_SAttributes sattrs = {};
186
- MemTxAttrs attrs = {};
187
+ GetPhysAddrResult res = {};
188
ARMMMUFaultInfo fi = {};
189
- ARMCacheAttrs cacheattrs = {};
190
MemTxResult txres;
191
- target_ulong page_size;
192
- hwaddr physaddr;
193
- int prot;
194
195
v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
196
if (!sattrs.nsc || sattrs.ns) {
197
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
198
"...really SecureFault with SFSR.INVEP\n");
199
return false;
200
}
201
- if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &physaddr,
202
- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
203
+ if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &res, &fi)) {
204
/* the MPU lookup failed */
205
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK;
206
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure);
207
qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL\n");
208
return false;
209
}
210
- *insn = address_space_lduw_le(arm_addressspace(cs, attrs), physaddr,
211
- attrs, &txres);
212
+ *insn = address_space_lduw_le(arm_addressspace(cs, res.attrs), res.phys,
213
+ res.attrs, &txres);
214
if (txres != MEMTX_OK) {
215
env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK;
216
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
217
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
218
*/
219
CPUState *cs = CPU(cpu);
220
CPUARMState *env = &cpu->env;
221
- MemTxAttrs attrs = {};
222
MemTxResult txres;
223
- target_ulong page_size;
224
- hwaddr physaddr;
225
- int prot;
226
+ GetPhysAddrResult res = {};
227
ARMMMUFaultInfo fi = {};
228
- ARMCacheAttrs cacheattrs = {};
229
uint32_t value;
230
231
- if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr,
232
- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
233
+ if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) {
234
/* MPU/SAU lookup failed */
235
if (fi.type == ARMFault_QEMU_SFault) {
236
qemu_log_mask(CPU_LOG_INT,
237
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
238
}
239
return false;
240
}
241
- value = address_space_ldl(arm_addressspace(cs, attrs), physaddr,
242
- attrs, &txres);
243
+ value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys,
244
+ res.attrs, &txres);
245
if (txres != MEMTX_OK) {
246
/* BusFault trying to read the data */
247
qemu_log_mask(CPU_LOG_INT,
248
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
249
index XXXXXXX..XXXXXXX 100644
250
--- a/target/arm/ptw.c
251
+++ b/target/arm/ptw.c
252
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
253
* @address: virtual address to get physical address for
254
* @access_type: 0 for read, 1 for write, 2 for execute
255
* @mmu_idx: MMU index indicating required translation regime
256
- * @phys_ptr: set to the physical address corresponding to the virtual address
257
- * @attrs: set to the memory transaction attributes to use
258
- * @prot: set to the permissions for the page containing phys_ptr
259
- * @page_size: set to the size of the page containing phys_ptr
260
+ * @result: set on translation success.
261
* @fi: set to fault info if the translation fails
262
- * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
263
*/
264
bool get_phys_addr(CPUARMState *env, target_ulong address,
265
MMUAccessType access_type, ARMMMUIdx mmu_idx,
266
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
267
- target_ulong *page_size,
268
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
269
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
270
{
271
ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
272
273
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
274
*/
275
if (arm_feature(env, ARM_FEATURE_EL2)) {
276
hwaddr ipa;
277
- int s2_prot;
278
+ int s1_prot;
279
int ret;
280
bool ipa_secure;
281
- ARMCacheAttrs cacheattrs2 = {};
282
+ ARMCacheAttrs cacheattrs1;
283
ARMMMUIdx s2_mmu_idx;
284
bool is_el0;
285
286
- ret = get_phys_addr(env, address, access_type, s1_mmu_idx, &ipa,
287
- attrs, prot, page_size, fi, cacheattrs);
288
+ ret = get_phys_addr(env, address, access_type, s1_mmu_idx,
289
+ result, fi);
290
291
/* If S1 fails or S2 is disabled, return early. */
292
if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
293
- *phys_ptr = ipa;
294
return ret;
295
}
296
297
- ipa_secure = attrs->secure;
298
+ ipa = result->phys;
299
+ ipa_secure = result->attrs.secure;
300
if (arm_is_secure_below_el3(env)) {
301
if (ipa_secure) {
302
- attrs->secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
303
+ result->attrs.secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
304
} else {
305
- attrs->secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
306
+ result->attrs.secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
307
}
308
} else {
309
assert(!ipa_secure);
310
}
311
312
- s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
313
+ s2_mmu_idx = (result->attrs.secure
314
+ ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2);
315
is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0;
316
317
- /* S1 is done. Now do S2 translation. */
318
+ /*
319
+ * S1 is done, now do S2 translation.
320
+ * Save the stage1 results so that we may merge
321
+ * prot and cacheattrs later.
322
+ */
323
+ s1_prot = result->prot;
324
+ cacheattrs1 = result->cacheattrs;
325
+ memset(result, 0, sizeof(*result));
326
+
327
ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, is_el0,
328
- phys_ptr, attrs, &s2_prot,
329
- page_size, fi, &cacheattrs2);
330
+ &result->phys, &result->attrs,
331
+ &result->prot, &result->page_size,
332
+ fi, &result->cacheattrs);
333
fi->s2addr = ipa;
334
+
335
/* Combine the S1 and S2 perms. */
336
- *prot &= s2_prot;
337
+ result->prot &= s1_prot;
338
339
/* If S2 fails, return early. */
340
if (ret) {
341
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
342
* Outer Write-Back Read-Allocate Write-Allocate.
343
* Do not overwrite Tagged within attrs.
344
*/
345
- if (cacheattrs->attrs != 0xf0) {
346
- cacheattrs->attrs = 0xff;
347
+ if (cacheattrs1.attrs != 0xf0) {
348
+ cacheattrs1.attrs = 0xff;
349
}
350
- cacheattrs->shareability = 0;
351
+ cacheattrs1.shareability = 0;
352
}
353
- *cacheattrs = combine_cacheattrs(env, *cacheattrs, cacheattrs2);
354
+ result->cacheattrs = combine_cacheattrs(env, cacheattrs1,
355
+ result->cacheattrs);
356
357
/* Check if IPA translates to secure or non-secure PA space. */
358
if (arm_is_secure_below_el3(env)) {
359
if (ipa_secure) {
360
- attrs->secure =
361
+ result->attrs.secure =
362
!(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW));
363
} else {
364
- attrs->secure =
365
+ result->attrs.secure =
366
!((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))
367
|| (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)));
368
}
369
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
370
* cannot upgrade an non-secure translation regime's attributes
371
* to secure.
372
*/
373
- attrs->secure = regime_is_secure(env, mmu_idx);
374
- attrs->user = regime_is_user(env, mmu_idx);
375
+ result->attrs.secure = regime_is_secure(env, mmu_idx);
376
+ result->attrs.user = regime_is_user(env, mmu_idx);
377
378
/*
379
* Fast Context Switch Extension. This doesn't exist at all in v8.
380
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
381
382
if (arm_feature(env, ARM_FEATURE_PMSA)) {
383
bool ret;
384
- *page_size = TARGET_PAGE_SIZE;
385
+ result->page_size = TARGET_PAGE_SIZE;
386
387
if (arm_feature(env, ARM_FEATURE_V8)) {
388
/* PMSAv8 */
389
ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
390
- phys_ptr, attrs, prot, page_size, fi);
391
+ &result->phys, &result->attrs,
392
+ &result->prot, &result->page_size, fi);
393
} else if (arm_feature(env, ARM_FEATURE_V7)) {
394
/* PMSAv7 */
395
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
396
- phys_ptr, prot, page_size, fi);
397
+ &result->phys, &result->prot,
398
+ &result->page_size, fi);
399
} else {
400
/* Pre-v7 MPU */
401
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
402
- phys_ptr, prot, fi);
403
+ &result->phys, &result->prot, fi);
404
}
405
qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
406
" mmu_idx %u -> %s (prot %c%c%c)\n",
407
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
408
(access_type == MMU_DATA_STORE ? "writing" : "execute"),
409
(uint32_t)address, mmu_idx,
410
ret ? "Miss" : "Hit",
411
- *prot & PAGE_READ ? 'r' : '-',
412
- *prot & PAGE_WRITE ? 'w' : '-',
413
- *prot & PAGE_EXEC ? 'x' : '-');
414
+ result->prot & PAGE_READ ? 'r' : '-',
415
+ result->prot & PAGE_WRITE ? 'w' : '-',
416
+ result->prot & PAGE_EXEC ? 'x' : '-');
417
418
return ret;
419
}
420
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
421
address = extract64(address, 0, 52);
422
}
423
}
424
- *phys_ptr = address;
425
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
426
- *page_size = TARGET_PAGE_SIZE;
427
+ result->phys = address;
428
+ result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
429
+ result->page_size = TARGET_PAGE_SIZE;
430
431
/* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
432
hcr = arm_hcr_el2_eff(env);
433
- cacheattrs->shareability = 0;
434
- cacheattrs->is_s2_format = false;
435
+ result->cacheattrs.shareability = 0;
436
+ result->cacheattrs.is_s2_format = false;
437
if (hcr & HCR_DC) {
438
if (hcr & HCR_DCT) {
439
memattr = 0xf0; /* Tagged, Normal, WB, RWA */
440
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
441
} else {
442
memattr = 0x44; /* Normal, NC, No */
443
}
444
- cacheattrs->shareability = 2; /* outer sharable */
445
+ result->cacheattrs.shareability = 2; /* outer sharable */
446
} else {
447
memattr = 0x00; /* Device, nGnRnE */
448
}
449
- cacheattrs->attrs = memattr;
450
+ result->cacheattrs.attrs = memattr;
451
return 0;
452
}
453
454
if (regime_using_lpae_format(env, mmu_idx)) {
455
return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
456
- phys_ptr, attrs, prot, page_size,
457
- fi, cacheattrs);
458
+ &result->phys, &result->attrs,
459
+ &result->prot, &result->page_size,
460
+ fi, &result->cacheattrs);
461
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
462
return get_phys_addr_v6(env, address, access_type, mmu_idx,
463
- phys_ptr, attrs, prot, page_size, fi);
464
+ &result->phys, &result->attrs,
465
+ &result->prot, &result->page_size, fi);
466
} else {
467
return get_phys_addr_v5(env, address, access_type, mmu_idx,
468
- phys_ptr, prot, page_size, fi);
469
+ &result->phys, &result->prot,
470
+ &result->page_size, fi);
471
}
472
}
473
474
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
475
{
476
ARMCPU *cpu = ARM_CPU(cs);
477
CPUARMState *env = &cpu->env;
478
- hwaddr phys_addr;
479
- target_ulong page_size;
480
- int prot;
481
- bool ret;
482
+ GetPhysAddrResult res = {};
483
ARMMMUFaultInfo fi = {};
484
ARMMMUIdx mmu_idx = arm_mmu_idx(env);
485
- ARMCacheAttrs cacheattrs = {};
486
+ bool ret;
487
488
- *attrs = (MemTxAttrs) {};
489
-
490
- ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr,
491
- attrs, &prot, &page_size, &fi, &cacheattrs);
492
+ ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi);
493
+ *attrs = res.attrs;
494
495
if (ret) {
496
return -1;
497
}
498
- return phys_addr;
499
+ return res.phys;
500
}
501
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
502
index XXXXXXX..XXXXXXX 100644
503
--- a/target/arm/tlb_helper.c
504
+++ b/target/arm/tlb_helper.c
505
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
506
{
507
ARMCPU *cpu = ARM_CPU(cs);
508
ARMMMUFaultInfo fi = {};
509
- hwaddr phys_addr;
510
- target_ulong page_size;
511
- int prot, ret;
512
- MemTxAttrs attrs = {};
513
- ARMCacheAttrs cacheattrs = {};
514
+ GetPhysAddrResult res = {};
515
+ int ret;
516
517
/*
518
* Walk the page table and (if the mapping exists) add the page
519
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
520
*/
521
ret = get_phys_addr(&cpu->env, address, access_type,
522
core_to_arm_mmu_idx(&cpu->env, mmu_idx),
523
- &phys_addr, &attrs, &prot, &page_size,
524
- &fi, &cacheattrs);
525
+ &res, &fi);
526
if (likely(!ret)) {
527
/*
528
* Map a single [sub]page. Regions smaller than our declared
529
* target page size are handled specially, so for those we
530
* pass in the exact addresses.
531
*/
532
- if (page_size >= TARGET_PAGE_SIZE) {
533
- phys_addr &= TARGET_PAGE_MASK;
534
+ if (res.page_size >= TARGET_PAGE_SIZE) {
535
+ res.phys &= TARGET_PAGE_MASK;
536
address &= TARGET_PAGE_MASK;
537
}
538
/* Notice and record tagged memory. */
539
- if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs == 0xf0) {
540
- arm_tlb_mte_tagged(&attrs) = true;
541
+ if (cpu_isar_feature(aa64_mte, cpu) && res.cacheattrs.attrs == 0xf0) {
542
+ arm_tlb_mte_tagged(&res.attrs) = true;
543
}
544
545
- tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
546
- prot, mmu_idx, page_size);
547
+ tlb_set_page_with_attrs(cs, address, res.phys, res.attrs,
548
+ res.prot, mmu_idx, res.page_size);
549
return true;
550
} else if (probe) {
551
return false;
552
--
553
2.25.1
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
A device shouldn't access its parent object which is QOM internal.
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Instead it should use type cast for this purporse. This patch fixes this
5
Message-id: 20220822152741.1617527-7-richard.henderson@linaro.org
5
issue for all NPCM7XX Devices.
6
7
Signed-off-by: Hao Wu <wuhaotsh@google.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20210108190945.949196-7-wuhaotsh@google.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
11
---
9
target/arm/ptw.c | 24 ++++++++++++------------
12
hw/arm/npcm7xx_boards.c | 2 +-
10
1 file changed, 12 insertions(+), 12 deletions(-)
13
hw/mem/npcm7xx_mc.c | 2 +-
14
hw/misc/npcm7xx_clk.c | 2 +-
15
hw/misc/npcm7xx_gcr.c | 2 +-
16
hw/misc/npcm7xx_rng.c | 2 +-
17
hw/nvram/npcm7xx_otp.c | 2 +-
18
hw/ssi/npcm7xx_fiu.c | 2 +-
19
7 files changed, 7 insertions(+), 7 deletions(-)
11
20
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
21
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
13
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/ptw.c
23
--- a/hw/arm/npcm7xx_boards.c
15
+++ b/target/arm/ptw.c
24
+++ b/hw/arm/npcm7xx_boards.c
16
@@ -XXX,XX +XXX,XX @@ do_fault:
25
@@ -XXX,XX +XXX,XX @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
17
26
uint32_t hw_straps)
18
static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
20
- hwaddr *phys_ptr, int *prot,
21
+ GetPhysAddrResult *result,
22
ARMMMUFaultInfo *fi)
23
{
27
{
24
int n;
28
NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
25
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
29
- MachineClass *mc = &nmc->parent;
26
30
+ MachineClass *mc = MACHINE_CLASS(nmc);
27
if (regime_translation_disabled(env, mmu_idx)) {
31
Object *obj;
28
/* MPU disabled. */
32
29
- *phys_ptr = address;
33
if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
30
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
34
diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c
31
+ result->phys = address;
35
index XXXXXXX..XXXXXXX 100644
32
+ result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
36
--- a/hw/mem/npcm7xx_mc.c
33
return false;
37
+++ b/hw/mem/npcm7xx_mc.c
34
}
38
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
35
39
36
- *phys_ptr = address;
40
memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
37
+ result->phys = address;
41
NPCM7XX_MC_REGS_SIZE);
38
for (n = 7; n >= 0; n--) {
42
- sysbus_init_mmio(&s->parent, &s->mmio);
39
base = env->cp15.c6_region[n];
43
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
40
if ((base & 1) == 0) {
41
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
42
fi->level = 1;
43
return true;
44
}
45
- *prot = PAGE_READ | PAGE_WRITE;
46
+ result->prot = PAGE_READ | PAGE_WRITE;
47
break;
48
case 2:
49
- *prot = PAGE_READ;
50
+ result->prot = PAGE_READ;
51
if (!is_user) {
52
- *prot |= PAGE_WRITE;
53
+ result->prot |= PAGE_WRITE;
54
}
55
break;
56
case 3:
57
- *prot = PAGE_READ | PAGE_WRITE;
58
+ result->prot = PAGE_READ | PAGE_WRITE;
59
break;
60
case 5:
61
if (is_user) {
62
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
63
fi->level = 1;
64
return true;
65
}
66
- *prot = PAGE_READ;
67
+ result->prot = PAGE_READ;
68
break;
69
case 6:
70
- *prot = PAGE_READ;
71
+ result->prot = PAGE_READ;
72
break;
73
default:
74
/* Bad permission. */
75
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
76
fi->level = 1;
77
return true;
78
}
79
- *prot |= PAGE_EXEC;
80
+ result->prot |= PAGE_EXEC;
81
return false;
82
}
44
}
83
45
84
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
46
static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
85
} else {
47
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
86
/* Pre-v7 MPU */
48
index XXXXXXX..XXXXXXX 100644
87
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
49
--- a/hw/misc/npcm7xx_clk.c
88
- &result->phys, &result->prot, fi);
50
+++ b/hw/misc/npcm7xx_clk.c
89
+ result, fi);
51
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
90
}
52
91
qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
53
memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
92
" mmu_idx %u -> %s (prot %c%c%c)\n",
54
TYPE_NPCM7XX_CLK, 4 * KiB);
55
- sysbus_init_mmio(&s->parent, &s->iomem);
56
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
57
}
58
59
static int npcm7xx_clk_post_load(void *opaque, int version_id)
60
diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/hw/misc/npcm7xx_gcr.c
63
+++ b/hw/misc/npcm7xx_gcr.c
64
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_init(Object *obj)
65
66
memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
67
TYPE_NPCM7XX_GCR, 4 * KiB);
68
- sysbus_init_mmio(&s->parent, &s->iomem);
69
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
70
}
71
72
static const VMStateDescription vmstate_npcm7xx_gcr = {
73
diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/hw/misc/npcm7xx_rng.c
76
+++ b/hw/misc/npcm7xx_rng.c
77
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_rng_init(Object *obj)
78
79
memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs",
80
NPCM7XX_RNG_REGS_SIZE);
81
- sysbus_init_mmio(&s->parent, &s->iomem);
82
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
83
}
84
85
static const VMStateDescription vmstate_npcm7xx_rng = {
86
diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/hw/nvram/npcm7xx_otp.c
89
+++ b/hw/nvram/npcm7xx_otp.c
90
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
91
{
92
NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
93
NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
94
- SysBusDevice *sbd = &s->parent;
95
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
96
97
memset(s->array, 0, sizeof(s->array));
98
99
diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/hw/ssi/npcm7xx_fiu.c
102
+++ b/hw/ssi/npcm7xx_fiu.c
103
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_hold_reset(Object *obj)
104
static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
105
{
106
NPCM7xxFIUState *s = NPCM7XX_FIU(dev);
107
- SysBusDevice *sbd = &s->parent;
108
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
109
int i;
110
111
if (s->cs_count <= 0) {
93
--
112
--
94
2.25.1
113
2.20.1
95
114
96
115
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Roman Bolshakov <r.bolshakov@yadro.com>
2
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in macOS 11.0 - Use -[NSWorkspace openURL:] instead.
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
[-Wdeprecated-declarations]
5
Message-id: 20220822152741.1617527-5-richard.henderson@linaro.org
5
if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
6
^
7
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1: note:
8
'openFile:' has been explicitly marked deprecated here
9
- (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace openURL:] instead.", macos(10.0, 11.0));
10
^
11
12
Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
16
---
9
target/arm/ptw.c | 30 ++++++++++++++----------------
17
ui/cocoa.m | 5 ++++-
10
1 file changed, 14 insertions(+), 16 deletions(-)
18
1 file changed, 4 insertions(+), 1 deletion(-)
11
19
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
20
diff --git a/ui/cocoa.m b/ui/cocoa.m
13
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/ptw.c
22
--- a/ui/cocoa.m
15
+++ b/target/arm/ptw.c
23
+++ b/ui/cocoa.m
16
@@ -XXX,XX +XXX,XX @@ do_fault:
24
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
17
25
/* Where to look for local files */
18
static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
26
NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
27
NSString *full_file_path;
20
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
28
+ NSURL *full_file_url;
21
- target_ulong *page_size, ARMMMUFaultInfo *fi)
29
22
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
30
/* iterate thru the possible paths until the file is found */
23
{
31
int index;
24
ARMCPU *cpu = env_archcpu(env);
32
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
25
int level = 1;
33
full_file_path = [full_file_path stringByDeletingLastPathComponent];
26
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
34
full_file_path = [NSString stringWithFormat: @"%@/%@%@", full_file_path,
27
phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
35
path_array[index], filename];
28
phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
36
- if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
29
phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
37
+ full_file_url = [NSURL fileURLWithPath: full_file_path
30
- *page_size = 0x1000000;
38
+ isDirectory: false];
31
+ result->page_size = 0x1000000;
39
+ if ([[NSWorkspace sharedWorkspace] openURL: full_file_url] == YES) {
32
} else {
40
return;
33
/* Section. */
34
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
35
- *page_size = 0x100000;
36
+ result->page_size = 0x100000;
37
}
38
ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
39
xn = desc & (1 << 4);
40
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
41
case 1: /* 64k page. */
42
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
43
xn = desc & (1 << 15);
44
- *page_size = 0x10000;
45
+ result->page_size = 0x10000;
46
break;
47
case 2: case 3: /* 4k page. */
48
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
49
xn = desc & 1;
50
- *page_size = 0x1000;
51
+ result->page_size = 0x1000;
52
break;
53
default:
54
/* Never happens, but compiler isn't smart enough to tell. */
55
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
56
}
41
}
57
}
42
}
58
if (domain_prot == 3) {
59
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
60
+ result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
61
} else {
62
if (pxn && !regime_is_user(env, mmu_idx)) {
63
xn = 1;
64
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
65
fi->type = ARMFault_AccessFlag;
66
goto do_fault;
67
}
68
- *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
69
+ result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
70
} else {
71
- *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
72
+ result->prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
73
}
74
- if (*prot && !xn) {
75
- *prot |= PAGE_EXEC;
76
+ if (result->prot && !xn) {
77
+ result->prot |= PAGE_EXEC;
78
}
79
- if (!(*prot & (1 << access_type))) {
80
+ if (!(result->prot & (1 << access_type))) {
81
/* Access permission fault. */
82
fi->type = ARMFault_Permission;
83
goto do_fault;
84
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
85
* the CPU doesn't support TZ or this is a non-secure translation
86
* regime, because the attribute will already be non-secure.
87
*/
88
- attrs->secure = false;
89
+ result->attrs.secure = false;
90
}
91
- *phys_ptr = phys_addr;
92
+ result->phys = phys_addr;
93
return false;
94
do_fault:
95
fi->domain = domain;
96
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
97
result, fi);
98
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
99
return get_phys_addr_v6(env, address, access_type, mmu_idx,
100
- &result->phys, &result->attrs,
101
- &result->prot, &result->page_size, fi);
102
+ result, fi);
103
} else {
104
return get_phys_addr_v5(env, address, access_type, mmu_idx,
105
&result->phys, &result->prot,
106
--
43
--
107
2.25.1
44
2.20.1
108
45
109
46
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
This can be made redundant with result->page_size, by moving the basic
4
set of page_size from get_phys_addr_pmsav8. We still need to overwrite
5
page_size when v8m_security_lookup signals a subpage.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-11-richard.henderson@linaro.org
9
[PMM: Update a comment that used to refer to is_subpage]
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/internals.h | 4 ++--
14
target/arm/m_helper.c | 3 +--
15
target/arm/ptw.c | 23 ++++++++++++-----------
16
3 files changed, 15 insertions(+), 15 deletions(-)
17
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/internals.h
21
+++ b/target/arm/internals.h
22
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
23
24
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
25
MMUAccessType access_type, ARMMMUIdx mmu_idx,
26
- GetPhysAddrResult *result, bool *is_subpage,
27
- ARMMMUFaultInfo *fi, uint32_t *mregion);
28
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi,
29
+ uint32_t *mregion);
30
31
void arm_log_exception(CPUState *cs);
32
33
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/m_helper.c
36
+++ b/target/arm/m_helper.c
37
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
38
if (arm_current_el(env) != 0 || alt) {
39
GetPhysAddrResult res = {};
40
ARMMMUFaultInfo fi = {};
41
- bool is_subpage;
42
43
/* We can ignore the return value as prot is always set */
44
pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
45
- &res, &is_subpage, &fi, &mregion);
46
+ &res, &fi, &mregion);
47
if (mregion == -1) {
48
mrvalid = false;
49
mregion = 0;
50
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/ptw.c
53
+++ b/target/arm/ptw.c
54
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
55
56
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
57
MMUAccessType access_type, ARMMMUIdx mmu_idx,
58
- GetPhysAddrResult *result, bool *is_subpage,
59
- ARMMMUFaultInfo *fi, uint32_t *mregion)
60
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi,
61
+ uint32_t *mregion)
62
{
63
/*
64
* Perform a PMSAv8 MPU lookup (without also doing the SAU check
65
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
66
* mregion is (if not NULL) set to the region number which matched,
67
* or -1 if no region number is returned (MPU off, address did not
68
* hit a region, address hit in multiple regions).
69
- * We set is_subpage to true if the region hit doesn't cover the
70
- * entire TARGET_PAGE the address is within.
71
+ * If the region hit doesn't cover the entire TARGET_PAGE the address
72
+ * is within, then we set the result page_size to 1 to force the
73
+ * memory system to use a subpage.
74
*/
75
ARMCPU *cpu = env_archcpu(env);
76
bool is_user = regime_is_user(env, mmu_idx);
77
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
78
uint32_t addr_page_base = address & TARGET_PAGE_MASK;
79
uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
80
81
- *is_subpage = false;
82
+ result->page_size = TARGET_PAGE_SIZE;
83
result->phys = address;
84
result->prot = 0;
85
if (mregion) {
86
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
87
ranges_overlap(base, limit - base + 1,
88
addr_page_base,
89
TARGET_PAGE_SIZE)) {
90
- *is_subpage = true;
91
+ result->page_size = 1;
92
}
93
continue;
94
}
95
96
if (base > addr_page_base || limit < addr_page_limit) {
97
- *is_subpage = true;
98
+ result->page_size = 1;
99
}
100
101
if (matchregion != -1) {
102
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
103
uint32_t secure = regime_is_secure(env, mmu_idx);
104
V8M_SAttributes sattrs = {};
105
bool ret;
106
- bool mpu_is_subpage;
107
108
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
109
v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs);
110
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
111
}
112
113
ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx,
114
- result, &mpu_is_subpage, fi, NULL);
115
- result->page_size =
116
- sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
117
+ result, fi, NULL);
118
+ if (sattrs.subpage) {
119
+ result->page_size = 1;
120
+ }
121
return ret;
122
}
123
124
--
125
2.25.1
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Remove the use of regime_is_secure from get_phys_addr_v6,
4
passing the new parameter to the lookup instead.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-15-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/ptw.c | 11 +++++------
13
1 file changed, 5 insertions(+), 6 deletions(-)
14
15
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/ptw.c
18
+++ b/target/arm/ptw.c
19
@@ -XXX,XX +XXX,XX @@ do_fault:
20
21
static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
22
MMUAccessType access_type, ARMMMUIdx mmu_idx,
23
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
24
+ bool is_secure, GetPhysAddrResult *result,
25
+ ARMMMUFaultInfo *fi)
26
{
27
ARMCPU *cpu = env_archcpu(env);
28
int level = 1;
29
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
30
fi->type = ARMFault_Translation;
31
goto do_fault;
32
}
33
- desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx),
34
- mmu_idx, fi);
35
+ desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
36
if (fi->type != ARMFault_None) {
37
goto do_fault;
38
}
39
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
40
ns = extract32(desc, 3, 1);
41
/* Lookup l2 entry. */
42
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
43
- desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx),
44
- mmu_idx, fi);
45
+ desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
46
if (fi->type != ARMFault_None) {
47
goto do_fault;
48
}
49
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
50
result, fi);
51
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
52
return get_phys_addr_v6(env, address, access_type, mmu_idx,
53
- result, fi);
54
+ is_secure, result, fi);
55
} else {
56
return get_phys_addr_v5(env, address, access_type, mmu_idx,
57
is_secure, result, fi);
58
--
59
2.25.1
60
61
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Remove the use of regime_is_secure from get_phys_addr_pmsav8.
4
Since we already had a local variable named secure, use that.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-16-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/ptw.c | 5 ++---
13
1 file changed, 2 insertions(+), 3 deletions(-)
14
15
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/ptw.c
18
+++ b/target/arm/ptw.c
19
@@ -XXX,XX +XXX,XX @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
20
21
static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
22
MMUAccessType access_type, ARMMMUIdx mmu_idx,
23
- GetPhysAddrResult *result,
24
+ bool secure, GetPhysAddrResult *result,
25
ARMMMUFaultInfo *fi)
26
{
27
- uint32_t secure = regime_is_secure(env, mmu_idx);
28
V8M_SAttributes sattrs = {};
29
bool ret;
30
31
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
32
if (arm_feature(env, ARM_FEATURE_V8)) {
33
/* PMSAv8 */
34
ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
35
- result, fi);
36
+ is_secure, result, fi);
37
} else if (arm_feature(env, ARM_FEATURE_V7)) {
38
/* PMSAv7 */
39
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
40
--
41
2.25.1
42
43
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Remove the use of regime_is_secure from pmsav7_use_background_region,
4
using the new parameter instead.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-17-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/ptw.c | 10 +++++-----
13
1 file changed, 5 insertions(+), 5 deletions(-)
14
15
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/ptw.c
18
+++ b/target/arm/ptw.c
19
@@ -XXX,XX +XXX,XX @@ static bool m_is_system_region(CPUARMState *env, uint32_t address)
20
}
21
22
static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
23
- bool is_user)
24
+ bool is_secure, bool is_user)
25
{
26
/*
27
* Return true if we should use the default memory map as a
28
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
29
}
30
31
if (arm_feature(env, ARM_FEATURE_M)) {
32
- return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)]
33
- & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
34
+ return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
35
} else {
36
return regime_sctlr(env, mmu_idx) & SCTLR_BR;
37
}
38
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
39
{
40
ARMCPU *cpu = env_archcpu(env);
41
int n;
42
+ bool secure = regime_is_secure(env, mmu_idx);
43
bool is_user = regime_is_user(env, mmu_idx);
44
45
result->phys = address;
46
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
47
}
48
49
if (n == -1) { /* no hits */
50
- if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
51
+ if (!pmsav7_use_background_region(cpu, mmu_idx, secure, is_user)) {
52
/* background fault */
53
fi->type = ARMFault_Background;
54
return true;
55
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
56
} else if (m_is_ppb_region(env, address)) {
57
hit = true;
58
} else {
59
- if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
60
+ if (pmsav7_use_background_region(cpu, mmu_idx, secure, is_user)) {
61
hit = true;
62
}
63
64
--
65
2.25.1
66
67
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Remove the use of regime_is_secure from get_phys_addr_pmsav7,
4
using the new parameter instead.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-19-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/ptw.c | 5 ++---
13
1 file changed, 2 insertions(+), 3 deletions(-)
14
15
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/ptw.c
18
+++ b/target/arm/ptw.c
19
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
20
21
static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
22
MMUAccessType access_type, ARMMMUIdx mmu_idx,
23
- GetPhysAddrResult *result,
24
+ bool secure, GetPhysAddrResult *result,
25
ARMMMUFaultInfo *fi)
26
{
27
ARMCPU *cpu = env_archcpu(env);
28
int n;
29
- bool secure = regime_is_secure(env, mmu_idx);
30
bool is_user = regime_is_user(env, mmu_idx);
31
32
result->phys = address;
33
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
34
} else if (arm_feature(env, ARM_FEATURE_V7)) {
35
/* PMSAv7 */
36
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
37
- result, fi);
38
+ is_secure, result, fi);
39
} else {
40
/* Pre-v7 MPU */
41
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
42
--
43
2.25.1
44
45
diff view generated by jsdifflib
Deleted patch
1
From: Keqian Zhu <zhukeqian1@huawei.com>
2
1
3
Setup an ARM virtual machine of machine virt and execute qmp "query-acpi-ospm-status"
4
causes segmentation fault with following dumpstack:
5
#1 0x0000aaaaab64235c in qmp_query_acpi_ospm_status (errp=errp@entry=0xfffffffff030) at ../monitor/qmp-cmds.c:312
6
#2 0x0000aaaaabfc4e20 in qmp_marshal_query_acpi_ospm_status (args=<optimized out>, ret=0xffffea4ffe90, errp=0xffffea4ffe88) at qapi/qapi-commands-acpi.c:63
7
#3 0x0000aaaaabff8ba0 in do_qmp_dispatch_bh (opaque=0xffffea4ffe98) at ../qapi/qmp-dispatch.c:128
8
#4 0x0000aaaaac02e594 in aio_bh_call (bh=0xffffe0004d80) at ../util/async.c:150
9
#5 aio_bh_poll (ctx=ctx@entry=0xaaaaad0f6040) at ../util/async.c:178
10
#6 0x0000aaaaac00bd40 in aio_dispatch (ctx=ctx@entry=0xaaaaad0f6040) at ../util/aio-posix.c:421
11
#7 0x0000aaaaac02e010 in aio_ctx_dispatch (source=0xaaaaad0f6040, callback=<optimized out>, user_data=<optimized out>) at ../util/async.c:320
12
#8 0x0000fffff76f6884 in g_main_context_dispatch () at /usr/lib64/libglib-2.0.so.0
13
#9 0x0000aaaaac0452d4 in glib_pollfds_poll () at ../util/main-loop.c:297
14
#10 os_host_main_loop_wait (timeout=0) at ../util/main-loop.c:320
15
#11 main_loop_wait (nonblocking=nonblocking@entry=0) at ../util/main-loop.c:596
16
#12 0x0000aaaaab5c9e50 in qemu_main_loop () at ../softmmu/runstate.c:734
17
#13 0x0000aaaaab185370 in qemu_main (argc=argc@entry=47, argv=argv@entry=0xfffffffff518, envp=envp@entry=0x0) at ../softmmu/main.c:38
18
#14 0x0000aaaaab16f99c in main (argc=47, argv=0xfffffffff518) at ../softmmu/main.c:47
19
20
Fixes: ebb62075021a ("hw/acpi: Add ACPI Generic Event Device Support")
21
Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
22
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
23
Message-id: 20220816094957.31700-1-zhukeqian1@huawei.com
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
26
hw/acpi/generic_event_device.c | 8 ++++++++
27
1 file changed, 8 insertions(+)
28
29
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/acpi/generic_event_device.c
32
+++ b/hw/acpi/generic_event_device.c
33
@@ -XXX,XX +XXX,XX @@ static void acpi_ged_unplug_cb(HotplugHandler *hotplug_dev,
34
}
35
}
36
37
+static void acpi_ged_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
38
+{
39
+ AcpiGedState *s = ACPI_GED(adev);
40
+
41
+ acpi_memory_ospm_status(&s->memhp_state, list);
42
+}
43
+
44
static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
45
{
46
AcpiGedState *s = ACPI_GED(adev);
47
@@ -XXX,XX +XXX,XX @@ static void acpi_ged_class_init(ObjectClass *class, void *data)
48
hc->unplug_request = acpi_ged_unplug_request_cb;
49
hc->unplug = acpi_ged_unplug_cb;
50
51
+ adevc->ospm_status = acpi_ged_ospm_status;
52
adevc->send_event = acpi_ged_send_event;
53
}
54
55
--
56
2.25.1
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Replace '84' magic value by the X_MAX definition, and '1' by Y_MAX.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
7
Reviewed-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220819153931.3147384-2-peter.maydell@linaro.org
10
---
11
chardev/baum.c | 11 +++++++----
12
1 file changed, 7 insertions(+), 4 deletions(-)
13
14
diff --git a/chardev/baum.c b/chardev/baum.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/chardev/baum.c
17
+++ b/chardev/baum.c
18
@@ -XXX,XX +XXX,XX @@
19
20
#define BUF_SIZE 256
21
22
+#define X_MAX 84
23
+#define Y_MAX 1
24
+
25
struct BaumChardev {
26
Chardev parent;
27
28
@@ -XXX,XX +XXX,XX @@ static int baum_deferred_init(BaumChardev *baum)
29
brlapi_perror("baum: brlapi__getDisplaySize");
30
return 0;
31
}
32
- if (baum->y > 1) {
33
- baum->y = 1;
34
+ if (baum->y > Y_MAX) {
35
+ baum->y = Y_MAX;
36
}
37
- if (baum->x > 84) {
38
- baum->x = 84;
39
+ if (baum->x > X_MAX) {
40
+ baum->x = X_MAX;
41
}
42
43
con = qemu_console_lookup_by_index(0);
44
--
45
2.25.1
46
47
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
We know 'x * y' will be at most 'X_MAX * Y_MAX' (which is not
4
a big value, it is actually 84). Instead of having the compiler
5
use variable-length array, declare an array able to hold the
6
maximum 'x * y'.
7
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
10
Reviewed-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20220819153931.3147384-3-peter.maydell@linaro.org
13
---
14
chardev/baum.c | 8 ++++----
15
1 file changed, 4 insertions(+), 4 deletions(-)
16
17
diff --git a/chardev/baum.c b/chardev/baum.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/chardev/baum.c
20
+++ b/chardev/baum.c
21
@@ -XXX,XX +XXX,XX @@ static int baum_eat_packet(BaumChardev *baum, const uint8_t *buf, int len)
22
switch (req) {
23
case BAUM_REQ_DisplayData:
24
{
25
- uint8_t cells[baum->x * baum->y], c;
26
- uint8_t text[baum->x * baum->y];
27
- uint8_t zero[baum->x * baum->y];
28
+ uint8_t cells[X_MAX * Y_MAX], c;
29
+ uint8_t text[X_MAX * Y_MAX];
30
+ uint8_t zero[X_MAX * Y_MAX];
31
int cursor = BRLAPI_CURSOR_OFF;
32
int i;
33
34
@@ -XXX,XX +XXX,XX @@ static int baum_eat_packet(BaumChardev *baum, const uint8_t *buf, int len)
35
}
36
timer_del(baum->cellCount_timer);
37
38
- memset(zero, 0, sizeof(zero));
39
+ memset(zero, 0, baum->x * baum->y);
40
41
brlapi_writeArguments_t wa = {
42
.displayNumber = BRLAPI_DISPLAY_DEFAULT,
43
--
44
2.25.1
45
46
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Use autofree heap allocation instead of variable-length
4
array on the stack.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
8
Reviewed-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20220819153931.3147384-4-peter.maydell@linaro.org
11
---
12
chardev/baum.c | 3 ++-
13
1 file changed, 2 insertions(+), 1 deletion(-)
14
15
diff --git a/chardev/baum.c b/chardev/baum.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/chardev/baum.c
18
+++ b/chardev/baum.c
19
@@ -XXX,XX +XXX,XX @@ static void baum_chr_accept_input(struct Chardev *chr)
20
static void baum_write_packet(BaumChardev *baum, const uint8_t *buf, int len)
21
{
22
Chardev *chr = CHARDEV(baum);
23
- uint8_t io_buf[1 + 2 * len], *cur = io_buf;
24
+ g_autofree uint8_t *io_buf = g_malloc(1 + 2 * len);
25
+ uint8_t *cur = io_buf;
26
int room;
27
*cur++ = ESC;
28
while (len--)
29
--
30
2.25.1
31
32
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
The combined_key[... QIO_CHANNEL_WEBSOCK_GUID_LEN ...] array in
4
qio_channel_websock_handshake_send_res_ok() expands to a call
5
to strlen(QIO_CHANNEL_WEBSOCK_GUID), and the compiler doesn't
6
realize the string is const, so consider combined_key[] being
7
a variable-length array.
8
9
To remove the variable-length array, we provide it a hint to
10
the compiler by using sizeof() - 1 instead of strlen().
11
12
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Message-id: 20220819153931.3147384-5-peter.maydell@linaro.org
16
---
17
io/channel-websock.c | 2 +-
18
1 file changed, 1 insertion(+), 1 deletion(-)
19
20
diff --git a/io/channel-websock.c b/io/channel-websock.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/io/channel-websock.c
23
+++ b/io/channel-websock.c
24
@@ -XXX,XX +XXX,XX @@
25
26
#define QIO_CHANNEL_WEBSOCK_CLIENT_KEY_LEN 24
27
#define QIO_CHANNEL_WEBSOCK_GUID "258EAFA5-E914-47DA-95CA-C5AB0DC85B11"
28
-#define QIO_CHANNEL_WEBSOCK_GUID_LEN strlen(QIO_CHANNEL_WEBSOCK_GUID)
29
+#define QIO_CHANNEL_WEBSOCK_GUID_LEN (sizeof(QIO_CHANNEL_WEBSOCK_GUID) - 1)
30
31
#define QIO_CHANNEL_WEBSOCK_HEADER_PROTOCOL "sec-websocket-protocol"
32
#define QIO_CHANNEL_WEBSOCK_HEADER_VERSION "sec-websocket-version"
33
--
34
2.25.1
35
36
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
The compiler isn't clever enough to figure 'min_buf_size'
4
is a constant, so help it by using a definitions instead.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Acked-by: Jason Wang <jasowang@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20220819153931.3147384-6-peter.maydell@linaro.org
11
---
12
hw/net/e1000e_core.c | 7 ++++---
13
1 file changed, 4 insertions(+), 3 deletions(-)
14
15
diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/net/e1000e_core.c
18
+++ b/hw/net/e1000e_core.c
19
@@ -XXX,XX +XXX,XX @@ e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt)
20
}
21
}
22
23
+/* Min. octets in an ethernet frame sans FCS */
24
+#define MIN_BUF_SIZE 60
25
+
26
ssize_t
27
e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt)
28
{
29
static const int maximum_ethernet_hdr_len = (14 + 4);
30
- /* Min. octets in an ethernet frame sans FCS */
31
- static const int min_buf_size = 60;
32
33
uint32_t n = 0;
34
- uint8_t min_buf[min_buf_size];
35
+ uint8_t min_buf[MIN_BUF_SIZE];
36
struct iovec min_iov;
37
uint8_t *filter_buf;
38
size_t size, orig_size;
39
--
40
2.25.1
41
42
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Use autofree heap allocation instead of variable-length
4
array on the stack.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Acked-by: David Gibson <david@gibson.dropbear.id.au>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
11
Message-id: 20220819153931.3147384-7-peter.maydell@linaro.org
12
---
13
hw/ppc/pnv.c | 4 ++--
14
hw/ppc/spapr.c | 8 ++++----
15
hw/ppc/spapr_pci_nvlink2.c | 2 +-
16
3 files changed, 7 insertions(+), 7 deletions(-)
17
18
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/ppc/pnv.c
21
+++ b/hw/ppc/pnv.c
22
@@ -XXX,XX +XXX,XX @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
23
int smt_threads = CPU_CORE(pc)->nr_threads;
24
CPUPPCState *env = &cpu->env;
25
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
26
- uint32_t servers_prop[smt_threads];
27
+ g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
28
int i;
29
uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
30
0xffffffff, 0xffffffff};
31
@@ -XXX,XX +XXX,XX @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
32
servers_prop[i] = cpu_to_be32(pc->pir + i);
33
}
34
_FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
35
- servers_prop, sizeof(servers_prop))));
36
+ servers_prop, sizeof(*servers_prop) * smt_threads)));
37
}
38
39
static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
40
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/ppc/spapr.c
43
+++ b/hw/ppc/spapr.c
44
@@ -XXX,XX +XXX,XX @@ static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
45
int smt_threads)
46
{
47
int i, ret = 0;
48
- uint32_t servers_prop[smt_threads];
49
- uint32_t gservers_prop[smt_threads * 2];
50
+ g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
51
+ g_autofree uint32_t *gservers_prop = g_new(uint32_t, smt_threads * 2);
52
int index = spapr_get_vcpu_id(cpu);
53
54
if (cpu->compat_pvr) {
55
@@ -XXX,XX +XXX,XX @@ static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
56
gservers_prop[i*2 + 1] = 0;
57
}
58
ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
59
- servers_prop, sizeof(servers_prop));
60
+ servers_prop, sizeof(*servers_prop) * smt_threads);
61
if (ret < 0) {
62
return ret;
63
}
64
ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
65
- gservers_prop, sizeof(gservers_prop));
66
+ gservers_prop, sizeof(*gservers_prop) * smt_threads * 2);
67
68
return ret;
69
}
70
diff --git a/hw/ppc/spapr_pci_nvlink2.c b/hw/ppc/spapr_pci_nvlink2.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/ppc/spapr_pci_nvlink2.c
73
+++ b/hw/ppc/spapr_pci_nvlink2.c
74
@@ -XXX,XX +XXX,XX @@ void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, int offset,
75
continue;
76
}
77
if (dev == nvslot->gpdev) {
78
- uint32_t npus[nvslot->linknum];
79
+ g_autofree uint32_t *npus = g_new(uint32_t, nvslot->linknum);
80
81
for (j = 0; j < nvslot->linknum; ++j) {
82
PCIDevice *npdev = nvslot->links[j].npdev;
83
--
84
2.25.1
85
86
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Use autofree heap allocation instead of variable-length
4
array on the stack.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Acked-by: David Gibson <david@gibson.dropbear.id.au>
8
Reviewed-by: Greg Kurz <groug@kaod.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20220819153931.3147384-8-peter.maydell@linaro.org
11
---
12
hw/intc/xics.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/xics.c
18
+++ b/hw/intc/xics.c
19
@@ -XXX,XX +XXX,XX @@ static void ics_reset_irq(ICSIRQState *irq)
20
static void ics_reset(DeviceState *dev)
21
{
22
ICSState *ics = ICS(dev);
23
+ g_autofree uint8_t *flags = g_malloc(ics->nr_irqs);
24
int i;
25
- uint8_t flags[ics->nr_irqs];
26
27
for (i = 0; i < ics->nr_irqs; i++) {
28
flags[i] = ics->irqs[i].flags;
29
--
30
2.25.1
31
32
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Use autofree heap allocation instead of variable-length array on
4
the stack. Replace the snprintf() call by g_strdup_printf().
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220819153931.3147384-9-peter.maydell@linaro.org
10
---
11
hw/i386/multiboot.c | 5 ++---
12
1 file changed, 2 insertions(+), 3 deletions(-)
13
14
diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/i386/multiboot.c
17
+++ b/hw/i386/multiboot.c
18
@@ -XXX,XX +XXX,XX @@ int load_multiboot(X86MachineState *x86ms,
19
uint8_t *mb_bootinfo_data;
20
uint32_t cmdline_len;
21
GList *mods = NULL;
22
+ g_autofree char *kcmdline = NULL;
23
24
/* Ok, let's see if it is a multiboot image.
25
The header is 12x32bit long, so the latest entry may be 8192 - 48. */
26
@@ -XXX,XX +XXX,XX @@ int load_multiboot(X86MachineState *x86ms,
27
}
28
29
/* Commandline support */
30
- char kcmdline[strlen(kernel_filename) + strlen(kernel_cmdline) + 2];
31
- snprintf(kcmdline, sizeof(kcmdline), "%s %s",
32
- kernel_filename, kernel_cmdline);
33
+ kcmdline = g_strdup_printf("%s %s", kernel_filename, kernel_cmdline);
34
stl_p(bootinfo + MBI_CMDLINE, mb_add_cmdline(&mbs, kcmdline));
35
36
stl_p(bootinfo + MBI_BOOTLOADER, mb_add_bootloader(&mbs, bootloader_name));
37
--
38
2.25.1
39
40
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Use autofree heap allocation instead of variable-length
4
array on the stack.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220819153931.3147384-11-peter.maydell@linaro.org
10
---
11
ui/curses.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/ui/curses.c b/ui/curses.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/ui/curses.c
17
+++ b/ui/curses.c
18
@@ -XXX,XX +XXX,XX @@ static void curses_update(DisplayChangeListener *dcl,
19
int x, int y, int w, int h)
20
{
21
console_ch_t *line;
22
- cchar_t curses_line[width];
23
+ g_autofree cchar_t *curses_line = g_new(cchar_t, width);
24
wchar_t wch[CCHARW_MAX];
25
attr_t attrs;
26
short colors;
27
--
28
2.25.1
29
30
diff view generated by jsdifflib
Deleted patch
1
Shellcheck correctly reports that we set python_version and never use
2
it. This is a leftover from commit f9332757898a7: we used to use
3
python_version purely to as part of the summary information printed
4
at the end of a configure run, and that commit changed to printing
5
the information from meson (which looks up the python version
6
itself). Remove the unused variable.
7
1
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20220825150703.4074125-2-peter.maydell@linaro.org
12
---
13
configure | 3 ---
14
1 file changed, 3 deletions(-)
15
16
diff --git a/configure b/configure
17
index XXXXXXX..XXXXXXX 100755
18
--- a/configure
19
+++ b/configure
20
@@ -XXX,XX +XXX,XX @@ if ! $python -c 'import sys; sys.exit(sys.version_info < (3,6))'; then
21
"Use --python=/path/to/python to specify a supported Python."
22
fi
23
24
-# Preserve python version since some functionality is dependent on it
25
-python_version=$($python -c 'import sys; print("%d.%d.%d" % (sys.version_info[0], sys.version_info[1], sys.version_info[2]))' 2>/dev/null)
26
-
27
# Suppress writing compiled files
28
python="$python -B"
29
30
--
31
2.25.1
32
33
diff view generated by jsdifflib