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[PATCH 2/5] target/loongarch: bstrins.w need set dest register EXT_SIGN

Song Gao posted 5 patches 3 years, 4 months ago
Maintainers: Song Gao <gaosong@loongson.cn>, Xiaojuan Yang <yangxiaojuan@loongson.cn>
[PATCH 2/5] target/loongarch: bstrins.w need set dest register EXT_SIGN
Posted by Song Gao 3 years, 4 months ago 
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/insn_trans/trans_bit.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc
index 9337714ec4..33e94878fd 100644
--- a/target/loongarch/insn_trans/trans_bit.c.inc
+++ b/target/loongarch/insn_trans/trans_bit.c.inc
@@ -37,7 +37,7 @@ static bool gen_rr_ms_ls(DisasContext *ctx, arg_rr_ms_ls *a,
                          DisasExtend src_ext, DisasExtend dst_ext,
                          void (*func)(TCGv, TCGv, unsigned int, unsigned int))
 {
-    TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
+    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
     TCGv src1 = gpr_src(ctx, a->rj, src_ext);
 
     if (a->ls > a->ms) {
@@ -206,7 +206,7 @@ TRANS(maskeqz, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
 TRANS(masknez, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
 TRANS(bytepick_w, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
 TRANS(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
-TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
+TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, gen_bstrins)
 TRANS(bstrins_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
 TRANS(bstrpick_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, tcg_gen_extract_tl)
 TRANS(bstrpick_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, tcg_gen_extract_tl)
-- 
2.31.1
Re: [PATCH 2/5] target/loongarch: bstrins.w need set dest register EXT_SIGN
Posted by Qi Hu 3 years, 4 months ago 
On 2022/9/17 15:59, Song Gao wrote:
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
>   target/loongarch/insn_trans/trans_bit.c.inc | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc
> index 9337714ec4..33e94878fd 100644
> --- a/target/loongarch/insn_trans/trans_bit.c.inc
> +++ b/target/loongarch/insn_trans/trans_bit.c.inc
> @@ -37,7 +37,7 @@ static bool gen_rr_ms_ls(DisasContext *ctx, arg_rr_ms_ls *a,
>                            DisasExtend src_ext, DisasExtend dst_ext,
>                            void (*func)(TCGv, TCGv, unsigned int, unsigned int))
>   {
> -    TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
> +    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
I think this may not be correct. Maybe the code was used for debugging 
but forgot to modify?
>       TCGv src1 = gpr_src(ctx, a->rj, src_ext);
>   
>       if (a->ls > a->ms) {
> @@ -206,7 +206,7 @@ TRANS(maskeqz, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
>   TRANS(masknez, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
>   TRANS(bytepick_w, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
>   TRANS(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
> -TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
> +TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, gen_bstrins)
>   TRANS(bstrins_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
>   TRANS(bstrpick_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, tcg_gen_extract_tl)
>   TRANS(bstrpick_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, tcg_gen_extract_tl)
Re: [PATCH 2/5] target/loongarch: bstrins.w need set dest register EXT_SIGN
Posted by gaosong 3 years, 4 months ago 
在 2022/9/17 下午4:41, Qi Hu 写道:
>
> On 2022/9/17 15:59, Song Gao wrote:
>> Signed-off-by: Song Gao <gaosong@loongson.cn>
>> ---
>>   target/loongarch/insn_trans/trans_bit.c.inc | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/loongarch/insn_trans/trans_bit.c.inc 
>> b/target/loongarch/insn_trans/trans_bit.c.inc
>> index 9337714ec4..33e94878fd 100644
>> --- a/target/loongarch/insn_trans/trans_bit.c.inc
>> +++ b/target/loongarch/insn_trans/trans_bit.c.inc
>> @@ -37,7 +37,7 @@ static bool gen_rr_ms_ls(DisasContext *ctx, 
>> arg_rr_ms_ls *a,
>>                            DisasExtend src_ext, DisasExtend dst_ext,
>>                            void (*func)(TCGv, TCGv, unsigned int, 
>> unsigned int))
>>   {
>> -    TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
>> +    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
> I think this may not be correct. Maybe the code was used for debugging 
> but forgot to modify?
We just need EXT_SIGN  the result.
>>       TCGv src1 = gpr_src(ctx, a->rj, src_ext);
>>         if (a->ls > a->ms) {
>> @@ -206,7 +206,7 @@ TRANS(maskeqz, gen_rrr, EXT_NONE, EXT_NONE, 
>> EXT_NONE, gen_maskeqz)
>>   TRANS(masknez, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
>>   TRANS(bytepick_w, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
>>   TRANS(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
>> -TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
>> +TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, gen_bstrins)
>>   TRANS(bstrins_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
>>   TRANS(bstrpick_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, 
>> tcg_gen_extract_tl)
>>   TRANS(bstrpick_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, 
>> tcg_gen_extract_tl)
>
Re: [PATCH 2/5] target/loongarch: bstrins.w need set dest register EXT_SIGN
Posted by Qi Hu 3 years, 4 months ago 
On 2022/9/17 17:16, gaosong wrote:
>
> 在 2022/9/17 下午4:41, Qi Hu 写道:
>>
>> On 2022/9/17 15:59, Song Gao wrote:
>>> Signed-off-by: Song Gao <gaosong@loongson.cn>
>>> ---
>>>   target/loongarch/insn_trans/trans_bit.c.inc | 4 ++--
>>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/target/loongarch/insn_trans/trans_bit.c.inc 
>>> b/target/loongarch/insn_trans/trans_bit.c.inc
>>> index 9337714ec4..33e94878fd 100644
>>> --- a/target/loongarch/insn_trans/trans_bit.c.inc
>>> +++ b/target/loongarch/insn_trans/trans_bit.c.inc
>>> @@ -37,7 +37,7 @@ static bool gen_rr_ms_ls(DisasContext *ctx, 
>>> arg_rr_ms_ls *a,
>>>                            DisasExtend src_ext, DisasExtend dst_ext,
>>>                            void (*func)(TCGv, TCGv, unsigned int, 
>>> unsigned int))
>>>   {
>>> -    TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
>>> +    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
>> I think this may not be correct. Maybe the code was used for 
>> debugging but forgot to modify?
> We just need EXT_SIGN  the result.

Got it. Thanks.

Qi

>>>       TCGv src1 = gpr_src(ctx, a->rj, src_ext);
>>>         if (a->ls > a->ms) {
>>> @@ -206,7 +206,7 @@ TRANS(maskeqz, gen_rrr, EXT_NONE, EXT_NONE, 
>>> EXT_NONE, gen_maskeqz)
>>>   TRANS(masknez, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
>>>   TRANS(bytepick_w, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
>>>   TRANS(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
>>> -TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
>>> +TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, gen_bstrins)
>>>   TRANS(bstrins_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
>>>   TRANS(bstrpick_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, 
>>> tcg_gen_extract_tl)
>>>   TRANS(bstrpick_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, 
>>> tcg_gen_extract_tl)
>>
>

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