We can use alternate stack, so that we can use sp register as intput/ouput register.
I had tested aarch64/LoongArch architecture.

Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 risu.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/risu.c b/risu.c
index 1c096a8..714074e 100644
--- a/risu.c
+++ b/risu.c
@@ -329,7 +329,7 @@ static void set_sigill_handler(void (*fn) (int, siginfo_t *, void *))
     memset(&sa, 0, sizeof(struct sigaction));
 
     sa.sa_sigaction = fn;
-    sa.sa_flags = SA_SIGINFO;
+    sa.sa_flags = SA_SIGINFO | SA_ONSTACK;
     sigemptyset(&sa.sa_mask);
     if (sigaction(SIGILL, &sa, 0) != 0) {
         perror("sigaction");
@@ -550,6 +550,7 @@ int main(int argc, char **argv)
     char *trace_fn = NULL;
     struct option *longopts;
     char *shortopts;
+    stack_t ss;
 
     longopts = setup_options(&shortopts);
 
@@ -617,6 +618,19 @@ int main(int argc, char **argv)
 
     load_image(imgfile);
 
+    /* create alternate stack */
+    ss.ss_sp = malloc(SIGSTKSZ);
+    if (ss.ss_sp == NULL) {
+        perror("malloc");
+        exit(EXIT_FAILURE);
+    }
+    ss.ss_size = SIGSTKSZ;
+    ss.ss_flags = 0;
+    if (sigaltstack(&ss, NULL) == -1) {
+        perror("sigaltstac");
+        exit(EXIT_FAILURE);
+    }
+
     /* E.g. select requested SVE vector length. */
     arch_init();
 
-- 
2.31.1

On 9/17/22 00:43, Song Gao wrote:
> We can use alternate stack, so that we can use sp register as intput/ouput register.
> I had tested aarch64/LoongArch architecture.
> 
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> ---
>   risu.c | 16 +++++++++++++++-
>   1 file changed, 15 insertions(+), 1 deletion(-)

Good idea.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

On Mon, 10 Oct 2022 at 15:20, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 9/17/22 00:43, Song Gao wrote:
> > We can use alternate stack, so that we can use sp register as intput/ouput register.
> > I had tested aarch64/LoongArch architecture.
> >
> > Signed-off-by: Song Gao<gaosong@loongson.cn>
> > ---
> >   risu.c | 16 +++++++++++++++-
> >   1 file changed, 15 insertions(+), 1 deletion(-)
>
> Good idea.

Depending on the architecture there might still need to be
restrictions on use of the stack pointer, eg aarch64's
alignment requirements, but this at least means you can
in theory write some risu rules that use SP.

-- PMM

在 2022/10/10 22:43, Peter Maydell 写道:
> On Mon, 10 Oct 2022 at 15:20, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>> On 9/17/22 00:43, Song Gao wrote:
>>> We can use alternate stack, so that we can use sp register as intput/ouput register.
>>> I had tested aarch64/LoongArch architecture.
>>>
>>> Signed-off-by: Song Gao<gaosong@loongson.cn>
>>> ---
>>>    risu.c | 16 +++++++++++++++-
>>>    1 file changed, 15 insertions(+), 1 deletion(-)
>> Good idea.
> Depending on the architecture there might still need to be
> restrictions on use of the stack pointer, eg aarch64's
> alignment requirements, but this at least means you can
> in theory write some risu rules that use SP.
I really want use alternate stack, this way can reduce risu rules.
what about use this only on LoongArch architecture ?

Thanks.
Song Gao

On Tue, 11 Oct 2022 at 07:57, gaosong <gaosong@loongson.cn> wrote:
>
>
> 在 2022/10/10 22:43, Peter Maydell 写道:
> > On Mon, 10 Oct 2022 at 15:20, Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >> On 9/17/22 00:43, Song Gao wrote:
> >>> We can use alternate stack, so that we can use sp register as intput/ouput register.
> >>> I had tested aarch64/LoongArch architecture.
> >>>
> >>> Signed-off-by: Song Gao<gaosong@loongson.cn>
> >>> ---
> >>>    risu.c | 16 +++++++++++++++-
> >>>    1 file changed, 15 insertions(+), 1 deletion(-)
> >> Good idea.
> > Depending on the architecture there might still need to be
> > restrictions on use of the stack pointer, eg aarch64's
> > alignment requirements, but this at least means you can
> > in theory write some risu rules that use SP.
> I really want use alternate stack, this way can reduce risu rules.
> what about use this only on LoongArch architecture ?

I just mean that although this patch is fine it might
still mean that depending on the architecture some care
and/or special casing of sp in the target risu rules
might be needed. I don't know if that applies to
loongarch or not.

-- PMM