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[PATCH v4 0/7] tcg: pc-relative translation blocks

Richard Henderson posted 7 patches 1 year, 7 months ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20220906091126.298041-1-richard.henderson@linaro.org
Maintainers: Richard Henderson <richard.henderson@linaro.org>, Paolo Bonzini <pbonzini@redhat.com>, Eduardo Habkost <eduardo@habkost.net>, Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, Yanan Wang <wangyanan55@huawei.com>, Peter Maydell <peter.maydell@linaro.org>, Michael Rolnik <mrolnik@gmail.com>, Taylor Simpson <tsimpson@quicinc.com>, Song Gao <gaosong@loongson.cn>, Xiaojuan Yang <yangxiaojuan@loongson.cn>, "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, Aurelien Jarno <aurelien@aurel32.net>, Jiaxun Yang <jiaxun.yang@flygoat.com>, Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>, Stafford Horne <shorne@gmail.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Yoshinori Sato <ysato@users.sourceforge.jp>, Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>, Artyom Tarasenko <atar4qemu@gmail.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
include/exec/cpu-defs.h                 |   3 +
include/exec/exec-all.h                 |  51 ++++++++++-
include/exec/plugin-gen.h               |   7 +-
include/hw/core/cpu.h                   |   9 +-
accel/tcg/cpu-exec.c                    | 108 ++++++++++++++++--------
accel/tcg/cputlb.c                      |   5 +-
accel/tcg/plugin-gen.c                  |  22 ++---
accel/tcg/translate-all.c               |  90 ++++++++++++--------
accel/tcg/translator.c                  |   2 +-
target/arm/cpu.c                        |   4 +-
target/avr/cpu.c                        |   2 +-
target/hexagon/cpu.c                    |   2 +-
target/hppa/cpu.c                       |   4 +-
target/i386/tcg/tcg-cpu.c               |   2 +-
target/loongarch/cpu.c                  |   2 +-
target/microblaze/cpu.c                 |   2 +-
target/mips/tcg/exception.c             |   2 +-
target/mips/tcg/sysemu/special_helper.c |   2 +-
target/openrisc/cpu.c                   |   2 +-
target/riscv/cpu.c                      |   4 +-
target/rx/cpu.c                         |   2 +-
target/sh4/cpu.c                        |   4 +-
target/sparc/cpu.c                      |   2 +-
target/tricore/cpu.c                    |   2 +-
tcg/tcg.c                               |   6 +-
25 files changed, 226 insertions(+), 115 deletions(-)
[PATCH v4 0/7] tcg: pc-relative translation blocks
Posted by Richard Henderson 1 year, 7 months ago 
The goal here is to reduce the amount of code generation when the
guest kernel enables address space randomization.  This requires
extensive changes to each target, so opt-in with TARGET_TB_PCREL.

This is split out of v3, which also contained target/arm changes,
as I now have patches for x86 and s390x as well.


r~


Based-on: 20220905202259.189852-1-richard.henderson@linaro.org
("[PATCH v3 0/6] tcg: Introduce CPUTLBEntryFull")

v2: https://lore.kernel.org/qemu-devel/20220816203400.161187-1-richard.henderson@linaro.org/
v3: https://lore.kernel.org/qemu-devel/20220822232338.1727934-1-richard.henderson@linaro.org/

branch: https://gitlab.com/rth7680/qemu/-/tree/tcg-pcrel


Richard Henderson (7):
  accel/tcg: Use bool for page_find_alloc
  accel/tcg: Use DisasContextBase in plugin_gen_tb_start
  accel/tcg: Do not align tb->page_addr[0]
  include/hw/core: Create struct CPUJumpCache
  accel/tcg: Introduce tb_pc and tb_pc_log
  accel/tcg: Introduce TARGET_TB_PCREL
  accel/tcg: Split log_cpu_exec into inline and slow path

 include/exec/cpu-defs.h                 |   3 +
 include/exec/exec-all.h                 |  51 ++++++++++-
 include/exec/plugin-gen.h               |   7 +-
 include/hw/core/cpu.h                   |   9 +-
 accel/tcg/cpu-exec.c                    | 108 ++++++++++++++++--------
 accel/tcg/cputlb.c                      |   5 +-
 accel/tcg/plugin-gen.c                  |  22 ++---
 accel/tcg/translate-all.c               |  90 ++++++++++++--------
 accel/tcg/translator.c                  |   2 +-
 target/arm/cpu.c                        |   4 +-
 target/avr/cpu.c                        |   2 +-
 target/hexagon/cpu.c                    |   2 +-
 target/hppa/cpu.c                       |   4 +-
 target/i386/tcg/tcg-cpu.c               |   2 +-
 target/loongarch/cpu.c                  |   2 +-
 target/microblaze/cpu.c                 |   2 +-
 target/mips/tcg/exception.c             |   2 +-
 target/mips/tcg/sysemu/special_helper.c |   2 +-
 target/openrisc/cpu.c                   |   2 +-
 target/riscv/cpu.c                      |   4 +-
 target/rx/cpu.c                         |   2 +-
 target/sh4/cpu.c                        |   4 +-
 target/sparc/cpu.c                      |   2 +-
 target/tricore/cpu.c                    |   2 +-
 tcg/tcg.c                               |   6 +-
 25 files changed, 226 insertions(+), 115 deletions(-)

-- 
2.34.1
Re: [PATCH v4 0/7] tcg: pc-relative translation blocks
Posted by Richard Henderson 1 year, 7 months ago 
On 9/6/22 10:11, Richard Henderson wrote:
> The goal here is to reduce the amount of code generation when the
> guest kernel enables address space randomization.  This requires
> extensive changes to each target, so opt-in with TARGET_TB_PCREL.
> 
> This is split out of v3, which also contained target/arm changes,
> as I now have patches for x86 and s390x as well.
> 
> 
> r~
> 
> 
> Based-on: 20220905202259.189852-1-richard.henderson@linaro.org
> ("[PATCH v3 0/6] tcg: Introduce CPUTLBEntryFull")
> 
> v2: https://lore.kernel.org/qemu-devel/20220816203400.161187-1-richard.henderson@linaro.org/
> v3: https://lore.kernel.org/qemu-devel/20220822232338.1727934-1-richard.henderson@linaro.org/
> 
> branch: https://gitlab.com/rth7680/qemu/-/tree/tcg-pcrel

Arg.  Accidentally dropped a patch from v3:


> 
> 
> Richard Henderson (7):
>    accel/tcg: Use bool for page_find_alloc
>    accel/tcg: Use DisasContextBase in plugin_gen_tb_start
>    accel/tcg: Do not align tb->page_addr[0]
>    include/hw/core: Create struct CPUJumpCache
>    accel/tcg: Introduce tb_pc and tb_pc_log
>    accel/tcg: Introduce TARGET_TB_PCREL
>    accel/tcg: Split log_cpu_exec into inline and slow path
> 
>   include/exec/cpu-defs.h                 |   3 +
>   include/exec/exec-all.h                 |  51 ++++++++++-
>   include/exec/plugin-gen.h               |   7 +-
>   include/hw/core/cpu.h                   |   9 +-
>   accel/tcg/cpu-exec.c                    | 108 ++++++++++++++++--------
>   accel/tcg/cputlb.c                      |   5 +-
>   accel/tcg/plugin-gen.c                  |  22 ++---
>   accel/tcg/translate-all.c               |  90 ++++++++++++--------
>   accel/tcg/translator.c                  |   2 +-
>   target/arm/cpu.c                        |   4 +-
>   target/avr/cpu.c                        |   2 +-
>   target/hexagon/cpu.c                    |   2 +-
>   target/hppa/cpu.c                       |   4 +-
>   target/i386/tcg/tcg-cpu.c               |   2 +-
>   target/loongarch/cpu.c                  |   2 +-
>   target/microblaze/cpu.c                 |   2 +-
>   target/mips/tcg/exception.c             |   2 +-
>   target/mips/tcg/sysemu/special_helper.c |   2 +-
>   target/openrisc/cpu.c                   |   2 +-
>   target/riscv/cpu.c                      |   4 +-
>   target/rx/cpu.c                         |   2 +-
>   target/sh4/cpu.c                        |   4 +-
>   target/sparc/cpu.c                      |   2 +-
>   target/tricore/cpu.c                    |   2 +-
>   tcg/tcg.c                               |   6 +-
>   25 files changed, 226 insertions(+), 115 deletions(-)
>
Re: [PATCH v4 0/7] tcg: pc-relative translation blocks
Posted by Richard Henderson 1 year, 7 months ago 
On 9/6/22 10:28, Richard Henderson wrote:
> On 9/6/22 10:11, Richard Henderson wrote:
>> The goal here is to reduce the amount of code generation when the
>> guest kernel enables address space randomization.  This requires
>> extensive changes to each target, so opt-in with TARGET_TB_PCREL.
>>
>> This is split out of v3, which also contained target/arm changes,
>> as I now have patches for x86 and s390x as well.
>>
>>
>> r~
>>
>>
>> Based-on: 20220905202259.189852-1-richard.henderson@linaro.org
>> ("[PATCH v3 0/6] tcg: Introduce CPUTLBEntryFull")
>>
>> v2: 
>> https://lore.kernel.org/qemu-devel/20220816203400.161187-1-richard.henderson@linaro.org/
>> v3: 
>> https://lore.kernel.org/qemu-devel/20220822232338.1727934-1-richard.henderson@linaro.org/
>>
>> branch: https://gitlab.com/rth7680/qemu/-/tree/tcg-pcrel
> 
> Arg.  Accidentally dropped a patch from v3:

... and managed to hit ctrl-enter while pasting ...

https://lore.kernel.org/qemu-devel/20220822232338.1727934-2-richard.henderson@linaro.org/


r~

Patchew 2.1-devel-0870f84

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