Previously address is set by default value 0x1000 which is hardcoded in target/riscv/cpu_bits.h
If add to new RISC-V Machine in which ROM area is based on 0x1000 address than there is problem of running simulation
Signed-off-by: Maksim Perov <coder@frtk.ru>
---
hw/riscv/boot.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 06b4fc5ac3..5e2438d39a 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -327,6 +327,10 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
kernel_entry);
+ /* change reset vector address */
+ for (i = 0; i < harts->num_harts; i++) {
+ harts->harts[i].env.resetvec = rom_base;
+ }
return;
}
--
2.17.1