Series comparison

-[PULL 0/5] target-arm queue
+[PULL 00/30] target-arm queue
-This pullreq has:
+The following changes since commit 003ba52a8b327180e284630b289c6ece5a3e08b9:
  * two arm bug fixes which fix some "Linux fails to boot" bugs
  * a docs typo-fixing patch
  * a couple of compile failure/warning issues
-I think they're all pretty safe and worth having in rc3.
+  Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-02-16 11:16:39 +0000)
 thanks
 -- PMM
 The following changes since commit a6b1c53e79d08a99a28cc3e67a3e1a7c34102d6b:
   Merge tag 'linux-user-for-7.1-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2022-08-10 10:26:57 -0700)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220812
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230216
-for you to fetch changes up to 4311682ea8293f720730f260e8a7601117d79e65:
+for you to fetch changes up to caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8:
-  cutils: Add missing dyld(3) include on macOS (2022-08-12 11:33:52 +0100)
+  tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG (2023-02-16 16:28:53 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * Don't report Statistical Profiling Extension in ID registers
+ * Some mostly M-profile-related code cleanups
- * virt ACPI tables: Present the GICR structure properly for GICv4
+ * avocado: Retire the boot_linux.py AArch64 TCG tests
- * Fix some typos in documentation
+ * hw/arm/smmuv3: Add GBPA register
- * tests/unit: fix a -Wformat-truncation warning
+ * arm/virt: don't try to spell out the accelerator
- * cutils: Add missing dyld(3) include on macOS
+ * hw/arm: Attach PSPI module to NPCM7XX SoC
  * Some cleanup/refactoring patches aiming towards
    allowing building Arm targets without CONFIG_TCG
 ----------------------------------------------------------------
-Marc-André Lureau (1):
+Alex Bennée (1):
-      tests/unit: fix a -Wformat-truncation warning
+      tests/avocado: retire the Aarch64 TCG tests from boot_linux.py
-Peter Maydell (1):
+Claudio Fontana (3):
-      target/arm: Don't report Statistical Profiling Extension in ID registers
+      target/arm: rename handle_semihosting to tcg_handle_semihosting
       target/arm: wrap psci call with tcg_enabled
       target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()
-Philippe Mathieu-Daudé (1):
+Cornelia Huck (1):
-      cutils: Add missing dyld(3) include on macOS
+      arm/virt: don't try to spell out the accelerator
-Stefan Weil (1):
+Fabiano Rosas (7):
-      Fix some typos in documentation (most of them found by codespell)
+      target/arm: Move PC alignment check
       target/arm: Move cpregs code out of cpu.h
       tests/avocado: Skip tests that require a missing accelerator
       tests/avocado: Tag TCG tests with accel:tcg
       target/arm: Use "max" as default cpu for the virt machine with KVM
       tests/qtest: arm-cpu-features: Match tests to required accelerators
       tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
-Zenghui Yu (1):
+Hao Wu (3):
-      hw/arm/virt-acpi-build: Present the GICR structure properly for GICv4
+      MAINTAINERS: Add myself to maintainers and remove Havard
       hw/ssi: Add Nuvoton PSPI Module
       hw/arm: Attach PSPI module to NPCM7XX SoC
- docs/about/deprecated.rst               |  2 +-
+Jean-Philippe Brucker (2):
- docs/specs/acpi_erst.rst                |  4 ++--
+      hw/arm/smmu-common: Support 64-bit addresses
- docs/system/devices/canokey.rst         |  8 ++++----
+      hw/arm/smmu-common: Fix TTB1 handling
  docs/system/devices/cxl.rst             | 12 ++++++------
  hw/arm/virt-acpi-build.c                |  4 ++--
  target/arm/cpu.c                        | 11 +++++++++++
  tests/unit/test-qobject-input-visitor.c |  3 +--
  util/cutils.c                           |  4 ++++
  util/oslib-posix.c                      |  4 ----
 files changed, 31 insertions(+), 21 deletions(-)
+Mostafa Saleh (1):
+      hw/arm/smmuv3: Add GBPA register
+Philippe Mathieu-Daudé (12):
+      hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro
+      target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation
+      target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope
+      target/arm: Constify ID_PFR1 on user emulation
+      target/arm: Convert CPUARMState::eabi to boolean
+      target/arm: Avoid resetting CPUARMState::eabi field
+      target/arm: Restrict CPUARMState::gicv3state to sysemu
+      target/arm: Restrict CPUARMState::arm_boot_info to sysemu
+      target/arm: Restrict CPUARMState::nvic to sysemu
+      target/arm: Store CPUARMState::nvic as NVICState*
+      target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
+      hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency
+ MAINTAINERS                            |   8 +-
+ docs/system/arm/nuvoton.rst            |   2 +-
+ hw/arm/smmuv3-internal.h               |   7 +
+ include/hw/arm/npcm7xx.h               |   2 +
+ include/hw/arm/smmu-common.h           |   2 -
+ include/hw/arm/smmuv3.h                |   1 +
+ include/hw/intc/armv7m_nvic.h          | 128 +++++++++++++++++-
+ include/hw/ssi/npcm_pspi.h             |  53 ++++++++
+ linux-user/user-internals.h            |   2 +-
+ target/arm/cpregs.h                    |  98 ++++++++++++++
+ target/arm/cpu.h                       | 228 ++-------------------------------
+ target/arm/internals.h                 |  14 --
+ hw/arm/npcm7xx.c                       |  25 +++-
+ hw/arm/smmu-common.c                   |   4 +-
+ hw/arm/smmuv3.c                        |  43 ++++++-
+ hw/arm/virt.c                          |  10 +-
+ hw/intc/armv7m_nvic.c                  |  38 ++----
+ hw/ssi/npcm_pspi.c                     | 221 ++++++++++++++++++++++++++++++++
+ linux-user/arm/cpu_loop.c              |   4 +-
+ target/arm/cpu.c                       |   5 +-
+ target/arm/cpu_tcg.c                   |   3 +
+ target/arm/helper.c                    |  31 +++--
+ target/arm/m_helper.c                  |  86 +++++++------
+ target/arm/machine.c                   |  18 +--
+ tests/qtest/arm-cpu-features.c         |  28 ++--
+ hw/arm/Kconfig                         |   1 +
+ hw/ssi/meson.build                     |   2 +-
+ hw/ssi/trace-events                    |   5 +
+ tests/avocado/avocado_qemu/__init__.py |   4 +
+ tests/avocado/boot_linux.py            |  48 ++-----
+ tests/avocado/boot_linux_console.py    |   1 +
+ tests/avocado/machine_aarch64_virt.py  |  63 ++++++++-
+ tests/avocado/reverse_debugging.py     |   8 ++
+ tests/qtest/meson.build                |   4 +-
+files changed, 798 insertions(+), 399 deletions(-)
+ create mode 100644 include/hw/ssi/npcm_pspi.h
+ create mode 100644 hw/ssi/npcm_pspi.c

-New patch
+[PULL 01/30] hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro,
+similarly to automatic conversion from commit 8063396bf3
+("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-2-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/intc/armv7m_nvic.h | 5 +----
+file changed, 1 insertion(+), 4 deletions(-)
+diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/intc/armv7m_nvic.h
++++ b/include/hw/intc/armv7m_nvic.h
+@@ -XXX,XX +XXX,XX @@
+ #include "qom/object.h"
+ #define TYPE_NVIC "armv7m_nvic"
+-
+-typedef struct NVICState NVICState;
+-DECLARE_INSTANCE_CHECKER(NVICState, NVIC,
+-                         TYPE_NVIC)
++OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC)
+ /* Highest permitted number of exceptions (architectural limit) */
+ #define NVIC_MAX_VECTORS 512
+--
+.34.1

-New patch
+[PULL 02/30] target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Suggested-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-3-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/m_helper.c | 11 ++++++++---
+file changed, 8 insertions(+), 3 deletions(-)
+diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/m_helper.c
++++ b/target/arm/m_helper.c
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
+     return 0;
+ }
+-#else
++ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
++{
++    return ARMMMUIdx_MUser;
++}
++
++#else /* !CONFIG_USER_ONLY */
+ /*
+  * What kind of stack write are we doing? This affects how exceptions
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
+     return tt_resp;
+ }
+-#endif /* !CONFIG_USER_ONLY */
+-
+ ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+                               bool secstate, bool priv, bool negpri)
+ {
+@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+     return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
+ }
++
++#endif /* !CONFIG_USER_ONLY */
+--
+.34.1

-New patch
+[PULL 03/30] target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv()
+are only used for system emulation in m_helper.c.
+Move the definitions to avoid prototype forward declarations.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-4-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/internals.h | 14 --------
+ target/arm/m_helper.c  | 74 +++++++++++++++++++++---------------------
+files changed, 37 insertions(+), 51 deletions(-)
+diff --git a/target/arm/internals.h b/target/arm/internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/internals.h
++++ b/target/arm/internals.h
+@@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx)
+ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
+-/*
+- * Return the MMU index for a v7M CPU with all relevant information
+- * manually specified.
+- */
+-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+-                              bool secstate, bool priv, bool negpri);
+-
+-/*
+- * Return the MMU index for a v7M CPU in the specified security and
+- * privilege state.
+- */
+-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+-                                                bool secstate, bool priv);
+-
+ /* Return the MMU index for a v7M CPU in the specified security state */
+ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
+diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/m_helper.c
++++ b/target/arm/m_helper.c
+@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+ #else /* !CONFIG_USER_ONLY */
++static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
++                                     bool secstate, bool priv, bool negpri)
++{
++    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
++
++    if (priv) {
++        mmu_idx |= ARM_MMU_IDX_M_PRIV;
++    }
++
++    if (negpri) {
++        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
++    }
++
++    if (secstate) {
++        mmu_idx |= ARM_MMU_IDX_M_S;
++    }
++
++    return mmu_idx;
++}
++
++static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
++                                                       bool secstate, bool priv)
++{
++    bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
++
++    return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
++}
++
++/* Return the MMU index for a v7M CPU in the specified security state */
++ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
++{
++    bool priv = arm_v7m_is_handler_mode(env) ||
++        !(env->v7m.control[secstate] & 1);
++
++    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
++}
++
+ /*
+  * What kind of stack write are we doing? This affects how exceptions
+  * generated during the stacking are treated.
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
+     return tt_resp;
+ }
+-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+-                              bool secstate, bool priv, bool negpri)
+-{
+-    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
+-
+-    if (priv) {
+-        mmu_idx |= ARM_MMU_IDX_M_PRIV;
+-    }
+-
+-    if (negpri) {
+-        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
+-    }
+-
+-    if (secstate) {
+-        mmu_idx |= ARM_MMU_IDX_M_S;
+-    }
+-
+-    return mmu_idx;
+-}
+-
+-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+-                                                bool secstate, bool priv)
+-{
+-    bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
+-
+-    return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
+-}
+-
+-/* Return the MMU index for a v7M CPU in the specified security state */
+-ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+-{
+-    bool priv = arm_v7m_is_handler_mode(env) ||
+-        !(env->v7m.control[secstate] & 1);
+-
+-    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
+-}
+-
+ #endif /* !CONFIG_USER_ONLY */
+--
+.34.1

-New patch
+[PULL 04/30] target/arm: Constify ID_PFR1 on user emulation
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230206223502.25122-5-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/helper.c | 12 ++++++++++--
+file changed, 10 insertions(+), 2 deletions(-)
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
+     }
+ }
++#ifndef CONFIG_USER_ONLY
+ /*
+  * We don't know until after realize whether there's a GICv3
+  * attached, and that is what registers the gicv3 sysregs.
+@@ -XXX,XX +XXX,XX @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
+     return pfr1;
+ }
+-#ifndef CONFIG_USER_ONLY
+ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
+ {
+     ARMCPU *cpu = env_archcpu(env);
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
+               .access = PL1_R, .type = ARM_CP_NO_RAW,
+               .accessfn = access_aa32_tid3,
++#ifdef CONFIG_USER_ONLY
++              .type = ARM_CP_CONST,
++              .resetvalue = cpu->isar.id_pfr1,
++#else
++              .type = ARM_CP_NO_RAW,
++              .accessfn = access_aa32_tid3,
+               .readfn = id_pfr1_read,
+-              .writefn = arm_cp_write_ignore },
++              .writefn = arm_cp_write_ignore
++#endif
++            },
+             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
+               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
+               .access = PL1_R, .type = ARM_CP_CONST,
+--
+.34.1

-New patch
+[PULL 05/30] target/arm: Convert CPUARMState::eabi to boolean
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Suggested-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-6-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ linux-user/user-internals.h | 2 +-
+ target/arm/cpu.h            | 2 +-
+ linux-user/arm/cpu_loop.c   | 4 ++--
+files changed, 4 insertions(+), 4 deletions(-)
+diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/linux-user/user-internals.h
++++ b/linux-user/user-internals.h
+@@ -XXX,XX +XXX,XX @@ void print_termios(void *arg);
+ #ifdef TARGET_ARM
+ static inline int regpairs_aligned(CPUArchState *cpu_env, int num)
+ {
+-    return cpu_env->eabi == 1;
++    return cpu_env->eabi;
+ }
+ #elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32)
+ static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; }
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+ #if defined(CONFIG_USER_ONLY)
+     /* For usermode syscall translation.  */
+-    int eabi;
++    bool eabi;
+ #endif
+     struct CPUBreakpoint *cpu_breakpoint[16];
+diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
+index XXXXXXX..XXXXXXX 100644
+--- a/linux-user/arm/cpu_loop.c
++++ b/linux-user/arm/cpu_loop.c
+@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
+             break;
+         case EXCP_SWI:
+             {
+-                env->eabi = 1;
++                env->eabi = true;
+                 /* system call */
+                 if (env->thumb) {
+                     /* Thumb is always EABI style with syscall number in r7 */
+@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
+                          * > 0xfffff and are handled below as out-of-range.
+                          */
+                         n ^= ARM_SYSCALL_BASE;
+-                        env->eabi = 0;
++                        env->eabi = false;
+                     }
+                 }
+--
+.34.1

-[PULL 5/5] cutils: Add missing dyld(3) include on macOS
+[PULL 06/30] target/arm: Avoid resetting CPUARMState::eabi field
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Commit 06680b15b4 moved qemu_*_exec_dir() to cutils but forgot
+Although the 'eabi' field is only used in user emulation where
-to move the macOS dyld(3) include, resulting in the following
+CPU reset doesn't occur, it doesn't belong to the area to reset.
-error (when building with Homebrew GCC on macOS Monterey 12.4):
+Move it after the 'end_reset_fields' for consistency.
-  [313/1197] Compiling C object libqemuutil.a.p/util_cutils.c.o
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-  FAILED: libqemuutil.a.p/util_cutils.c.o
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-  ../../util/cutils.c:1039:13: error: implicit declaration of function '_NSGetExecutablePath' [-Werror=implicit-function-declaration]
+Message-id: 20230206223502.25122-7-philmd@linaro.org
 |         if (_NSGetExecutablePath(fpath, &len) == 0) {
         |             ^~~~~~~~~~~~~~~~~~~~
   ../../util/cutils.c:1039:13: error: nested extern declaration of '_NSGetExecutablePath' [-Werror=nested-externs]
 Fix by moving the include line to cutils.
 Fixes: 06680b15b4 ("include: move qemu_*_exec_dir() to cutils")
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20220809222046.30812-1-f4bug@amsat.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- util/cutils.c      | 4 ++++
+ target/arm/cpu.h | 9 ++++-----
- util/oslib-posix.c | 4 ----
+file changed, 4 insertions(+), 5 deletions(-)
 files changed, 4 insertions(+), 4 deletions(-)
-diff --git a/util/cutils.c b/util/cutils.c
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/util/cutils.c
+--- a/target/arm/cpu.h
-+++ b/util/cutils.c
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
- #include <kernel/image.h>
+     ARMVectorReg zarray[ARM_MAX_VQ * 16];
  #endif
-+#ifdef __APPLE__
+-#if defined(CONFIG_USER_ONLY)
-+#include <mach-o/dyld.h>
+-    /* For usermode syscall translation.  */
-+#endif
+-    bool eabi;
 +
  #ifdef G_OS_WIN32
  #include <pathcch.h>
  #include <wchar.h>
 diff --git a/util/oslib-posix.c b/util/oslib-posix.c
 index XXXXXXX..XXXXXXX 100644
 --- a/util/oslib-posix.c
 +++ b/util/oslib-posix.c
@@ -XXX,XX +XXX,XX @@
  #include <lwp.h>
  #endif
 -#ifdef __APPLE__
 -#include <mach-o/dyld.h>
 -#endif
 -
- #include "qemu/mmap-alloc.h"
+     struct CPUBreakpoint *cpu_breakpoint[16];
+     struct CPUWatchpoint *cpu_watchpoint[16];
- #ifdef CONFIG_DEBUG_STACK_USAGE
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
      const struct arm_boot_info *boot_info;
      /* Store GICv3CPUState to access from this struct */
      void *gicv3state;
 +#if defined(CONFIG_USER_ONLY)
 +    /* For usermode syscall translation.  */
 +    bool eabi;
 +#endif /* CONFIG_USER_ONLY */
  #ifdef TARGET_TAGGED_ADDRESSES
      /* Linux syscall tagged address support */
 --
-.25.1
+.34.1

-New patch
+[PULL 07/30] target/arm: Restrict CPUARMState::gicv3state to sysemu
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230206223502.25122-8-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 3 ++-
+file changed, 2 insertions(+), 1 deletion(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+     void *nvic;
+     const struct arm_boot_info *boot_info;
++#if !defined(CONFIG_USER_ONLY)
+     /* Store GICv3CPUState to access from this struct */
+     void *gicv3state;
+-#if defined(CONFIG_USER_ONLY)
++#else /* CONFIG_USER_ONLY */
+     /* For usermode syscall translation.  */
+     bool eabi;
+ #endif /* CONFIG_USER_ONLY */
+--
+.34.1

-New patch
+[PULL 08/30] target/arm: Restrict CPUARMState::arm_boot_info to sysemu
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230206223502.25122-9-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+     } sau;
+     void *nvic;
+-    const struct arm_boot_info *boot_info;
+ #if !defined(CONFIG_USER_ONLY)
++    const struct arm_boot_info *boot_info;
+     /* Store GICv3CPUState to access from this struct */
+     void *gicv3state;
+ #else /* CONFIG_USER_ONLY */
+--
+.34.1

-New patch
+[PULL 09/30] target/arm: Restrict CPUARMState::nvic to sysemu
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-10-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+         uint32_t ctrl;
+     } sau;
+-    void *nvic;
+ #if !defined(CONFIG_USER_ONLY)
++    void *nvic;
+     const struct arm_boot_info *boot_info;
+     /* Store GICv3CPUState to access from this struct */
+     void *gicv3state;
+--
+.34.1

-New patch
+[PULL 10/30] target/arm: Store CPUARMState::nvic as NVICState*
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 There is no point in using a void pointer to access the NVIC.
 Use the real type to avoid casting it while debugging.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230206223502.25122-11-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu.h      | 46 ++++++++++++++++++++++---------------------
  hw/intc/armv7m_nvic.c | 38 ++++++++++++-----------------------
  target/arm/cpu.c      |  1 +
  target/arm/m_helper.c |  2 +-
 files changed, 39 insertions(+), 48 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMTBFlags {
  typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
 +typedef struct NVICState NVICState;
 +
  typedef struct CPUArchState {
      /* Regs for current mode.  */
      uint32_t regs[16];
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
      } sau;
  #if !defined(CONFIG_USER_ONLY)
 -    void *nvic;
 +    NVICState *nvic;
      const struct arm_boot_info *boot_info;
      /* Store GICv3CPUState to access from this struct */
      void *gicv3state;
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
  /* Interface between CPU and Interrupt controller.  */
  #ifndef CONFIG_USER_ONLY
 -bool armv7m_nvic_can_take_pending_exception(void *opaque);
 +bool armv7m_nvic_can_take_pending_exception(NVICState *s);
  #else
 -static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
 +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
  {
      return true;
  }
  #endif
  /**
   * armv7m_nvic_set_pending: mark the specified exception as pending
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to mark pending
   * @secure: false for non-banked exceptions or for the nonsecure
   * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
   * if @secure is true and @irq does not specify one of the fixed set
   * of architecturally banked exceptions.
   */
 -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
 +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_set_pending_derived: mark this derived exception as pending
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to mark pending
   * @secure: false for non-banked exceptions or for the nonsecure
   * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
   * exceptions (exceptions generated in the course of trying to take
   * a different exception).
   */
 -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
 +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to mark pending
   * @secure: false for non-banked exceptions or for the nonsecure
   * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
   * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
   * generated in the course of lazy stacking of FP registers.
   */
 -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
 +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_get_pending_irq_info: return highest priority pending
   *    exception, and whether it targets Secure state
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @pirq: set to pending exception number
   * @ptargets_secure: set to whether pending exception targets Secure
   *
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
   * to true if the current highest priority pending exception should
   * be taken to Secure state, false for NS.
   */
 -void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
 +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
                                        bool *ptargets_secure);
  /**
   * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
 - * @opaque: the NVIC
 + * @s: the NVIC
   *
   * Move the current highest priority pending exception from the pending
   * state to the active state, and update v7m.exception to indicate that
   * it is the exception currently being handled.
   */
 -void armv7m_nvic_acknowledge_irq(void *opaque);
 +void armv7m_nvic_acknowledge_irq(NVICState *s);
  /**
   * armv7m_nvic_complete_irq: complete specified interrupt or exception
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to complete
   * @secure: true if this exception was secure
   *
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque);
   *           0 if there is still an irq active after this one was completed
   * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
   */
 -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
 +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to mark pending
   * @secure: false for non-banked exceptions or for the nonsecure
   * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
   * interrupt the current execution priority. This controls whether the
   * RDY bit for it in the FPCCR is set.
   */
 -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
 +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_raw_execution_priority: return the raw execution priority
 - * @opaque: the NVIC
 + * @s: the NVIC
   *
   * Returns: the raw execution priority as defined by the v8M architecture.
   * This is the execution priority minus the effects of AIRCR.PRIS,
   * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
   * (v8M ARM ARM I_PKLD.)
   */
 -int armv7m_nvic_raw_execution_priority(void *opaque);
 +int armv7m_nvic_raw_execution_priority(NVICState *s);
  /**
   * armv7m_nvic_neg_prio_requested: return true if the requested execution
   * priority is negative for the specified security state.
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @secure: the security state to test
   * This corresponds to the pseudocode IsReqExecPriNeg().
   */
  #ifndef CONFIG_USER_ONLY
 -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
 +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
  #else
 -static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
 +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
  {
      return false;
  }
 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/armv7m_nvic.c
 +++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
      return MIN(running, s->exception_prio);
  }
 -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
 +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
  {
      /* Return true if the requested execution priority is negative
       * for the specified security state, ie that security state
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
       * mean we don't allow FAULTMASK_NS to actually make the execution
       * priority negative). Compare pseudocode IsReqExcPriNeg().
       */
 -    NVICState *s = opaque;
 -
      if (s->cpu->env.v7m.faultmask[secure]) {
          return true;
      }
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
      return false;
  }
 -bool armv7m_nvic_can_take_pending_exception(void *opaque)
 +bool armv7m_nvic_can_take_pending_exception(NVICState *s)
  {
 -    NVICState *s = opaque;
 -
      return nvic_exec_prio(s) > nvic_pending_prio(s);
  }
 -int armv7m_nvic_raw_execution_priority(void *opaque)
 +int armv7m_nvic_raw_execution_priority(NVICState *s)
  {
 -    NVICState *s = opaque;
 -
      return s->exception_prio;
  }
@@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s)
   * if @secure is true and @irq does not specify one of the fixed set
   * of architecturally banked exceptions.
   */
 -static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
 +static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure)
  {
 -    NVICState *s = (NVICState *)opaque;
      VecInfo *vec;
      assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
@@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
      }
  }
 -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
 +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure)
  {
 -    do_armv7m_nvic_set_pending(opaque, irq, secure, false);
 +    do_armv7m_nvic_set_pending(s, irq, secure, false);
  }
 -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure)
 +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure)
  {
 -    do_armv7m_nvic_set_pending(opaque, irq, secure, true);
 +    do_armv7m_nvic_set_pending(s, irq, secure, true);
  }
 -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
 +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure)
  {
      /*
       * Pend an exception during lazy FP stacking. This differs
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
       * whether we should escalate depends on the saved context
       * in the FPCCR register, not on the current state of the CPU/NVIC.
       */
 -    NVICState *s = (NVICState *)opaque;
      bool banked = exc_is_banked(irq);
      VecInfo *vec;
      bool targets_secure;
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
  }
  /* Make pending IRQ active.  */
 -void armv7m_nvic_acknowledge_irq(void *opaque)
 +void armv7m_nvic_acknowledge_irq(NVICState *s)
  {
 -    NVICState *s = (NVICState *)opaque;
      CPUARMState *env = &s->cpu->env;
      const int pending = s->vectpending;
      const int running = nvic_exec_prio(s);
@@ -XXX,XX +XXX,XX @@ static bool vectpending_targets_secure(NVICState *s)
          exc_targets_secure(s, s->vectpending);
  }
 -void armv7m_nvic_get_pending_irq_info(void *opaque,
 +void armv7m_nvic_get_pending_irq_info(NVICState *s,
                                        int *pirq, bool *ptargets_secure)
  {
 -    NVICState *s = (NVICState *)opaque;
      const int pending = s->vectpending;
      bool targets_secure;
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque,
      *pirq = pending;
  }
 -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
 +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure)
  {
 -    NVICState *s = (NVICState *)opaque;
      VecInfo *vec = NULL;
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
      return ret;
  }
 -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
 +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure)
  {
      /*
       * Return whether an exception is "ready", i.e. it is enabled and is
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
       * for non-banked exceptions secure is always false; for banked exceptions
       * it indicates which of the exceptions is required.
       */
 -    NVICState *s = (NVICState *)opaque;
      bool banked = exc_is_banked(irq);
      VecInfo *vec;
      int running = nvic_exec_prio(s);
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
  #if !defined(CONFIG_USER_ONLY)
  #include "hw/loader.h"
  #include "hw/boards.h"
 +#include "hw/intc/armv7m_nvic.h"
  #endif
  #include "sysemu/tcg.h"
  #include "sysemu/qtest.h"
 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/m_helper.c
 +++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr,
       * that we will need later in order to do lazy FP reg stacking.
       */
      bool is_secure = env->v7m.secure;
 -    void *nvic = env->nvic;
 +    NVICState *nvic = env->nvic;
      /*
       * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits
       * are banked and we want to update the bit in the bank for the
 --
 .34.1

-New patch
+[PULL 11/30] target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 While dozens of files include "cpu.h", only 3 files require
 these NVIC helper declarations.
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20230206223502.25122-12-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++
  target/arm/cpu.h              | 123 ----------------------------------
  target/arm/cpu.c              |   4 +-
  target/arm/cpu_tcg.c          |   3 +
  target/arm/m_helper.c         |   3 +
 files changed, 132 insertions(+), 124 deletions(-)
 diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/intc/armv7m_nvic.h
 +++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@ struct NVICState {
      qemu_irq sysresetreq;
  };
 +/* Interface between CPU and Interrupt controller.  */
 +/**
 + * armv7m_nvic_set_pending: mark the specified exception as pending
 + * @s: the NVIC
 + * @irq: the exception number to mark pending
 + * @secure: false for non-banked exceptions or for the nonsecure
 + * version of a banked exception, true for the secure version of a banked
 + * exception.
 + *
 + * Marks the specified exception as pending. Note that we will assert()
 + * if @secure is true and @irq does not specify one of the fixed set
 + * of architecturally banked exceptions.
 + */
 +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_set_pending_derived: mark this derived exception as pending
 + * @s: the NVIC
 + * @irq: the exception number to mark pending
 + * @secure: false for non-banked exceptions or for the nonsecure
 + * version of a banked exception, true for the secure version of a banked
 + * exception.
 + *
 + * Similar to armv7m_nvic_set_pending(), but specifically for derived
 + * exceptions (exceptions generated in the course of trying to take
 + * a different exception).
 + */
 +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
 + * @s: the NVIC
 + * @irq: the exception number to mark pending
 + * @secure: false for non-banked exceptions or for the nonsecure
 + * version of a banked exception, true for the secure version of a banked
 + * exception.
 + *
 + * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
 + * generated in the course of lazy stacking of FP registers.
 + */
 +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_get_pending_irq_info: return highest priority pending
 + *    exception, and whether it targets Secure state
 + * @s: the NVIC
 + * @pirq: set to pending exception number
 + * @ptargets_secure: set to whether pending exception targets Secure
 + *
 + * This function writes the number of the highest priority pending
 + * exception (the one which would be made active by
 + * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
 + * to true if the current highest priority pending exception should
 + * be taken to Secure state, false for NS.
 + */
 +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
 +                                      bool *ptargets_secure);
 +/**
 + * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
 + * @s: the NVIC
 + *
 + * Move the current highest priority pending exception from the pending
 + * state to the active state, and update v7m.exception to indicate that
 + * it is the exception currently being handled.
 + */
 +void armv7m_nvic_acknowledge_irq(NVICState *s);
 +/**
 + * armv7m_nvic_complete_irq: complete specified interrupt or exception
 + * @s: the NVIC
 + * @irq: the exception number to complete
 + * @secure: true if this exception was secure
 + *
 + * Returns: -1 if the irq was not active
 + *           1 if completing this irq brought us back to base (no active irqs)
 + *           0 if there is still an irq active after this one was completed
 + * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
 + */
 +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
 + * @s: the NVIC
 + * @irq: the exception number to mark pending
 + * @secure: false for non-banked exceptions or for the nonsecure
 + * version of a banked exception, true for the secure version of a banked
 + * exception.
 + *
 + * Return whether an exception is "ready", i.e. whether the exception is
 + * enabled and is configured at a priority which would allow it to
 + * interrupt the current execution priority. This controls whether the
 + * RDY bit for it in the FPCCR is set.
 + */
 +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_raw_execution_priority: return the raw execution priority
 + * @s: the NVIC
 + *
 + * Returns: the raw execution priority as defined by the v8M architecture.
 + * This is the execution priority minus the effects of AIRCR.PRIS,
 + * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
 + * (v8M ARM ARM I_PKLD.)
 + */
 +int armv7m_nvic_raw_execution_priority(NVICState *s);
 +/**
 + * armv7m_nvic_neg_prio_requested: return true if the requested execution
 + * priority is negative for the specified security state.
 + * @s: the NVIC
 + * @secure: the security state to test
 + * This corresponds to the pseudocode IsReqExecPriNeg().
 + */
 +#ifndef CONFIG_USER_ONLY
 +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
 +#else
 +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
 +{
 +    return false;
 +}
 +#endif
 +#ifndef CONFIG_USER_ONLY
 +bool armv7m_nvic_can_take_pending_exception(NVICState *s);
 +#else
 +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
 +{
 +    return true;
 +}
 +#endif
 +
  #endif
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
  uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                   uint32_t cur_el, bool secure);
 -/* Interface between CPU and Interrupt controller.  */
 -#ifndef CONFIG_USER_ONLY
 -bool armv7m_nvic_can_take_pending_exception(NVICState *s);
 -#else
 -static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
 -{
 -    return true;
 -}
 -#endif
 -/**
 - * armv7m_nvic_set_pending: mark the specified exception as pending
 - * @s: the NVIC
 - * @irq: the exception number to mark pending
 - * @secure: false for non-banked exceptions or for the nonsecure
 - * version of a banked exception, true for the secure version of a banked
 - * exception.
 - *
 - * Marks the specified exception as pending. Note that we will assert()
 - * if @secure is true and @irq does not specify one of the fixed set
 - * of architecturally banked exceptions.
 - */
 -void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_set_pending_derived: mark this derived exception as pending
 - * @s: the NVIC
 - * @irq: the exception number to mark pending
 - * @secure: false for non-banked exceptions or for the nonsecure
 - * version of a banked exception, true for the secure version of a banked
 - * exception.
 - *
 - * Similar to armv7m_nvic_set_pending(), but specifically for derived
 - * exceptions (exceptions generated in the course of trying to take
 - * a different exception).
 - */
 -void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
 - * @s: the NVIC
 - * @irq: the exception number to mark pending
 - * @secure: false for non-banked exceptions or for the nonsecure
 - * version of a banked exception, true for the secure version of a banked
 - * exception.
 - *
 - * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
 - * generated in the course of lazy stacking of FP registers.
 - */
 -void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_get_pending_irq_info: return highest priority pending
 - *    exception, and whether it targets Secure state
 - * @s: the NVIC
 - * @pirq: set to pending exception number
 - * @ptargets_secure: set to whether pending exception targets Secure
 - *
 - * This function writes the number of the highest priority pending
 - * exception (the one which would be made active by
 - * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
 - * to true if the current highest priority pending exception should
 - * be taken to Secure state, false for NS.
 - */
 -void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
 -                                      bool *ptargets_secure);
 -/**
 - * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
 - * @s: the NVIC
 - *
 - * Move the current highest priority pending exception from the pending
 - * state to the active state, and update v7m.exception to indicate that
 - * it is the exception currently being handled.
 - */
 -void armv7m_nvic_acknowledge_irq(NVICState *s);
 -/**
 - * armv7m_nvic_complete_irq: complete specified interrupt or exception
 - * @s: the NVIC
 - * @irq: the exception number to complete
 - * @secure: true if this exception was secure
 - *
 - * Returns: -1 if the irq was not active
 - *           1 if completing this irq brought us back to base (no active irqs)
 - *           0 if there is still an irq active after this one was completed
 - * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
 - */
 -int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
 - * @s: the NVIC
 - * @irq: the exception number to mark pending
 - * @secure: false for non-banked exceptions or for the nonsecure
 - * version of a banked exception, true for the secure version of a banked
 - * exception.
 - *
 - * Return whether an exception is "ready", i.e. whether the exception is
 - * enabled and is configured at a priority which would allow it to
 - * interrupt the current execution priority. This controls whether the
 - * RDY bit for it in the FPCCR is set.
 - */
 -bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_raw_execution_priority: return the raw execution priority
 - * @s: the NVIC
 - *
 - * Returns: the raw execution priority as defined by the v8M architecture.
 - * This is the execution priority minus the effects of AIRCR.PRIS,
 - * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
 - * (v8M ARM ARM I_PKLD.)
 - */
 -int armv7m_nvic_raw_execution_priority(NVICState *s);
 -/**
 - * armv7m_nvic_neg_prio_requested: return true if the requested execution
 - * priority is negative for the specified security state.
 - * @s: the NVIC
 - * @secure: the security state to test
 - * This corresponds to the pseudocode IsReqExecPriNeg().
 - */
 -#ifndef CONFIG_USER_ONLY
 -bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
 -#else
 -static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
 -{
 -    return false;
 -}
 -#endif
 -
  /* Interface for defining coprocessor registers.
   * Registers are defined in tables of arm_cp_reginfo structs
   * which are passed to define_arm_cp_regs().
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
  #if !defined(CONFIG_USER_ONLY)
  #include "hw/loader.h"
  #include "hw/boards.h"
 +#ifdef CONFIG_TCG
  #include "hw/intc/armv7m_nvic.h"
 -#endif
 +#endif /* CONFIG_TCG */
 +#endif /* !CONFIG_USER_ONLY */
  #include "sysemu/tcg.h"
  #include "sysemu/qtest.h"
  #include "sysemu/hw_accel.h"
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/boards.h"
  #endif
  #include "cpregs.h"
 +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
 +#include "hw/intc/armv7m_nvic.h"
 +#endif
  /* Share AArch32 -cpu max features with AArch64. */
 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/m_helper.c
 +++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@
  #include "exec/cpu_ldst.h"
  #include "semihosting/common-semi.h"
  #endif
 +#if !defined(CONFIG_USER_ONLY)
 +#include "hw/intc/armv7m_nvic.h"
 +#endif
  static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask,
                           uint32_t reg, uint32_t val)
 --
 .34.1

-New patch
+[PULL 12/30] tests/avocado: retire the Aarch64 TCG tests from boot_linux.py
+From: Alex Bennée <alex.bennee@linaro.org>
 The two TCG tests for GICv2 and GICv3 are very heavy weight distros
 that take a long time to boot up, especially for an --enable-debug
 build. The total code coverage they give is:
   Overall coverage rate:
     lines......: 11.2% (59584 of 530123 lines)
     functions..: 15.0% (7436 of 49443 functions)
     branches...: 6.3% (19273 of 303933 branches)
 We already get pretty close to that with the machine_aarch64_virt
 tests which only does one full boot (~120s vs ~600s) of alpine. We
 expand the kernel+initrd boot (~8s) to test both GICs and also add an
 RNG device and a block device to generate a few IRQs and exercise the
 storage layer. With that we get to a coverage of:
   Overall coverage rate:
     lines......: 11.0% (58121 of 530123 lines)
     functions..: 14.9% (7343 of 49443 functions)
     branches...: 6.0% (18269 of 303933 branches)
 which I feel is close enough given the massive time saving. If we want
 to target any more sub-systems we can use lighter weight more directed
 tests.
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Fabiano Rosas <farosas@suse.de>
 Acked-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230203181632.2919715-1-alex.bennee@linaro.org
 Cc: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  tests/avocado/boot_linux.py           | 48 ++++----------------
  tests/avocado/machine_aarch64_virt.py | 63 ++++++++++++++++++++++++---
 files changed, 65 insertions(+), 46 deletions(-)
 diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/avocado/boot_linux.py
 +++ b/tests/avocado/boot_linux.py
@@ -XXX,XX +XXX,XX @@ def test_pc_q35_kvm(self):
          self.launch_and_wait(set_up_ssh_connection=False)
 -# For Aarch64 we only boot KVM tests in CI as the TCG tests are very
 -# heavyweight. There are lighter weight distros which we use in the
 -# machine_aarch64_virt.py tests.
 +# For Aarch64 we only boot KVM tests in CI as booting the current
 +# Fedora OS in TCG tests is very heavyweight. There are lighter weight
 +# distros which we use in the machine_aarch64_virt.py tests.
  class BootLinuxAarch64(LinuxTest):
      """
      :avocado: tags=arch:aarch64
      :avocado: tags=machine:virt
 -    :avocado: tags=machine:gic-version=2
      """
      timeout = 720
 -    def add_common_args(self):
 -        self.vm.add_args('-bios',
 -                         os.path.join(BUILD_DIR, 'pc-bios',
 -                                      'edk2-aarch64-code.fd'))
 -        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
 -        self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
 -
 -    @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
 -    def test_fedora_cloud_tcg_gicv2(self):
 -        """
 -        :avocado: tags=accel:tcg
 -        :avocado: tags=cpu:max
 -        :avocado: tags=device:gicv2
 -        """
 -        self.require_accelerator("tcg")
 -        self.vm.add_args("-accel", "tcg")
 -        self.vm.add_args("-cpu", "max,lpa2=off")
 -        self.vm.add_args("-machine", "virt,gic-version=2")
 -        self.add_common_args()
 -        self.launch_and_wait(set_up_ssh_connection=False)
 -
 -    @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
 -    def test_fedora_cloud_tcg_gicv3(self):
 -        """
 -        :avocado: tags=accel:tcg
 -        :avocado: tags=cpu:max
 -        :avocado: tags=device:gicv3
 -        """
 -        self.require_accelerator("tcg")
 -        self.vm.add_args("-accel", "tcg")
 -        self.vm.add_args("-cpu", "max,lpa2=off")
 -        self.vm.add_args("-machine", "virt,gic-version=3")
 -        self.add_common_args()
 -        self.launch_and_wait(set_up_ssh_connection=False)
 -
      def test_virt_kvm(self):
          """
          :avocado: tags=accel:kvm
@@ -XXX,XX +XXX,XX @@ def test_virt_kvm(self):
          self.require_accelerator("kvm")
          self.vm.add_args("-accel", "kvm")
          self.vm.add_args("-machine", "virt,gic-version=host")
 -        self.add_common_args()
 +        self.vm.add_args('-bios',
 +                         os.path.join(BUILD_DIR, 'pc-bios',
 +                                      'edk2-aarch64-code.fd'))
 +        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
 +        self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
          self.launch_and_wait(set_up_ssh_connection=False)
 diff --git a/tests/avocado/machine_aarch64_virt.py b/tests/avocado/machine_aarch64_virt.py
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/avocado/machine_aarch64_virt.py
 +++ b/tests/avocado/machine_aarch64_virt.py
@@ -XXX,XX +XXX,XX @@
  import time
  import os
 +import logging
  from avocado_qemu import QemuSystemTest
  from avocado_qemu import wait_for_console_pattern
  from avocado_qemu import exec_command
  from avocado_qemu import BUILD_DIR
 +from avocado.utils import process
 +from avocado.utils.path import find_command
  class Aarch64VirtMachine(QemuSystemTest):
      KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
@@ -XXX,XX +XXX,XX @@ def test_alpine_virt_tcg_gic_max(self):
          self.wait_for_console_pattern('Welcome to Alpine Linux 3.16')
 -    def test_aarch64_virt(self):
 +    def common_aarch64_virt(self, machine):
          """
 -        :avocado: tags=arch:aarch64
 -        :avocado: tags=machine:virt
 -        :avocado: tags=accel:tcg
 -        :avocado: tags=cpu:max
 +        Common code to launch basic virt machine with kernel+initrd
 +        and a scratch disk.
          """
 +        logger = logging.getLogger('aarch64_virt')
 +
          kernel_url = ('https://fileserver.linaro.org/s/'
                        'z6B2ARM7DQT3HWN/download')
 -
          kernel_hash = 'ed11daab50c151dde0e1e9c9cb8b2d9bd3215347'
          kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
@@ -XXX,XX +XXX,XX @@ def test_aarch64_virt(self):
                                 'console=ttyAMA0')
          self.require_accelerator("tcg")
          self.vm.add_args('-cpu', 'max,pauth-impdef=on',
 +                         '-machine', machine,
                           '-accel', 'tcg',
                           '-kernel', kernel_path,
                           '-append', kernel_command_line)
 +
 +        # A RNG offers an easy way to generate a few IRQs
 +        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
 +        self.vm.add_args('-object',
 +                         'rng-random,id=rng0,filename=/dev/urandom')
 +
 +        # Also add a scratch block device
 +        logger.info('creating scratch qcow2 image')
 +        image_path = os.path.join(self.workdir, 'scratch.qcow2')
 +        qemu_img = os.path.join(BUILD_DIR, 'qemu-img')
 +        if not os.path.exists(qemu_img):
 +            qemu_img = find_command('qemu-img', False)
 +        if qemu_img is False:
 +            self.cancel('Could not find "qemu-img", which is required to '
 +                        'create the temporary qcow2 image')
 +        cmd = '%s create -f qcow2 %s 8M' % (qemu_img, image_path)
 +        process.run(cmd)
 +
 +        # Add the device
 +        self.vm.add_args('-blockdev',
 +                         f"driver=qcow2,file.driver=file,file.filename={image_path},node-name=scratch")
 +        self.vm.add_args('-device',
 +                         'virtio-blk-device,drive=scratch')
 +
          self.vm.launch()
          self.wait_for_console_pattern('Welcome to Buildroot')
          time.sleep(0.1)
          exec_command(self, 'root')
          time.sleep(0.1)
 +        exec_command(self, 'dd if=/dev/hwrng of=/dev/vda bs=512 count=4')
 +        time.sleep(0.1)
 +        exec_command(self, 'md5sum /dev/vda')
 +        time.sleep(0.1)
 +        exec_command(self, 'cat /proc/interrupts')
 +        time.sleep(0.1)
          exec_command(self, 'cat /proc/self/maps')
          time.sleep(0.1)
 +
 +    def test_aarch64_virt_gicv3(self):
 +        """
 +        :avocado: tags=arch:aarch64
 +        :avocado: tags=machine:virt
 +        :avocado: tags=accel:tcg
 +        :avocado: tags=cpu:max
 +        """
 +        self.common_aarch64_virt("virt,gic_version=3")
 +
 +    def test_aarch64_virt_gicv2(self):
 +        """
 +        :avocado: tags=arch:aarch64
 +        :avocado: tags=machine:virt
 +        :avocado: tags=accel:tcg
 +        :avocado: tags=cpu:max
 +        """
 +        self.common_aarch64_virt("virt,gic-version=2")
 --
 .34.1

-[PULL 2/5] Fix some typos in documentation (most of them found by codespell)
+[PULL 13/30] hw/arm/smmuv3: Add GBPA register
-From: Stefan Weil <sw@weilnetz.de>
+From: Mostafa Saleh <smostafa@google.com>
-Signed-off-by: Stefan Weil <sw@weilnetz.de>
+GBPA register can be used to globally abort all
-Reviewed-by: Hongren (Zenithal) Zheng <i@zenithal.me>
+transactions.
-Message-id: 20220812075642.1200578-1-sw@weilnetz.de
 It is described in the SMMU manual in "6.3.14 SMMU_GBPA".
 ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to
 be zero(Do not abort incoming transactions).
 Other fields have default values of Use Incoming.
 If UPDATE is not set, the write is ignored. This is the only permitted
 behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure)
 As this patch adds a new state to the SMMU (GBPA), it is added
 in a new subsection for forward migration compatibility.
 GBPA is only migrated if its value is different from the reset value.
 It does this to be backward migration compatible if SW didn't write
 the register.
 Signed-off-by: Mostafa Saleh <smostafa@google.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 20230214094009.2445653-1-smostafa@google.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/about/deprecated.rst       |  2 +-
+ hw/arm/smmuv3-internal.h |  7 +++++++
- docs/specs/acpi_erst.rst        |  4 ++--
+ include/hw/arm/smmuv3.h  |  1 +
- docs/system/devices/canokey.rst |  8 ++++----
+ hw/arm/smmuv3.c          | 43 +++++++++++++++++++++++++++++++++++++++-
- docs/system/devices/cxl.rst     | 12 ++++++------
+files changed, 50 insertions(+), 1 deletion(-)
 files changed, 13 insertions(+), 13 deletions(-)
-diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
+diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
 index XXXXXXX..XXXXXXX 100644
---- a/docs/about/deprecated.rst
+--- a/hw/arm/smmuv3-internal.h
-+++ b/docs/about/deprecated.rst
++++ b/hw/arm/smmuv3-internal.h
-@@ -XXX,XX +XXX,XX @@ by using ``-machine graphics=off``.
+@@ -XXX,XX +XXX,XX @@ REG32(CR0ACK,              0x24)
- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+ REG32(CR1,                 0x28)
+ REG32(CR2,                 0x2c)
- In QEMU versions 6.1, 6.2 and 7.0, the ``nvme-ns`` generates an EUI-64
+ REG32(STATUSR,             0x40)
--identifer that is not globally unique. If an EUI-64 identifer is required, the
++REG32(GBPA,                0x44)
-+identifier that is not globally unique. If an EUI-64 identifier is required, the
++    FIELD(GBPA, ABORT,        20, 1)
- user must set it explicitly using the ``nvme-ns`` device parameter ``eui64``.
++    FIELD(GBPA, UPDATE,       31, 1)
++
- ``-device nvme,use-intel-id=on|off`` (since 7.1)
++/* Use incoming. */
-diff --git a/docs/specs/acpi_erst.rst b/docs/specs/acpi_erst.rst
++#define SMMU_GBPA_RESET_VAL 0x1000
 +
  REG32(IRQ_CTRL,            0x50)
      FIELD(IRQ_CTRL, GERROR_IRQEN,        0, 1)
      FIELD(IRQ_CTRL, PRI_IRQEN,           1, 1)
 diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
 index XXXXXXX..XXXXXXX 100644
---- a/docs/specs/acpi_erst.rst
+--- a/include/hw/arm/smmuv3.h
-+++ b/docs/specs/acpi_erst.rst
++++ b/include/hw/arm/smmuv3.h
-@@ -XXX,XX +XXX,XX @@ Slot 0 contains a backend storage header that identifies the contents
+@@ -XXX,XX +XXX,XX @@ struct SMMUv3State {
- as ERST and also facilitates efficient access to the records.
+     uint32_t cr[3];
- Depending upon the size of the backend storage, additional slots will
+     uint32_t cr0ack;
- be designated to be a part of the slot 0 header. For example, at 8KiB,
+     uint32_t statusr;
--the slot 0 header can accomodate 1021 records. Thus a storage size
++    uint32_t gbpa;
-+the slot 0 header can accommodate 1021 records. Thus a storage size
+     uint32_t irq_ctrl;
- of 8MiB (8KiB * 1024) requires an additional slot for use by the
+     uint32_t gerror;
- header. In this scenario, slot 0 and slot 1 form the backend storage
+     uint32_t gerrorn;
- header, and records can be stored starting at slot 2.
+diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
@@ -XXX,XX +XXX,XX @@ References
  [2] "Unified Extensible Firmware Interface Specification",
      version 2.1, October 2008.
 -[3] "Windows Hardware Error Architecture", specfically
 +[3] "Windows Hardware Error Architecture", specifically
      "Error Record Persistence Mechanism".
 diff --git a/docs/system/devices/canokey.rst b/docs/system/devices/canokey.rst
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/devices/canokey.rst
+--- a/hw/arm/smmuv3.c
-+++ b/docs/system/devices/canokey.rst
++++ b/hw/arm/smmuv3.c
-@@ -XXX,XX +XXX,XX @@ With the same software configuration as a hardware key,
+@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
- the guest OS can use all the functionalities of a secure key as if
+     s->gerror = 0;
- there was actually an hardware key plugged in.
+     s->gerrorn = 0;
+     s->statusr = 0;
--CanoKey QEMU provides much convenience for debuging:
++    s->gbpa = SMMU_GBPA_RESET_VAL;
-+CanoKey QEMU provides much convenience for debugging:
+ }
--* libcanokey-qemu supports debuging output thus developers can
+ static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
-+* libcanokey-qemu supports debugging output thus developers can
+@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
-   inspect what happens inside a secure key
+     qemu_mutex_lock(&s->mutex);
- * CanoKey QEMU supports trace event thus event
- * QEMU USB stack supports pcap thus USB packet between the guest
+     if (!smmu_enabled(s)) {
-@@ -XXX,XX +XXX,XX @@ and find CanoKey QEMU there:
+-        status = SMMU_TRANS_DISABLE;
++        if (FIELD_EX32(s->gbpa, GBPA, ABORT)) {
- You may setup the key as guided in [6]_. The console for the key is at [7]_.
++            status = SMMU_TRANS_ABORT;
++        } else {
--Debuging
++            status = SMMU_TRANS_DISABLE;
--========
++        }
-+Debugging
+         goto epilogue;
-+=========
+     }
- CanoKey QEMU consists of two parts, ``libcanokey-qemu.so`` and ``canokey.c``,
+@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,
- the latter of which resides in QEMU. The former provides core functionality
+     case A_GERROR_IRQ_CFG2:
-diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
+         s->gerror_irq_cfg2 = data;
-index XXXXXXX..XXXXXXX 100644
+         return MEMTX_OK;
---- a/docs/system/devices/cxl.rst
++    case A_GBPA:
-+++ b/docs/system/devices/cxl.rst
++        /*
-@@ -XXX,XX +XXX,XX @@ CXL Fixed Memory Windows (CFMW)
++         * If UPDATE is not set, the write is ignored. This is the only
- A CFMW consists of a particular range of Host Physical Address space
++         * permitted behavior in SMMUv3.2 and later.
- which is routed to particular CXL Host Bridges.  At time of generic
++         */
- software initialization it will have a particularly interleaving
++        if (data & R_GBPA_UPDATE_MASK) {
--configuration and associated Quality of Serice Throtling Group (QTG).
++            /* Ignore update bit as write is synchronous. */
-+configuration and associated Quality of Service Throttling Group (QTG).
++            s->gbpa = data & ~R_GBPA_UPDATE_MASK;
- This information is available to system software, when making
++        }
- decisions about how to configure interleave across available CXL
++        return MEMTX_OK;
- memory devices.  It is provide as CFMW Structures (CFMWS) in
+     case A_STRTAB_BASE: /* 64b */
-@@ -XXX,XX +XXX,XX @@ specification defined register interface called CXL Host Bridge
+         s->strtab_base = deposit64(s->strtab_base, 0, 32, data);
- Component Registers (CHBCR). The location of this CHBCR MMIO
+         return MEMTX_OK;
- space is described to system software via a CXL Host Bridge
+@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset,
- Structure (CHBS) in the CEDT ACPI table.  The actual interfaces
+     case A_STATUSR:
--are identical to those used for other parts of the CXL heirarchy
+         *data = s->statusr;
-+are identical to those used for other parts of the CXL hierarchy
+         return MEMTX_OK;
- as CXL Component Registers in PCI BARs.
++    case A_GBPA:
++        *data = s->gbpa;
- Interfaces provided include:
++        return MEMTX_OK;
-@@ -XXX,XX +XXX,XX @@ CXL Memory Devices - Type 3
+     case A_IRQ_CTRL:
- ~~~~~~~~~~~~~~~~~~~~~~~~~~~
+     case A_IRQ_CTRL_ACK:
- CXL type 3 devices use a PCI class code and are intended to be supported
+         *data = s->irq_ctrl;
- by a generic operating system driver. They have HDM decoders
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3_queue = {
--though in these EP devices, the decoder is reponsible not for
+     },
-+though in these EP devices, the decoder is responsible not for
+ };
- routing but for translation of the incoming host physical address (HPA)
- into a Device Physical Address (DPA).
++static bool smmuv3_gbpa_needed(void *opaque)
++{
-@@ -XXX,XX +XXX,XX @@ Notes:
++    SMMUv3State *s = opaque;
-     ranges of the system physical address map.  Each CFMW has
++
-     particular interleave setup across the CXL Host Bridges (HB)
++    /* Only migrate GBPA if it has different reset value. */
-     CFMW0 provides uninterleaved access to HB0, CFW2 provides
++    return s->gbpa != SMMU_GBPA_RESET_VAL;
--    uninterleaved acess to HB1. CFW1 provides interleaved memory access
++}
-+    uninterleaved access to HB1. CFW1 provides interleaved memory access
++
-     across HB0 and HB1.
++static const VMStateDescription vmstate_gbpa = {
++    .name = "smmuv3/gbpa",
- (2) **Two CXL Host Bridges**. Each of these has 2 CXL Root Ports and
++    .version_id = 1,
-@@ -XXX,XX +XXX,XX @@ Example topology involving a switch::
++    .minimum_version_id = 1,
-             ---------------------------------------------------
++    .needed = smmuv3_gbpa_needed,
-            |    Switch 0  USP as PCI 0d:00.0                   |
++    .fields = (VMStateField[]) {
-            |    USP has HDM decoder which direct traffic to    |
++        VMSTATE_UINT32(gbpa, SMMUv3State),
--           |    appropiate downstream port                     |
++        VMSTATE_END_OF_LIST()
-+           |    appropriate downstream port                    |
++    }
-            |    Switch BUS appears as 0e                       |
++};
-            |x__________________________________________________|
++
-             |                  |               |              |
+ static const VMStateDescription vmstate_smmuv3 = {
-@@ -XXX,XX +XXX,XX @@ An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave::
+     .name = "smmuv3",
- Kernel Configuration Options
+     .version_id = 1,
- ----------------------------
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = {
--In Linux 5.18 the followings options are necessary to make use of
+         VMSTATE_END_OF_LIST(),
-+In Linux 5.18 the following options are necessary to make use of
+     },
- OS management of CXL memory devices as described here.
++    .subsections = (const VMStateDescription * []) {
++        &vmstate_gbpa,
- * CONFIG_CXL_BUS
++        NULL
 +    }
  };
  static void smmuv3_instance_init(Object *obj)
 --
-.25.1
+.34.1

-New patch
+[PULL 14/30] hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Since commit acc0b8b05a when running the ZynqMP ZCU102 board with
+a QEMU configured using --without-default-devices, we get:
+  $ qemu-system-aarch64 -M xlnx-zcu102
+  qemu-system-aarch64: missing object type 'usb_dwc3'
+  Abort trap: 6
+Fix by adding the missing Kconfig dependency.
+Fixes: acc0b8b05a ("hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers")
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230216092327.2203-1-philmd@linaro.org
+Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/Kconfig | 1 +
+file changed, 1 insertion(+)
+diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/Kconfig
++++ b/hw/arm/Kconfig
+@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP_ARM
+     select XLNX_CSU_DMA
+     select XLNX_ZYNQMP
+     select XLNX_ZDMA
++    select USB_DWC3
+ config XLNX_VERSAL
+     bool
+--
+.34.1

-New patch
+[PULL 15/30] arm/virt: don't try to spell out the accelerator
+From: Cornelia Huck <cohuck@redhat.com>
+Just use current_accel_name() directly.
+Signed-off-by: Cornelia Huck <cohuck@redhat.com>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/virt.c | 6 +++---
+file changed, 3 insertions(+), 3 deletions(-)
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/virt.c
++++ b/hw/arm/virt.c
+@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
+     if (vms->secure && (kvm_enabled() || hvf_enabled())) {
+         error_report("mach-virt: %s does not support providing "
+                      "Security extensions (TrustZone) to the guest CPU",
+-                     kvm_enabled() ? "KVM" : "HVF");
++                     current_accel_name());
+         exit(1);
+     }
+     if (vms->virt && (kvm_enabled() || hvf_enabled())) {
+         error_report("mach-virt: %s does not support providing "
+                      "Virtualization extensions to the guest CPU",
+-                     kvm_enabled() ? "KVM" : "HVF");
++                     current_accel_name());
+         exit(1);
+     }
+     if (vms->mte && (kvm_enabled() || hvf_enabled())) {
+         error_report("mach-virt: %s does not support providing "
+                      "MTE to the guest CPU",
+-                     kvm_enabled() ? "KVM" : "HVF");
++                     current_accel_name());
+         exit(1);
+     }
+--
+.34.1

-New patch
+[PULL 16/30] MAINTAINERS: Add myself to maintainers and remove Havard
+From: Hao Wu <wuhaotsh@google.com>
+Havard is no longer working on the Nuvoton systems for a while
+and won't be able to do any work on it in the future. So I'll
+take over maintaining the Nuvoton system from him.
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Acked-by: Havard Skinnemoen <hskinnemoen@google.com>
+Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
+Message-id: 20230208235433.3989937-2-wuhaotsh@google.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ MAINTAINERS | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ F: include/hw/net/mv88w8618_eth.h
+ F: docs/system/arm/musicpal.rst
+ Nuvoton NPCM7xx
+-M: Havard Skinnemoen <hskinnemoen@google.com>
+ M: Tyrone Ting <kfting@nuvoton.com>
++M: Hao Wu <wuhaotsh@google.com>
+ L: qemu-arm@nongnu.org
+ S: Supported
+ F: hw/*/npcm7xx*
+--
+.34.1

-New patch
+[PULL 17/30] hw/ssi: Add Nuvoton PSPI Module
+From: Hao Wu <wuhaotsh@google.com>
+Nuvoton's PSPI is a general purpose SPI module which enables
+connections to SPI-based peripheral devices.
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Reviewed-by: Chris Rauer <crauer@google.com>
+Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
+Message-id: 20230208235433.3989937-3-wuhaotsh@google.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ MAINTAINERS                |   6 +-
+ include/hw/ssi/npcm_pspi.h |  53 +++++++++
+ hw/ssi/npcm_pspi.c         | 221 +++++++++++++++++++++++++++++++++++++
+ hw/ssi/meson.build         |   2 +-
+ hw/ssi/trace-events        |   5 +
+files changed, 283 insertions(+), 4 deletions(-)
+ create mode 100644 include/hw/ssi/npcm_pspi.h
+ create mode 100644 hw/ssi/npcm_pspi.c
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ M: Tyrone Ting <kfting@nuvoton.com>
+ M: Hao Wu <wuhaotsh@google.com>
+ L: qemu-arm@nongnu.org
+ S: Supported
+-F: hw/*/npcm7xx*
+-F: include/hw/*/npcm7xx*
+-F: tests/qtest/npcm7xx*
++F: hw/*/npcm*
++F: include/hw/*/npcm*
++F: tests/qtest/npcm*
+ F: pc-bios/npcm7xx_bootrom.bin
+ F: roms/vbootrom
+ F: docs/system/arm/nuvoton.rst
+diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/include/hw/ssi/npcm_pspi.h
+@@ -XXX,XX +XXX,XX @@
++/*
++ * Nuvoton Peripheral SPI Module
++ *
++ * Copyright 2023 Google LLC
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++#ifndef NPCM_PSPI_H
++#define NPCM_PSPI_H
++
++#include "hw/ssi/ssi.h"
++#include "hw/sysbus.h"
++
++/*
++ * Number of registers in our device state structure. Don't change this without
++ * incrementing the version_id in the vmstate.
++ */
++#define NPCM_PSPI_NR_REGS 3
++
++/**
++ * NPCMPSPIState - Device state for one Flash Interface Unit.
++ * @parent: System bus device.
++ * @mmio: Memory region for register access.
++ * @spi: The SPI bus mastered by this controller.
++ * @regs: Register contents.
++ * @irq: The interrupt request queue for this module.
++ *
++ * Each PSPI has a shared bank of registers, and controls up to four chip
++ * selects. Each chip select has a dedicated memory region which may be used to
++ * read and write the flash connected to that chip select as if it were memory.
++ */
++typedef struct NPCMPSPIState {
++    SysBusDevice parent;
++
++    MemoryRegion mmio;
++
++    SSIBus *spi;
++    uint16_t regs[NPCM_PSPI_NR_REGS];
++    qemu_irq irq;
++} NPCMPSPIState;
++
++#define TYPE_NPCM_PSPI "npcm-pspi"
++OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI)
++
++#endif /* NPCM_PSPI_H */
+diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/hw/ssi/npcm_pspi.c
+@@ -XXX,XX +XXX,XX @@
++/*
++ * Nuvoton NPCM Peripheral SPI Module (PSPI)
++ *
++ * Copyright 2023 Google LLC
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++
++#include "qemu/osdep.h"
++
++#include "hw/irq.h"
++#include "hw/registerfields.h"
++#include "hw/ssi/npcm_pspi.h"
++#include "migration/vmstate.h"
++#include "qapi/error.h"
++#include "qemu/error-report.h"
++#include "qemu/log.h"
++#include "qemu/module.h"
++#include "qemu/units.h"
++
++#include "trace.h"
++
++REG16(PSPI_DATA, 0x0)
++REG16(PSPI_CTL1, 0x2)
++    FIELD(PSPI_CTL1, SPIEN, 0,  1)
++    FIELD(PSPI_CTL1, MOD,   2,  1)
++    FIELD(PSPI_CTL1, EIR,   5,  1)
++    FIELD(PSPI_CTL1, EIW,   6,  1)
++    FIELD(PSPI_CTL1, SCM,   7,  1)
++    FIELD(PSPI_CTL1, SCIDL, 8,  1)
++    FIELD(PSPI_CTL1, SCDV,  9,  7)
++REG16(PSPI_STAT, 0x4)
++    FIELD(PSPI_STAT, BSY,  0,  1)
++    FIELD(PSPI_STAT, RBF,  1,  1)
++
++static void npcm_pspi_update_irq(NPCMPSPIState *s)
++{
++    int level = 0;
++
++    /* Only fire IRQ when the module is enabled. */
++    if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) {
++        /* Update interrupt as BSY is cleared. */
++        if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) &&
++            FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) {
++            level = 1;
++        }
++
++        /* Update interrupt as RBF is set. */
++        if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) &&
++            FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) {
++            level = 1;
++        }
++    }
++    qemu_set_irq(s->irq, level);
++}
++
++static uint16_t npcm_pspi_read_data(NPCMPSPIState *s)
++{
++    uint16_t value = s->regs[R_PSPI_DATA];
++
++    /* Clear stat bits as the value are read out. */
++    s->regs[R_PSPI_STAT] = 0;
++
++    return value;
++}
++
++static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data)
++{
++    uint16_t value = 0;
++
++    if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) {
++        value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8;
++    }
++    value |= ssi_transfer(s->spi, extract16(data, 0, 8));
++    s->regs[R_PSPI_DATA] = value;
++
++    /* Mark data as available */
++    s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK;
++}
++
++/* Control register read handler. */
++static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr,
++                                    unsigned int size)
++{
++    NPCMPSPIState *s = opaque;
++    uint16_t value;
++
++    switch (addr) {
++    case A_PSPI_DATA:
++        value = npcm_pspi_read_data(s);
++        break;
++
++    case A_PSPI_CTL1:
++        value = s->regs[R_PSPI_CTL1];
++        break;
++
++    case A_PSPI_STAT:
++        value = s->regs[R_PSPI_STAT];
++        break;
++
++    default:
++        qemu_log_mask(LOG_GUEST_ERROR,
++                      "%s: write to invalid offset 0x%" PRIx64 "\n",
++                      DEVICE(s)->canonical_path, addr);
++        return 0;
++    }
++    trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value);
++    npcm_pspi_update_irq(s);
++
++    return value;
++}
++
++/* Control register write handler. */
++static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v,
++                                 unsigned int size)
++{
++    NPCMPSPIState *s = opaque;
++    uint16_t value = v;
++
++    trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value);
++
++    switch (addr) {
++    case A_PSPI_DATA:
++        npcm_pspi_write_data(s, value);
++        break;
++
++    case A_PSPI_CTL1:
++        s->regs[R_PSPI_CTL1] = value;
++        break;
++
++    case A_PSPI_STAT:
++        qemu_log_mask(LOG_GUEST_ERROR,
++                      "%s: write to read-only register PSPI_STAT: 0x%08"
++                      PRIx64 "\n", DEVICE(s)->canonical_path, v);
++        break;
++
++    default:
++        qemu_log_mask(LOG_GUEST_ERROR,
++                      "%s: write to invalid offset 0x%" PRIx64 "\n",
++                      DEVICE(s)->canonical_path, addr);
++        return;
++    }
++    npcm_pspi_update_irq(s);
++}
++
++static const MemoryRegionOps npcm_pspi_ctrl_ops = {
++    .read = npcm_pspi_ctrl_read,
++    .write = npcm_pspi_ctrl_write,
++    .endianness = DEVICE_LITTLE_ENDIAN,
++    .valid = {
++        .min_access_size = 1,
++        .max_access_size = 2,
++        .unaligned = false,
++    },
++    .impl = {
++        .min_access_size = 2,
++        .max_access_size = 2,
++        .unaligned = false,
++    },
++};
++
++static void npcm_pspi_enter_reset(Object *obj, ResetType type)
++{
++    NPCMPSPIState *s = NPCM_PSPI(obj);
++
++    trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type);
++    memset(s->regs, 0, sizeof(s->regs));
++}
++
++static void npcm_pspi_realize(DeviceState *dev, Error **errp)
++{
++    NPCMPSPIState *s = NPCM_PSPI(dev);
++    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
++    Object *obj = OBJECT(dev);
++
++    s->spi = ssi_create_bus(dev, "pspi");
++    memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s,
++                          "mmio", 4 * KiB);
++    sysbus_init_mmio(sbd, &s->mmio);
++    sysbus_init_irq(sbd, &s->irq);
++}
++
++static const VMStateDescription vmstate_npcm_pspi = {
++    .name = "npcm-pspi",
++    .version_id = 0,
++    .minimum_version_id = 0,
++    .fields = (VMStateField[]) {
++        VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS),
++        VMSTATE_END_OF_LIST(),
++    },
++};
++
++
++static void npcm_pspi_class_init(ObjectClass *klass, void *data)
++{
++    ResettableClass *rc = RESETTABLE_CLASS(klass);
++    DeviceClass *dc = DEVICE_CLASS(klass);
++
++    dc->desc = "NPCM Peripheral SPI Module";
++    dc->realize = npcm_pspi_realize;
++    dc->vmsd = &vmstate_npcm_pspi;
++    rc->phases.enter = npcm_pspi_enter_reset;
++}
++
++static const TypeInfo npcm_pspi_types[] = {
++    {
++        .name = TYPE_NPCM_PSPI,
++        .parent = TYPE_SYS_BUS_DEVICE,
++        .instance_size = sizeof(NPCMPSPIState),
++        .class_init = npcm_pspi_class_init,
++    },
++};
++DEFINE_TYPES(npcm_pspi_types);
+diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/ssi/meson.build
++++ b/hw/ssi/meson.build
+@@ -XXX,XX +XXX,XX @@
+ softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c'))
+ softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c'))
+-softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c'))
++softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'npcm_pspi.c'))
+ softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c'))
+ softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c'))
+ softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c'))
+diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/ssi/trace-events
++++ b/hw/ssi/trace-events
+@@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset:
+ npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
+ npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
++# npcm_pspi.c
++npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d"
++npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
++npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
++
+ # ibex_spi_host.c
+ ibex_spi_host_reset(const char *msg) "%s"
+--
+.34.1

-New patch
+[PULL 18/30] hw/arm: Attach PSPI module to NPCM7XX SoC
+From: Hao Wu <wuhaotsh@google.com>
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Reviewed-by: Titus Rwantare <titusr@google.com>
+Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
+Message-id: 20230208235433.3989937-4-wuhaotsh@google.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ docs/system/arm/nuvoton.rst |  2 +-
+ include/hw/arm/npcm7xx.h    |  2 ++
+ hw/arm/npcm7xx.c            | 25 +++++++++++++++++++++++--
+files changed, 26 insertions(+), 3 deletions(-)
+diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/system/arm/nuvoton.rst
++++ b/docs/system/arm/nuvoton.rst
+@@ -XXX,XX +XXX,XX @@ Supported devices
+  * SMBus controller (SMBF)
+  * Ethernet controller (EMC)
+  * Tachometer
++ * Peripheral SPI controller (PSPI)
+ Missing devices
+ ---------------
+@@ -XXX,XX +XXX,XX @@ Missing devices
+  * Ethernet controller (GMAC)
+  * USB device (USBD)
+- * Peripheral SPI controller (PSPI)
+  * SD/MMC host
+  * PECI interface
+  * PCI and PCIe root complex and bridges
+diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/npcm7xx.h
++++ b/include/hw/arm/npcm7xx.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/nvram/npcm7xx_otp.h"
+ #include "hw/timer/npcm7xx_timer.h"
+ #include "hw/ssi/npcm7xx_fiu.h"
++#include "hw/ssi/npcm_pspi.h"
+ #include "hw/usb/hcd-ehci.h"
+ #include "hw/usb/hcd-ohci.h"
+ #include "target/arm/cpu.h"
+@@ -XXX,XX +XXX,XX @@ struct NPCM7xxState {
+     NPCM7xxFIUState     fiu[2];
+     NPCM7xxEMCState     emc[2];
+     NPCM7xxSDHCIState   mmc;
++    NPCMPSPIState       pspi[2];
+ };
+ #define TYPE_NPCM7XX    "npcm7xx"
+diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/npcm7xx.c
++++ b/hw/arm/npcm7xx.c
+@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
+     NPCM7XX_EMC1RX_IRQ          = 15,
+     NPCM7XX_EMC1TX_IRQ,
+     NPCM7XX_MMC_IRQ             = 26,
++    NPCM7XX_PSPI2_IRQ           = 28,
++    NPCM7XX_PSPI1_IRQ           = 31,
+     NPCM7XX_TIMER0_IRQ          = 32,   /* Timer Module 0 */
+     NPCM7XX_TIMER1_IRQ,
+     NPCM7XX_TIMER2_IRQ,
+@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_emc_addr[] = {
+xf0826000,
+ };
++/* Register base address for each PSPI Module */
++static const hwaddr npcm7xx_pspi_addr[] = {
++    0xf0200000,
++    0xf0201000,
++};
++
+ static const struct {
+     hwaddr regs_addr;
+     uint32_t unconnected_pins;
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
+         object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC);
+     }
++    for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
++        object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI);
++    }
++
+     object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
+ }
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0,
+             npcm7xx_irq(s, NPCM7XX_MMC_IRQ));
++    /* PSPI */
++    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi));
++    for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
++        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]);
++        int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ;
++
++        sysbus_realize(sbd, &error_abort);
++        sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]);
++        sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq));
++    }
++
+     create_unimplemented_device("npcm7xx.shm",          0xc0001000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
+     create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
+-    create_unimplemented_device("npcm7xx.pspi1",        0xf0200000,   4 * KiB);
+-    create_unimplemented_device("npcm7xx.pspi2",        0xf0201000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.ahbpci",       0xf0400000,   1 * MiB);
+     create_unimplemented_device("npcm7xx.mcphy",        0xf05f0000,  64 * KiB);
+     create_unimplemented_device("npcm7xx.gmac1",        0xf0802000,   8 * KiB);
+--
+.34.1

-New patch
+[PULL 19/30] hw/arm/smmu-common: Support 64-bit addresses
+From: Jean-Philippe Brucker <jean-philippe@linaro.org>
+Addresses targeting the second translation table (TTB1) in the SMMU have
+all upper bits set. Ensure the IOMMU region covers all 64 bits.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Message-id: 20230214171921.1917916-2-jean-philippe@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/smmu-common.h | 2 --
+ hw/arm/smmu-common.c         | 2 +-
+files changed, 1 insertion(+), 3 deletions(-)
+diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/smmu-common.h
++++ b/include/hw/arm/smmu-common.h
+@@ -XXX,XX +XXX,XX @@
+ #define SMMU_PCI_DEVFN_MAX    256
+ #define SMMU_PCI_DEVFN(sid)   (sid & 0xFF)
+-#define SMMU_MAX_VA_BITS      48
+-
+ /*
+  * Page table walk error types
+  */
+diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/smmu-common.c
++++ b/hw/arm/smmu-common.c
+@@ -XXX,XX +XXX,XX @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn)
+         memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu),
+                                  s->mrtypename,
+-                                 OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS);
++                                 OBJECT(s), name, UINT64_MAX);
+         address_space_init(&sdev->as,
+                            MEMORY_REGION(&sdev->iommu), name);
+         trace_smmu_add_mr(name);
+--
+.34.1

-New patch
+[PULL 20/30] hw/arm/smmu-common: Fix TTB1 handling
+From: Jean-Philippe Brucker <jean-philippe@linaro.org>
+Addresses targeting the second translation table (TTB1) in the SMMU have
+all upper bits set (except for the top byte when TBI is enabled). Fix
+the TTB1 check.
+Reported-by: Ola Hugosson <ola.hugosson@arm.com>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
+Message-id: 20230214171921.1917916-3-jean-philippe@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/smmu-common.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/smmu-common.c
++++ b/hw/arm/smmu-common.c
+@@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
+         /* there is a ttbr0 region and we are in it (high bits all zero) */
+         return &cfg->tt[0];
+     } else if (cfg->tt[1].tsz &&
+-           !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) {
++        sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) {
+         /* there is a ttbr1 region and we are in it (high bits all one) */
+         return &cfg->tt[1];
+     } else if (!cfg->tt[0].tsz) {
+--
+.34.1

-New patch
+[PULL 21/30] target/arm: rename handle_semihosting to tcg_handle_semihosting
+From: Claudio Fontana <cfontana@suse.de>
+make it clearer from the name that this is a tcg-only function.
+Signed-off-by: Claudio Fontana <cfontana@suse.de>
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/helper.c | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
+  * trapped to the hypervisor in KVM.
+  */
+ #ifdef CONFIG_TCG
+-static void handle_semihosting(CPUState *cs)
++static void tcg_handle_semihosting(CPUState *cs)
+ {
+     ARMCPU *cpu = ARM_CPU(cs);
+     CPUARMState *env = &cpu->env;
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
+      */
+ #ifdef CONFIG_TCG
+     if (cs->exception_index == EXCP_SEMIHOST) {
+-        handle_semihosting(cs);
++        tcg_handle_semihosting(cs);
+         return;
+     }
+ #endif
+--
+.34.1

-New patch
+[PULL 22/30] target/arm: wrap psci call with tcg_enabled
+From: Claudio Fontana <cfontana@suse.de>
+for "all" builds (tcg + kvm), we want to avoid doing
+the psci check if tcg is built-in, but not enabled.
+Signed-off-by: Claudio Fontana <cfontana@suse.de>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/helper.c | 3 ++-
+file changed, 2 insertions(+), 1 deletion(-)
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/irq.h"
+ #include "sysemu/cpu-timers.h"
+ #include "sysemu/kvm.h"
++#include "sysemu/tcg.h"
+ #include "qapi/qapi-commands-machine-target.h"
+ #include "qapi/error.h"
+ #include "qemu/guest-random.h"
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
+                       env->exception.syndrome);
+     }
+-    if (arm_is_psci_call(cpu, cs->exception_index)) {
++    if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) {
+         arm_handle_psci_call(cpu);
+         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
+         return;
+--
+.34.1

-[PULL 1/5] target/arm: Don't report Statistical Profiling Extension in ID registers
+[PULL 23/30] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()
-The newly added neoverse-n1 CPU has ID register values which indicate
+From: Claudio Fontana <cfontana@suse.de>
 the presence of the Statistical Profiling Extension, because the real
 hardware has this feature.  QEMU's TCG emulation does not yet
 implement SPE, though (not even as a minimal stub implementation), so
 guests will crash if they try to use it because the SPE system
 registers don't exist.
-Force ID_AA64DFR0_EL1.PMSVer to 0 in CPU realize for TCG, so that
+Signed-off-by: Claudio Fontana <cfontana@suse.de>
-we don't advertise to the guest a feature that doesn't exist.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Fabiano Rosas <farosas@suse.de>
 Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/helper.c | 12 +++++++-----
 file changed, 7 insertions(+), 5 deletions(-)
-(We could alternatively do this by editing the value that
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 aarch64_neoverse_n1_initfn() sets for this ID register, but
 suppressing the field in realize means we won't re-introduce this bug
 when we add other CPUs that have SPE in hardware, such as the
 Neoverse-V1.)
 An example of a non-booting guest is current mainline Linux (5.19),
 when booting in EL2 on the virt board (ie with -machine
 virtualization=on).
 Reported-by: Zenghui Yu <yuzenghui@huawei.com>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
 Message-id: 20220811131127.947334-1-peter.maydell@linaro.org
 ---
  target/arm/cpu.c | 11 +++++++++++
 file changed, 11 insertions(+)
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/target/arm/helper.c
-+++ b/target/arm/cpu.c
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
-     }
+     unsigned int cur_el = arm_current_el(env);
- #endif
+     int rt;
 -    /*
 -     * Note that new_el can never be 0.  If cur_el is 0, then
 -     * el0_a64 is is_a64(), else el0_a64 is ignored.
 -     */
 -    aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
 +    if (tcg_enabled()) {
 +        /*
-+         * Don't report the Statistical Profiling Extension in the ID
++         * Note that new_el can never be 0.  If cur_el is 0, then
-+         * registers, because TCG doesn't implement it yet (not even a
++         * el0_a64 is is_a64(), else el0_a64 is ignored.
 +         * minimal stub version) and guests will fall over when they
 +         * try to access the non-existent system registers for it.
 +         */
-+        cpu->isar.id_aa64dfr0 =
++        aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
 +            FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
 +    }
-+
-     /* MPU can be configured out of a PMSA CPU either by setting has-mpu
+     if (cur_el < new_el) {
-      * to false or by setting pmsav7-dregion to 0.
+         /*
       */
 --
-.25.1
+.34.1

-[PULL 3/5] tests/unit: fix a -Wformat-truncation warning
+[PULL 24/30] target/arm: Move PC alignment check
-From: Marc-André Lureau <marcandre.lureau@redhat.com>
+From: Fabiano Rosas <farosas@suse.de>
-../tests/test-qobject-input-visitor.c: In function ‘test_visitor_in_list’:
+Move this earlier to make the next patch diff cleaner. While here
-../tests/test-qobject-input-visitor.c:454:49: warning: ‘%d’ directive output may be truncated writing between 1 and 10 bytes into a region of size 6 [-Wformat-truncation=]
+update the comment slightly to not give the impression that the
-|         snprintf(string, sizeof(string), "string%d", i);
+misalignment affects only TCG.
       |                                                 ^~
 ../tests/test-qobject-input-visitor.c:454:42: note: directive argument in the range [0, 2147483606]
 |         snprintf(string, sizeof(string), "string%d", i);
       |                                          ^~~~~~~~~~
 ../tests/test-qobject-input-visitor.c:454:9: note: ‘snprintf’ output between 8 and 17 bytes into a destination of size 12
 |         snprintf(string, sizeof(string), "string%d", i);
       |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-Rather than trying to be clever, since this is called 3 times during
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-tests, let's simply use g_strdup_printf().
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
-Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Markus Armbruster <armbru@redhat.com>
 Message-id: 20220810121513.1356081-1-marcandre.lureau@redhat.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 [PMM: fixed commit message typos]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- tests/unit/test-qobject-input-visitor.c | 3 +--
+ target/arm/machine.c | 18 +++++++++---------
-file changed, 1 insertion(+), 2 deletions(-)
+file changed, 9 insertions(+), 9 deletions(-)
-diff --git a/tests/unit/test-qobject-input-visitor.c b/tests/unit/test-qobject-input-visitor.c
+diff --git a/target/arm/machine.c b/target/arm/machine.c
 index XXXXXXX..XXXXXXX 100644
---- a/tests/unit/test-qobject-input-visitor.c
+--- a/target/arm/machine.c
-+++ b/tests/unit/test-qobject-input-visitor.c
++++ b/target/arm/machine.c
-@@ -XXX,XX +XXX,XX @@ static void test_visitor_in_list(TestInputVisitorData *data,
+@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
-     g_assert(head != NULL);
+         }
+     }
-     for (i = 0, item = head; item; item = item->next, i++) {
--        char string[12];
++    /*
-+        g_autofree char *string = g_strdup_printf("string%d", i);
++     * Misaligned thumb pc is architecturally impossible. Fail the
++     * incoming migration. For TCG it would trigger the assert in
--        snprintf(string, sizeof(string), "string%d", i);
++     * thumb_tr_translate_insn().
-         g_assert_cmpstr(item->value->string, ==, string);
++     */
-         g_assert_cmpint(item->value->integer, ==, 42 + i);
++    if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
 +        return -1;
 +    }
 +
      hw_breakpoint_update_all(cpu);
      hw_watchpoint_update_all(cpu);
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
          }
      }
 -    /*
 -     * Misaligned thumb pc is architecturally impossible.
 -     * We have an assert in thumb_tr_translate_insn to verify this.
 -     * Fail an incoming migrate to avoid this assert.
 -     */
 -    if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
 -        return -1;
 -    }
 -
      if (!kvm_enabled()) {
          pmu_op_finish(&cpu->env);
      }
 --
-.25.1
+.34.1

-New patch
+[PULL 25/30] target/arm: Move cpregs code out of cpu.h
+From: Fabiano Rosas <farosas@suse.de>
 Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have
 a cpregs.h header which is more suitable for this code.
 Code moved verbatim.
 Signed-off-by: Fabiano Rosas <farosas@suse.de>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpregs.h | 98 +++++++++++++++++++++++++++++++++++++++++++++
  target/arm/cpu.h    | 91 -----------------------------------------
 files changed, 98 insertions(+), 91 deletions(-)
 diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpregs.h
 +++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
      ARM_CP_SME                   = 1 << 19,
  };
 +/*
 + * Interface for defining coprocessor registers.
 + * Registers are defined in tables of arm_cp_reginfo structs
 + * which are passed to define_arm_cp_regs().
 + */
 +
 +/*
 + * When looking up a coprocessor register we look for it
 + * via an integer which encodes all of:
 + *  coprocessor number
 + *  Crn, Crm, opc1, opc2 fields
 + *  32 or 64 bit register (ie is it accessed via MRC/MCR
 + *    or via MRRC/MCRR?)
 + *  non-secure/secure bank (AArch32 only)
 + * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 + * (In this case crn and opc2 should be zero.)
 + * For AArch64, there is no 32/64 bit size distinction;
 + * instead all registers have a 2 bit op0, 3 bit op1 and op2,
 + * and 4 bit CRn and CRm. The encoding patterns are chosen
 + * to be easy to convert to and from the KVM encodings, and also
 + * so that the hashtable can contain both AArch32 and AArch64
 + * registers (to allow for interprocessing where we might run
 + * 32 bit code on a 64 bit core).
 + */
 +/*
 + * This bit is private to our hashtable cpreg; in KVM register
 + * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
 + * in the upper bits of the 64 bit ID.
 + */
 +#define CP_REG_AA64_SHIFT 28
 +#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
 +
 +/*
 + * To enable banking of coprocessor registers depending on ns-bit we
 + * add a bit to distinguish between secure and non-secure cpregs in the
 + * hashtable.
 + */
 +#define CP_REG_NS_SHIFT 29
 +#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
 +
 +#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
 +    ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
 +     ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
 +
 +#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
 +    (CP_REG_AA64_MASK |                                 \
 +     ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
 +     ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
 +     ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
 +     ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
 +     ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
 +     ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
 +
 +/*
 + * Convert a full 64 bit KVM register ID to the truncated 32 bit
 + * version used as a key for the coprocessor register hashtable
 + */
 +static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
 +{
 +    uint32_t cpregid = kvmid;
 +    if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
 +        cpregid |= CP_REG_AA64_MASK;
 +    } else {
 +        if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
 +            cpregid |= (1 << 15);
 +        }
 +
 +        /*
 +         * KVM is always non-secure so add the NS flag on AArch32 register
 +         * entries.
 +         */
 +         cpregid |= 1 << CP_REG_NS_SHIFT;
 +    }
 +    return cpregid;
 +}
 +
 +/*
 + * Convert a truncated 32 bit hashtable key into the full
 + * 64 bit KVM register ID.
 + */
 +static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
 +{
 +    uint64_t kvmid;
 +
 +    if (cpregid & CP_REG_AA64_MASK) {
 +        kvmid = cpregid & ~CP_REG_AA64_MASK;
 +        kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
 +    } else {
 +        kvmid = cpregid & ~(1 << 15);
 +        if (cpregid & (1 << 15)) {
 +            kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
 +        } else {
 +            kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
 +        }
 +    }
 +    return kvmid;
 +}
 +
  /*
   * Valid values for ARMCPRegInfo state field, indicating which of
   * the AArch32 and AArch64 execution states this register is visible in.
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
  uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                   uint32_t cur_el, bool secure);
 -/* Interface for defining coprocessor registers.
 - * Registers are defined in tables of arm_cp_reginfo structs
 - * which are passed to define_arm_cp_regs().
 - */
 -
 -/* When looking up a coprocessor register we look for it
 - * via an integer which encodes all of:
 - *  coprocessor number
 - *  Crn, Crm, opc1, opc2 fields
 - *  32 or 64 bit register (ie is it accessed via MRC/MCR
 - *    or via MRRC/MCRR?)
 - *  non-secure/secure bank (AArch32 only)
 - * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 - * (In this case crn and opc2 should be zero.)
 - * For AArch64, there is no 32/64 bit size distinction;
 - * instead all registers have a 2 bit op0, 3 bit op1 and op2,
 - * and 4 bit CRn and CRm. The encoding patterns are chosen
 - * to be easy to convert to and from the KVM encodings, and also
 - * so that the hashtable can contain both AArch32 and AArch64
 - * registers (to allow for interprocessing where we might run
 - * 32 bit code on a 64 bit core).
 - */
 -/* This bit is private to our hashtable cpreg; in KVM register
 - * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
 - * in the upper bits of the 64 bit ID.
 - */
 -#define CP_REG_AA64_SHIFT 28
 -#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
 -
 -/* To enable banking of coprocessor registers depending on ns-bit we
 - * add a bit to distinguish between secure and non-secure cpregs in the
 - * hashtable.
 - */
 -#define CP_REG_NS_SHIFT 29
 -#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
 -
 -#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
 -    ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
 -     ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
 -
 -#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
 -    (CP_REG_AA64_MASK |                                 \
 -     ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
 -     ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
 -     ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
 -     ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
 -     ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
 -     ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
 -
 -/* Convert a full 64 bit KVM register ID to the truncated 32 bit
 - * version used as a key for the coprocessor register hashtable
 - */
 -static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
 -{
 -    uint32_t cpregid = kvmid;
 -    if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
 -        cpregid |= CP_REG_AA64_MASK;
 -    } else {
 -        if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
 -            cpregid |= (1 << 15);
 -        }
 -
 -        /* KVM is always non-secure so add the NS flag on AArch32 register
 -         * entries.
 -         */
 -         cpregid |= 1 << CP_REG_NS_SHIFT;
 -    }
 -    return cpregid;
 -}
 -
 -/* Convert a truncated 32 bit hashtable key into the full
 - * 64 bit KVM register ID.
 - */
 -static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
 -{
 -    uint64_t kvmid;
 -
 -    if (cpregid & CP_REG_AA64_MASK) {
 -        kvmid = cpregid & ~CP_REG_AA64_MASK;
 -        kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
 -    } else {
 -        kvmid = cpregid & ~(1 << 15);
 -        if (cpregid & (1 << 15)) {
 -            kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
 -        } else {
 -            kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
 -        }
 -    }
 -    return kvmid;
 -}
 -
  /* Return the highest implemented Exception Level */
  static inline int arm_highest_el(CPUARMState *env)
  {
 --
 .34.1

-New patch
+[PULL 26/30] tests/avocado: Skip tests that require a missing accelerator
+From: Fabiano Rosas <farosas@suse.de>
+If a test was tagged with the "accel" tag and the specified
+accelerator it not present in the qemu binary, cancel the test.
+We can now write tests without explicit calls to require_accelerator,
+just the tag is enough.
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ tests/avocado/avocado_qemu/__init__.py | 4 ++++
+file changed, 4 insertions(+)
+diff --git a/tests/avocado/avocado_qemu/__init__.py b/tests/avocado/avocado_qemu/__init__.py
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/avocado/avocado_qemu/__init__.py
++++ b/tests/avocado/avocado_qemu/__init__.py
+@@ -XXX,XX +XXX,XX @@ def setUp(self):
+         super().setUp('qemu-system-')
++        accel_required = self._get_unique_tag_val('accel')
++        if accel_required:
++            self.require_accelerator(accel_required)
++
+         self.machine = self.params.get('machine',
+                                        default=self._get_unique_tag_val('machine'))
+--
+.34.1

-New patch
+[PULL 27/30] tests/avocado: Tag TCG tests with accel:tcg
+From: Fabiano Rosas <farosas@suse.de>
+This allows the test to be skipped when TCG is not present in the QEMU
+binary.
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ tests/avocado/boot_linux_console.py | 1 +
+ tests/avocado/reverse_debugging.py  | 8 ++++++++
+files changed, 9 insertions(+)
+diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/avocado/boot_linux_console.py
++++ b/tests/avocado/boot_linux_console.py
+@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_uboot_netbsd9(self):
+     def test_aarch64_raspi3_atf(self):
+         """
++        :avocado: tags=accel:tcg
+         :avocado: tags=arch:aarch64
+         :avocado: tags=machine:raspi3b
+         :avocado: tags=cpu:cortex-a53
+diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/avocado/reverse_debugging.py
++++ b/tests/avocado/reverse_debugging.py
+@@ -XXX,XX +XXX,XX @@ def reverse_debugging(self, shift=7, args=None):
+         vm.shutdown()
+ class ReverseDebugging_X86_64(ReverseDebugging):
++    """
++    :avocado: tags=accel:tcg
++    """
++
+     REG_PC = 0x10
+     REG_CS = 0x12
+     def get_pc(self, g):
+@@ -XXX,XX +XXX,XX @@ def test_x86_64_pc(self):
+         self.reverse_debugging()
+ class ReverseDebugging_AArch64(ReverseDebugging):
++    """
++    :avocado: tags=accel:tcg
++    """
++
+     REG_PC = 32
+     # unidentified gitlab timeout problem
+--
+.34.1

-New patch
+[PULL 28/30] target/arm: Use "max" as default cpu for the virt machine with KVM
+From: Fabiano Rosas <farosas@suse.de>
+Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a
+KVM-only build the 'max' cpu.
+Note that we cannot use 'host' here because the qtests can run without
+any other accelerator (than qtest) and 'host' depends on KVM being
+enabled.
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Acked-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/virt.c | 4 ++++
+file changed, 4 insertions(+)
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/virt.c
++++ b/hw/arm/virt.c
+@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
+     mc->minimum_page_bits = 12;
+     mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
+     mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
++#ifdef CONFIG_TCG
+     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
++#else
++    mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
++#endif
+     mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
+     mc->kvm_type = virt_kvm_type;
+     assert(!mc->get_hotplug_handler);
+--
+.34.1

-New patch
+[PULL 29/30] tests/qtest: arm-cpu-features: Match tests to required accelerators
+From: Fabiano Rosas <farosas@suse.de>
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Acked-by: Thomas Huth <thuth@redhat.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ tests/qtest/arm-cpu-features.c | 28 ++++++++++++++++++----------
+file changed, 18 insertions(+), 10 deletions(-)
+diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/qtest/arm-cpu-features.c
++++ b/tests/qtest/arm-cpu-features.c
+@@ -XXX,XX +XXX,XX @@
+ #define SVE_MAX_VQ 16
+ #define MACHINE     "-machine virt,gic-version=max -accel tcg "
+-#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg "
++#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm "
+ #define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
+                     "  'arguments': { 'type': 'full', "
+ #define QUERY_TAIL  "}}"
+@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
+ {
+     g_test_init(&argc, &argv, NULL);
+-    qtest_add_data_func("/arm/query-cpu-model-expansion",
+-                        NULL, test_query_cpu_model_expansion);
++    if (qtest_has_accel("tcg")) {
++        qtest_add_data_func("/arm/query-cpu-model-expansion",
++                            NULL, test_query_cpu_model_expansion);
++    }
++
++    if (!g_str_equal(qtest_get_arch(), "aarch64")) {
++        goto out;
++    }
+     /*
+      * For now we only run KVM specific tests with AArch64 QEMU in
+      * order avoid attempting to run an AArch32 QEMU with KVM on
+      * AArch64 hosts. That won't work and isn't easy to detect.
+      */
+-    if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) {
++    if (qtest_has_accel("kvm")) {
+         /*
+          * This tests target the 'host' CPU type, so register it only if
+          * KVM is available.
+          */
+         qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
+                             NULL, test_query_cpu_model_expansion_kvm);
+-    }
+-    if (g_str_equal(qtest_get_arch(), "aarch64")) {
+-        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
+-                            NULL, sve_tests_sve_max_vq_8);
+-        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
+-                            NULL, sve_tests_sve_off);
+         qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
+                             NULL, sve_tests_sve_off_kvm);
+     }
++    if (qtest_has_accel("tcg")) {
++        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
++                            NULL, sve_tests_sve_max_vq_8);
++        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
++                            NULL, sve_tests_sve_off);
++    }
++
++out:
+     return g_test_run();
+ }
+--
+.34.1

-[PULL 4/5] hw/arm/virt-acpi-build: Present the GICR structure properly for GICv4
+[PULL 30/30] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
-From: Zenghui Yu <yuzenghui@huawei.com>
+From: Fabiano Rosas <farosas@suse.de>
-With the introduction of the new TCG GICv4, build_madt() is badly broken
+These tests set -accel tcg, so restrict them to when TCG is present.
 as we do not present any GIC Redistributor structure in MADT for GICv4
 guests, so that they have no idea about where the Redistributor
 register frames are. This fixes a Linux guest crash at boot time with
 ACPI enabled and '-machine gic-version=4'.
-While at it, let's convert the remaining hard coded gic_version into
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
-enumeration VIRT_GIC_VERSION_2 for consistency.
+Acked-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
 Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
 Message-id: 20220812022018.1069-1-yuzenghui@huawei.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt-acpi-build.c | 4 ++--
+ tests/qtest/meson.build | 4 ++--
 file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
+diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt-acpi-build.c
+--- a/tests/qtest/meson.build
-+++ b/hw/arm/virt-acpi-build.c
++++ b/tests/qtest/meson.build
-@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
+@@ -XXX,XX +XXX,XX @@ qtests_arm = \
-         uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
+ # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional
-                                              PPI(VIRTUAL_PMU_IRQ) : 0;
+ qtests_aarch64 = \
+   (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) +                            \
--        if (vms->gic_version == 2) {
+-  (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) +        \
-+        if (vms->gic_version == VIRT_GIC_VERSION_2) {
+-  (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) +  \
-             physical_base_address = memmap[VIRT_GIC_CPU].base;
++  (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ?            \
-             gicv = memmap[VIRT_GIC_VCPU].base;
++    ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) +                                         \
-             gich = memmap[VIRT_GIC_HYP].base;
+   (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \
-@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
+   (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) +  \
-         build_append_int_noprefix(table_data, armcpu->mp_affinity, 8);
+   ['arm-cpu-features',
      }
 -    if (vms->gic_version == 3) {
 +    if (vms->gic_version != VIRT_GIC_VERSION_2) {
          build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base,
                                        memmap[VIRT_GIC_REDIST].size);
          if (virt_gicv3_redist_region_count(vms) == 2) {
 --
-.25.1
+.34.1

This pullreq has:
 * two arm bug fixes which fix some "Linux fails to boot" bugs
 * a docs typo-fixing patch
 * a couple of compile failure/warning issues

I think they're all pretty safe and worth having in rc3.

thanks
-- PMM

The following changes since commit a6b1c53e79d08a99a28cc3e67a3e1a7c34102d6b:

Merge tag 'linux-user-for-7.1-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2022-08-10 10:26:57 -0700)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220812

for you to fetch changes up to 4311682ea8293f720730f260e8a7601117d79e65:

cutils: Add missing dyld(3) include on macOS (2022-08-12 11:33:52 +0100)

----------------------------------------------------------------
target-arm queue:
 * Don't report Statistical Profiling Extension in ID registers
 * virt ACPI tables: Present the GICR structure properly for GICv4
 * Fix some typos in documentation
 * tests/unit: fix a -Wformat-truncation warning
 * cutils: Add missing dyld(3) include on macOS

----------------------------------------------------------------
Marc-André Lureau (1):
      tests/unit: fix a -Wformat-truncation warning

Peter Maydell (1):
      target/arm: Don't report Statistical Profiling Extension in ID registers

Philippe Mathieu-Daudé (1):
      cutils: Add missing dyld(3) include on macOS

Stefan Weil (1):
      Fix some typos in documentation (most of them found by codespell)

Zenghui Yu (1):
      hw/arm/virt-acpi-build: Present the GICR structure properly for GICv4

The newly added neoverse-n1 CPU has ID register values which indicate
the presence of the Statistical Profiling Extension, because the real
hardware has this feature.  QEMU's TCG emulation does not yet
implement SPE, though (not even as a minimal stub implementation), so
guests will crash if they try to use it because the SPE system
registers don't exist.

Force ID_AA64DFR0_EL1.PMSVer to 0 in CPU realize for TCG, so that
we don't advertise to the guest a feature that doesn't exist.

(We could alternatively do this by editing the value that
aarch64_neoverse_n1_initfn() sets for this ID register, but
suppressing the field in realize means we won't re-introduce this bug
when we add other CPUs that have SPE in hardware, such as the
Neoverse-V1.)

An example of a non-booting guest is current mainline Linux (5.19),
when booting in EL2 on the virt board (ie with -machine
virtualization=on).

Reported-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Message-id: 20220811131127.947334-1-peter.maydell@linaro.org
---
 target/arm/cpu.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     }
 #endif
 
+    if (tcg_enabled()) {
+        /*
+         * Don't report the Statistical Profiling Extension in the ID
+         * registers, because TCG doesn't implement it yet (not even a
+         * minimal stub version) and guests will fall over when they
+         * try to access the non-existent system registers for it.
+         */
+        cpu->isar.id_aa64dfr0 =
+            FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
+    }
+
     /* MPU can be configured out of a PMSA CPU either by setting has-mpu
      * to false or by setting pmsav7-dregion to 0.
      */
-- 
2.25.1

From: Stefan Weil <sw@weilnetz.de>

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Hongren (Zenithal) Zheng <i@zenithal.me>
Message-id: 20220812075642.1200578-1-sw@weilnetz.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/about/deprecated.rst       |  2 +-
 docs/specs/acpi_erst.rst        |  4 ++--
 docs/system/devices/canokey.rst |  8 ++++----
 docs/system/devices/cxl.rst     | 12 ++++++------
 4 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -XXX,XX +XXX,XX @@ by using ``-machine graphics=off``.
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 In QEMU versions 6.1, 6.2 and 7.0, the ``nvme-ns`` generates an EUI-64
-identifer that is not globally unique. If an EUI-64 identifer is required, the
+identifier that is not globally unique. If an EUI-64 identifier is required, the
 user must set it explicitly using the ``nvme-ns`` device parameter ``eui64``.
 
 ``-device nvme,use-intel-id=on|off`` (since 7.1)
diff --git a/docs/specs/acpi_erst.rst b/docs/specs/acpi_erst.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/specs/acpi_erst.rst
+++ b/docs/specs/acpi_erst.rst
@@ -XXX,XX +XXX,XX @@ Slot 0 contains a backend storage header that identifies the contents
 as ERST and also facilitates efficient access to the records.
 Depending upon the size of the backend storage, additional slots will
 be designated to be a part of the slot 0 header. For example, at 8KiB,
-the slot 0 header can accomodate 1021 records. Thus a storage size
+the slot 0 header can accommodate 1021 records. Thus a storage size
 of 8MiB (8KiB * 1024) requires an additional slot for use by the
 header. In this scenario, slot 0 and slot 1 form the backend storage
 header, and records can be stored starting at slot 2.
@@ -XXX,XX +XXX,XX @@ References
 [2] "Unified Extensible Firmware Interface Specification",
     version 2.1, October 2008.
 
-[3] "Windows Hardware Error Architecture", specfically
+[3] "Windows Hardware Error Architecture", specifically
     "Error Record Persistence Mechanism".
diff --git a/docs/system/devices/canokey.rst b/docs/system/devices/canokey.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/devices/canokey.rst
+++ b/docs/system/devices/canokey.rst
@@ -XXX,XX +XXX,XX @@ With the same software configuration as a hardware key,
 the guest OS can use all the functionalities of a secure key as if
 there was actually an hardware key plugged in.
 
-CanoKey QEMU provides much convenience for debuging:
+CanoKey QEMU provides much convenience for debugging:
 
-* libcanokey-qemu supports debuging output thus developers can
+* libcanokey-qemu supports debugging output thus developers can
   inspect what happens inside a secure key
 * CanoKey QEMU supports trace event thus event
 * QEMU USB stack supports pcap thus USB packet between the guest
@@ -XXX,XX +XXX,XX @@ and find CanoKey QEMU there:
 
 You may setup the key as guided in [6]_. The console for the key is at [7]_.
 
-Debuging
-========
+Debugging
+=========
 
 CanoKey QEMU consists of two parts, ``libcanokey-qemu.so`` and ``canokey.c``,
 the latter of which resides in QEMU. The former provides core functionality
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/devices/cxl.rst
+++ b/docs/system/devices/cxl.rst
@@ -XXX,XX +XXX,XX @@ CXL Fixed Memory Windows (CFMW)
 A CFMW consists of a particular range of Host Physical Address space
 which is routed to particular CXL Host Bridges.  At time of generic
 software initialization it will have a particularly interleaving
-configuration and associated Quality of Serice Throtling Group (QTG).
+configuration and associated Quality of Service Throttling Group (QTG).
 This information is available to system software, when making
 decisions about how to configure interleave across available CXL
 memory devices.  It is provide as CFMW Structures (CFMWS) in
@@ -XXX,XX +XXX,XX @@ specification defined register interface called CXL Host Bridge
 Component Registers (CHBCR). The location of this CHBCR MMIO
 space is described to system software via a CXL Host Bridge
 Structure (CHBS) in the CEDT ACPI table.  The actual interfaces
-are identical to those used for other parts of the CXL heirarchy
+are identical to those used for other parts of the CXL hierarchy
 as CXL Component Registers in PCI BARs.
 
 Interfaces provided include:
@@ -XXX,XX +XXX,XX @@ CXL Memory Devices - Type 3
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
 CXL type 3 devices use a PCI class code and are intended to be supported
 by a generic operating system driver. They have HDM decoders
-though in these EP devices, the decoder is reponsible not for
+though in these EP devices, the decoder is responsible not for
 routing but for translation of the incoming host physical address (HPA)
 into a Device Physical Address (DPA).
 
@@ -XXX,XX +XXX,XX @@ Notes:
     ranges of the system physical address map.  Each CFMW has
     particular interleave setup across the CXL Host Bridges (HB)
     CFMW0 provides uninterleaved access to HB0, CFW2 provides
-    uninterleaved acess to HB1. CFW1 provides interleaved memory access
+    uninterleaved access to HB1. CFW1 provides interleaved memory access
     across HB0 and HB1.
 
 (2) **Two CXL Host Bridges**. Each of these has 2 CXL Root Ports and
@@ -XXX,XX +XXX,XX @@ Example topology involving a switch::
             ---------------------------------------------------
            |    Switch 0  USP as PCI 0d:00.0                   |
            |    USP has HDM decoder which direct traffic to    |
-           |    appropiate downstream port                     |
+           |    appropriate downstream port                    |
            |    Switch BUS appears as 0e                       |
            |x__________________________________________________|
             |                  |               |              |
@@ -XXX,XX +XXX,XX @@ An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave::
 Kernel Configuration Options
 ----------------------------
 
-In Linux 5.18 the followings options are necessary to make use of
+In Linux 5.18 the following options are necessary to make use of
 OS management of CXL memory devices as described here.
 
 * CONFIG_CXL_BUS
-- 
2.25.1

From: Marc-André Lureau <marcandre.lureau@redhat.com>

../tests/test-qobject-input-visitor.c: In function ‘test_visitor_in_list’:
../tests/test-qobject-input-visitor.c:454:49: warning: ‘%d’ directive output may be truncated writing between 1 and 10 bytes into a region of size 6 [-Wformat-truncation=]
  454 |         snprintf(string, sizeof(string), "string%d", i);
      |                                                 ^~
../tests/test-qobject-input-visitor.c:454:42: note: directive argument in the range [0, 2147483606]
  454 |         snprintf(string, sizeof(string), "string%d", i);
      |                                          ^~~~~~~~~~
../tests/test-qobject-input-visitor.c:454:9: note: ‘snprintf’ output between 8 and 17 bytes into a destination of size 12
  454 |         snprintf(string, sizeof(string), "string%d", i);
      |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Rather than trying to be clever, since this is called 3 times during
tests, let's simply use g_strdup_printf().

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-id: 20220810121513.1356081-1-marcandre.lureau@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: fixed commit message typos]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/unit/test-qobject-input-visitor.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/tests/unit/test-qobject-input-visitor.c b/tests/unit/test-qobject-input-visitor.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/unit/test-qobject-input-visitor.c
+++ b/tests/unit/test-qobject-input-visitor.c
@@ -XXX,XX +XXX,XX @@ static void test_visitor_in_list(TestInputVisitorData *data,
     g_assert(head != NULL);
 
     for (i = 0, item = head; item; item = item->next, i++) {
-        char string[12];
+        g_autofree char *string = g_strdup_printf("string%d", i);
 
-        snprintf(string, sizeof(string), "string%d", i);
         g_assert_cmpstr(item->value->string, ==, string);
         g_assert_cmpint(item->value->integer, ==, 42 + i);
     }
-- 
2.25.1

From: Zenghui Yu <yuzenghui@huawei.com>

With the introduction of the new TCG GICv4, build_madt() is badly broken
as we do not present any GIC Redistributor structure in MADT for GICv4
guests, so that they have no idea about where the Redistributor
register frames are. This fixes a Linux guest crash at boot time with
ACPI enabled and '-machine gic-version=4'.

While at it, let's convert the remaining hard coded gic_version into
enumeration VIRT_GIC_VERSION_2 for consistency.

Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Message-id: 20220812022018.1069-1-yuzenghui@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt-acpi-build.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
                                              PPI(VIRTUAL_PMU_IRQ) : 0;
 
-        if (vms->gic_version == 2) {
+        if (vms->gic_version == VIRT_GIC_VERSION_2) {
             physical_base_address = memmap[VIRT_GIC_CPU].base;
             gicv = memmap[VIRT_GIC_VCPU].base;
             gich = memmap[VIRT_GIC_HYP].base;
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         build_append_int_noprefix(table_data, armcpu->mp_affinity, 8);
     }
 
-    if (vms->gic_version == 3) {
+    if (vms->gic_version != VIRT_GIC_VERSION_2) {
         build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base,
                                       memmap[VIRT_GIC_REDIST].size);
         if (virt_gicv3_redist_region_count(vms) == 2) {
-- 
2.25.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Commit 06680b15b4 moved qemu_*_exec_dir() to cutils but forgot
to move the macOS dyld(3) include, resulting in the following
error (when building with Homebrew GCC on macOS Monterey 12.4):

[313/1197] Compiling C object libqemuutil.a.p/util_cutils.c.o
  FAILED: libqemuutil.a.p/util_cutils.c.o
  ../../util/cutils.c:1039:13: error: implicit declaration of function '_NSGetExecutablePath' [-Werror=implicit-function-declaration]
   1039 |         if (_NSGetExecutablePath(fpath, &len) == 0) {
        |             ^~~~~~~~~~~~~~~~~~~~
  ../../util/cutils.c:1039:13: error: nested extern declaration of '_NSGetExecutablePath' [-Werror=nested-externs]

Fix by moving the include line to cutils.

Fixes: 06680b15b4 ("include: move qemu_*_exec_dir() to cutils")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220809222046.30812-1-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 util/cutils.c      | 4 ++++
 util/oslib-posix.c | 4 ----
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/util/cutils.c b/util/cutils.c
index XXXXXXX..XXXXXXX 100644
--- a/util/cutils.c
+++ b/util/cutils.c
@@ -XXX,XX +XXX,XX @@
 #include <kernel/image.h>
 #endif
 
+#ifdef __APPLE__
+#include <mach-o/dyld.h>
+#endif
+
 #ifdef G_OS_WIN32
 #include <pathcch.h>
 #include <wchar.h>
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
index XXXXXXX..XXXXXXX 100644
--- a/util/oslib-posix.c
+++ b/util/oslib-posix.c
@@ -XXX,XX +XXX,XX @@
 #include <lwp.h>
 #endif
 
-#ifdef __APPLE__
-#include <mach-o/dyld.h>
-#endif
-
 #include "qemu/mmap-alloc.h"
 
 #ifdef CONFIG_DEBUG_STACK_USAGE
-- 
2.25.1

The following changes since commit 003ba52a8b327180e284630b289c6ece5a3e08b9:

Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-02-16 11:16:39 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230216

for you to fetch changes up to caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8:

tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG (2023-02-16 16:28:53 +0000)

----------------------------------------------------------------
target-arm queue:
 * Some mostly M-profile-related code cleanups
 * avocado: Retire the boot_linux.py AArch64 TCG tests
 * hw/arm/smmuv3: Add GBPA register
 * arm/virt: don't try to spell out the accelerator
 * hw/arm: Attach PSPI module to NPCM7XX SoC
 * Some cleanup/refactoring patches aiming towards
   allowing building Arm targets without CONFIG_TCG

----------------------------------------------------------------
Alex Bennée (1):
      tests/avocado: retire the Aarch64 TCG tests from boot_linux.py

Claudio Fontana (3):
      target/arm: rename handle_semihosting to tcg_handle_semihosting
      target/arm: wrap psci call with tcg_enabled
      target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()

Cornelia Huck (1):
      arm/virt: don't try to spell out the accelerator

Fabiano Rosas (7):
      target/arm: Move PC alignment check
      target/arm: Move cpregs code out of cpu.h
      tests/avocado: Skip tests that require a missing accelerator
      tests/avocado: Tag TCG tests with accel:tcg
      target/arm: Use "max" as default cpu for the virt machine with KVM
      tests/qtest: arm-cpu-features: Match tests to required accelerators
      tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG

Hao Wu (3):
      MAINTAINERS: Add myself to maintainers and remove Havard
      hw/ssi: Add Nuvoton PSPI Module
      hw/arm: Attach PSPI module to NPCM7XX SoC

Jean-Philippe Brucker (2):
      hw/arm/smmu-common: Support 64-bit addresses
      hw/arm/smmu-common: Fix TTB1 handling

Mostafa Saleh (1):
      hw/arm/smmuv3: Add GBPA register

Philippe Mathieu-Daudé (12):
      hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro
      target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation
      target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope
      target/arm: Constify ID_PFR1 on user emulation
      target/arm: Convert CPUARMState::eabi to boolean
      target/arm: Avoid resetting CPUARMState::eabi field
      target/arm: Restrict CPUARMState::gicv3state to sysemu
      target/arm: Restrict CPUARMState::arm_boot_info to sysemu
      target/arm: Restrict CPUARMState::nvic to sysemu
      target/arm: Store CPUARMState::nvic as NVICState*
      target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
      hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro,
similarly to automatic conversion from commit 8063396bf3
("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/intc/armv7m_nvic.h | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@
 #include "qom/object.h"
 
 #define TYPE_NVIC "armv7m_nvic"
-
-typedef struct NVICState NVICState;
-DECLARE_INSTANCE_CHECKER(NVICState, NVIC,
-                         TYPE_NVIC)
+OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC)
 
 /* Highest permitted number of exceptions (architectural limit) */
 #define NVIC_MAX_VECTORS 512
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/m_helper.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
     return 0;
 }
 
-#else
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+{
+    return ARMMMUIdx_MUser;
+}
+
+#else /* !CONFIG_USER_ONLY */
 
 /*
  * What kind of stack write are we doing? This affects how exceptions
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
     return tt_resp;
 }
 
-#endif /* !CONFIG_USER_ONLY */
-
 ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
                               bool secstate, bool priv, bool negpri)
 {
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
 
     return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
 }
+
+#endif /* !CONFIG_USER_ONLY */
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv()
are only used for system emulation in m_helper.c.
Move the definitions to avoid prototype forward declarations.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h | 14 --------
 target/arm/m_helper.c  | 74 +++++++++++++++++++++---------------------
 2 files changed, 37 insertions(+), 51 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx)
 
 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
 
-/*
- * Return the MMU index for a v7M CPU with all relevant information
- * manually specified.
- */
-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
-                              bool secstate, bool priv, bool negpri);
-
-/*
- * Return the MMU index for a v7M CPU in the specified security and
- * privilege state.
- */
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
-                                                bool secstate, bool priv);
-
 /* Return the MMU index for a v7M CPU in the specified security state */
 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
 
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
 
 #else /* !CONFIG_USER_ONLY */
 
+static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+                                     bool secstate, bool priv, bool negpri)
+{
+    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
+
+    if (priv) {
+        mmu_idx |= ARM_MMU_IDX_M_PRIV;
+    }
+
+    if (negpri) {
+        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
+    }
+
+    if (secstate) {
+        mmu_idx |= ARM_MMU_IDX_M_S;
+    }
+
+    return mmu_idx;
+}
+
+static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+                                                       bool secstate, bool priv)
+{
+    bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
+
+    return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
+}
+
+/* Return the MMU index for a v7M CPU in the specified security state */
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+{
+    bool priv = arm_v7m_is_handler_mode(env) ||
+        !(env->v7m.control[secstate] & 1);
+
+    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
+}
+
 /*
  * What kind of stack write are we doing? This affects how exceptions
  * generated during the stacking are treated.
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
     return tt_resp;
 }
 
-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
-                              bool secstate, bool priv, bool negpri)
-{
-    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
-
-    if (priv) {
-        mmu_idx |= ARM_MMU_IDX_M_PRIV;
-    }
-
-    if (negpri) {
-        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
-    }
-
-    if (secstate) {
-        mmu_idx |= ARM_MMU_IDX_M_S;
-    }
-
-    return mmu_idx;
-}
-
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
-                                                bool secstate, bool priv)
-{
-    bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
-
-    return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
-}
-
-/* Return the MMU index for a v7M CPU in the specified security state */
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
-{
-    bool priv = arm_v7m_is_handler_mode(env) ||
-        !(env->v7m.control[secstate] & 1);
-
-    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
-}
-
 #endif /* !CONFIG_USER_ONLY */
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230206223502.25122-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
     }
 }
 
+#ifndef CONFIG_USER_ONLY
 /*
  * We don't know until after realize whether there's a GICv3
  * attached, and that is what registers the gicv3 sysregs.
@@ -XXX,XX +XXX,XX @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
     return pfr1;
 }
 
-#ifndef CONFIG_USER_ONLY
 static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     ARMCPU *cpu = env_archcpu(env);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
               .access = PL1_R, .type = ARM_CP_NO_RAW,
               .accessfn = access_aa32_tid3,
+#ifdef CONFIG_USER_ONLY
+              .type = ARM_CP_CONST,
+              .resetvalue = cpu->isar.id_pfr1,
+#else
+              .type = ARM_CP_NO_RAW,
+              .accessfn = access_aa32_tid3,
               .readfn = id_pfr1_read,
-              .writefn = arm_cp_write_ignore },
+              .writefn = arm_cp_write_ignore
+#endif
+            },
             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
               .access = PL1_R, .type = ARM_CP_CONST,
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/user-internals.h | 2 +-
 target/arm/cpu.h            | 2 +-
 linux-user/arm/cpu_loop.c   | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/user-internals.h
+++ b/linux-user/user-internals.h
@@ -XXX,XX +XXX,XX @@ void print_termios(void *arg);
 #ifdef TARGET_ARM
 static inline int regpairs_aligned(CPUArchState *cpu_env, int num)
 {
-    return cpu_env->eabi == 1;
+    return cpu_env->eabi;
 }
 #elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32)
 static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; }
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
 
 #if defined(CONFIG_USER_ONLY)
     /* For usermode syscall translation.  */
-    int eabi;
+    bool eabi;
 #endif
 
     struct CPUBreakpoint *cpu_breakpoint[16];
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/arm/cpu_loop.c
+++ b/linux-user/arm/cpu_loop.c
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
             break;
         case EXCP_SWI:
             {
-                env->eabi = 1;
+                env->eabi = true;
                 /* system call */
                 if (env->thumb) {
                     /* Thumb is always EABI style with syscall number in r7 */
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
                          * > 0xfffff and are handled below as out-of-range.
                          */
                         n ^= ARM_SYSCALL_BASE;
-                        env->eabi = 0;
+                        env->eabi = false;
                     }
                 }
 
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Although the 'eabi' field is only used in user emulation where
CPU reset doesn't occur, it doesn't belong to the area to reset.
Move it after the 'end_reset_fields' for consistency.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230206223502.25122-7-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
     ARMVectorReg zarray[ARM_MAX_VQ * 16];
 #endif
 
-#if defined(CONFIG_USER_ONLY)
-    /* For usermode syscall translation.  */
-    bool eabi;
-#endif
-
     struct CPUBreakpoint *cpu_breakpoint[16];
     struct CPUWatchpoint *cpu_watchpoint[16];
 
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
     const struct arm_boot_info *boot_info;
     /* Store GICv3CPUState to access from this struct */
     void *gicv3state;
+#if defined(CONFIG_USER_ONLY)
+    /* For usermode syscall translation.  */
+    bool eabi;
+#endif /* CONFIG_USER_ONLY */
 
 #ifdef TARGET_TAGGED_ADDRESSES
     /* Linux syscall tagged address support */
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

There is no point in using a void pointer to access the NVIC.
Use the real type to avoid casting it while debugging.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-11-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h      | 46 ++++++++++++++++++++++---------------------
 hw/intc/armv7m_nvic.c | 38 ++++++++++++-----------------------
 target/arm/cpu.c      |  1 +
 target/arm/m_helper.c |  2 +-
 4 files changed, 39 insertions(+), 48 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMTBFlags {
 
 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
 
+typedef struct NVICState NVICState;
+
 typedef struct CPUArchState {
     /* Regs for current mode.  */
     uint32_t regs[16];
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
     } sau;
 
 #if !defined(CONFIG_USER_ONLY)
-    void *nvic;
+    NVICState *nvic;
     const struct arm_boot_info *boot_info;
     /* Store GICv3CPUState to access from this struct */
     void *gicv3state;
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
 
 /* Interface between CPU and Interrupt controller.  */
 #ifndef CONFIG_USER_ONLY
-bool armv7m_nvic_can_take_pending_exception(void *opaque);
+bool armv7m_nvic_can_take_pending_exception(NVICState *s);
 #else
-static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
+static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
 {
     return true;
 }
 #endif
 /**
  * armv7m_nvic_set_pending: mark the specified exception as pending
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to mark pending
  * @secure: false for non-banked exceptions or for the nonsecure
  * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
  * if @secure is true and @irq does not specify one of the fixed set
  * of architecturally banked exceptions.
  */
-void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
+void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_set_pending_derived: mark this derived exception as pending
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to mark pending
  * @secure: false for non-banked exceptions or for the nonsecure
  * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
  * exceptions (exceptions generated in the course of trying to take
  * a different exception).
  */
-void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
+void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to mark pending
  * @secure: false for non-banked exceptions or for the nonsecure
  * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
  * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
  * generated in the course of lazy stacking of FP registers.
  */
-void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
+void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_get_pending_irq_info: return highest priority pending
  *    exception, and whether it targets Secure state
- * @opaque: the NVIC
+ * @s: the NVIC
  * @pirq: set to pending exception number
  * @ptargets_secure: set to whether pending exception targets Secure
  *
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
  * to true if the current highest priority pending exception should
  * be taken to Secure state, false for NS.
  */
-void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
+void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
                                       bool *ptargets_secure);
 /**
  * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
- * @opaque: the NVIC
+ * @s: the NVIC
  *
  * Move the current highest priority pending exception from the pending
  * state to the active state, and update v7m.exception to indicate that
  * it is the exception currently being handled.
  */
-void armv7m_nvic_acknowledge_irq(void *opaque);
+void armv7m_nvic_acknowledge_irq(NVICState *s);
 /**
  * armv7m_nvic_complete_irq: complete specified interrupt or exception
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to complete
  * @secure: true if this exception was secure
  *
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque);
  *           0 if there is still an irq active after this one was completed
  * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
  */
-int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
+int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to mark pending
  * @secure: false for non-banked exceptions or for the nonsecure
  * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
  * interrupt the current execution priority. This controls whether the
  * RDY bit for it in the FPCCR is set.
  */
-bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
+bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_raw_execution_priority: return the raw execution priority
- * @opaque: the NVIC
+ * @s: the NVIC
  *
  * Returns: the raw execution priority as defined by the v8M architecture.
  * This is the execution priority minus the effects of AIRCR.PRIS,
  * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
  * (v8M ARM ARM I_PKLD.)
  */
-int armv7m_nvic_raw_execution_priority(void *opaque);
+int armv7m_nvic_raw_execution_priority(NVICState *s);
 /**
  * armv7m_nvic_neg_prio_requested: return true if the requested execution
  * priority is negative for the specified security state.
- * @opaque: the NVIC
+ * @s: the NVIC
  * @secure: the security state to test
  * This corresponds to the pseudocode IsReqExecPriNeg().
  */
 #ifndef CONFIG_USER_ONLY
-bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
+bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
 #else
-static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
+static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
 {
     return false;
 }
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
     return MIN(running, s->exception_prio);
 }
 
-bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
+bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
 {
     /* Return true if the requested execution priority is negative
      * for the specified security state, ie that security state
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
      * mean we don't allow FAULTMASK_NS to actually make the execution
      * priority negative). Compare pseudocode IsReqExcPriNeg().
      */
-    NVICState *s = opaque;
-
     if (s->cpu->env.v7m.faultmask[secure]) {
         return true;
     }
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
     return false;
 }
 
-bool armv7m_nvic_can_take_pending_exception(void *opaque)
+bool armv7m_nvic_can_take_pending_exception(NVICState *s)
 {
-    NVICState *s = opaque;
-
     return nvic_exec_prio(s) > nvic_pending_prio(s);
 }
 
-int armv7m_nvic_raw_execution_priority(void *opaque)
+int armv7m_nvic_raw_execution_priority(NVICState *s)
 {
-    NVICState *s = opaque;
-
     return s->exception_prio;
 }
 
@@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s)
  * if @secure is true and @irq does not specify one of the fixed set
  * of architecturally banked exceptions.
  */
-static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
+static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure)
 {
-    NVICState *s = (NVICState *)opaque;
     VecInfo *vec;
 
     assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
@@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
     }
 }
 
-void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
+void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure)
 {
-    do_armv7m_nvic_set_pending(opaque, irq, secure, false);
+    do_armv7m_nvic_set_pending(s, irq, secure, false);
 }
 
-void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure)
+void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure)
 {
-    do_armv7m_nvic_set_pending(opaque, irq, secure, true);
+    do_armv7m_nvic_set_pending(s, irq, secure, true);
 }
 
-void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
+void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure)
 {
     /*
      * Pend an exception during lazy FP stacking. This differs
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
      * whether we should escalate depends on the saved context
      * in the FPCCR register, not on the current state of the CPU/NVIC.
      */
-    NVICState *s = (NVICState *)opaque;
     bool banked = exc_is_banked(irq);
     VecInfo *vec;
     bool targets_secure;
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
 }
 
 /* Make pending IRQ active.  */
-void armv7m_nvic_acknowledge_irq(void *opaque)
+void armv7m_nvic_acknowledge_irq(NVICState *s)
 {
-    NVICState *s = (NVICState *)opaque;
     CPUARMState *env = &s->cpu->env;
     const int pending = s->vectpending;
     const int running = nvic_exec_prio(s);
@@ -XXX,XX +XXX,XX @@ static bool vectpending_targets_secure(NVICState *s)
         exc_targets_secure(s, s->vectpending);
 }
 
-void armv7m_nvic_get_pending_irq_info(void *opaque,
+void armv7m_nvic_get_pending_irq_info(NVICState *s,
                                       int *pirq, bool *ptargets_secure)
 {
-    NVICState *s = (NVICState *)opaque;
     const int pending = s->vectpending;
     bool targets_secure;
 
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque,
     *pirq = pending;
 }
 
-int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
+int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure)
 {
-    NVICState *s = (NVICState *)opaque;
     VecInfo *vec = NULL;
     int ret = 0;
 
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
     return ret;
 }
 
-bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
+bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure)
 {
     /*
      * Return whether an exception is "ready", i.e. it is enabled and is
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
      * for non-banked exceptions secure is always false; for banked exceptions
      * it indicates which of the exceptions is required.
      */
-    NVICState *s = (NVICState *)opaque;
     bool banked = exc_is_banked(irq);
     VecInfo *vec;
     int running = nvic_exec_prio(s);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #include "hw/boards.h"
+#include "hw/intc/armv7m_nvic.h"
 #endif
 #include "sysemu/tcg.h"
 #include "sysemu/qtest.h"
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr,
      * that we will need later in order to do lazy FP reg stacking.
      */
     bool is_secure = env->v7m.secure;
-    void *nvic = env->nvic;
+    NVICState *nvic = env->nvic;
     /*
      * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits
      * are banked and we want to update the bit in the bank for the
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

While dozens of files include "cpu.h", only 3 files require
these NVIC helper declarations.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230206223502.25122-12-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++
 target/arm/cpu.h              | 123 ----------------------------------
 target/arm/cpu.c              |   4 +-
 target/arm/cpu_tcg.c          |   3 +
 target/arm/m_helper.c         |   3 +
 5 files changed, 132 insertions(+), 124 deletions(-)

diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@ struct NVICState {
     qemu_irq sysresetreq;
 };
 
+/* Interface between CPU and Interrupt controller.  */
+/**
+ * armv7m_nvic_set_pending: mark the specified exception as pending
+ * @s: the NVIC
+ * @irq: the exception number to mark pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Marks the specified exception as pending. Note that we will assert()
+ * if @secure is true and @irq does not specify one of the fixed set
+ * of architecturally banked exceptions.
+ */
+void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_set_pending_derived: mark this derived exception as pending
+ * @s: the NVIC
+ * @irq: the exception number to mark pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Similar to armv7m_nvic_set_pending(), but specifically for derived
+ * exceptions (exceptions generated in the course of trying to take
+ * a different exception).
+ */
+void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
+ * @s: the NVIC
+ * @irq: the exception number to mark pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
+ * generated in the course of lazy stacking of FP registers.
+ */
+void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_get_pending_irq_info: return highest priority pending
+ *    exception, and whether it targets Secure state
+ * @s: the NVIC
+ * @pirq: set to pending exception number
+ * @ptargets_secure: set to whether pending exception targets Secure
+ *
+ * This function writes the number of the highest priority pending
+ * exception (the one which would be made active by
+ * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
+ * to true if the current highest priority pending exception should
+ * be taken to Secure state, false for NS.
+ */
+void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
+                                      bool *ptargets_secure);
+/**
+ * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
+ * @s: the NVIC
+ *
+ * Move the current highest priority pending exception from the pending
+ * state to the active state, and update v7m.exception to indicate that
+ * it is the exception currently being handled.
+ */
+void armv7m_nvic_acknowledge_irq(NVICState *s);
+/**
+ * armv7m_nvic_complete_irq: complete specified interrupt or exception
+ * @s: the NVIC
+ * @irq: the exception number to complete
+ * @secure: true if this exception was secure
+ *
+ * Returns: -1 if the irq was not active
+ *           1 if completing this irq brought us back to base (no active irqs)
+ *           0 if there is still an irq active after this one was completed
+ * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
+ */
+int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
+ * @s: the NVIC
+ * @irq: the exception number to mark pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Return whether an exception is "ready", i.e. whether the exception is
+ * enabled and is configured at a priority which would allow it to
+ * interrupt the current execution priority. This controls whether the
+ * RDY bit for it in the FPCCR is set.
+ */
+bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_raw_execution_priority: return the raw execution priority
+ * @s: the NVIC
+ *
+ * Returns: the raw execution priority as defined by the v8M architecture.
+ * This is the execution priority minus the effects of AIRCR.PRIS,
+ * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
+ * (v8M ARM ARM I_PKLD.)
+ */
+int armv7m_nvic_raw_execution_priority(NVICState *s);
+/**
+ * armv7m_nvic_neg_prio_requested: return true if the requested execution
+ * priority is negative for the specified security state.
+ * @s: the NVIC
+ * @secure: the security state to test
+ * This corresponds to the pseudocode IsReqExecPriNeg().
+ */
+#ifndef CONFIG_USER_ONLY
+bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
+#else
+static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
+{
+    return false;
+}
+#endif
+#ifndef CONFIG_USER_ONLY
+bool armv7m_nvic_can_take_pending_exception(NVICState *s);
+#else
+static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
+{
+    return true;
+}
+#endif
+
 #endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                  uint32_t cur_el, bool secure);
 
-/* Interface between CPU and Interrupt controller.  */
-#ifndef CONFIG_USER_ONLY
-bool armv7m_nvic_can_take_pending_exception(NVICState *s);
-#else
-static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
-{
-    return true;
-}
-#endif
-/**
- * armv7m_nvic_set_pending: mark the specified exception as pending
- * @s: the NVIC
- * @irq: the exception number to mark pending
- * @secure: false for non-banked exceptions or for the nonsecure
- * version of a banked exception, true for the secure version of a banked
- * exception.
- *
- * Marks the specified exception as pending. Note that we will assert()
- * if @secure is true and @irq does not specify one of the fixed set
- * of architecturally banked exceptions.
- */
-void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_set_pending_derived: mark this derived exception as pending
- * @s: the NVIC
- * @irq: the exception number to mark pending
- * @secure: false for non-banked exceptions or for the nonsecure
- * version of a banked exception, true for the secure version of a banked
- * exception.
- *
- * Similar to armv7m_nvic_set_pending(), but specifically for derived
- * exceptions (exceptions generated in the course of trying to take
- * a different exception).
- */
-void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
- * @s: the NVIC
- * @irq: the exception number to mark pending
- * @secure: false for non-banked exceptions or for the nonsecure
- * version of a banked exception, true for the secure version of a banked
- * exception.
- *
- * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
- * generated in the course of lazy stacking of FP registers.
- */
-void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_get_pending_irq_info: return highest priority pending
- *    exception, and whether it targets Secure state
- * @s: the NVIC
- * @pirq: set to pending exception number
- * @ptargets_secure: set to whether pending exception targets Secure
- *
- * This function writes the number of the highest priority pending
- * exception (the one which would be made active by
- * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
- * to true if the current highest priority pending exception should
- * be taken to Secure state, false for NS.
- */
-void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
-                                      bool *ptargets_secure);
-/**
- * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
- * @s: the NVIC
- *
- * Move the current highest priority pending exception from the pending
- * state to the active state, and update v7m.exception to indicate that
- * it is the exception currently being handled.
- */
-void armv7m_nvic_acknowledge_irq(NVICState *s);
-/**
- * armv7m_nvic_complete_irq: complete specified interrupt or exception
- * @s: the NVIC
- * @irq: the exception number to complete
- * @secure: true if this exception was secure
- *
- * Returns: -1 if the irq was not active
- *           1 if completing this irq brought us back to base (no active irqs)
- *           0 if there is still an irq active after this one was completed
- * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
- */
-int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
- * @s: the NVIC
- * @irq: the exception number to mark pending
- * @secure: false for non-banked exceptions or for the nonsecure
- * version of a banked exception, true for the secure version of a banked
- * exception.
- *
- * Return whether an exception is "ready", i.e. whether the exception is
- * enabled and is configured at a priority which would allow it to
- * interrupt the current execution priority. This controls whether the
- * RDY bit for it in the FPCCR is set.
- */
-bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_raw_execution_priority: return the raw execution priority
- * @s: the NVIC
- *
- * Returns: the raw execution priority as defined by the v8M architecture.
- * This is the execution priority minus the effects of AIRCR.PRIS,
- * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
- * (v8M ARM ARM I_PKLD.)
- */
-int armv7m_nvic_raw_execution_priority(NVICState *s);
-/**
- * armv7m_nvic_neg_prio_requested: return true if the requested execution
- * priority is negative for the specified security state.
- * @s: the NVIC
- * @secure: the security state to test
- * This corresponds to the pseudocode IsReqExecPriNeg().
- */
-#ifndef CONFIG_USER_ONLY
-bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
-#else
-static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
-{
-    return false;
-}
-#endif
-
 /* Interface for defining coprocessor registers.
  * Registers are defined in tables of arm_cp_reginfo structs
  * which are passed to define_arm_cp_regs().
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #include "hw/boards.h"
+#ifdef CONFIG_TCG
 #include "hw/intc/armv7m_nvic.h"
-#endif
+#endif /* CONFIG_TCG */
+#endif /* !CONFIG_USER_ONLY */
 #include "sysemu/tcg.h"
 #include "sysemu/qtest.h"
 #include "sysemu/hw_accel.h"
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #endif
 #include "cpregs.h"
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
+#include "hw/intc/armv7m_nvic.h"
+#endif
 
 
 /* Share AArch32 -cpu max features with AArch64. */
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/cpu_ldst.h"
 #include "semihosting/common-semi.h"
 #endif
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/intc/armv7m_nvic.h"
+#endif
 
 static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask,
                          uint32_t reg, uint32_t val)
-- 
2.34.1

From: Alex Bennée <alex.bennee@linaro.org>

The two TCG tests for GICv2 and GICv3 are very heavy weight distros
that take a long time to boot up, especially for an --enable-debug
build. The total code coverage they give is:

Overall coverage rate:
    lines......: 11.2% (59584 of 530123 lines)
    functions..: 15.0% (7436 of 49443 functions)
    branches...: 6.3% (19273 of 303933 branches)

We already get pretty close to that with the machine_aarch64_virt
tests which only does one full boot (~120s vs ~600s) of alpine. We
expand the kernel+initrd boot (~8s) to test both GICs and also add an
RNG device and a block device to generate a few IRQs and exercise the
storage layer. With that we get to a coverage of:

Overall coverage rate:
    lines......: 11.0% (58121 of 530123 lines)
    functions..: 14.9% (7343 of 49443 functions)
    branches...: 6.0% (18269 of 303933 branches)

which I feel is close enough given the massive time saving. If we want
to target any more sub-systems we can use lighter weight more directed
tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230203181632.2919715-1-alex.bennee@linaro.org
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/avocado/boot_linux.py           | 48 ++++----------------
 tests/avocado/machine_aarch64_virt.py | 63 ++++++++++++++++++++++++---
 2 files changed, 65 insertions(+), 46 deletions(-)

diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/boot_linux.py
+++ b/tests/avocado/boot_linux.py
@@ -XXX,XX +XXX,XX @@ def test_pc_q35_kvm(self):
         self.launch_and_wait(set_up_ssh_connection=False)
 
 
-# For Aarch64 we only boot KVM tests in CI as the TCG tests are very
-# heavyweight. There are lighter weight distros which we use in the
-# machine_aarch64_virt.py tests.
+# For Aarch64 we only boot KVM tests in CI as booting the current
+# Fedora OS in TCG tests is very heavyweight. There are lighter weight
+# distros which we use in the machine_aarch64_virt.py tests.
 class BootLinuxAarch64(LinuxTest):
     """
     :avocado: tags=arch:aarch64
     :avocado: tags=machine:virt
-    :avocado: tags=machine:gic-version=2
     """
     timeout = 720
 
-    def add_common_args(self):
-        self.vm.add_args('-bios',
-                         os.path.join(BUILD_DIR, 'pc-bios',
-                                      'edk2-aarch64-code.fd'))
-        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
-        self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
-
-    @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
-    def test_fedora_cloud_tcg_gicv2(self):
-        """
-        :avocado: tags=accel:tcg
-        :avocado: tags=cpu:max
-        :avocado: tags=device:gicv2
-        """
-        self.require_accelerator("tcg")
-        self.vm.add_args("-accel", "tcg")
-        self.vm.add_args("-cpu", "max,lpa2=off")
-        self.vm.add_args("-machine", "virt,gic-version=2")
-        self.add_common_args()
-        self.launch_and_wait(set_up_ssh_connection=False)
-
-    @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
-    def test_fedora_cloud_tcg_gicv3(self):
-        """
-        :avocado: tags=accel:tcg
-        :avocado: tags=cpu:max
-        :avocado: tags=device:gicv3
-        """
-        self.require_accelerator("tcg")
-        self.vm.add_args("-accel", "tcg")
-        self.vm.add_args("-cpu", "max,lpa2=off")
-        self.vm.add_args("-machine", "virt,gic-version=3")
-        self.add_common_args()
-        self.launch_and_wait(set_up_ssh_connection=False)
-
     def test_virt_kvm(self):
         """
         :avocado: tags=accel:kvm
@@ -XXX,XX +XXX,XX @@ def test_virt_kvm(self):
         self.require_accelerator("kvm")
         self.vm.add_args("-accel", "kvm")
         self.vm.add_args("-machine", "virt,gic-version=host")
-        self.add_common_args()
+        self.vm.add_args('-bios',
+                         os.path.join(BUILD_DIR, 'pc-bios',
+                                      'edk2-aarch64-code.fd'))
+        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
+        self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
         self.launch_and_wait(set_up_ssh_connection=False)
 
 
diff --git a/tests/avocado/machine_aarch64_virt.py b/tests/avocado/machine_aarch64_virt.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/machine_aarch64_virt.py
+++ b/tests/avocado/machine_aarch64_virt.py
@@ -XXX,XX +XXX,XX @@
 
 import time
 import os
+import logging
 
 from avocado_qemu import QemuSystemTest
 from avocado_qemu import wait_for_console_pattern
 from avocado_qemu import exec_command
 from avocado_qemu import BUILD_DIR
+from avocado.utils import process
+from avocado.utils.path import find_command
 
 class Aarch64VirtMachine(QemuSystemTest):
     KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
@@ -XXX,XX +XXX,XX @@ def test_alpine_virt_tcg_gic_max(self):
         self.wait_for_console_pattern('Welcome to Alpine Linux 3.16')
 
 
-    def test_aarch64_virt(self):
+    def common_aarch64_virt(self, machine):
         """
-        :avocado: tags=arch:aarch64
-        :avocado: tags=machine:virt
-        :avocado: tags=accel:tcg
-        :avocado: tags=cpu:max
+        Common code to launch basic virt machine with kernel+initrd
+        and a scratch disk.
         """
+        logger = logging.getLogger('aarch64_virt')
+
         kernel_url = ('https://fileserver.linaro.org/s/'
                       'z6B2ARM7DQT3HWN/download')
-
         kernel_hash = 'ed11daab50c151dde0e1e9c9cb8b2d9bd3215347'
         kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
 
@@ -XXX,XX +XXX,XX @@ def test_aarch64_virt(self):
                                'console=ttyAMA0')
         self.require_accelerator("tcg")
         self.vm.add_args('-cpu', 'max,pauth-impdef=on',
+                         '-machine', machine,
                          '-accel', 'tcg',
                          '-kernel', kernel_path,
                          '-append', kernel_command_line)
+
+        # A RNG offers an easy way to generate a few IRQs
+        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
+        self.vm.add_args('-object',
+                         'rng-random,id=rng0,filename=/dev/urandom')
+
+        # Also add a scratch block device
+        logger.info('creating scratch qcow2 image')
+        image_path = os.path.join(self.workdir, 'scratch.qcow2')
+        qemu_img = os.path.join(BUILD_DIR, 'qemu-img')
+        if not os.path.exists(qemu_img):
+            qemu_img = find_command('qemu-img', False)
+        if qemu_img is False:
+            self.cancel('Could not find "qemu-img", which is required to '
+                        'create the temporary qcow2 image')
+        cmd = '%s create -f qcow2 %s 8M' % (qemu_img, image_path)
+        process.run(cmd)
+
+        # Add the device
+        self.vm.add_args('-blockdev',
+                         f"driver=qcow2,file.driver=file,file.filename={image_path},node-name=scratch")
+        self.vm.add_args('-device',
+                         'virtio-blk-device,drive=scratch')
+
         self.vm.launch()
         self.wait_for_console_pattern('Welcome to Buildroot')
         time.sleep(0.1)
         exec_command(self, 'root')
         time.sleep(0.1)
+        exec_command(self, 'dd if=/dev/hwrng of=/dev/vda bs=512 count=4')
+        time.sleep(0.1)
+        exec_command(self, 'md5sum /dev/vda')
+        time.sleep(0.1)
+        exec_command(self, 'cat /proc/interrupts')
+        time.sleep(0.1)
         exec_command(self, 'cat /proc/self/maps')
         time.sleep(0.1)
+
+    def test_aarch64_virt_gicv3(self):
+        """
+        :avocado: tags=arch:aarch64
+        :avocado: tags=machine:virt
+        :avocado: tags=accel:tcg
+        :avocado: tags=cpu:max
+        """
+        self.common_aarch64_virt("virt,gic_version=3")
+
+    def test_aarch64_virt_gicv2(self):
+        """
+        :avocado: tags=arch:aarch64
+        :avocado: tags=machine:virt
+        :avocado: tags=accel:tcg
+        :avocado: tags=cpu:max
+        """
+        self.common_aarch64_virt("virt,gic-version=2")
-- 
2.34.1

From: Mostafa Saleh <smostafa@google.com>

GBPA register can be used to globally abort all
transactions.

It is described in the SMMU manual in "6.3.14 SMMU_GBPA".
ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to
be zero(Do not abort incoming transactions).

Other fields have default values of Use Incoming.

If UPDATE is not set, the write is ignored. This is the only permitted
behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure)

As this patch adds a new state to the SMMU (GBPA), it is added
in a new subsection for forward migration compatibility.
GBPA is only migrated if its value is different from the reset value.
It does this to be backward migration compatible if SW didn't write
the register.

Signed-off-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230214094009.2445653-1-smostafa@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/smmuv3-internal.h |  7 +++++++
 include/hw/arm/smmuv3.h  |  1 +
 hw/arm/smmuv3.c          | 43 +++++++++++++++++++++++++++++++++++++++-
 3 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -XXX,XX +XXX,XX @@ REG32(CR0ACK,              0x24)
 REG32(CR1,                 0x28)
 REG32(CR2,                 0x2c)
 REG32(STATUSR,             0x40)
+REG32(GBPA,                0x44)
+    FIELD(GBPA, ABORT,        20, 1)
+    FIELD(GBPA, UPDATE,       31, 1)
+
+/* Use incoming. */
+#define SMMU_GBPA_RESET_VAL 0x1000
+
 REG32(IRQ_CTRL,            0x50)
     FIELD(IRQ_CTRL, GERROR_IRQEN,        0, 1)
     FIELD(IRQ_CTRL, PRI_IRQEN,           1, 1)
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/smmuv3.h
+++ b/include/hw/arm/smmuv3.h
@@ -XXX,XX +XXX,XX @@ struct SMMUv3State {
     uint32_t cr[3];
     uint32_t cr0ack;
     uint32_t statusr;
+    uint32_t gbpa;
     uint32_t irq_ctrl;
     uint32_t gerror;
     uint32_t gerrorn;
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
     s->gerror = 0;
     s->gerrorn = 0;
     s->statusr = 0;
+    s->gbpa = SMMU_GBPA_RESET_VAL;
 }
 
 static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
     qemu_mutex_lock(&s->mutex);
 
     if (!smmu_enabled(s)) {
-        status = SMMU_TRANS_DISABLE;
+        if (FIELD_EX32(s->gbpa, GBPA, ABORT)) {
+            status = SMMU_TRANS_ABORT;
+        } else {
+            status = SMMU_TRANS_DISABLE;
+        }
         goto epilogue;
     }
 
@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,
     case A_GERROR_IRQ_CFG2:
         s->gerror_irq_cfg2 = data;
         return MEMTX_OK;
+    case A_GBPA:
+        /*
+         * If UPDATE is not set, the write is ignored. This is the only
+         * permitted behavior in SMMUv3.2 and later.
+         */
+        if (data & R_GBPA_UPDATE_MASK) {
+            /* Ignore update bit as write is synchronous. */
+            s->gbpa = data & ~R_GBPA_UPDATE_MASK;
+        }
+        return MEMTX_OK;
     case A_STRTAB_BASE: /* 64b */
         s->strtab_base = deposit64(s->strtab_base, 0, 32, data);
         return MEMTX_OK;
@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset,
     case A_STATUSR:
         *data = s->statusr;
         return MEMTX_OK;
+    case A_GBPA:
+        *data = s->gbpa;
+        return MEMTX_OK;
     case A_IRQ_CTRL:
     case A_IRQ_CTRL_ACK:
         *data = s->irq_ctrl;
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3_queue = {
     },
 };
 
+static bool smmuv3_gbpa_needed(void *opaque)
+{
+    SMMUv3State *s = opaque;
+
+    /* Only migrate GBPA if it has different reset value. */
+    return s->gbpa != SMMU_GBPA_RESET_VAL;
+}
+
+static const VMStateDescription vmstate_gbpa = {
+    .name = "smmuv3/gbpa",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = smmuv3_gbpa_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(gbpa, SMMUv3State),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static const VMStateDescription vmstate_smmuv3 = {
     .name = "smmuv3",
     .version_id = 1,
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = {
 
         VMSTATE_END_OF_LIST(),
     },
+    .subsections = (const VMStateDescription * []) {
+        &vmstate_gbpa,
+        NULL
+    }
 };
 
 static void smmuv3_instance_init(Object *obj)
-- 
2.34.1

From: Cornelia Huck <cohuck@redhat.com>

Just use current_accel_name() directly.

Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
     if (vms->secure && (kvm_enabled() || hvf_enabled())) {
         error_report("mach-virt: %s does not support providing "
                      "Security extensions (TrustZone) to the guest CPU",
-                     kvm_enabled() ? "KVM" : "HVF");
+                     current_accel_name());
         exit(1);
     }
 
     if (vms->virt && (kvm_enabled() || hvf_enabled())) {
         error_report("mach-virt: %s does not support providing "
                      "Virtualization extensions to the guest CPU",
-                     kvm_enabled() ? "KVM" : "HVF");
+                     current_accel_name());
         exit(1);
     }
 
     if (vms->mte && (kvm_enabled() || hvf_enabled())) {
         error_report("mach-virt: %s does not support providing "
                      "MTE to the guest CPU",
-                     kvm_enabled() ? "KVM" : "HVF");
+                     current_accel_name());
         exit(1);
     }
 
-- 
2.34.1

From: Hao Wu <wuhaotsh@google.com>

Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices.

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Chris Rauer <crauer@google.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
Message-id: 20230208235433.3989937-3-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 MAINTAINERS                |   6 +-
 include/hw/ssi/npcm_pspi.h |  53 +++++++++
 hw/ssi/npcm_pspi.c         | 221 +++++++++++++++++++++++++++++++++++++
 hw/ssi/meson.build         |   2 +-
 hw/ssi/trace-events        |   5 +
 5 files changed, 283 insertions(+), 4 deletions(-)
 create mode 100644 include/hw/ssi/npcm_pspi.h
 create mode 100644 hw/ssi/npcm_pspi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Tyrone Ting <kfting@nuvoton.com>
 M: Hao Wu <wuhaotsh@google.com>
 L: qemu-arm@nongnu.org
 S: Supported
-F: hw/*/npcm7xx*
-F: include/hw/*/npcm7xx*
-F: tests/qtest/npcm7xx*
+F: hw/*/npcm*
+F: include/hw/*/npcm*
+F: tests/qtest/npcm*
 F: pc-bios/npcm7xx_bootrom.bin
 F: roms/vbootrom
 F: docs/system/arm/nuvoton.rst
diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/ssi/npcm_pspi.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton Peripheral SPI Module
+ *
+ * Copyright 2023 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM_PSPI_H
+#define NPCM_PSPI_H
+
+#include "hw/ssi/ssi.h"
+#include "hw/sysbus.h"
+
+/*
+ * Number of registers in our device state structure. Don't change this without
+ * incrementing the version_id in the vmstate.
+ */
+#define NPCM_PSPI_NR_REGS 3
+
+/**
+ * NPCMPSPIState - Device state for one Flash Interface Unit.
+ * @parent: System bus device.
+ * @mmio: Memory region for register access.
+ * @spi: The SPI bus mastered by this controller.
+ * @regs: Register contents.
+ * @irq: The interrupt request queue for this module.
+ *
+ * Each PSPI has a shared bank of registers, and controls up to four chip
+ * selects. Each chip select has a dedicated memory region which may be used to
+ * read and write the flash connected to that chip select as if it were memory.
+ */
+typedef struct NPCMPSPIState {
+    SysBusDevice parent;
+
+    MemoryRegion mmio;
+
+    SSIBus *spi;
+    uint16_t regs[NPCM_PSPI_NR_REGS];
+    qemu_irq irq;
+} NPCMPSPIState;
+
+#define TYPE_NPCM_PSPI "npcm-pspi"
+OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI)
+
+#endif /* NPCM_PSPI_H */
diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/ssi/npcm_pspi.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM Peripheral SPI Module (PSPI)
+ *
+ * Copyright 2023 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/irq.h"
+#include "hw/registerfields.h"
+#include "hw/ssi/npcm_pspi.h"
+#include "migration/vmstate.h"
+#include "qapi/error.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+
+#include "trace.h"
+
+REG16(PSPI_DATA, 0x0)
+REG16(PSPI_CTL1, 0x2)
+    FIELD(PSPI_CTL1, SPIEN, 0,  1)
+    FIELD(PSPI_CTL1, MOD,   2,  1)
+    FIELD(PSPI_CTL1, EIR,   5,  1)
+    FIELD(PSPI_CTL1, EIW,   6,  1)
+    FIELD(PSPI_CTL1, SCM,   7,  1)
+    FIELD(PSPI_CTL1, SCIDL, 8,  1)
+    FIELD(PSPI_CTL1, SCDV,  9,  7)
+REG16(PSPI_STAT, 0x4)
+    FIELD(PSPI_STAT, BSY,  0,  1)
+    FIELD(PSPI_STAT, RBF,  1,  1)
+
+static void npcm_pspi_update_irq(NPCMPSPIState *s)
+{
+    int level = 0;
+
+    /* Only fire IRQ when the module is enabled. */
+    if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) {
+        /* Update interrupt as BSY is cleared. */
+        if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) &&
+            FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) {
+            level = 1;
+        }
+
+        /* Update interrupt as RBF is set. */
+        if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) &&
+            FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) {
+            level = 1;
+        }
+    }
+    qemu_set_irq(s->irq, level);
+}
+
+static uint16_t npcm_pspi_read_data(NPCMPSPIState *s)
+{
+    uint16_t value = s->regs[R_PSPI_DATA];
+
+    /* Clear stat bits as the value are read out. */
+    s->regs[R_PSPI_STAT] = 0;
+
+    return value;
+}
+
+static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data)
+{
+    uint16_t value = 0;
+
+    if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) {
+        value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8;
+    }
+    value |= ssi_transfer(s->spi, extract16(data, 0, 8));
+    s->regs[R_PSPI_DATA] = value;
+
+    /* Mark data as available */
+    s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK;
+}
+
+/* Control register read handler. */
+static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr,
+                                    unsigned int size)
+{
+    NPCMPSPIState *s = opaque;
+    uint16_t value;
+
+    switch (addr) {
+    case A_PSPI_DATA:
+        value = npcm_pspi_read_data(s);
+        break;
+
+    case A_PSPI_CTL1:
+        value = s->regs[R_PSPI_CTL1];
+        break;
+
+    case A_PSPI_STAT:
+        value = s->regs[R_PSPI_STAT];
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: write to invalid offset 0x%" PRIx64 "\n",
+                      DEVICE(s)->canonical_path, addr);
+        return 0;
+    }
+    trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value);
+    npcm_pspi_update_irq(s);
+
+    return value;
+}
+
+/* Control register write handler. */
+static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v,
+                                 unsigned int size)
+{
+    NPCMPSPIState *s = opaque;
+    uint16_t value = v;
+
+    trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value);
+
+    switch (addr) {
+    case A_PSPI_DATA:
+        npcm_pspi_write_data(s, value);
+        break;
+
+    case A_PSPI_CTL1:
+        s->regs[R_PSPI_CTL1] = value;
+        break;
+
+    case A_PSPI_STAT:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: write to read-only register PSPI_STAT: 0x%08"
+                      PRIx64 "\n", DEVICE(s)->canonical_path, v);
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: write to invalid offset 0x%" PRIx64 "\n",
+                      DEVICE(s)->canonical_path, addr);
+        return;
+    }
+    npcm_pspi_update_irq(s);
+}
+
+static const MemoryRegionOps npcm_pspi_ctrl_ops = {
+    .read = npcm_pspi_ctrl_read,
+    .write = npcm_pspi_ctrl_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 1,
+        .max_access_size = 2,
+        .unaligned = false,
+    },
+    .impl = {
+        .min_access_size = 2,
+        .max_access_size = 2,
+        .unaligned = false,
+    },
+};
+
+static void npcm_pspi_enter_reset(Object *obj, ResetType type)
+{
+    NPCMPSPIState *s = NPCM_PSPI(obj);
+
+    trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type);
+    memset(s->regs, 0, sizeof(s->regs));
+}
+
+static void npcm_pspi_realize(DeviceState *dev, Error **errp)
+{
+    NPCMPSPIState *s = NPCM_PSPI(dev);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+    Object *obj = OBJECT(dev);
+
+    s->spi = ssi_create_bus(dev, "pspi");
+    memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s,
+                          "mmio", 4 * KiB);
+    sysbus_init_mmio(sbd, &s->mmio);
+    sysbus_init_irq(sbd, &s->irq);
+}
+
+static const VMStateDescription vmstate_npcm_pspi = {
+    .name = "npcm-pspi",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+
+static void npcm_pspi_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM Peripheral SPI Module";
+    dc->realize = npcm_pspi_realize;
+    dc->vmsd = &vmstate_npcm_pspi;
+    rc->phases.enter = npcm_pspi_enter_reset;
+}
+
+static const TypeInfo npcm_pspi_types[] = {
+    {
+        .name = TYPE_NPCM_PSPI,
+        .parent = TYPE_SYS_BUS_DEVICE,
+        .instance_size = sizeof(NPCMPSPIState),
+        .class_init = npcm_pspi_class_init,
+    },
+};
+DEFINE_TYPES(npcm_pspi_types);
diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/meson.build
+++ b/hw/ssi/meson.build
@@ -XXX,XX +XXX,XX @@
 softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c'))
 softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c'))
-softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c'))
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'npcm_pspi.c'))
 softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c'))
 softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c'))
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/trace-events
+++ b/hw/ssi/trace-events
@@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset:
 npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
 npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
 
+# npcm_pspi.c
+npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d"
+npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
+npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
+
 # ibex_spi_host.c
 
 ibex_spi_host_reset(const char *msg) "%s"
-- 
2.34.1

From: Hao Wu <wuhaotsh@google.com>

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
Message-id: 20230208235433.3989937-4-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/nuvoton.rst |  2 +-
 include/hw/arm/npcm7xx.h    |  2 ++
 hw/arm/npcm7xx.c            | 25 +++++++++++++++++++++++--
 3 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@ Supported devices
  * SMBus controller (SMBF)
  * Ethernet controller (EMC)
  * Tachometer
+ * Peripheral SPI controller (PSPI)
 
 Missing devices
 ---------------
@@ -XXX,XX +XXX,XX @@ Missing devices
 
  * Ethernet controller (GMAC)
  * USB device (USBD)
- * Peripheral SPI controller (PSPI)
  * SD/MMC host
  * PECI interface
  * PCI and PCIe root complex and bridges
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/nvram/npcm7xx_otp.h"
 #include "hw/timer/npcm7xx_timer.h"
 #include "hw/ssi/npcm7xx_fiu.h"
+#include "hw/ssi/npcm_pspi.h"
 #include "hw/usb/hcd-ehci.h"
 #include "hw/usb/hcd-ohci.h"
 #include "target/arm/cpu.h"
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxState {
     NPCM7xxFIUState     fiu[2];
     NPCM7xxEMCState     emc[2];
     NPCM7xxSDHCIState   mmc;
+    NPCMPSPIState       pspi[2];
 };
 
 #define TYPE_NPCM7XX    "npcm7xx"
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
     NPCM7XX_EMC1RX_IRQ          = 15,
     NPCM7XX_EMC1TX_IRQ,
     NPCM7XX_MMC_IRQ             = 26,
+    NPCM7XX_PSPI2_IRQ           = 28,
+    NPCM7XX_PSPI1_IRQ           = 31,
     NPCM7XX_TIMER0_IRQ          = 32,   /* Timer Module 0 */
     NPCM7XX_TIMER1_IRQ,
     NPCM7XX_TIMER2_IRQ,
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_emc_addr[] = {
     0xf0826000,
 };
 
+/* Register base address for each PSPI Module */
+static const hwaddr npcm7xx_pspi_addr[] = {
+    0xf0200000,
+    0xf0201000,
+};
+
 static const struct {
     hwaddr regs_addr;
     uint32_t unconnected_pins;
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
         object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC);
     }
 
+    for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
+        object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI);
+    }
+
     object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
 }
 
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0,
             npcm7xx_irq(s, NPCM7XX_MMC_IRQ));
 
+    /* PSPI */
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi));
+    for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
+        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]);
+        int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ;
+
+        sysbus_realize(sbd, &error_abort);
+        sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]);
+        sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq));
+    }
+
     create_unimplemented_device("npcm7xx.shm",          0xc0001000,   4 * KiB);
     create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
     create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
     create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
     create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.pspi1",        0xf0200000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.pspi2",        0xf0201000,   4 * KiB);
     create_unimplemented_device("npcm7xx.ahbpci",       0xf0400000,   1 * MiB);
     create_unimplemented_device("npcm7xx.mcphy",        0xf05f0000,  64 * KiB);
     create_unimplemented_device("npcm7xx.gmac1",        0xf0802000,   8 * KiB);
-- 
2.34.1

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

Addresses targeting the second translation table (TTB1) in the SMMU have
all upper bits set. Ensure the IOMMU region covers all 64 bits.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230214171921.1917916-2-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/smmu-common.h | 2 --
 hw/arm/smmu-common.c         | 2 +-
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -XXX,XX +XXX,XX @@
 #define SMMU_PCI_DEVFN_MAX    256
 #define SMMU_PCI_DEVFN(sid)   (sid & 0xFF)
 
-#define SMMU_MAX_VA_BITS      48
-
 /*
  * Page table walk error types
  */
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn)
 
         memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu),
                                  s->mrtypename,
-                                 OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS);
+                                 OBJECT(s), name, UINT64_MAX);
         address_space_init(&sdev->as,
                            MEMORY_REGION(&sdev->iommu), name);
         trace_smmu_add_mr(name);
-- 
2.34.1

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

Addresses targeting the second translation table (TTB1) in the SMMU have
all upper bits set (except for the top byte when TBI is enabled). Fix
the TTB1 check.

Reported-by: Ola Hugosson <ola.hugosson@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230214171921.1917916-3-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/smmu-common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
         /* there is a ttbr0 region and we are in it (high bits all zero) */
         return &cfg->tt[0];
     } else if (cfg->tt[1].tsz &&
-           !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) {
+        sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) {
         /* there is a ttbr1 region and we are in it (high bits all one) */
         return &cfg->tt[1];
     } else if (!cfg->tt[0].tsz) {
-- 
2.34.1

From: Claudio Fontana <cfontana@suse.de>

make it clearer from the name that this is a tcg-only function.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
  * trapped to the hypervisor in KVM.
  */
 #ifdef CONFIG_TCG
-static void handle_semihosting(CPUState *cs)
+static void tcg_handle_semihosting(CPUState *cs)
 {
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
      */
 #ifdef CONFIG_TCG
     if (cs->exception_index == EXCP_SEMIHOST) {
-        handle_semihosting(cs);
+        tcg_handle_semihosting(cs);
         return;
     }
 #endif
-- 
2.34.1

From: Claudio Fontana <cfontana@suse.de>

for "all" builds (tcg + kvm), we want to avoid doing
the psci check if tcg is built-in, but not enabled.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/irq.h"
 #include "sysemu/cpu-timers.h"
 #include "sysemu/kvm.h"
+#include "sysemu/tcg.h"
 #include "qapi/qapi-commands-machine-target.h"
 #include "qapi/error.h"
 #include "qemu/guest-random.h"
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
                       env->exception.syndrome);
     }
 
-    if (arm_is_psci_call(cpu, cs->exception_index)) {
+    if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) {
         arm_handle_psci_call(cpu);
         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
         return;
-- 
2.34.1

From: Claudio Fontana <cfontana@suse.de>

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
     unsigned int cur_el = arm_current_el(env);
     int rt;
 
-    /*
-     * Note that new_el can never be 0.  If cur_el is 0, then
-     * el0_a64 is is_a64(), else el0_a64 is ignored.
-     */
-    aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
+    if (tcg_enabled()) {
+        /*
+         * Note that new_el can never be 0.  If cur_el is 0, then
+         * el0_a64 is is_a64(), else el0_a64 is ignored.
+         */
+        aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
+    }
 
     if (cur_el < new_el) {
         /*
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

Move this earlier to make the next patch diff cleaner. While here
update the comment slightly to not give the impression that the
misalignment affects only TCG.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/machine.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/target/arm/machine.c b/target/arm/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
         }
     }
 
+    /*
+     * Misaligned thumb pc is architecturally impossible. Fail the
+     * incoming migration. For TCG it would trigger the assert in
+     * thumb_tr_translate_insn().
+     */
+    if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
+        return -1;
+    }
+
     hw_breakpoint_update_all(cpu);
     hw_watchpoint_update_all(cpu);
 
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
         }
     }
 
-    /*
-     * Misaligned thumb pc is architecturally impossible.
-     * We have an assert in thumb_tr_translate_insn to verify this.
-     * Fail an incoming migrate to avoid this assert.
-     */
-    if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
-        return -1;
-    }
-
     if (!kvm_enabled()) {
         pmu_op_finish(&cpu->env);
     }
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have
a cpregs.h header which is more suitable for this code.

Code moved verbatim.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h | 98 +++++++++++++++++++++++++++++++++++++++++++++
 target/arm/cpu.h    | 91 -----------------------------------------
 2 files changed, 98 insertions(+), 91 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
     ARM_CP_SME                   = 1 << 19,
 };
 
+/*
+ * Interface for defining coprocessor registers.
+ * Registers are defined in tables of arm_cp_reginfo structs
+ * which are passed to define_arm_cp_regs().
+ */
+
+/*
+ * When looking up a coprocessor register we look for it
+ * via an integer which encodes all of:
+ *  coprocessor number
+ *  Crn, Crm, opc1, opc2 fields
+ *  32 or 64 bit register (ie is it accessed via MRC/MCR
+ *    or via MRRC/MCRR?)
+ *  non-secure/secure bank (AArch32 only)
+ * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
+ * (In this case crn and opc2 should be zero.)
+ * For AArch64, there is no 32/64 bit size distinction;
+ * instead all registers have a 2 bit op0, 3 bit op1 and op2,
+ * and 4 bit CRn and CRm. The encoding patterns are chosen
+ * to be easy to convert to and from the KVM encodings, and also
+ * so that the hashtable can contain both AArch32 and AArch64
+ * registers (to allow for interprocessing where we might run
+ * 32 bit code on a 64 bit core).
+ */
+/*
+ * This bit is private to our hashtable cpreg; in KVM register
+ * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
+ * in the upper bits of the 64 bit ID.
+ */
+#define CP_REG_AA64_SHIFT 28
+#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
+
+/*
+ * To enable banking of coprocessor registers depending on ns-bit we
+ * add a bit to distinguish between secure and non-secure cpregs in the
+ * hashtable.
+ */
+#define CP_REG_NS_SHIFT 29
+#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
+
+#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
+    ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
+     ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
+
+#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
+    (CP_REG_AA64_MASK |                                 \
+     ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
+     ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
+     ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
+     ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
+     ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
+     ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
+
+/*
+ * Convert a full 64 bit KVM register ID to the truncated 32 bit
+ * version used as a key for the coprocessor register hashtable
+ */
+static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
+{
+    uint32_t cpregid = kvmid;
+    if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
+        cpregid |= CP_REG_AA64_MASK;
+    } else {
+        if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
+            cpregid |= (1 << 15);
+        }
+
+        /*
+         * KVM is always non-secure so add the NS flag on AArch32 register
+         * entries.
+         */
+         cpregid |= 1 << CP_REG_NS_SHIFT;
+    }
+    return cpregid;
+}
+
+/*
+ * Convert a truncated 32 bit hashtable key into the full
+ * 64 bit KVM register ID.
+ */
+static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
+{
+    uint64_t kvmid;
+
+    if (cpregid & CP_REG_AA64_MASK) {
+        kvmid = cpregid & ~CP_REG_AA64_MASK;
+        kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
+    } else {
+        kvmid = cpregid & ~(1 << 15);
+        if (cpregid & (1 << 15)) {
+            kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
+        } else {
+            kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
+        }
+    }
+    return kvmid;
+}
+
 /*
  * Valid values for ARMCPRegInfo state field, indicating which of
  * the AArch32 and AArch64 execution states this register is visible in.
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                  uint32_t cur_el, bool secure);
 
-/* Interface for defining coprocessor registers.
- * Registers are defined in tables of arm_cp_reginfo structs
- * which are passed to define_arm_cp_regs().
- */
-
-/* When looking up a coprocessor register we look for it
- * via an integer which encodes all of:
- *  coprocessor number
- *  Crn, Crm, opc1, opc2 fields
- *  32 or 64 bit register (ie is it accessed via MRC/MCR
- *    or via MRRC/MCRR?)
- *  non-secure/secure bank (AArch32 only)
- * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
- * (In this case crn and opc2 should be zero.)
- * For AArch64, there is no 32/64 bit size distinction;
- * instead all registers have a 2 bit op0, 3 bit op1 and op2,
- * and 4 bit CRn and CRm. The encoding patterns are chosen
- * to be easy to convert to and from the KVM encodings, and also
- * so that the hashtable can contain both AArch32 and AArch64
- * registers (to allow for interprocessing where we might run
- * 32 bit code on a 64 bit core).
- */
-/* This bit is private to our hashtable cpreg; in KVM register
- * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
- * in the upper bits of the 64 bit ID.
- */
-#define CP_REG_AA64_SHIFT 28
-#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
-
-/* To enable banking of coprocessor registers depending on ns-bit we
- * add a bit to distinguish between secure and non-secure cpregs in the
- * hashtable.
- */
-#define CP_REG_NS_SHIFT 29
-#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
-
-#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
-    ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
-     ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
-
-#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
-    (CP_REG_AA64_MASK |                                 \
-     ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
-     ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
-     ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
-     ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
-     ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
-     ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
-
-/* Convert a full 64 bit KVM register ID to the truncated 32 bit
- * version used as a key for the coprocessor register hashtable
- */
-static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
-{
-    uint32_t cpregid = kvmid;
-    if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
-        cpregid |= CP_REG_AA64_MASK;
-    } else {
-        if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
-            cpregid |= (1 << 15);
-        }
-
-        /* KVM is always non-secure so add the NS flag on AArch32 register
-         * entries.
-         */
-         cpregid |= 1 << CP_REG_NS_SHIFT;
-    }
-    return cpregid;
-}
-
-/* Convert a truncated 32 bit hashtable key into the full
- * 64 bit KVM register ID.
- */
-static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
-{
-    uint64_t kvmid;
-
-    if (cpregid & CP_REG_AA64_MASK) {
-        kvmid = cpregid & ~CP_REG_AA64_MASK;
-        kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
-    } else {
-        kvmid = cpregid & ~(1 << 15);
-        if (cpregid & (1 << 15)) {
-            kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
-        } else {
-            kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
-        }
-    }
-    return kvmid;
-}
-
 /* Return the highest implemented Exception Level */
 static inline int arm_highest_el(CPUARMState *env)
 {
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

If a test was tagged with the "accel" tag and the specified
accelerator it not present in the qemu binary, cancel the test.

We can now write tests without explicit calls to require_accelerator,
just the tag is enough.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/avocado/avocado_qemu/__init__.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tests/avocado/avocado_qemu/__init__.py b/tests/avocado/avocado_qemu/__init__.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/avocado_qemu/__init__.py
+++ b/tests/avocado/avocado_qemu/__init__.py
@@ -XXX,XX +XXX,XX @@ def setUp(self):
 
         super().setUp('qemu-system-')
 
+        accel_required = self._get_unique_tag_val('accel')
+        if accel_required:
+            self.require_accelerator(accel_required)
+
         self.machine = self.params.get('machine',
                                        default=self._get_unique_tag_val('machine'))
 
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

This allows the test to be skipped when TCG is not present in the QEMU
binary.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/avocado/boot_linux_console.py | 1 +
 tests/avocado/reverse_debugging.py  | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_uboot_netbsd9(self):
 
     def test_aarch64_raspi3_atf(self):
         """
+        :avocado: tags=accel:tcg
         :avocado: tags=arch:aarch64
         :avocado: tags=machine:raspi3b
         :avocado: tags=cpu:cortex-a53
diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/reverse_debugging.py
+++ b/tests/avocado/reverse_debugging.py
@@ -XXX,XX +XXX,XX @@ def reverse_debugging(self, shift=7, args=None):
         vm.shutdown()
 
 class ReverseDebugging_X86_64(ReverseDebugging):
+    """
+    :avocado: tags=accel:tcg
+    """
+
     REG_PC = 0x10
     REG_CS = 0x12
     def get_pc(self, g):
@@ -XXX,XX +XXX,XX @@ def test_x86_64_pc(self):
         self.reverse_debugging()
 
 class ReverseDebugging_AArch64(ReverseDebugging):
+    """
+    :avocado: tags=accel:tcg
+    """
+
     REG_PC = 32
 
     # unidentified gitlab timeout problem
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a
KVM-only build the 'max' cpu.

Note that we cannot use 'host' here because the qtests can run without
any other accelerator (than qtest) and 'host' depends on KVM being
enabled.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     mc->minimum_page_bits = 12;
     mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
     mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
+#ifdef CONFIG_TCG
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
+#else
+    mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
+#endif
     mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
     mc->kvm_type = virt_kvm_type;
     assert(!mc->get_hotplug_handler);
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/arm-cpu-features.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@
 #define SVE_MAX_VQ 16
 
 #define MACHINE     "-machine virt,gic-version=max -accel tcg "
-#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg "
+#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm "
 #define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
                     "  'arguments': { 'type': 'full', "
 #define QUERY_TAIL  "}}"
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
 {
     g_test_init(&argc, &argv, NULL);
 
-    qtest_add_data_func("/arm/query-cpu-model-expansion",
-                        NULL, test_query_cpu_model_expansion);
+    if (qtest_has_accel("tcg")) {
+        qtest_add_data_func("/arm/query-cpu-model-expansion",
+                            NULL, test_query_cpu_model_expansion);
+    }
+
+    if (!g_str_equal(qtest_get_arch(), "aarch64")) {
+        goto out;
+    }
 
     /*
      * For now we only run KVM specific tests with AArch64 QEMU in
      * order avoid attempting to run an AArch32 QEMU with KVM on
      * AArch64 hosts. That won't work and isn't easy to detect.
      */
-    if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) {
+    if (qtest_has_accel("kvm")) {
         /*
          * This tests target the 'host' CPU type, so register it only if
          * KVM is available.
          */
         qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
                             NULL, test_query_cpu_model_expansion_kvm);
-    }
 
-    if (g_str_equal(qtest_get_arch(), "aarch64")) {
-        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
-                            NULL, sve_tests_sve_max_vq_8);
-        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
-                            NULL, sve_tests_sve_off);
         qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
                             NULL, sve_tests_sve_off_kvm);
     }
 
+    if (qtest_has_accel("tcg")) {
+        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
+                            NULL, sve_tests_sve_max_vq_8);
+        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
+                            NULL, sve_tests_sve_off);
+    }
+
+out:
     return g_test_run();
 }
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

These tests set -accel tcg, so restrict them to when TCG is present.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/meson.build | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_arm = \
 # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional
 qtests_aarch64 = \
   (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) +                            \
-  (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) +        \
-  (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) +  \
+  (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ?            \
+    ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) +                                         \
   (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \
   (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) +  \
   ['arm-cpu-features',
-- 
2.34.1