The newly added neoverse-n1 CPU has ID register values which indicate

the presence of the Statistical Profiling Extension, because the real

hardware has this feature. QEMU's TCG emulation does not yet

implement SPE, though (not even as a minimal stub implementation), so

guests will crash if they try to use it because the SPE system

registers don't exist.

Force ID_AA64DFR0_EL1.PMSVer to 0 in CPU realize for TCG, so that

we don't advertise to the guest a feature that doesn't exist.

(We could alternatively do this by editing the value that

aarch64_neoverse_n1_initfn() sets for this ID register, but

suppressing the field in realize means we won't re-introduce this bug

when we add other CPUs that have SPE in hardware, such as the

Neoverse-V1.)

An example of a non-booting guest is current mainline Linux (5.19),

when booting in EL2 on the virt board (ie with -machine

virtualization=on).

Reported-by: Zenghui Yu <yuzenghui@huawei.com>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>

Message-id: 20220811131127.947334-1-peter.maydell@linaro.org

---

target/arm/cpu.c | 11 +++++++++++

1 file changed, 11 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)

}

#endif

+ if (tcg_enabled()) {

+ /*

+ * Don't report the Statistical Profiling Extension in the ID

+ * registers, because TCG doesn't implement it yet (not even a

+ * minimal stub version) and guests will fall over when they

+ * try to access the non-existent system registers for it.

+ */

+ cpu->isar.id_aa64dfr0 =

+ FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);

+ }

+

/* MPU can be configured out of a PMSA CPU either by setting has-mpu

* to false or by setting pmsav7-dregion to 0.

*/

--

2.25.1

From: Stefan Weil <sw@weilnetz.de>

Signed-off-by: Stefan Weil <sw@weilnetz.de>

Reviewed-by: Hongren (Zenithal) Zheng <i@zenithal.me>

Message-id: 20220812075642.1200578-1-sw@weilnetz.de

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

docs/about/deprecated.rst | 2 +-

docs/specs/acpi_erst.rst | 4 ++--

docs/system/devices/canokey.rst | 8 ++++----

docs/system/devices/cxl.rst | 12 ++++++------

4 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/about/deprecated.rst

+++ b/docs/about/deprecated.rst

@@ -XXX,XX +XXX,XX @@ by using ``-machine graphics=off``.

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

In QEMU versions 6.1, 6.2 and 7.0, the ``nvme-ns`` generates an EUI-64

-identifer that is not globally unique. If an EUI-64 identifer is required, the

+identifier that is not globally unique. If an EUI-64 identifier is required, the

user must set it explicitly using the ``nvme-ns`` device parameter ``eui64``.

``-device nvme,use-intel-id=on|off`` (since 7.1)

diff --git a/docs/specs/acpi_erst.rst b/docs/specs/acpi_erst.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/specs/acpi_erst.rst

+++ b/docs/specs/acpi_erst.rst

@@ -XXX,XX +XXX,XX @@ Slot 0 contains a backend storage header that identifies the contents

as ERST and also facilitates efficient access to the records.

Depending upon the size of the backend storage, additional slots will

be designated to be a part of the slot 0 header. For example, at 8KiB,

-the slot 0 header can accomodate 1021 records. Thus a storage size

+the slot 0 header can accommodate 1021 records. Thus a storage size

of 8MiB (8KiB * 1024) requires an additional slot for use by the

header. In this scenario, slot 0 and slot 1 form the backend storage

header, and records can be stored starting at slot 2.

@@ -XXX,XX +XXX,XX @@ References

[2] "Unified Extensible Firmware Interface Specification",

version 2.1, October 2008.

-[3] "Windows Hardware Error Architecture", specfically

+[3] "Windows Hardware Error Architecture", specifically

"Error Record Persistence Mechanism".

diff --git a/docs/system/devices/canokey.rst b/docs/system/devices/canokey.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/system/devices/canokey.rst

+++ b/docs/system/devices/canokey.rst

@@ -XXX,XX +XXX,XX @@ With the same software configuration as a hardware key,

the guest OS can use all the functionalities of a secure key as if

there was actually an hardware key plugged in.

-CanoKey QEMU provides much convenience for debuging:

+CanoKey QEMU provides much convenience for debugging:

-* libcanokey-qemu supports debuging output thus developers can

+* libcanokey-qemu supports debugging output thus developers can

inspect what happens inside a secure key

* CanoKey QEMU supports trace event thus event

* QEMU USB stack supports pcap thus USB packet between the guest

@@ -XXX,XX +XXX,XX @@ and find CanoKey QEMU there:

You may setup the key as guided in [6]_. The console for the key is at [7]_.

-Debuging

-========

+Debugging

+=========

CanoKey QEMU consists of two parts, ``libcanokey-qemu.so`` and ``canokey.c``,

the latter of which resides in QEMU. The former provides core functionality

diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/system/devices/cxl.rst

+++ b/docs/system/devices/cxl.rst

@@ -XXX,XX +XXX,XX @@ CXL Fixed Memory Windows (CFMW)

A CFMW consists of a particular range of Host Physical Address space

which is routed to particular CXL Host Bridges. At time of generic

software initialization it will have a particularly interleaving

-configuration and associated Quality of Serice Throtling Group (QTG).

+configuration and associated Quality of Service Throttling Group (QTG).

This information is available to system software, when making

decisions about how to configure interleave across available CXL

memory devices. It is provide as CFMW Structures (CFMWS) in

@@ -XXX,XX +XXX,XX @@ specification defined register interface called CXL Host Bridge

Component Registers (CHBCR). The location of this CHBCR MMIO

space is described to system software via a CXL Host Bridge

Structure (CHBS) in the CEDT ACPI table. The actual interfaces

-are identical to those used for other parts of the CXL heirarchy

+are identical to those used for other parts of the CXL hierarchy

as CXL Component Registers in PCI BARs.

Interfaces provided include:

@@ -XXX,XX +XXX,XX @@ CXL Memory Devices - Type 3

~~~~~~~~~~~~~~~~~~~~~~~~~~~

CXL type 3 devices use a PCI class code and are intended to be supported

by a generic operating system driver. They have HDM decoders

-though in these EP devices, the decoder is reponsible not for

+though in these EP devices, the decoder is responsible not for

routing but for translation of the incoming host physical address (HPA)

into a Device Physical Address (DPA).

@@ -XXX,XX +XXX,XX @@ Notes:

ranges of the system physical address map. Each CFMW has

particular interleave setup across the CXL Host Bridges (HB)

CFMW0 provides uninterleaved access to HB0, CFW2 provides

- uninterleaved acess to HB1. CFW1 provides interleaved memory access

+ uninterleaved access to HB1. CFW1 provides interleaved memory access

across HB0 and HB1.

(2) **Two CXL Host Bridges**. Each of these has 2 CXL Root Ports and

@@ -XXX,XX +XXX,XX @@ Example topology involving a switch::

---------------------------------------------------

| Switch 0 USP as PCI 0d:00.0 |

| USP has HDM decoder which direct traffic to |

- | appropiate downstream port |

+ | appropriate downstream port |

| Switch BUS appears as 0e |

|x__________________________________________________|

| | | |

@@ -XXX,XX +XXX,XX @@ An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave::

Kernel Configuration Options

----------------------------

-In Linux 5.18 the followings options are necessary to make use of

+In Linux 5.18 the following options are necessary to make use of

OS management of CXL memory devices as described here.

* CONFIG_CXL_BUS

--

2.25.1

From: Marc-André Lureau <marcandre.lureau@redhat.com>

../tests/test-qobject-input-visitor.c: In function ‘test_visitor_in_list’:

../tests/test-qobject-input-visitor.c:454:49: warning: ‘%d’ directive output may be truncated writing between 1 and 10 bytes into a region of size 6 [-Wformat-truncation=]

454 | snprintf(string, sizeof(string), "string%d", i);

| ^~

../tests/test-qobject-input-visitor.c:454:42: note: directive argument in the range [0, 2147483606]

454 | snprintf(string, sizeof(string), "string%d", i);

| ^~~~~~~~~~

../tests/test-qobject-input-visitor.c:454:9: note: ‘snprintf’ output between 8 and 17 bytes into a destination of size 12

454 | snprintf(string, sizeof(string), "string%d", i);

| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Rather than trying to be clever, since this is called 3 times during

tests, let's simply use g_strdup_printf().

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>

Reviewed-by: Markus Armbruster <armbru@redhat.com>

Message-id: 20220810121513.1356081-1-marcandre.lureau@redhat.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

[PMM: fixed commit message typos]

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

tests/unit/test-qobject-input-visitor.c | 3 +--

1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/tests/unit/test-qobject-input-visitor.c b/tests/unit/test-qobject-input-visitor.c

index XXXXXXX..XXXXXXX 100644

--- a/tests/unit/test-qobject-input-visitor.c

+++ b/tests/unit/test-qobject-input-visitor.c

@@ -XXX,XX +XXX,XX @@ static void test_visitor_in_list(TestInputVisitorData *data,

g_assert(head != NULL);

for (i = 0, item = head; item; item = item->next, i++) {

- char string[12];

+ g_autofree char *string = g_strdup_printf("string%d", i);

- snprintf(string, sizeof(string), "string%d", i);

g_assert_cmpstr(item->value->string, ==, string);

g_assert_cmpint(item->value->integer, ==, 42 + i);

}

--

2.25.1

From: Zenghui Yu <yuzenghui@huawei.com>

With the introduction of the new TCG GICv4, build_madt() is badly broken

as we do not present any GIC Redistributor structure in MADT for GICv4

guests, so that they have no idea about where the Redistributor

register frames are. This fixes a Linux guest crash at boot time with

ACPI enabled and '-machine gic-version=4'.

While at it, let's convert the remaining hard coded gic_version into

enumeration VIRT_GIC_VERSION_2 for consistency.

Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>

Message-id: 20220812022018.1069-1-yuzenghui@huawei.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/virt-acpi-build.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/virt-acpi-build.c

+++ b/hw/arm/virt-acpi-build.c

@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)

uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?

PPI(VIRTUAL_PMU_IRQ) : 0;

- if (vms->gic_version == 2) {

+ if (vms->gic_version == VIRT_GIC_VERSION_2) {

physical_base_address = memmap[VIRT_GIC_CPU].base;

gicv = memmap[VIRT_GIC_VCPU].base;

gich = memmap[VIRT_GIC_HYP].base;

@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)

build_append_int_noprefix(table_data, armcpu->mp_affinity, 8);

}

- if (vms->gic_version == 3) {

+ if (vms->gic_version != VIRT_GIC_VERSION_2) {

build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base,

memmap[VIRT_GIC_REDIST].size);

if (virt_gicv3_redist_region_count(vms) == 2) {

--

2.25.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Commit 06680b15b4 moved qemu_*_exec_dir() to cutils but forgot

to move the macOS dyld(3) include, resulting in the following

error (when building with Homebrew GCC on macOS Monterey 12.4):

[313/1197] Compiling C object libqemuutil.a.p/util_cutils.c.o

FAILED: libqemuutil.a.p/util_cutils.c.o

../../util/cutils.c:1039:13: error: implicit declaration of function '_NSGetExecutablePath' [-Werror=implicit-function-declaration]

1039 | if (_NSGetExecutablePath(fpath, &len) == 0) {

| ^~~~~~~~~~~~~~~~~~~~

../../util/cutils.c:1039:13: error: nested extern declaration of '_NSGetExecutablePath' [-Werror=nested-externs]

Fix by moving the include line to cutils.

Fixes: 06680b15b4 ("include: move qemu_*_exec_dir() to cutils")

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20220809222046.30812-1-f4bug@amsat.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

util/cutils.c | 4 ++++

util/oslib-posix.c | 4 ----

2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/util/cutils.c b/util/cutils.c

index XXXXXXX..XXXXXXX 100644

--- a/util/cutils.c

+++ b/util/cutils.c

@@ -XXX,XX +XXX,XX @@

#include <kernel/image.h>

#endif

+#ifdef __APPLE__

+#include <mach-o/dyld.h>

+#endif

+

#ifdef G_OS_WIN32

#include <pathcch.h>

#include <wchar.h>

diff --git a/util/oslib-posix.c b/util/oslib-posix.c

index XXXXXXX..XXXXXXX 100644

--- a/util/oslib-posix.c

+++ b/util/oslib-posix.c

@@ -XXX,XX +XXX,XX @@

#include <lwp.h>

#endif

-#ifdef __APPLE__

-#include <mach-o/dyld.h>

-#endif

-

#include "qemu/mmap-alloc.h"

#ifdef CONFIG_DEBUG_STACK_USAGE

--

2.25.1