On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
> The same rationale provided in the PHB3 bus case applies here.
>
> Note: we could have merged both buses in a single object, like we did
> with the root ports, and spare some boilerplate. The reason we opted to
> preserve both buses objects is twofold:
>
> - there's not user side advantage in doing so. Unifying the root ports
> presents a clear user QOL change when we enable user created devices back.
> The buses objects, aside from having a different QOM name, is transparent
> to the user;
>
> - we leave a door opened in case we want to increase the root port limit
> for phb4/5 later on without having to deal with phb3 code.
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> hw/pci-host/pnv_phb4.c | 51 ++++++++++++++++++++++++++++++++++
> include/hw/pci-host/pnv_phb4.h | 10 +++++++
> 2 files changed, 61 insertions(+)
>
> diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
> index b98c394713..824e1a73fb 100644
> --- a/hw/pci-host/pnv_phb4.c
> +++ b/hw/pci-host/pnv_phb4.c
> @@ -1551,6 +1551,12 @@ void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb)
> pnv_phb4_set_irq, pnv_phb4_map_irq, phb,
> &phb->pci_mmio, &phb->pci_io,
> 0, 4, TYPE_PNV_PHB4_ROOT_BUS);
> +
> + object_property_set_int(OBJECT(pci->bus), "phb-id", phb->phb_id,
> + &error_abort);
> + object_property_set_int(OBJECT(pci->bus), "chip-id", phb->chip_id,
> + &error_abort);
> +
> pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb);
> pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
> }
> @@ -1708,10 +1714,55 @@ static const TypeInfo pnv_phb5_type_info = {
> .instance_size = sizeof(PnvPHB4),
> };
>
> +static void pnv_phb4_root_bus_get_prop(Object *obj, Visitor *v,
> + const char *name,
> + void *opaque, Error **errp)
> +{
> + PnvPHB4RootBus *bus = PNV_PHB4_ROOT_BUS(obj);
> + uint64_t value = 0;
> +
> + if (strcmp(name, "phb-id") == 0) {
> + value = bus->phb_id;
> + } else {
> + value = bus->chip_id;
> + }
> +
> + visit_type_size(v, name, &value, errp);
> +}
> +
> +static void pnv_phb4_root_bus_set_prop(Object *obj, Visitor *v,
> + const char *name,
> + void *opaque, Error **errp)
> +
> +{
> + PnvPHB4RootBus *bus = PNV_PHB4_ROOT_BUS(obj);
> + uint64_t value;
> +
> + if (!visit_type_size(v, name, &value, errp)) {
> + return;
> + }
> +
> + if (strcmp(name, "phb-id") == 0) {
> + bus->phb_id = value;
> + } else {
> + bus->chip_id = value;
> + }
> +}
> +
> static void pnv_phb4_root_bus_class_init(ObjectClass *klass, void *data)
> {
> BusClass *k = BUS_CLASS(klass);
>
> + object_class_property_add(klass, "phb-id", "int",
> + pnv_phb4_root_bus_get_prop,
> + pnv_phb4_root_bus_set_prop,
> + NULL, NULL);
> +
> + object_class_property_add(klass, "chip-id", "int",
> + pnv_phb4_root_bus_get_prop,
> + pnv_phb4_root_bus_set_prop,
> + NULL, NULL);
> +
> /*
> * PHB4 has only a single root complex. Enforce the limit on the
> * parent bus
> diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
> index 20aa4819d3..50d4faa001 100644
> --- a/include/hw/pci-host/pnv_phb4.h
> +++ b/include/hw/pci-host/pnv_phb4.h
> @@ -45,7 +45,17 @@ typedef struct PnvPhb4DMASpace {
> QLIST_ENTRY(PnvPhb4DMASpace) list;
> } PnvPhb4DMASpace;
>
> +/*
> + * PHB4 PCIe Root Bus
> + */
> #define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root"
> +struct PnvPHB4RootBus {
> + PCIBus parent;
> +
> + uint32_t chip_id;
> + uint32_t phb_id;
> +};
> +OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4RootBus, PNV_PHB4_ROOT_BUS)
>
> /*
> * PHB4 PCIe Host Bridge for PowerNV machines (POWER9)