[PULL 0/1] target-arm queue
[PULL v2 00/57] target-arm queue
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Just one bugfix patch for this rc:
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Squashed in a trivial fix for 32-bit hosts:
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The following changes since commit ca5f3d4df1b47d7f66a109cdb504e83dfd7ec433:
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--- a/target/arm/mve_helper.c
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+++ b/target/arm/mve_helper.c
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@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
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acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
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m[H##ESIZE(e)])); \
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} \
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- acc = int128_add(acc, 1 << 7); \
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+ acc = int128_add(acc, int128_make64(1 << 7)); \
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} \
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} \
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mve_advance_vpt(env); \
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Merge tag 'pull-la-20220808' of https://gitlab.com/rth7680/qemu into staging (2022-08-08 19:51:12 -0700)
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-- PMM
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The following changes since commit 53f306f316549d20c76886903181413d20842423:
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Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220809
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
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for you to fetch changes up to c7f26ded6d5065e4116f630f6a490b55f6c5f58e:
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for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
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icount: Take iothread lock when running QEMU timers (2022-08-09 10:55:14 +0100)
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docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* icount: Take iothread lock when running QEMU timers
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* Don't require 'virt' board to be compiled in for ACPI GHES code
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* docs: Document which architecture extensions we emulate
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* Fix bugs in M-profile FPCXT_NS accesses
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* First slice of MVE patches
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* Implement MTE3
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* docs/system: arm: Add nRF boards description
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----------------------------------------------------------------
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----------------------------------------------------------------
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Peter Maydell (1):
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Alexandre Iooss (1):
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icount: Take iothread lock when running QEMU timers
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docs/system: arm: Add nRF boards description
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accel/tcg/tcg-accel-ops-icount.c | 6 ++++++
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Peter Collingbourne (1):
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1 file changed, 6 insertions(+)
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target/arm: Implement MTE3
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Peter Maydell (55):
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hw/acpi: Provide stub version of acpi_ghes_record_errors()
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hw/acpi: Provide function acpi_ghes_present()
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target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
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docs/system/arm: Document which architecture extensions we emulate
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target/arm/translate-vfp.c: Whitespace fixes
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target/arm: Handle FPU being disabled in FPCXT_NS accesses
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target/arm: Don't NOCP fault for FPCXT_NS accesses
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target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
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target/arm: Factor FP context update code out into helper function
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target/arm: Split vfp_access_check() into A and M versions
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target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
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target/arm: Implement MVE VLDR/VSTR (non-widening forms)
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target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
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target/arm: Implement MVE VCLZ
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target/arm: Implement MVE VCLS
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target/arm: Implement MVE VREV16, VREV32, VREV64
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target/arm: Implement MVE VMVN (register)
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target/arm: Implement MVE VABS
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target/arm: Implement MVE VNEG
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tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
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target/arm: Implement MVE VDUP
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target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
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target/arm: Implement MVE VADD, VSUB, VMUL
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target/arm: Implement MVE VMULH
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target/arm: Implement MVE VRMULH
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target/arm: Implement MVE VMAX, VMIN
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target/arm: Implement MVE VABD
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target/arm: Implement MVE VHADD, VHSUB
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target/arm: Implement MVE VMULL
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target/arm: Implement MVE VMLALDAV
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target/arm: Implement MVE VMLSLDAV
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target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
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target/arm: Implement MVE VADD (scalar)
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target/arm: Implement MVE VSUB, VMUL (scalar)
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target/arm: Implement MVE VHADD, VHSUB (scalar)
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target/arm: Implement MVE VBRSR
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target/arm: Implement MVE VPST
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target/arm: Implement MVE VQADD and VQSUB
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target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
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target/arm: Implement MVE VQDMULL scalar
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target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
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target/arm: Implement MVE VQADD, VQSUB (vector)
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target/arm: Implement MVE VQSHL (vector)
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target/arm: Implement MVE VQRSHL
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target/arm: Implement MVE VSHL insn
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target/arm: Implement MVE VRSHL
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target/arm: Implement MVE VQDMLADH and VQRDMLADH
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target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
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target/arm: Implement MVE VQDMULL (vector)
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target/arm: Implement MVE VRHADD
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target/arm: Implement MVE VADC, VSBC
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target/arm: Implement MVE VCADD
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target/arm: Implement MVE VHCADD
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target/arm: Implement MVE VADDV
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target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
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docs/system/arm/emulation.rst | 103 ++++
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docs/system/arm/nrf.rst | 51 ++
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docs/system/target-arm.rst | 7 +
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include/hw/acpi/ghes.h | 9 +
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include/tcg/tcg-op.h | 8 +
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include/tcg/tcg.h | 1 -
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target/arm/helper-mve.h | 357 +++++++++++++
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target/arm/helper.h | 2 +
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target/arm/internals.h | 11 +
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target/arm/translate-a32.h | 3 +
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target/arm/translate.h | 10 +
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target/arm/m-nocp.decode | 24 +
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target/arm/mve.decode | 240 +++++++++
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target/arm/vfp.decode | 14 -
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hw/acpi/ghes-stub.c | 22 +
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hw/acpi/ghes.c | 17 +
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target/arm/cpu64.c | 2 +-
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target/arm/kvm64.c | 6 +-
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target/arm/mte_helper.c | 82 +--
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target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
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target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
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target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
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target/arm/translate-vfp.c | 741 +++++++-------------------
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tcg/tcg-op-gvec.c | 20 +-
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MAINTAINERS | 1 +
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hw/acpi/meson.build | 6 +-
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target/arm/meson.build | 1 +
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27 files changed, 3578 insertions(+), 629 deletions(-)
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create mode 100644 docs/system/arm/emulation.rst
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create mode 100644 docs/system/arm/nrf.rst
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create mode 100644 target/arm/helper-mve.h
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create mode 100644 hw/acpi/ghes-stub.c
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create mode 100644 target/arm/mve_helper.c
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diff view generated by jsdifflib
[PULL 1/1] icount: Take iothread lock when running QEMU timers
Deleted patch
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The function icount_prepare_for_run() is called with the iothread
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unlocked, but it can call icount_notify_aio_contexts() which will
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run qemu timer handlers. Those are supposed to be run only with
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the iothread lock held, so take the lock while we do that.
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1
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Since icount mode runs everything on a single thread anyway,
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not holding the lock is likely mostly not going to introduce
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races, but it can cause us to trip over assertions that we
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do hold the lock, such as the one reported in issue 1130.
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1130
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Tested-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
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Message-id: 20220801164527.3134765-1-peter.maydell@linaro.org
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---
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accel/tcg/tcg-accel-ops-icount.c | 6 ++++++
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1 file changed, 6 insertions(+)
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diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-icount.c
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index XXXXXXX..XXXXXXX 100644
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--- a/accel/tcg/tcg-accel-ops-icount.c
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+++ b/accel/tcg/tcg-accel-ops-icount.c
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@@ -XXX,XX +XXX,XX @@ void icount_prepare_for_run(CPUState *cpu)
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replay_mutex_lock();
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if (cpu->icount_budget == 0) {
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+ /*
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+ * We're called without the iothread lock, so must take it while
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+ * we're calling timer handlers.
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+ */
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+ qemu_mutex_lock_iothread();
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icount_notify_aio_contexts();
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+ qemu_mutex_unlock_iothread();
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}
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}
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--
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2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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