Series comparison

-[PULL 0/1] target-arm queue
+[PULL v2 00/11] target-arm queue
-Just one bugfix patch for this rc:
+Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
 ethernet device failed 'make check' on big-endian hosts.
-The following changes since commit ca5f3d4df1b47d7f66a109cdb504e83dfd7ec433:
+-- PMM
-  Merge tag 'pull-la-20220808' of https://gitlab.com/rth7680/qemu into staging (2022-08-08 19:51:12 -0700)
+The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:
   Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220809
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1
-for you to fetch changes up to c7f26ded6d5065e4116f630f6a490b55f6c5f58e:
+for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:
-  icount: Take iothread lock when running QEMU timers (2022-08-09 10:55:14 +0100)
+  target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * icount: Take iothread lock when running QEMU timers
+ * Correctly initialize MDCR_EL2.HPMN
  * versal: Use nr_apu_cpus in favor of hard coding 2
  * accel/tcg: Add URL of clang bug to comment about our workaround
  * Add support for FEAT_DIT, Data Independent Timing
  * Remove GPIO from unimplemented NPCM7XX
  * Fix SCR RES1 handling
  * Don't migrate CPUARMState.features
 ----------------------------------------------------------------
-Peter Maydell (1):
+Aaron Lindsay (1):
-      icount: Take iothread lock when running QEMU timers
+      target/arm: Don't migrate CPUARMState.features
- accel/tcg/tcg-accel-ops-icount.c | 6 ++++++
+Daniel Müller (1):
-file changed, 6 insertions(+)
+      target/arm: Correctly initialize MDCR_EL2.HPMN
 Edgar E. Iglesias (1):
       hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
 Hao Wu (1):
       hw/arm: Remove GPIO from unimplemented NPCM7XX
 Mike Nawrocki (1):
       target/arm: Fix SCR RES1 handling
 Peter Maydell (2):
       arm: Update infocenter.arm.com URLs
       accel/tcg: Add URL of clang bug to comment about our workaround
 Rebecca Cran (4):
       target/arm: Add support for FEAT_DIT, Data Independent Timing
       target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
       target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
       target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
  include/hw/dma/pl080.h                 |  7 ++--
  include/hw/misc/arm_integrator_debug.h |  2 +-
  include/hw/ssi/pl022.h                 |  5 ++-
  target/arm/cpu.h                       | 17 ++++++++
  target/arm/internals.h                 |  6 +++
  accel/tcg/cpu-exec.c                   | 25 +++++++++---
  hw/arm/aspeed_ast2600.c                |  2 +-
  hw/arm/musca.c                         |  4 +-
  hw/arm/npcm7xx.c                       |  8 ----
  hw/arm/xlnx-versal.c                   |  4 +-
  hw/misc/arm_integrator_debug.c         |  2 +-
  hw/timer/arm_timer.c                   |  7 ++--
  target/arm/cpu.c                       |  4 ++
  target/arm/cpu64.c                     |  5 +++
  target/arm/helper-a64.c                | 27 +++++++++++--
  target/arm/helper.c                    | 71 +++++++++++++++++++++++++++-------
  target/arm/machine.c                   |  2 +-
  target/arm/op_helper.c                 |  9 +----
  target/arm/translate-a64.c             | 12 ++++++
 files changed, 164 insertions(+), 55 deletions(-)

-[PULL 1/1] icount: Take iothread lock when running QEMU timers
+Deleted patch
-The function icount_prepare_for_run() is called with the iothread
-unlocked, but it can call icount_notify_aio_contexts() which will
-run qemu timer handlers. Those are supposed to be run only with
-the iothread lock held, so take the lock while we do that.
-Since icount mode runs everything on a single thread anyway,
-not holding the lock is likely mostly not going to introduce
-races, but it can cause us to trip over assertions that we
-do hold the lock, such as the one reported in issue 1130.
-Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1130
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Tested-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
-Message-id: 20220801164527.3134765-1-peter.maydell@linaro.org
----
- accel/tcg/tcg-accel-ops-icount.c | 6 ++++++
-file changed, 6 insertions(+)
-diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-icount.c
-index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/tcg-accel-ops-icount.c
-+++ b/accel/tcg/tcg-accel-ops-icount.c
-@@ -XXX,XX +XXX,XX @@ void icount_prepare_for_run(CPUState *cpu)
-     replay_mutex_lock();
-     if (cpu->icount_budget == 0) {
-+        /*
-+         * We're called without the iothread lock, so must take it while
-+         * we're calling timer handlers.
-+         */
-+        qemu_mutex_lock_iothread();
-         icount_notify_aio_contexts();
-+        qemu_mutex_unlock_iothread();
-     }
- }
---
-.25.1

The function icount_prepare_for_run() is called with the iothread
unlocked, but it can call icount_notify_aio_contexts() which will
run qemu timer handlers. Those are supposed to be run only with
the iothread lock held, so take the lock while we do that.

Since icount mode runs everything on a single thread anyway,
not holding the lock is likely mostly not going to introduce
races, but it can cause us to trip over assertions that we
do hold the lock, such as the one reported in issue 1130.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1130
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Message-id: 20220801164527.3134765-1-peter.maydell@linaro.org
---
 accel/tcg/tcg-accel-ops-icount.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-icount.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/tcg-accel-ops-icount.c
+++ b/accel/tcg/tcg-accel-ops-icount.c
@@ -XXX,XX +XXX,XX @@ void icount_prepare_for_run(CPUState *cpu)
     replay_mutex_lock();
 
     if (cpu->icount_budget == 0) {
+        /*
+         * We're called without the iothread lock, so must take it while
+         * we're calling timer handlers.
+         */
+        qemu_mutex_lock_iothread();
         icount_notify_aio_contexts();
+        qemu_mutex_unlock_iothread();
     }
 }
 
-- 
2.25.1

Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
ethernet device failed 'make check' on big-endian hosts.

-- PMM

The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:

Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1

for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:

target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)

----------------------------------------------------------------
target-arm queue:
 * Correctly initialize MDCR_EL2.HPMN
 * versal: Use nr_apu_cpus in favor of hard coding 2
 * accel/tcg: Add URL of clang bug to comment about our workaround
 * Add support for FEAT_DIT, Data Independent Timing
 * Remove GPIO from unimplemented NPCM7XX
 * Fix SCR RES1 handling
 * Don't migrate CPUARMState.features

----------------------------------------------------------------
Aaron Lindsay (1):
      target/arm: Don't migrate CPUARMState.features

Daniel Müller (1):
      target/arm: Correctly initialize MDCR_EL2.HPMN

Edgar E. Iglesias (1):
      hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2

Hao Wu (1):
      hw/arm: Remove GPIO from unimplemented NPCM7XX

Mike Nawrocki (1):
      target/arm: Fix SCR RES1 handling

Peter Maydell (2):
      arm: Update infocenter.arm.com URLs
      accel/tcg: Add URL of clang bug to comment about our workaround

Rebecca Cran (4):
      target/arm: Add support for FEAT_DIT, Data Independent Timing
      target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
      target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
      target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU