[PATCH v2 00/20] ppc: QOM'ify 405 board

Cédric Le Goater posted 20 patches 3 years, 6 months ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20220803132844.2370514-1-clg@kaod.org
There is a newer version of this series
docs/about/deprecated.rst       |   9 -
docs/about/removed-features.rst |   6 +
docs/system/ppc/embedded.rst    |   1 -
hw/ppc/ppc405.h                 | 210 ++++++++-
include/hw/ppc/ppc4xx.h         |  29 ++
hw/ppc/ppc405_boards.c          | 366 ++++-----------
hw/ppc/ppc405_uc.c              | 799 +++++++++++++++++++-------------
hw/ppc/ppc4xx_devs.c            | 124 +++--
MAINTAINERS                     |   2 +-
9 files changed, 894 insertions(+), 652 deletions(-)
[PATCH v2 00/20] ppc: QOM'ify 405 board
Posted by Cédric Le Goater 3 years, 6 months ago
Hello,

Here is large series QOM'ifying the PPC405 board. It introduces a new
generic machine and SoC models, converts the current device models to
QOM and populates the SoC. The process is quite mechanical without too
much issues to handle. The noisy part is the initial patch introducing
the SoC realize routine.

What's left ?

* The DCR read/writre handlers are attached in table to the CPU
  instance. We could probably rework the whole with a specific address
  space and memory regions handling the implemented registers. I don't
  think this is necessary.

* the SDRAM mappings are very baroque and certainly could be simplified.
  I think we should QOMify the ppc440 machines before addressing this
  part.

Thanks,

C.

Changes in v2 :

 - docs/about/removed-features.rst update
 - Fix compile breakage (uic)
 - Fix CPU reset, which breaking u-boot boot
 - Changed prefix of memory regions to "ppc405"
 - Reduced the number of RAM banks to 1. Second was a dummy one to
   please ppc405ep_init()

Cédric Le Goater (20):
  ppc/ppc405: Remove taihu machine
  ppc/ppc405: Introduce a PPC405 generic machine
  ppc/ppc405: Move devices under the ref405ep machine
  ppc/ppc405: Introduce a PPC405 SoC
  ppc/ppc405: Start QOMification of the SoC
  ppc/ppc405: QOM'ify CPU
  ppc/ppc405: QOM'ify CPC
  ppc/ppc405: QOM'ify GPT
  ppc/ppc405: QOM'ify OCM
  ppc/ppc405: QOM'ify GPIO
  ppc/ppc405: QOM'ify DMA
  ppc/ppc405: QOM'ify EBC
  ppc/ppc405: QOM'ify OPBA
  ppc/ppc405: QOM'ify POB
  ppc/ppc405: QOM'ify PLB
  ppc/ppc405: QOM'ify MAL
  ppc/ppc405: QOM'ify FPGA
  ppc/ppc405: QOM'ify UIC
  ppc/ppc405: QOM'ify I2C
  ppc/ppc4xx: Fix sdram trace events

 docs/about/deprecated.rst       |   9 -
 docs/about/removed-features.rst |   6 +
 docs/system/ppc/embedded.rst    |   1 -
 hw/ppc/ppc405.h                 | 210 ++++++++-
 include/hw/ppc/ppc4xx.h         |  29 ++
 hw/ppc/ppc405_boards.c          | 366 ++++-----------
 hw/ppc/ppc405_uc.c              | 799 +++++++++++++++++++-------------
 hw/ppc/ppc4xx_devs.c            | 124 +++--
 MAINTAINERS                     |   2 +-
 9 files changed, 894 insertions(+), 652 deletions(-)

-- 
2.37.1


Re: [PATCH v2 00/20] ppc: QOM'ify 405 board
Posted by Cédric Le Goater 3 years, 6 months ago
Daniel,

On 8/3/22 15:28, Cédric Le Goater wrote:
> Hello,
> 
> Here is large series QOM'ifying the PPC405 board. It introduces a new
> generic machine and SoC models, converts the current device models to
> QOM and populates the SoC. The process is quite mechanical without too
> much issues to handle. The noisy part is the initial patch introducing
> the SoC realize routine.
>
> What's left ?
> 
> * The DCR read/writre handlers are attached in table to the CPU
>    instance. We could probably rework the whole with a specific address
>    space and memory regions handling the implemented registers. I don't
>    think this is necessary.
> 
> * the SDRAM mappings are very baroque and certainly could be simplified.
>    I think we should QOMify the ppc440 machines before addressing this
>    part.


I will resend a v3 taking into account the comments (and fixes) from you
and Zoltan.

Also, the PPC405 controller has 2 SDRAM banks, I should try to model
that with a single bank default. The ppc4xx_sdram_init() routine is
a bit of a pain to do anything clean really.


Thanks,
  
C.


  
> Changes in v2 :
> 
>   - docs/about/removed-features.rst update
>   - Fix compile breakage (uic)
>   - Fix CPU reset, which breaking u-boot boot
>   - Changed prefix of memory regions to "ppc405"
>   - Reduced the number of RAM banks to 1. Second was a dummy one to
>     please ppc405ep_init()
> 
> Cédric Le Goater (20):
>    ppc/ppc405: Remove taihu machine
>    ppc/ppc405: Introduce a PPC405 generic machine
>    ppc/ppc405: Move devices under the ref405ep machine
>    ppc/ppc405: Introduce a PPC405 SoC
>    ppc/ppc405: Start QOMification of the SoC
>    ppc/ppc405: QOM'ify CPU
>    ppc/ppc405: QOM'ify CPC
>    ppc/ppc405: QOM'ify GPT
>    ppc/ppc405: QOM'ify OCM
>    ppc/ppc405: QOM'ify GPIO
>    ppc/ppc405: QOM'ify DMA
>    ppc/ppc405: QOM'ify EBC
>    ppc/ppc405: QOM'ify OPBA
>    ppc/ppc405: QOM'ify POB
>    ppc/ppc405: QOM'ify PLB
>    ppc/ppc405: QOM'ify MAL
>    ppc/ppc405: QOM'ify FPGA
>    ppc/ppc405: QOM'ify UIC
>    ppc/ppc405: QOM'ify I2C
>    ppc/ppc4xx: Fix sdram trace events
> 
>   docs/about/deprecated.rst       |   9 -
>   docs/about/removed-features.rst |   6 +
>   docs/system/ppc/embedded.rst    |   1 -
>   hw/ppc/ppc405.h                 | 210 ++++++++-
>   include/hw/ppc/ppc4xx.h         |  29 ++
>   hw/ppc/ppc405_boards.c          | 366 ++++-----------
>   hw/ppc/ppc405_uc.c              | 799 +++++++++++++++++++-------------
>   hw/ppc/ppc4xx_devs.c            | 124 +++--
>   MAINTAINERS                     |   2 +-
>   9 files changed, 894 insertions(+), 652 deletions(-)
> 


Re: [PATCH v2 00/20] ppc: QOM'ify 405 board
Posted by Daniel Henrique Barboza 3 years, 6 months ago

On 8/4/22 03:07, Cédric Le Goater wrote:
> Daniel,
> 
> On 8/3/22 15:28, Cédric Le Goater wrote:
>> Hello,
>>
>> Here is large series QOM'ifying the PPC405 board. It introduces a new
>> generic machine and SoC models, converts the current device models to
>> QOM and populates the SoC. The process is quite mechanical without too
>> much issues to handle. The noisy part is the initial patch introducing
>> the SoC realize routine.
>>
>> What's left ?
>>
>> * The DCR read/writre handlers are attached in table to the CPU
>>    instance. We could probably rework the whole with a specific address
>>    space and memory regions handling the implemented registers. I don't
>>    think this is necessary.
>>
>> * the SDRAM mappings are very baroque and certainly could be simplified.
>>    I think we should QOMify the ppc440 machines before addressing this
>>    part.
> 
> 
> I will resend a v3 taking into account the comments (and fixes) from you
> and Zoltan.

I'll get whatever pending fixes we have for the freeze and send a PR including
the mal_irqs[] fix today. I'll be less stuff to worry about for this series.


Daniel

> 
> Also, the PPC405 controller has 2 SDRAM banks, I should try to model
> that with a single bank default. The ppc4xx_sdram_init() routine is
> a bit of a pain to do anything clean really.
> 
> 
> Thanks,
> 
> C.
> 
> 
> 
>> Changes in v2 :
>>
>>   - docs/about/removed-features.rst update
>>   - Fix compile breakage (uic)
>>   - Fix CPU reset, which breaking u-boot boot
>>   - Changed prefix of memory regions to "ppc405"
>>   - Reduced the number of RAM banks to 1. Second was a dummy one to
>>     please ppc405ep_init()
>>
>> Cédric Le Goater (20):
>>    ppc/ppc405: Remove taihu machine
>>    ppc/ppc405: Introduce a PPC405 generic machine
>>    ppc/ppc405: Move devices under the ref405ep machine
>>    ppc/ppc405: Introduce a PPC405 SoC
>>    ppc/ppc405: Start QOMification of the SoC
>>    ppc/ppc405: QOM'ify CPU
>>    ppc/ppc405: QOM'ify CPC
>>    ppc/ppc405: QOM'ify GPT
>>    ppc/ppc405: QOM'ify OCM
>>    ppc/ppc405: QOM'ify GPIO
>>    ppc/ppc405: QOM'ify DMA
>>    ppc/ppc405: QOM'ify EBC
>>    ppc/ppc405: QOM'ify OPBA
>>    ppc/ppc405: QOM'ify POB
>>    ppc/ppc405: QOM'ify PLB
>>    ppc/ppc405: QOM'ify MAL
>>    ppc/ppc405: QOM'ify FPGA
>>    ppc/ppc405: QOM'ify UIC
>>    ppc/ppc405: QOM'ify I2C
>>    ppc/ppc4xx: Fix sdram trace events
>>
>>   docs/about/deprecated.rst       |   9 -
>>   docs/about/removed-features.rst |   6 +
>>   docs/system/ppc/embedded.rst    |   1 -
>>   hw/ppc/ppc405.h                 | 210 ++++++++-
>>   include/hw/ppc/ppc4xx.h         |  29 ++
>>   hw/ppc/ppc405_boards.c          | 366 ++++-----------
>>   hw/ppc/ppc405_uc.c              | 799 +++++++++++++++++++-------------
>>   hw/ppc/ppc4xx_devs.c            | 124 +++--
>>   MAINTAINERS                     |   2 +-
>>   9 files changed, 894 insertions(+), 652 deletions(-)
>>
> 

Re: [PATCH v2 00/20] ppc: QOM'ify 405 board
Posted by Cédric Le Goater 3 years, 6 months ago
On 8/4/22 12:07, Daniel Henrique Barboza wrote:
> 
> 
> On 8/4/22 03:07, Cédric Le Goater wrote:
>> Daniel,
>>
>> On 8/3/22 15:28, Cédric Le Goater wrote:
>>> Hello,
>>>
>>> Here is large series QOM'ifying the PPC405 board. It introduces a new
>>> generic machine and SoC models, converts the current device models to
>>> QOM and populates the SoC. The process is quite mechanical without too
>>> much issues to handle. The noisy part is the initial patch introducing
>>> the SoC realize routine.
>>>
>>> What's left ?
>>>
>>> * The DCR read/writre handlers are attached in table to the CPU
>>>    instance. We could probably rework the whole with a specific address
>>>    space and memory regions handling the implemented registers. I don't
>>>    think this is necessary.
>>>
>>> * the SDRAM mappings are very baroque and certainly could be simplified.
>>>    I think we should QOMify the ppc440 machines before addressing this
>>>    part.
>>
>>
>> I will resend a v3 taking into account the comments (and fixes) from you
>> and Zoltan.
> 
> I'll get whatever pending fixes we have for the freeze and send a PR including
> the mal_irqs[] fix today. 

Yes. Please do that. The mal_irqs[] issue is clearly a "for-7.1" fix.

> I'll be less stuff to worry about for this series.

I think I am going to add some extras to remove the plb/ebc/mal init
routines while I am at changing things.

Thanks,

C.

> 
> Daniel
> 
>>
>> Also, the PPC405 controller has 2 SDRAM banks, I should try to model
>> that with a single bank default. The ppc4xx_sdram_init() routine is
>> a bit of a pain to do anything clean really.
>>
>>
>> Thanks,
>>
>> C.
>>
>>
>>
>>> Changes in v2 :
>>>
>>>   - docs/about/removed-features.rst update
>>>   - Fix compile breakage (uic)
>>>   - Fix CPU reset, which breaking u-boot boot
>>>   - Changed prefix of memory regions to "ppc405"
>>>   - Reduced the number of RAM banks to 1. Second was a dummy one to
>>>     please ppc405ep_init()
>>>
>>> Cédric Le Goater (20):
>>>    ppc/ppc405: Remove taihu machine
>>>    ppc/ppc405: Introduce a PPC405 generic machine
>>>    ppc/ppc405: Move devices under the ref405ep machine
>>>    ppc/ppc405: Introduce a PPC405 SoC
>>>    ppc/ppc405: Start QOMification of the SoC
>>>    ppc/ppc405: QOM'ify CPU
>>>    ppc/ppc405: QOM'ify CPC
>>>    ppc/ppc405: QOM'ify GPT
>>>    ppc/ppc405: QOM'ify OCM
>>>    ppc/ppc405: QOM'ify GPIO
>>>    ppc/ppc405: QOM'ify DMA
>>>    ppc/ppc405: QOM'ify EBC
>>>    ppc/ppc405: QOM'ify OPBA
>>>    ppc/ppc405: QOM'ify POB
>>>    ppc/ppc405: QOM'ify PLB
>>>    ppc/ppc405: QOM'ify MAL
>>>    ppc/ppc405: QOM'ify FPGA
>>>    ppc/ppc405: QOM'ify UIC
>>>    ppc/ppc405: QOM'ify I2C
>>>    ppc/ppc4xx: Fix sdram trace events
>>>
>>>   docs/about/deprecated.rst       |   9 -
>>>   docs/about/removed-features.rst |   6 +
>>>   docs/system/ppc/embedded.rst    |   1 -
>>>   hw/ppc/ppc405.h                 | 210 ++++++++-
>>>   include/hw/ppc/ppc4xx.h         |  29 ++
>>>   hw/ppc/ppc405_boards.c          | 366 ++++-----------
>>>   hw/ppc/ppc405_uc.c              | 799 +++++++++++++++++++-------------
>>>   hw/ppc/ppc4xx_devs.c            | 124 +++--
>>>   MAINTAINERS                     |   2 +-
>>>   9 files changed, 894 insertions(+), 652 deletions(-)
>>>
>>