[PATCH v12 6/6] target/riscv: Remove additional priv version check for mcountinhibit

Atish Patra posted 6 patches 3 years, 6 months ago
There is a newer version of this series
[PATCH v12 6/6] target/riscv: Remove additional priv version check for mcountinhibit
Posted by Atish Patra 3 years, 6 months ago
With .min_priv_version, additiona priv version check is uncessary
for mcountinhibit read/write functions.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 target/riscv/csr.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 8753280e95b2..67367e678f38 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1489,10 +1489,6 @@ static RISCVException write_mtvec(CPURISCVState *env, int csrno,
 static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
                                          target_ulong *val)
 {
-    if (env->priv_ver < PRIV_VERSION_1_11_0) {
-        return RISCV_EXCP_ILLEGAL_INST;
-    }
-
     *val = env->mcountinhibit;
     return RISCV_EXCP_NONE;
 }
@@ -1503,10 +1499,6 @@ static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
     int cidx;
     PMUCTRState *counter;
 
-    if (env->priv_ver < PRIV_VERSION_1_11_0) {
-        return RISCV_EXCP_ILLEGAL_INST;
-    }
-
     env->mcountinhibit = val;
 
     /* Check if any other counter is also monitoring cycles/instructions */
-- 
2.25.1
Re: [PATCH v12 6/6] target/riscv: Remove additional priv version check for mcountinhibit
Posted by Alistair Francis 3 years, 5 months ago
On Wed, Aug 3, 2022 at 9:34 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> With .min_priv_version, additiona priv version check is uncessary
> for mcountinhibit read/write functions.
>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> Tested-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 8 --------
>  1 file changed, 8 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 8753280e95b2..67367e678f38 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1489,10 +1489,6 @@ static RISCVException write_mtvec(CPURISCVState *env, int csrno,
>  static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
>                                           target_ulong *val)
>  {
> -    if (env->priv_ver < PRIV_VERSION_1_11_0) {
> -        return RISCV_EXCP_ILLEGAL_INST;
> -    }
> -
>      *val = env->mcountinhibit;
>      return RISCV_EXCP_NONE;
>  }
> @@ -1503,10 +1499,6 @@ static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
>      int cidx;
>      PMUCTRState *counter;
>
> -    if (env->priv_ver < PRIV_VERSION_1_11_0) {
> -        return RISCV_EXCP_ILLEGAL_INST;
> -    }
> -
>      env->mcountinhibit = val;
>
>      /* Check if any other counter is also monitoring cycles/instructions */
> --
> 2.25.1
>
>