docs/specs/aspeed-intc.rst | 136 +++++

docs/specs/index.rst | 1 +

include/hw/arm/aspeed_soc.h | 4 +-

include/hw/intc/aspeed_intc.h | 36 +-

include/hw/misc/aspeed_hace.h | 2 +

include/hw/misc/aspeed_scu.h | 2 +

hw/arm/aspeed.c | 39 +-

hw/arm/aspeed_ast10x0.c | 3 +-

hw/arm/aspeed_ast2400.c | 4 +-

hw/arm/aspeed_ast2600.c | 3 +-

hw/arm/aspeed_ast27x0.c | 359 +++++++++----

hw/intc/aspeed_intc.c | 667 ++++++++++++++++++------

hw/misc/aspeed_hace.c | 55 +-

hw/misc/aspeed_scu.c | 10 +-

hw/intc/trace-events | 25 +-

tests/functional/aspeed.py | 24 +-

tests/functional/meson.build | 4 +

tests/functional/test_aarch64_aspeed.py | 47 +-

tests/functional/test_arm_aspeed_bletchley.py | 25 +

tests/functional/test_arm_aspeed_palmetto.py | 13 +-

tests/functional/test_arm_aspeed_romulus.py | 13 +-

tests/functional/test_arm_aspeed_witherspoon.py | 25 +

22 files changed, 1150 insertions(+), 347 deletions(-)

create mode 100644 docs/specs/aspeed-intc.rst

create mode 100644 tests/functional/test_arm_aspeed_bletchley.py

create mode 100644 tests/functional/test_arm_aspeed_witherspoon.py

The OpenBMC images currently used by QEMU to test the Aspeed machines

are rather old. To prepare an update to the latest builds, we need to

adjust the console patterns. Introduce a new routine to preserve the

current tests.

Reviewed-by: Thomas Huth <thuth@redhat.com>

Link: https://lore.kernel.org/qemu-devel/20250129071820.1258133-2-clg@redhat.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

tests/functional/aspeed.py | 18 ++++++++++++++++++

1 file changed, 18 insertions(+)

diff --git a/tests/functional/aspeed.py b/tests/functional/aspeed.py

index XXXXXXX..XXXXXXX 100644

--- a/tests/functional/aspeed.py

+++ b/tests/functional/aspeed.py

@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed(self, machine, image):

self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: irq ")

self.wait_for_console_pattern("systemd[1]: Set hostname to")

+ def do_test_arm_aspeed_openbmc(self, machine, image, uboot='2019.04',

+ cpu_id='0x0', soc='AST2500 rev A1'):

+ hostname = machine.removesuffix('-bmc')

+

+ self.set_machine(machine)

+ self.vm.set_console()

+ self.vm.add_args('-drive', f'file={image},if=mtd,format=raw',

+ '-snapshot')

+ self.vm.launch()

+

+ self.wait_for_console_pattern(f'U-Boot {uboot}')

+ self.wait_for_console_pattern('## Loading kernel from FIT Image')

+ self.wait_for_console_pattern('Starting kernel ...')

+ self.wait_for_console_pattern(f'Booting Linux on physical CPU {cpu_id}')

+ self.wait_for_console_pattern(f'ASPEED {soc}')

+ self.wait_for_console_pattern('/init as init process')

+ self.wait_for_console_pattern(f'systemd[1]: Hostname set to <{hostname}>.')

+

def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern='Aspeed EVB'):

self.require_netdev('user')

self.vm.set_console()

--

2.48.1

Use the new do_test_arm_aspeed_openbmc() routine to run the latest

OpenBMC firmware build of the palmetto BMC.

Reviewed-by: Thomas Huth <thuth@redhat.com>

Link: https://lore.kernel.org/qemu-devel/20250129071820.1258133-3-clg@redhat.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

tests/functional/test_arm_aspeed_palmetto.py | 13 +++++++------

1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/tests/functional/test_arm_aspeed_palmetto.py b/tests/functional/test_arm_aspeed_palmetto.py

index XXXXXXX..XXXXXXX 100755

--- a/tests/functional/test_arm_aspeed_palmetto.py

+++ b/tests/functional/test_arm_aspeed_palmetto.py

@@ -XXX,XX +XXX,XX @@

from qemu_test import Asset

from aspeed import AspeedTest

+

class PalmettoMachine(AspeedTest):

ASSET_PALMETTO_FLASH = Asset(

- ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'

- 'obmc-phosphor-image-palmetto.static.mtd'),

- '3e13bbbc28e424865dc42f35ad672b10f2e82cdb11846bb28fa625b48beafd0d');

+ 'https://github.com/legoater/qemu-aspeed-boot/raw/master/images/palmetto-bmc/openbmc-20250128071432/obmc-phosphor-image-palmetto-20250128071432.static.mtd',

+ 'bce7c392eec75c707a91cfc8fad7ca9a69d7e4f10df936930d65c1cb9897ac81');

- def test_arm_ast2400_palmetto_openbmc_v2_9_0(self):

+ def test_arm_ast2400_palmetto_openbmc(self):

image_path = self.ASSET_PALMETTO_FLASH.fetch()

- self.do_test_arm_aspeed('palmetto-bmc', image_path)

-

+ self.do_test_arm_aspeed_openbmc('palmetto-bmc', image=image_path,

+ uboot='2019.04', cpu_id='0x0',

+ soc='AST2400 rev A1');

if __name__ == '__main__':

AspeedTest.main()

--

2.48.1

Use the new do_test_arm_aspeed_openbmc() routine to run the latest

OpenBMC firmware build of the romulus BMC. Remove the older routine

which is now unused.

Reviewed-by: Thomas Huth <thuth@redhat.com>

Link: https://lore.kernel.org/qemu-devel/20250129071820.1258133-4-clg@redhat.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

tests/functional/aspeed.py | 16 ----------------

tests/functional/test_arm_aspeed_romulus.py | 13 +++++++------

2 files changed, 7 insertions(+), 22 deletions(-)

diff --git a/tests/functional/aspeed.py b/tests/functional/aspeed.py

index XXXXXXX..XXXXXXX 100644

--- a/tests/functional/aspeed.py

+++ b/tests/functional/aspeed.py

@@ -XXX,XX +XXX,XX @@

class AspeedTest(LinuxKernelTest):

- def do_test_arm_aspeed(self, machine, image):

- self.set_machine(machine)

- self.vm.set_console()

- self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw',

- '-net', 'nic', '-snapshot')

- self.vm.launch()

-

- self.wait_for_console_pattern("U-Boot 2016.07")

- self.wait_for_console_pattern("## Loading kernel from FIT Image at 20080000")

- self.wait_for_console_pattern("Starting kernel ...")

- self.wait_for_console_pattern("Booting Linux on physical CPU 0x0")

- self.wait_for_console_pattern(

- "aspeed-smc 1e620000.spi: read control register: 203b0641")

- self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: irq ")

- self.wait_for_console_pattern("systemd[1]: Set hostname to")

-

def do_test_arm_aspeed_openbmc(self, machine, image, uboot='2019.04',

cpu_id='0x0', soc='AST2500 rev A1'):

hostname = machine.removesuffix('-bmc')

diff --git a/tests/functional/test_arm_aspeed_romulus.py b/tests/functional/test_arm_aspeed_romulus.py

index XXXXXXX..XXXXXXX 100755

--- a/tests/functional/test_arm_aspeed_romulus.py

+++ b/tests/functional/test_arm_aspeed_romulus.py

@@ -XXX,XX +XXX,XX @@

from qemu_test import Asset

from aspeed import AspeedTest

+

class RomulusMachine(AspeedTest):

ASSET_ROMULUS_FLASH = Asset(

- ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'

- 'obmc-phosphor-image-romulus.static.mtd'),

- '820341076803f1955bc31e647a512c79f9add4f5233d0697678bab4604c7bb25')

+ 'https://github.com/legoater/qemu-aspeed-boot/raw/master/images/romulus-bmc/openbmc-20250128071340/obmc-phosphor-image-romulus-20250128071340.static.mtd',

+ '6d031376440c82ed9d087d25e9fa76aea75b42f80daa252ec402c0bc3cf6cf5b');

- def test_arm_ast2500_romulus_openbmc_v2_9_0(self):

+ def test_arm_ast2500_romulus_openbmc(self):

image_path = self.ASSET_ROMULUS_FLASH.fetch()

- self.do_test_arm_aspeed('romulus-bmc', image_path)

-

+ self.do_test_arm_aspeed_openbmc('romulus-bmc', image=image_path,

+ uboot='2019.04', cpu_id='0x0',

+ soc='AST2500 rev A1');

if __name__ == '__main__':

AspeedTest.main()

--

2.48.1

Use do_test_arm_aspeed_openbmc() routine to run the latest OpenBMC

firmware build of the witherspoon BMC.

Reviewed-by: Thomas Huth <thuth@redhat.com>

Link: https://lore.kernel.org/qemu-devel/20250129071820.1258133-5-clg@redhat.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

tests/functional/meson.build | 2 ++

.../functional/test_arm_aspeed_witherspoon.py | 25 +++++++++++++++++++

2 files changed, 27 insertions(+)

create mode 100644 tests/functional/test_arm_aspeed_witherspoon.py

diff --git a/tests/functional/meson.build b/tests/functional/meson.build

index XXXXXXX..XXXXXXX 100644

--- a/tests/functional/meson.build

+++ b/tests/functional/meson.build

@@ -XXX,XX +XXX,XX @@ test_timeouts = {

'acpi_bits' : 420,

'arm_aspeed_palmetto' : 120,

'arm_aspeed_romulus' : 120,

+ 'arm_aspeed_witherspoon' : 120,

'arm_aspeed_ast2500' : 720,

'arm_aspeed_ast2600' : 1200,

'arm_aspeed_rainier' : 480,

@@ -XXX,XX +XXX,XX @@ tests_arm_system_thorough = [

'arm_aspeed_ast1030',

'arm_aspeed_palmetto',

'arm_aspeed_romulus',

+ 'arm_aspeed_witherspoon',

'arm_aspeed_ast2500',

'arm_aspeed_ast2600',

'arm_aspeed_rainier',

diff --git a/tests/functional/test_arm_aspeed_witherspoon.py b/tests/functional/test_arm_aspeed_witherspoon.py

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/tests/functional/test_arm_aspeed_witherspoon.py

@@ -XXX,XX +XXX,XX @@

+#!/usr/bin/env python3

+#

+# Functional test that boots the ASPEED machines

+#

+# SPDX-License-Identifier: GPL-2.0-or-later

+

+from qemu_test import Asset

+from aspeed import AspeedTest

+

+

+class WitherspoonMachine(AspeedTest):

+

+ ASSET_WITHERSPOON_FLASH = Asset(

+ 'https://github.com/legoater/qemu-aspeed-boot/raw/master/images/witherspoon-bmc/openbmc-20240618035022/obmc-phosphor-image-witherspoon-20240618035022.ubi.mtd',

+ '937d9ed449ea6c6cbed983519088a42d0cafe276bcfe4fce07772ca6673f9213');

+

+ def test_arm_ast2500_witherspoon_openbmc(self):

+ image_path = self.ASSET_WITHERSPOON_FLASH.fetch()

+

+ self.do_test_arm_aspeed_openbmc('witherspoon-bmc', image=image_path,

+ uboot='2016.07', cpu_id='0x0',

+ soc='AST2500 rev A1');

+

+if __name__ == '__main__':

+ AspeedTest.main()

--

2.48.1

Use do_test_arm_aspeed_openbmc() to run the latest OpenBMC firmware

build of the bletchley BMC.

Reviewed-by: Patrick Williams <patrick@stwcx.xyz>

Reviewed-by: Thomas Huth <thuth@redhat.com>

Link: https://lore.kernel.org/qemu-devel/20250129071820.1258133-6-clg@redhat.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

tests/functional/meson.build | 2 ++

tests/functional/test_arm_aspeed_bletchley.py | 25 +++++++++++++++++++

2 files changed, 27 insertions(+)

create mode 100644 tests/functional/test_arm_aspeed_bletchley.py

diff --git a/tests/functional/meson.build b/tests/functional/meson.build

index XXXXXXX..XXXXXXX 100644

--- a/tests/functional/meson.build

+++ b/tests/functional/meson.build

@@ -XXX,XX +XXX,XX @@ test_timeouts = {

'arm_aspeed_witherspoon' : 120,

'arm_aspeed_ast2500' : 720,

'arm_aspeed_ast2600' : 1200,

+ 'arm_aspeed_bletchley' : 120,

'arm_aspeed_rainier' : 480,

'arm_bpim2u' : 500,

'arm_collie' : 180,

@@ -XXX,XX +XXX,XX @@ tests_arm_system_thorough = [

'arm_aspeed_witherspoon',

'arm_aspeed_ast2500',

'arm_aspeed_ast2600',

+ 'arm_aspeed_bletchley',

'arm_aspeed_rainier',

'arm_bpim2u',

'arm_canona1100',

diff --git a/tests/functional/test_arm_aspeed_bletchley.py b/tests/functional/test_arm_aspeed_bletchley.py

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/tests/functional/test_arm_aspeed_bletchley.py

@@ -XXX,XX +XXX,XX @@

+#!/usr/bin/env python3

+#

+# Functional test that boots the ASPEED machines

+#

+# SPDX-License-Identifier: GPL-2.0-or-later

+

+from qemu_test import Asset

+from aspeed import AspeedTest

+

+

+class BletchleyMachine(AspeedTest):

+

+ ASSET_BLETCHLEY_FLASH = Asset(

+ 'https://github.com/legoater/qemu-aspeed-boot/raw/master/images/bletchley-bmc/openbmc-20250128071329/obmc-phosphor-image-bletchley-20250128071329.static.mtd.xz',

+ 'db21d04d47d7bb2a276f59d308614b4dfb70b9c7c81facbbca40a3977a2d8844');

+

+ def test_arm_ast2600_bletchley_openbmc(self):

+ image_path = self.uncompress(self.ASSET_BLETCHLEY_FLASH)

+

+ self.do_test_arm_aspeed_openbmc('bletchley-bmc', image=image_path,

+ uboot='2019.04', cpu_id='0xf00',

+ soc='AST2600 rev A3');

+

+if __name__ == '__main__':

+ AspeedTest.main()

--

2.48.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

QEMU supports GICv3 Non-maskable Interrupt, adds to support Non-maskable

Interrupt for AST2700.

Reference:

https://github.com/qemu/qemu/commit/b36a32ead

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Link: https://lore.kernel.org/qemu-devel/20250204060955.3546022-1-jamin_lin@aspeedtech.com

---

hw/arm/aspeed_ast27x0.c | 4 ++++

1 file changed, 4 insertions(+)

diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/aspeed_ast27x0.c

+++ b/hw/arm/aspeed_ast27x0.c

@@ -XXX,XX +XXX,XX @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)

qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));

sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus,

qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));

+ sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus,

+ qdev_get_gpio_in(cpudev, ARM_CPU_NMI));

+ sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus,

+ qdev_get_gpio_in(cpudev, ARM_CPU_VINMI));

}

return true;

--

2.48.1

The SoC type name is stored under AspeedSoCClass which is

redundant. Use object_get_typename() instead where needed.

Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>

Link: https://lore.kernel.org/qemu-devel/20250218073534.585066-1-clg@redhat.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

include/hw/arm/aspeed_soc.h | 1 -

hw/arm/aspeed_ast10x0.c | 3 +--

hw/arm/aspeed_ast2400.c | 4 +---

hw/arm/aspeed_ast2600.c | 3 +--

hw/arm/aspeed_ast27x0.c | 3 +--

5 files changed, 4 insertions(+), 10 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/arm/aspeed_soc.h

+++ b/include/hw/arm/aspeed_soc.h

@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)

struct AspeedSoCClass {

DeviceClass parent_class;

- const char *name;

/** valid_cpu_types: NULL terminated array of a single CPU type. */

const char * const *valid_cpu_types;

uint32_t silicon_rev;

diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/aspeed_ast10x0.c

+++ b/hw/arm/aspeed_ast10x0.c

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)

char typename[64];

int i;

- if (sscanf(sc->name, "%7s", socname) != 1) {

+ if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {

g_assert_not_reached();

}

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)

dc->user_creatable = false;

dc->realize = aspeed_soc_ast1030_realize;

- sc->name = "ast1030-a1";

sc->valid_cpu_types = valid_cpu_types;

sc->silicon_rev = AST1030_A1_SILICON_REV;

sc->sram_size = 0xc0000;

diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/aspeed_ast2400.c

+++ b/hw/arm/aspeed_ast2400.c

@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)

char socname[8];

char typename[64];

- if (sscanf(sc->name, "%7s", socname) != 1) {

+ if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {

g_assert_not_reached();

}

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)

/* Reason: Uses serial_hds and nd_table in realize() directly */

dc->user_creatable = false;

- sc->name = "ast2400-a1";

sc->valid_cpu_types = valid_cpu_types;

sc->silicon_rev = AST2400_A1_SILICON_REV;

sc->sram_size = 0x8000;

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)

/* Reason: Uses serial_hds and nd_table in realize() directly */

dc->user_creatable = false;

- sc->name = "ast2500-a1";

sc->valid_cpu_types = valid_cpu_types;

sc->silicon_rev = AST2500_A1_SILICON_REV;

sc->sram_size = 0x9000;

diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/aspeed_ast2600.c

+++ b/hw/arm/aspeed_ast2600.c

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)

char socname[8];

char typename[64];

- if (sscanf(sc->name, "%7s", socname) != 1) {

+ if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {

g_assert_not_reached();

}

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)

/* Reason: The Aspeed SoC can only be instantiated from a board */

dc->user_creatable = false;

- sc->name = "ast2600-a3";

sc->valid_cpu_types = valid_cpu_types;

sc->silicon_rev = AST2600_A3_SILICON_REV;

sc->sram_size = 0x16400;

diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/aspeed_ast27x0.c

+++ b/hw/arm/aspeed_ast27x0.c

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_init(Object *obj)

char socname[8];

char typename[64];

- if (sscanf(sc->name, "%7s", socname) != 1) {

+ if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {

g_assert_not_reached();

}

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data)

dc->user_creatable = false;

dc->realize = aspeed_soc_ast2700_realize;

- sc->name = "ast2700-a0";

sc->valid_cpu_types = valid_cpu_types;

sc->silicon_rev = AST2700_A0_SILICON_REV;

sc->sram_size = 0x20000;

--

2.48.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Fix coding style issues from checkpatch.pl.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Reviewed-by: Cédric Le Goater <clg@redhat.com>

Link: https://lore.kernel.org/qemu-devel/20250225075622.305515-2-jamin_lin@aspeedtech.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

hw/misc/aspeed_hace.c | 12 ++++++++----

1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/aspeed_hace.c

+++ b/hw/misc/aspeed_hace.c

@@ -XXX,XX +XXX,XX @@ static const struct {

{ HASH_ALGO_SHA1, QCRYPTO_HASH_ALGO_SHA1 },

{ HASH_ALGO_SHA224, QCRYPTO_HASH_ALGO_SHA224 },

{ HASH_ALGO_SHA256, QCRYPTO_HASH_ALGO_SHA256 },

- { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA512, QCRYPTO_HASH_ALGO_SHA512 },

- { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA384, QCRYPTO_HASH_ALGO_SHA384 },

- { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA256, QCRYPTO_HASH_ALGO_SHA256 },

+ { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA512,

+ QCRYPTO_HASH_ALGO_SHA512 },

+ { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA384,

+ QCRYPTO_HASH_ALGO_SHA384 },

+ { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA256,

+ QCRYPTO_HASH_ALGO_SHA256 },

};

static int hash_algo_lookup(uint32_t reg)

@@ -XXX,XX +XXX,XX @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,

haddr = address_space_map(&s->dram_as, addr, &plen, false,

MEMTXATTRS_UNSPECIFIED);

if (haddr == NULL) {

- qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: qcrypto failed\n", __func__);

return;

}

iov[i].iov_base = haddr;

--

2.48.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Introduce a new ast2700 class to support AST2700.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>

Link: https://lore.kernel.org/qemu-devel/20250225075622.305515-3-jamin_lin@aspeedtech.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

include/hw/misc/aspeed_hace.h | 1 +

hw/misc/aspeed_hace.c | 20 ++++++++++++++++++++

2 files changed, 21 insertions(+)

diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/misc/aspeed_hace.h

+++ b/include/hw/misc/aspeed_hace.h

@@ -XXX,XX +XXX,XX @@

#define TYPE_ASPEED_AST2500_HACE TYPE_ASPEED_HACE "-ast2500"

#define TYPE_ASPEED_AST2600_HACE TYPE_ASPEED_HACE "-ast2600"

#define TYPE_ASPEED_AST1030_HACE TYPE_ASPEED_HACE "-ast1030"

+#define TYPE_ASPEED_AST2700_HACE TYPE_ASPEED_HACE "-ast2700"

OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE)

diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/aspeed_hace.c

+++ b/hw/misc/aspeed_hace.c

@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_ast1030_hace_info = {

.class_init = aspeed_ast1030_hace_class_init,

};

+static void aspeed_ast2700_hace_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+ AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass);

+

+ dc->desc = "AST2700 Hash and Crypto Engine";

+

+ ahc->src_mask = 0x7FFFFFFF;

+ ahc->dest_mask = 0x7FFFFFF8;

+ ahc->key_mask = 0x7FFFFFF8;

+ ahc->hash_mask = 0x00147FFF;

+}

+

+static const TypeInfo aspeed_ast2700_hace_info = {

+ .name = TYPE_ASPEED_AST2700_HACE,

+ .parent = TYPE_ASPEED_HACE,

+ .class_init = aspeed_ast2700_hace_class_init,

+};

+

static void aspeed_hace_register_types(void)

{

type_register_static(&aspeed_ast2400_hace_info);

type_register_static(&aspeed_ast2500_hace_info);

type_register_static(&aspeed_ast2600_hace_info);

type_register_static(&aspeed_ast1030_hace_info);

+ type_register_static(&aspeed_ast2700_hace_info);

type_register_static(&aspeed_hace_info);

}

--

2.48.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

The HACE controller between AST2600 and AST2700 are almost identical.

The HACE controller registers base address starts at 0x1207_0000 and

its alarm interrupt is connected to GICINT4.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>

Link: https://lore.kernel.org/qemu-devel/20250225075622.305515-4-jamin_lin@aspeedtech.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

hw/arm/aspeed_ast27x0.c | 15 +++++++++++++++

1 file changed, 15 insertions(+)

diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/aspeed_ast27x0.c

+++ b/hw/arm/aspeed_ast27x0.c

@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {

[ASPEED_DEV_RTC] = 0x12C0F000,

[ASPEED_DEV_SDHCI] = 0x14080000,

[ASPEED_DEV_TIMER1] = 0x12C10000,

+ [ASPEED_DEV_HACE] = 0x12070000,

};

#define AST2700_MAX_IRQ 256

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_init(Object *obj)

snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);

object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);

+

+ snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);

+ object_initialize_child(obj, "hace", &s->hace, typename);

}

/*

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)

sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);

}

+ /* HACE */

+ object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),

+ &error_abort);

+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {

+ return;

+ }

+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,

+ sc->memmap[ASPEED_DEV_HACE]);

+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,

+ aspeed_soc_get_irq(s, ASPEED_DEV_HACE));

+

create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);

create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);

create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);

--

2.48.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Currently, it does not support the CRYPT command. Instead, it only sends an

interrupt to notify the firmware that the crypt command has completed.

It is a temporary workaround to resolve the boot issue in the Crypto Manager

Self Test.

Introduce a new "use_crypt_workaround" class attribute and set it to true in

the AST2700 HACE model to enable this workaround by default for AST2700.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Reviewed-by: Cédric Le Goater <clg@redhat.com>

Link: https://lore.kernel.org/qemu-devel/20250225075622.305515-5-jamin_lin@aspeedtech.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

include/hw/misc/aspeed_hace.h | 1 +

hw/misc/aspeed_hace.c | 23 +++++++++++++++++++++++

2 files changed, 24 insertions(+)

diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/misc/aspeed_hace.h

+++ b/include/hw/misc/aspeed_hace.h

@@ -XXX,XX +XXX,XX @@ struct AspeedHACEClass {

uint32_t dest_mask;

uint32_t key_mask;

uint32_t hash_mask;

+ bool raise_crypt_interrupt_workaround;

};

#endif /* ASPEED_HACE_H */

diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/aspeed_hace.c

+++ b/hw/misc/aspeed_hace.c

@@ -XXX,XX +XXX,XX @@

/* Other cmd bits */

#define HASH_IRQ_EN BIT(9)

#define HASH_SG_EN BIT(18)

+#define CRYPT_IRQ_EN BIT(12)

/* Scatter-gather data list */

#define SG_LIST_LEN_SIZE 4

#define SG_LIST_LEN_MASK 0x0FFFFFFF

@@ -XXX,XX +XXX,XX @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,

qemu_irq_lower(s->irq);

}

}

+ if (ahc->raise_crypt_interrupt_workaround) {

+ if (data & CRYPT_IRQ) {

+ data &= ~CRYPT_IRQ;

+

+ if (s->regs[addr] & CRYPT_IRQ) {

+ qemu_irq_lower(s->irq);

+ }

+ }

+ }

break;

case R_HASH_SRC:

data &= ahc->src_mask;

@@ -XXX,XX +XXX,XX @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,

case R_CRYPT_CMD:

qemu_log_mask(LOG_UNIMP, "%s: Crypt commands not implemented\n",

__func__);

+ if (ahc->raise_crypt_interrupt_workaround) {

+ s->regs[R_STATUS] |= CRYPT_IRQ;

+ if (data & CRYPT_IRQ_EN) {

+ qemu_irq_raise(s->irq);

+ }

+ }

break;

default:

break;

@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2700_hace_class_init(ObjectClass *klass, void *data)

ahc->dest_mask = 0x7FFFFFF8;

ahc->key_mask = 0x7FFFFFF8;

ahc->hash_mask = 0x00147FFF;

+

+ /*

+ * Currently, it does not support the CRYPT command. Instead, it only

+ * sends an interrupt to notify the firmware that the crypt command

+ * has completed. It is a temporary workaround.

+ */

+ ahc->raise_crypt_interrupt_workaround = true;

}

static const TypeInfo aspeed_ast2700_hace_info = {

--

2.48.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Setting BIT6 in VGA0 SCRATCH register will indicate that the ddr traning

is done, therefore skipping the u-boot-spl dram_init() process.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>

Reviewed-by: Cédric Le Goater <clg@redhat.com>

Tested-by: Nabih Estefan <nabihestefan@google.com>

Link: https://lore.kernel.org/qemu-devel/20250304064710.2128993-2-jamin_lin@aspeedtech.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

hw/misc/aspeed_scu.c | 2 ++

1 file changed, 2 insertions(+)

diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/aspeed_scu.c

+++ b/hw/misc/aspeed_scu.c

@@ -XXX,XX +XXX,XX @@

#define AST2700_SCU_FREQ_CNTR TO_REG(0x3b0)

#define AST2700_SCU_CPU_SCRATCH_0 TO_REG(0x780)

#define AST2700_SCU_CPU_SCRATCH_1 TO_REG(0x784)

+#define AST2700_SCU_VGA_SCRATCH_0 TO_REG(0x900)

#define AST2700_SCUIO_CLK_STOP_CTL_1 TO_REG(0x240)

#define AST2700_SCUIO_CLK_STOP_CLR_1 TO_REG(0x244)

@@ -XXX,XX +XXX,XX @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {

[AST2700_SCU_FREQ_CNTR] = 0x000375eb,

[AST2700_SCU_CPU_SCRATCH_0] = 0x00000000,

[AST2700_SCU_CPU_SCRATCH_1] = 0x00000004,

+ [AST2700_SCU_VGA_SCRATCH_0] = 0x00000040,

};

static void aspeed_ast2700_scu_reset(DeviceState *dev)

--

2.48.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

According to the design of the AST2600, it has a Silicon Revision ID Register,

specifically SCU004 and SCU014, to set the Revision ID for the AST2600.

For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x05030303.

In the "aspeed_ast2600_scu_reset" function, the hardcoded value

"AST2600_A3_SILICON_REV" is set in SCU004, and "s->silicon_rev" is set in

SCU014. The value of "s->silicon_rev" is set by the SOC layer via the

"silicon-rev" property.

However, the design of the AST2700 is different. There are two SCU controllers:

SCU0 (CPU Die) and SCU1 (IO Die). In the AST2700, the firmware reads the SCU

Silicon Revision ID register (SCU0_000) and the SCUIO Silicon Revision ID

register (SCU1_000), combining them into a single 64-bit value.

The upper 32 bits represent the SCUIO, while the lower 32 bits correspond to the

SCU. For example, the AST2700-A1 revision is represented as 0x0601010306010103.

SCUIO_000 occupies bits [63:32] with a value of 0x06010103 and SCU_000 occupies

bits [31:0] with a value of 0x06010103.

Reference:

https://github.com/AspeedTech-BMC/u-boot/blob/aspeed-master-v2023.10/arch/arm/mach-aspeed/ast2700/cpu-info.c

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Tested-by: Nabih Estefan <nabihestefan@google.com>

Reviewed-by: Cédric Le Goater <clg@redhat.com>

Link: https://lore.kernel.org/qemu-devel/20250304064710.2128993-3-jamin_lin@aspeedtech.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

hw/misc/aspeed_scu.c | 3 +--

1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/aspeed_scu.c

+++ b/hw/misc/aspeed_scu.c

@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_ast2700_scu_ops = {

};

static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {

- [AST2700_SILICON_REV] = AST2700_A0_SILICON_REV,

[AST2700_HW_STRAP1] = 0x00000800,

[AST2700_HW_STRAP1_CLR] = 0xFFF0FFF0,

[AST2700_HW_STRAP1_LOCK] = 0x00000FFF,

@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)

AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);

memcpy(s->regs, asc->resets, asc->nr_regs * 4);

+ s->regs[AST2700_SILICON_REV] = s->silicon_rev;

}

static void aspeed_2700_scu_class_init(ObjectClass *klass, void *data)

@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_ast2700_scuio_ops = {

};

static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] = {

- [AST2700_SILICON_REV] = 0x06000003,

[AST2700_HW_STRAP1] = 0x00000504,

[AST2700_HW_STRAP1_CLR] = 0xFFF0FFF0,

[AST2700_HW_STRAP1_LOCK] = 0x00000FFF,

--

2.48.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

There is one hw_strap1 register in the SCU (CPU DIE) and another hw_strap1

register in the SCUIO (IO DIE).

In the "ast2700_a0_resets" function, the hardcoded value "0x00000800" is set in

SCU hw-strap1 (CPU DIE), and in "ast2700_a0_resets_io" the hardcoded value

"0x00000504" is set in SCUIO hw-strap1 (IO DIE). Both values cannot be set via

the SOC layer.

The value of "s->hw_strap1" is set by the SOC layer via the "hw-strap1" property.

Update the "aspeed_ast2700_scu_reset" function to set the value of "s->hw_strap1"

in both the SCU and SCUIO hw-strap1 registers.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Reviewed-by: Cédric Le Goater <clg@redhat.com>

Tested-by: Nabih Estefan <nabihestefan@google.com>

Link: https://lore.kernel.org/qemu-devel/20250304064710.2128993-5-jamin_lin@aspeedtech.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

hw/misc/aspeed_scu.c | 3 +--

1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/aspeed_scu.c

+++ b/hw/misc/aspeed_scu.c

@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_ast2700_scu_ops = {

};

static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {

- [AST2700_HW_STRAP1] = 0x00000800,

[AST2700_HW_STRAP1_CLR] = 0xFFF0FFF0,

[AST2700_HW_STRAP1_LOCK] = 0x00000FFF,

[AST2700_HW_STRAP1_SEC1] = 0x000000FF,

@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)

memcpy(s->regs, asc->resets, asc->nr_regs * 4);

s->regs[AST2700_SILICON_REV] = s->silicon_rev;

+ s->regs[AST2700_HW_STRAP1] = s->hw_strap1;

}

static void aspeed_2700_scu_class_init(ObjectClass *klass, void *data)

@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_ast2700_scuio_ops = {

};

static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] = {

- [AST2700_HW_STRAP1] = 0x00000504,

[AST2700_HW_STRAP1_CLR] = 0xFFF0FFF0,

[AST2700_HW_STRAP1_LOCK] = 0x00000FFF,

[AST2700_HW_STRAP1_SEC1] = 0x000000FF,

--

2.48.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

There is one hw-strap1 register in the SCU (CPU DIE) and another hw-strap1

register in the SCUIO (IO DIE). The values of these two registers should not be

the same. To reuse the current design of hw-strap, hw-strap1 is assigned to the

SCU and sets the value in the SCU hw-strap1 register, while hw-strap2 is

assigned to the SCUIO and sets the value in the SCUIO hw-strap1 register.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Tested-by: Nabih Estefan <nabihestefan@google.com>

Reviewed-by: Cédric Le Goater <clg@redhat.com>

Link: https://lore.kernel.org/qemu-devel/20250304064710.2128993-6-jamin_lin@aspeedtech.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

hw/arm/aspeed_ast27x0.c | 11 +++++++++--

1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/aspeed_ast27x0.c

+++ b/hw/arm/aspeed_ast27x0.c

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_init(Object *obj)

sc->silicon_rev);

object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),

"hw-strap1");

- object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),

- "hw-strap2");

object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),

"hw-prot-key");

object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO);

qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev",

sc->silicon_rev);

+ /*

+ * There is one hw-strap1 register in the SCU (CPU DIE) and another

+ * hw-strap1 register in the SCUIO (IO DIE). To reuse the current design

+ * of hw-strap, hw-strap1 is assigned to the SCU and sets the value in the

+ * SCU hw-strap1 register, while hw-strap2 is assigned to the SCUIO and

+ * sets the value in the SCUIO hw-strap1 register.

+ */

+ object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scuio),

+ "hw-strap1");

snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);

object_initialize_child(obj, "fmc", &s->fmc, typename);

--

2.48.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Currently, ASPEED_DEV_SPI_BOOT is set to "0x400000000", which is the DRAM start

address, and the QEMU loader is used to load the U-Boot binary into this address.

However, if users want to install FMC flash contents as a boot ROM, the DRAM

address 0x400000000 would be overwritten with Boot ROM data. This causes the

AST2700 to fail to boot because the U-Boot data becomes incorrect.

To fix this, change the ASPEED_DEV_SPI_BOOT address to "0x100000000", which is

the FMC0 memory-mapped start address in the AST2700.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Reviewed-by: Cédric Le Goater <clg@redhat.com>

Tested-by: Nabih Estefan <nabihestefan@google.com>

Link: https://lore.kernel.org/qemu-devel/20250304064710.2128993-7-jamin_lin@aspeedtech.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

hw/arm/aspeed_ast27x0.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/aspeed_ast27x0.c

+++ b/hw/arm/aspeed_ast27x0.c

@@ -XXX,XX +XXX,XX @@

#include "qemu/log.h"

static const hwaddr aspeed_soc_ast2700_memmap[] = {

- [ASPEED_DEV_SPI_BOOT] = 0x400000000,

+ [ASPEED_DEV_SPI_BOOT] = 0x100000000,

[ASPEED_DEV_SRAM] = 0x10000000,

[ASPEED_DEV_SDMC] = 0x12C00000,

[ASPEED_DEV_SCU] = 0x12C02000,

--

2.48.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

According to the AST2700 datasheet, the INTC(CPU DIE) controller has 16KB

(0x4000) of register space, and the INTCIO (I/O DIE) controller has 1KB (0x400)

of register space.

Introduced a new class attribute "mem_size" to set different memory sizes for

the INTC models in AST2700.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Reviewed-by: Cédric Le Goater <clg@redhat.com>

Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-2-jamin_lin@aspeedtech.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

include/hw/intc/aspeed_intc.h | 3 +++

hw/intc/aspeed_intc.c | 9 ++++++++-

2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/intc/aspeed_intc.h

+++ b/include/hw/intc/aspeed_intc.h

@@ -XXX,XX +XXX,XX @@ struct AspeedINTCState {

/*< public >*/

MemoryRegion iomem;

+ MemoryRegion iomem_container;

+

uint32_t regs[ASPEED_INTC_NR_REGS];

OrIRQState orgates[ASPEED_INTC_NR_INTS];

qemu_irq output_pins[ASPEED_INTC_NR_INTS];

@@ -XXX,XX +XXX,XX @@ struct AspeedINTCClass {

uint32_t num_lines;

uint32_t num_ints;

+ uint64_t mem_size;

};

#endif /* ASPEED_INTC_H */

diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/aspeed_intc.c

+++ b/hw/intc/aspeed_intc.c

@@ -XXX,XX +XXX,XX @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)

AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);

int i;

+ memory_region_init(&s->iomem_container, OBJECT(s),

+ TYPE_ASPEED_INTC ".container", aic->mem_size);

+

+ sysbus_init_mmio(sbd, &s->iomem_container);

+

memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s,

TYPE_ASPEED_INTC ".regs", ASPEED_INTC_NR_REGS << 2);

- sysbus_init_mmio(sbd, &s->iomem);

+ memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem);

+

qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_ints);

for (i = 0; i < aic->num_ints; i++) {

@@ -XXX,XX +XXX,XX @@ static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)

dc->desc = "ASPEED 2700 INTC Controller";

aic->num_lines = 32;

aic->num_ints = 9;

+ aic->mem_size = 0x4000;

}

static const TypeInfo aspeed_2700_intc_info = {

--

2.48.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Rename the variables "status_addr" to "status_reg" and "addr" to "reg" because

they are used as register index. This change makes the code more appropriate

and improves readability.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Reviewed-by: Cédric Le Goater <clg@redhat.com>

Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-3-jamin_lin@aspeedtech.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

hw/intc/aspeed_intc.c | 38 +++++++++++++++++++-------------------

1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/aspeed_intc.c

+++ b/hw/intc/aspeed_intc.c

@@ -XXX,XX +XXX,XX @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)

{

AspeedINTCState *s = (AspeedINTCState *)opaque;

AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);

- uint32_t status_addr = GICINT_STATUS_BASE + ((0x100 * irq) >> 2);

+ uint32_t status_reg = GICINT_STATUS_BASE + ((0x100 * irq) >> 2);

uint32_t select = 0;

uint32_t enable;

int i;

@@ -XXX,XX +XXX,XX @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)

trace_aspeed_intc_select(select);

- if (s->mask[irq] || s->regs[status_addr]) {

+ if (s->mask[irq] || s->regs[status_reg]) {

/*

* a. mask is not 0 means in ISR mode

* sources interrupt routine are executing.

@@ -XXX,XX +XXX,XX @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)

* notify firmware which source interrupt are coming

* by setting status register

*/

- s->regs[status_addr] = select;

- trace_aspeed_intc_trigger_irq(irq, s->regs[status_addr]);

+ s->regs[status_reg] = select;

+ trace_aspeed_intc_trigger_irq(irq, s->regs[status_reg]);

aspeed_intc_update(s, irq, 1);

}

}

@@ -XXX,XX +XXX,XX @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)

static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int size)

{

AspeedINTCState *s = ASPEED_INTC(opaque);

- uint32_t addr = offset >> 2;

+ uint32_t reg = offset >> 2;

uint32_t value = 0;

- if (addr >= ASPEED_INTC_NR_REGS) {

+ if (reg >= ASPEED_INTC_NR_REGS) {

qemu_log_mask(LOG_GUEST_ERROR,

"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",

__func__, offset);

return 0;

}

- value = s->regs[addr];

+ value = s->regs[reg];

trace_aspeed_intc_read(offset, size, value);

return value;

@@ -XXX,XX +XXX,XX @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,

{

AspeedINTCState *s = ASPEED_INTC(opaque);

AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);

- uint32_t addr = offset >> 2;

+ uint32_t reg = offset >> 2;

uint32_t old_enable;

uint32_t change;

uint32_t irq;

- if (addr >= ASPEED_INTC_NR_REGS) {

+ if (reg >= ASPEED_INTC_NR_REGS) {

qemu_log_mask(LOG_GUEST_ERROR,

"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",

__func__, offset);

@@ -XXX,XX +XXX,XX @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,

trace_aspeed_intc_write(offset, size, data);

- switch (addr) {

+ switch (reg) {

case R_GICINT128_EN:

case R_GICINT129_EN:

case R_GICINT130_EN:

@@ -XXX,XX +XXX,XX @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,

/* disable all source interrupt */

if (!data && !s->enable[irq]) {

- s->regs[addr] = data;

+ s->regs[reg] = data;