| 1 | Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code. | 1 | v2 changes: dropped the patch that enables the new 'notcg' CI test: |
|---|---|---|---|
| 2 | it doesn't pass on our aarch64 runner because the CI runner doesn't | ||
| 3 | have access to /dev/kvm. | ||
| 2 | 4 | ||
| 5 | thanks | ||
| 3 | -- PMM | 6 | -- PMM |
| 4 | 7 | ||
| 5 | The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236: | 8 | The following changes since commit 7c18f2d663521f1b31b821a13358ce38075eaf7d: |
| 6 | 9 | ||
| 7 | Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700) | 10 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-04-29 23:07:17 +0100) |
| 8 | 11 | ||
| 9 | are available in the Git repository at: | 12 | are available in the Git repository at: |
| 10 | 13 | ||
| 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230502-2 |
| 12 | 15 | ||
| 13 | for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc: | 16 | for you to fetch changes up to a4ae17e5ec512862bf73e40dfbb1e7db71f2c1e7: |
| 14 | 17 | ||
| 15 | target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100) | 18 | hw/net/allwinner-sun8i-emac: Correctly byteswap descriptor fields (2023-05-02 15:47:41 +0100) |
| 16 | 19 | ||
| 17 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
| 18 | target-arm queue: | 21 | target-arm queue: |
| 19 | * Fix KVM SVE ID register probe code | 22 | * Support building Arm targets with CONFIG_TCG=no (ie KVM only) |
| 23 | * hw/net: npcm7xx_emc: set MAC in register space | ||
| 24 | * hw/arm/bcm2835_property: Implement "get command line" message | ||
| 25 | * Deprecate the '-singlestep' command line option in favour of | ||
| 26 | '-one-insn-per-tb' and '-accel one-insn-per-tb=on' | ||
| 27 | * Deprecate 'singlestep' member of QMP StatusInfo struct | ||
| 28 | * docs/about/deprecated.rst: Add "since 7.1" tag to dtb-kaslr-seed deprecation | ||
| 29 | * hw/net/msf2-emac: Don't modify descriptor in-place in emac_store_desc() | ||
| 30 | * raspi, aspeed: Write bootloader code correctly on big-endian hosts | ||
| 31 | * hw/intc/allwinner-a10-pic: Fix bug on big-endian hosts | ||
| 32 | * Fix bug in A32 ERET on big-endian hosts that caused guest crash | ||
| 33 | * hw/sd/allwinner-sdhost: Correctly byteswap descriptor fields | ||
| 34 | * hw/net/allwinner-sun8i-emac: Correctly byteswap descriptor fields | ||
| 20 | 35 | ||
| 21 | ---------------------------------------------------------------- | 36 | ---------------------------------------------------------------- |
| 22 | Richard Henderson (3): | 37 | Claudio Fontana (1): |
| 23 | target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features | 38 | target/arm: move cpu_tcg to tcg/cpu32.c |
| 24 | target/arm: Set KVM_ARM_VCPU_SVE while probing the host | ||
| 25 | target/arm: Move sve probe inside kvm >= 4.15 branch | ||
| 26 | 39 | ||
| 27 | target/arm/kvm64.c | 45 ++++++++++++++++++++++----------------------- | 40 | Cédric Le Goater (2): |
| 28 | 1 file changed, 22 insertions(+), 23 deletions(-) | 41 | hw/arm/boot: Make write_bootloader() public as arm_write_bootloader() |
| 42 | hw/arm/aspeed: Use arm_write_bootloader() to write the bootloader | ||
| 43 | |||
| 44 | Daniel Bertalan (1): | ||
| 45 | hw/arm/bcm2835_property: Implement "get command line" message | ||
| 46 | |||
| 47 | Fabiano Rosas (11): | ||
| 48 | target/arm: Move cortex sysregs into a separate file | ||
| 49 | target/arm: Remove dead code from cpu_max_set_sve_max_vq | ||
| 50 | target/arm: Extract TCG -cpu max code into a function | ||
| 51 | target/arm: Do not expose all -cpu max features to qtests | ||
| 52 | target/arm: Move 64-bit TCG CPUs into tcg/ | ||
| 53 | tests/qtest: Adjust and document query-cpu-model-expansion test for arm | ||
| 54 | tests/qtest: Fix tests when no KVM or TCG are present | ||
| 55 | tests/avocado: Pass parameters to migration test | ||
| 56 | arm/Kconfig: Always select SEMIHOSTING when TCG is present | ||
| 57 | arm/Kconfig: Do not build TCG-only boards on a KVM-only build | ||
| 58 | tests/qtest: Restrict tpm-tis-i2c-test to CONFIG_TCG | ||
| 59 | |||
| 60 | Patrick Venture (1): | ||
| 61 | hw/net: npcm7xx_emc: set MAC in register space | ||
| 62 | |||
| 63 | Peter Maydell (18): | ||
| 64 | make one-insn-per-tb an accel option | ||
| 65 | softmmu: Don't use 'singlestep' global in QMP and HMP commands | ||
| 66 | accel/tcg: Use one_insn_per_tb global instead of old singlestep global | ||
| 67 | linux-user: Add '-one-insn-per-tb' option equivalent to '-singlestep' | ||
| 68 | bsd-user: Add '-one-insn-per-tb' option equivalent to '-singlestep' | ||
| 69 | Document that -singlestep command line option is deprecated | ||
| 70 | accel/tcg: Report one-insn-per-tb in 'info jit', not 'info status' | ||
| 71 | hmp: Add 'one-insn-per-tb' command equivalent to 'singlestep' | ||
| 72 | qapi/run-state.json: Fix missing newline at end of file | ||
| 73 | qmp: Deprecate 'singlestep' member of StatusInfo | ||
| 74 | docs/about/deprecated.rst: Add "since 7.1" tag to dtb-kaslr-seed deprecation | ||
| 75 | hw/net/msf2-emac: Don't modify descriptor in-place in emac_store_desc() | ||
| 76 | hw/arm/raspi: Use arm_write_bootloader() to write boot code | ||
| 77 | hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit() | ||
| 78 | target/arm: Define and use new load_cpu_field_low32() | ||
| 79 | target/arm: Add compile time asserts to load/store_cpu_field macros | ||
| 80 | hw/sd/allwinner-sdhost: Correctly byteswap descriptor fields | ||
| 81 | hw/net/allwinner-sun8i-emac: Correctly byteswap descriptor fields | ||
| 82 | |||
| 83 | docs/about/deprecated.rst | 43 +- | ||
| 84 | docs/user/main.rst | 14 +- | ||
| 85 | configs/devices/aarch64-softmmu/default.mak | 4 - | ||
| 86 | configs/devices/arm-softmmu/default.mak | 39 -- | ||
| 87 | qapi/run-state.json | 16 +- | ||
| 88 | accel/tcg/internal.h | 2 + | ||
| 89 | include/exec/cpu-common.h | 2 - | ||
| 90 | include/hw/arm/boot.h | 49 ++ | ||
| 91 | include/hw/misc/bcm2835_property.h | 1 + | ||
| 92 | include/monitor/hmp.h | 2 +- | ||
| 93 | target/arm/cpregs.h | 6 + | ||
| 94 | target/arm/internals.h | 10 +- | ||
| 95 | target/arm/translate-a32.h | 24 +- | ||
| 96 | accel/tcg/cpu-exec.c | 2 +- | ||
| 97 | accel/tcg/monitor.c | 14 + | ||
| 98 | accel/tcg/tcg-all.c | 23 + | ||
| 99 | bsd-user/main.c | 14 +- | ||
| 100 | hw/arm/aspeed.c | 38 +- | ||
| 101 | hw/arm/bcm2835_peripherals.c | 2 + | ||
| 102 | hw/arm/bcm2836.c | 2 + | ||
| 103 | hw/arm/boot.c | 35 +- | ||
| 104 | hw/arm/raspi.c | 66 +-- | ||
| 105 | hw/arm/virt.c | 6 +- | ||
| 106 | hw/intc/allwinner-a10-pic.c | 7 +- | ||
| 107 | hw/misc/bcm2835_property.c | 13 +- | ||
| 108 | hw/net/allwinner-sun8i-emac.c | 22 +- | ||
| 109 | hw/net/msf2-emac.c | 16 +- | ||
| 110 | hw/net/npcm7xx_emc.c | 32 +- | ||
| 111 | hw/sd/allwinner-sdhost.c | 31 +- | ||
| 112 | linux-user/main.c | 18 +- | ||
| 113 | softmmu/globals.c | 1 - | ||
| 114 | softmmu/runstate-hmp-cmds.c | 25 +- | ||
| 115 | softmmu/runstate.c | 10 +- | ||
| 116 | softmmu/vl.c | 17 +- | ||
| 117 | target/arm/cortex-regs.c | 69 +++ | ||
| 118 | target/arm/cpu64.c | 702 +-------------------------- | ||
| 119 | target/arm/{cpu_tcg.c => tcg/cpu32.c} | 72 +-- | ||
| 120 | target/arm/tcg/cpu64.c | 723 ++++++++++++++++++++++++++++ | ||
| 121 | target/arm/tcg/translate.c | 4 +- | ||
| 122 | tests/qtest/arm-cpu-features.c | 20 +- | ||
| 123 | tests/qtest/bios-tables-test.c | 11 +- | ||
| 124 | tests/qtest/boot-serial-test.c | 5 + | ||
| 125 | tests/qtest/migration-test.c | 9 +- | ||
| 126 | tests/qtest/pxe-test.c | 8 +- | ||
| 127 | tests/qtest/test-hmp.c | 1 + | ||
| 128 | tests/qtest/vmgenid-test.c | 9 +- | ||
| 129 | hmp-commands.hx | 25 +- | ||
| 130 | hw/arm/Kconfig | 43 +- | ||
| 131 | qemu-options.hx | 12 +- | ||
| 132 | target/arm/Kconfig | 7 + | ||
| 133 | target/arm/meson.build | 2 +- | ||
| 134 | target/arm/tcg/meson.build | 2 + | ||
| 135 | tcg/tci/README | 2 +- | ||
| 136 | tests/avocado/migration.py | 83 +++- | ||
| 137 | tests/qtest/meson.build | 3 +- | ||
| 138 | 55 files changed, 1438 insertions(+), 980 deletions(-) | ||
| 139 | create mode 100644 target/arm/cortex-regs.c | ||
| 140 | rename target/arm/{cpu_tcg.c => tcg/cpu32.c} (93%) | ||
| 141 | create mode 100644 target/arm/tcg/cpu64.c | ||
| 142 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Indication for support for SVE will not depend on whether we | ||
| 4 | perform the query on the main kvm_state or the temp vcpu. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-2-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 2 +- | ||
| 12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | } | ||
| 20 | } | ||
| 21 | |||
| 22 | - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; | ||
| 23 | + sve_supported = kvm_arm_sve_supported(); | ||
| 24 | |||
| 25 | /* Add feature bits that can't appear until after VCPU init. */ | ||
| 26 | if (sve_supported) { | ||
| 27 | -- | ||
| 28 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Because we weren't setting this flag, our probe of ID_AA64ZFR0 | ||
| 4 | was always returning zero. This also obviates the adjustment | ||
| 5 | of ID_AA64PFR0, which had sanitized the SVE field. | ||
| 6 | |||
| 7 | The effects of the bug are not visible, because the only thing that | ||
| 8 | ID_AA64ZFR0 is used for within qemu at present is tcg translation. | ||
| 9 | The other tests for SVE within KVM are via ID_AA64PFR0.SVE. | ||
| 10 | |||
| 11 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Message-id: 20220726045828.53697-3-richard.henderson@linaro.org | ||
| 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | --- | ||
| 17 | target/arm/kvm64.c | 27 +++++++++++++-------------- | ||
| 18 | 1 file changed, 13 insertions(+), 14 deletions(-) | ||
| 19 | |||
| 20 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/target/arm/kvm64.c | ||
| 23 | +++ b/target/arm/kvm64.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 25 | bool sve_supported; | ||
| 26 | bool pmu_supported = false; | ||
| 27 | uint64_t features = 0; | ||
| 28 | - uint64_t t; | ||
| 29 | int err; | ||
| 30 | |||
| 31 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | ||
| 32 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 33 | struct kvm_vcpu_init init = { .target = -1, }; | ||
| 34 | |||
| 35 | /* | ||
| 36 | - * Ask for Pointer Authentication if supported. We can't play the | ||
| 37 | - * SVE trick of synthesising the ID reg as KVM won't tell us | ||
| 38 | - * whether we have the architected or IMPDEF version of PAuth, so | ||
| 39 | - * we have to use the actual ID regs. | ||
| 40 | + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, | ||
| 41 | + * which is otherwise RAZ. | ||
| 42 | + */ | ||
| 43 | + sve_supported = kvm_arm_sve_supported(); | ||
| 44 | + if (sve_supported) { | ||
| 45 | + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; | ||
| 46 | + } | ||
| 47 | + | ||
| 48 | + /* | ||
| 49 | + * Ask for Pointer Authentication if supported, so that we get | ||
| 50 | + * the unsanitized field values for AA64ISAR1_EL1. | ||
| 51 | */ | ||
| 52 | if (kvm_arm_pauth_supported()) { | ||
| 53 | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | | ||
| 54 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 55 | } | ||
| 56 | } | ||
| 57 | |||
| 58 | - sve_supported = kvm_arm_sve_supported(); | ||
| 59 | - | ||
| 60 | - /* Add feature bits that can't appear until after VCPU init. */ | ||
| 61 | if (sve_supported) { | ||
| 62 | - t = ahcf->isar.id_aa64pfr0; | ||
| 63 | - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
| 64 | - ahcf->isar.id_aa64pfr0 = t; | ||
| 65 | - | ||
| 66 | /* | ||
| 67 | * There is a range of kernels between kernel commit 73433762fcae | ||
| 68 | * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 69 | * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 70 | - * SVE support, so we only read it here, rather than together with all | ||
| 71 | - * the other ID registers earlier. | ||
| 72 | + * SVE support, which resulted in an error rather than RAZ. | ||
| 73 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 74 | */ | ||
| 75 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 76 | ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 77 | -- | ||
| 78 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The test for the IF block indicates no ID registers are exposed, much | ||
| 4 | less host support for SVE. Move the SVE probe into the ELSE block. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-4-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 22 +++++++++++----------- | ||
| 12 | 1 file changed, 11 insertions(+), 11 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, | ||
| 20 | ARM64_SYS_REG(3, 3, 9, 12, 0)); | ||
| 21 | } | ||
| 22 | - } | ||
| 23 | |||
| 24 | - if (sve_supported) { | ||
| 25 | - /* | ||
| 26 | - * There is a range of kernels between kernel commit 73433762fcae | ||
| 27 | - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 28 | - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 29 | - * SVE support, which resulted in an error rather than RAZ. | ||
| 30 | - * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 31 | - */ | ||
| 32 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 33 | - ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 34 | + if (sve_supported) { | ||
| 35 | + /* | ||
| 36 | + * There is a range of kernels between kernel commit 73433762fcae | ||
| 37 | + * and f81cb2c3ad41 which have a bug where the kernel doesn't | ||
| 38 | + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has | ||
| 39 | + * enabled SVE support, which resulted in an error rather than RAZ. | ||
| 40 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 41 | + */ | ||
| 42 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 43 | + ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 44 | + } | ||
| 45 | } | ||
| 46 | |||
| 47 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
| 48 | -- | ||
| 49 | 2.25.1 | diff view generated by jsdifflib |