1 | Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code. | 1 | This pullreq is (1) my GICv4 patches (2) most of the first third of RTH's |
---|---|---|---|
2 | cleanup patchset (3) one patch fixing an smmuv3 bug... | ||
2 | 3 | ||
4 | v2 changes: fix build failure on aarch64 hosts by moving the | ||
5 | gicv3_add_its() and gicv3_foreach_its() functions to | ||
6 | arm_gicv3_its_common.h. | ||
7 | |||
8 | thanks | ||
3 | -- PMM | 9 | -- PMM |
4 | 10 | ||
5 | The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236: | ||
6 | 11 | ||
7 | Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700) | 12 | The following changes since commit a74782936dc6e979ce371dabda4b1c05624ea87f: |
13 | |||
14 | Merge tag 'pull-migration-20220421a' of https://gitlab.com/dagrh/qemu into staging (2022-04-21 18:48:18 -0700) | ||
8 | 15 | ||
9 | are available in the Git repository at: | 16 | are available in the Git repository at: |
10 | 17 | ||
11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801 | 18 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220422-1 |
12 | 19 | ||
13 | for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc: | 20 | for you to fetch changes up to c3ca7d56c4790c2223122f7e84b71161cd36dbce: |
14 | 21 | ||
15 | target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100) | 22 | hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() (2022-04-22 14:44:55 +0100) |
16 | 23 | ||
17 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
18 | target-arm queue: | 25 | target-arm queue: |
19 | * Fix KVM SVE ID register probe code | 26 | * Implement GICv4 emulation |
27 | * Some cleanup patches in target/arm | ||
28 | * hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() | ||
20 | 29 | ||
21 | ---------------------------------------------------------------- | 30 | ---------------------------------------------------------------- |
22 | Richard Henderson (3): | 31 | Peter Maydell (41): |
23 | target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features | 32 | hw/intc/arm_gicv3_its: Add missing blank line |
24 | target/arm: Set KVM_ARM_VCPU_SVE while probing the host | 33 | hw/intc/arm_gicv3: Sanity-check num-cpu property |
25 | target/arm: Move sve probe inside kvm >= 4.15 branch | 34 | hw/intc/arm_gicv3: Insist that redist region capacity matches CPU count |
35 | hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers | ||
36 | target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2 | ||
37 | hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?" | ||
38 | hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4 | ||
39 | hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTI | ||
40 | hw/intc/arm_gicv3_its: Implement VMAPP | ||
41 | hw/intc/arm_gicv3_its: Distinguish success and error cases of CMD_CONTINUE | ||
42 | hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid" | ||
43 | hw/intc/arm_gicv3_its: Factor out CTE lookup sequence | ||
44 | hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt code | ||
45 | hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd() | ||
46 | hw/intc/arm_gicv3: Keep pointers to every connected ITS | ||
47 | hw/intc/arm_gicv3_its: Implement VMOVP | ||
48 | hw/intc/arm_gicv3_its: Implement VSYNC | ||
49 | hw/intc/arm_gicv3_its: Implement INV command properly | ||
50 | hw/intc/arm_gicv3_its: Implement INV for virtual interrupts | ||
51 | hw/intc/arm_gicv3_its: Implement VMOVI | ||
52 | hw/intc/arm_gicv3_its: Implement VINVALL | ||
53 | hw/intc/arm_gicv3: Implement GICv4's new redistributor frame | ||
54 | hw/intc/arm_gicv3: Implement new GICv4 redistributor registers | ||
55 | hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update() | ||
56 | hw/intc/arm_gicv3_cpuif: Support vLPIs | ||
57 | hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarily | ||
58 | hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one LPI" logic | ||
59 | hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logic | ||
60 | hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writes | ||
61 | hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code | ||
62 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi() | ||
63 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending() | ||
64 | hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handling | ||
65 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi() | ||
66 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall() | ||
67 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi() | ||
68 | hw/intc/arm_gicv3: Update ID and feature registers for GICv4 | ||
69 | hw/intc/arm_gicv3: Allow 'revision' property to be set to 4 | ||
70 | hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic() | ||
71 | hw/arm/virt: Abstract out calculation of redistributor region capacity | ||
72 | hw/arm/virt: Support TCG GICv4 | ||
26 | 73 | ||
27 | target/arm/kvm64.c | 45 ++++++++++++++++++++++----------------------- | 74 | Richard Henderson (19): |
28 | 1 file changed, 22 insertions(+), 23 deletions(-) | 75 | target/arm: Update ISAR fields for ARMv8.8 |
76 | target/arm: Update SCR_EL3 bits to ARMv8.8 | ||
77 | target/arm: Update SCTLR bits to ARMv9.2 | ||
78 | target/arm: Change DisasContext.aarch64 to bool | ||
79 | target/arm: Change CPUArchState.aarch64 to bool | ||
80 | target/arm: Extend store_cpu_offset to take field size | ||
81 | target/arm: Change DisasContext.thumb to bool | ||
82 | target/arm: Change CPUArchState.thumb to bool | ||
83 | target/arm: Remove fpexc32_access | ||
84 | target/arm: Split out set_btype_raw | ||
85 | target/arm: Split out gen_rebuild_hflags | ||
86 | target/arm: Simplify GEN_SHIFT in translate.c | ||
87 | target/arm: Simplify gen_sar | ||
88 | target/arm: Simplify aa32 DISAS_WFI | ||
89 | target/arm: Use tcg_constant in translate-m-nocp.c | ||
90 | target/arm: Use tcg_constant in translate-neon.c | ||
91 | target/arm: Use smin/smax for do_sat_addsub_32 | ||
92 | target/arm: Use tcg_constant in translate-vfp.c | ||
93 | target/arm: Use tcg_constant_i32 in translate.h | ||
94 | |||
95 | Xiang Chen (1): | ||
96 | hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() | ||
97 | |||
98 | docs/system/arm/virt.rst | 5 +- | ||
99 | hw/intc/gicv3_internal.h | 213 +++++++- | ||
100 | include/hw/arm/virt.h | 19 +- | ||
101 | include/hw/intc/arm_gicv3_common.h | 13 + | ||
102 | include/hw/intc/arm_gicv3_its_common.h | 19 + | ||
103 | target/arm/cpu.h | 59 ++- | ||
104 | target/arm/translate-a32.h | 13 +- | ||
105 | target/arm/translate.h | 17 +- | ||
106 | hw/arm/smmuv3.c | 2 +- | ||
107 | hw/arm/virt.c | 102 +++- | ||
108 | hw/intc/arm_gicv3_common.c | 54 +- | ||
109 | hw/intc/arm_gicv3_cpuif.c | 195 ++++++-- | ||
110 | hw/intc/arm_gicv3_dist.c | 7 +- | ||
111 | hw/intc/arm_gicv3_its.c | 876 +++++++++++++++++++++++++++------ | ||
112 | hw/intc/arm_gicv3_its_kvm.c | 2 + | ||
113 | hw/intc/arm_gicv3_kvm.c | 5 + | ||
114 | hw/intc/arm_gicv3_redist.c | 480 +++++++++++++++--- | ||
115 | linux-user/arm/cpu_loop.c | 2 +- | ||
116 | target/arm/cpu.c | 16 +- | ||
117 | target/arm/helper-a64.c | 4 +- | ||
118 | target/arm/helper.c | 19 +- | ||
119 | target/arm/hvf/hvf.c | 2 +- | ||
120 | target/arm/m_helper.c | 6 +- | ||
121 | target/arm/op_helper.c | 13 - | ||
122 | target/arm/translate-a64.c | 50 +- | ||
123 | target/arm/translate-m-nocp.c | 12 +- | ||
124 | target/arm/translate-neon.c | 21 +- | ||
125 | target/arm/translate-sve.c | 9 +- | ||
126 | target/arm/translate-vfp.c | 76 +-- | ||
127 | target/arm/translate.c | 101 ++-- | ||
128 | hw/intc/trace-events | 18 +- | ||
129 | 31 files changed, 1890 insertions(+), 540 deletions(-) | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Indication for support for SVE will not depend on whether we | ||
4 | perform the query on the main kvm_state or the temp vcpu. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20220726045828.53697-2-richard.henderson@linaro.org | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/kvm64.c | 2 +- | ||
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/kvm64.c | ||
17 | +++ b/target/arm/kvm64.c | ||
18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
19 | } | ||
20 | } | ||
21 | |||
22 | - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; | ||
23 | + sve_supported = kvm_arm_sve_supported(); | ||
24 | |||
25 | /* Add feature bits that can't appear until after VCPU init. */ | ||
26 | if (sve_supported) { | ||
27 | -- | ||
28 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Because we weren't setting this flag, our probe of ID_AA64ZFR0 | ||
4 | was always returning zero. This also obviates the adjustment | ||
5 | of ID_AA64PFR0, which had sanitized the SVE field. | ||
6 | |||
7 | The effects of the bug are not visible, because the only thing that | ||
8 | ID_AA64ZFR0 is used for within qemu at present is tcg translation. | ||
9 | The other tests for SVE within KVM are via ID_AA64PFR0.SVE. | ||
10 | |||
11 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Message-id: 20220726045828.53697-3-richard.henderson@linaro.org | ||
14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | --- | ||
17 | target/arm/kvm64.c | 27 +++++++++++++-------------- | ||
18 | 1 file changed, 13 insertions(+), 14 deletions(-) | ||
19 | |||
20 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/target/arm/kvm64.c | ||
23 | +++ b/target/arm/kvm64.c | ||
24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
25 | bool sve_supported; | ||
26 | bool pmu_supported = false; | ||
27 | uint64_t features = 0; | ||
28 | - uint64_t t; | ||
29 | int err; | ||
30 | |||
31 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | ||
32 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
33 | struct kvm_vcpu_init init = { .target = -1, }; | ||
34 | |||
35 | /* | ||
36 | - * Ask for Pointer Authentication if supported. We can't play the | ||
37 | - * SVE trick of synthesising the ID reg as KVM won't tell us | ||
38 | - * whether we have the architected or IMPDEF version of PAuth, so | ||
39 | - * we have to use the actual ID regs. | ||
40 | + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, | ||
41 | + * which is otherwise RAZ. | ||
42 | + */ | ||
43 | + sve_supported = kvm_arm_sve_supported(); | ||
44 | + if (sve_supported) { | ||
45 | + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; | ||
46 | + } | ||
47 | + | ||
48 | + /* | ||
49 | + * Ask for Pointer Authentication if supported, so that we get | ||
50 | + * the unsanitized field values for AA64ISAR1_EL1. | ||
51 | */ | ||
52 | if (kvm_arm_pauth_supported()) { | ||
53 | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | | ||
54 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
55 | } | ||
56 | } | ||
57 | |||
58 | - sve_supported = kvm_arm_sve_supported(); | ||
59 | - | ||
60 | - /* Add feature bits that can't appear until after VCPU init. */ | ||
61 | if (sve_supported) { | ||
62 | - t = ahcf->isar.id_aa64pfr0; | ||
63 | - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
64 | - ahcf->isar.id_aa64pfr0 = t; | ||
65 | - | ||
66 | /* | ||
67 | * There is a range of kernels between kernel commit 73433762fcae | ||
68 | * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
69 | * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
70 | - * SVE support, so we only read it here, rather than together with all | ||
71 | - * the other ID registers earlier. | ||
72 | + * SVE support, which resulted in an error rather than RAZ. | ||
73 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
74 | */ | ||
75 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
76 | ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
77 | -- | ||
78 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | The test for the IF block indicates no ID registers are exposed, much | ||
4 | less host support for SVE. Move the SVE probe into the ELSE block. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20220726045828.53697-4-richard.henderson@linaro.org | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/kvm64.c | 22 +++++++++++----------- | ||
12 | 1 file changed, 11 insertions(+), 11 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/kvm64.c | ||
17 | +++ b/target/arm/kvm64.c | ||
18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
19 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, | ||
20 | ARM64_SYS_REG(3, 3, 9, 12, 0)); | ||
21 | } | ||
22 | - } | ||
23 | |||
24 | - if (sve_supported) { | ||
25 | - /* | ||
26 | - * There is a range of kernels between kernel commit 73433762fcae | ||
27 | - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
28 | - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
29 | - * SVE support, which resulted in an error rather than RAZ. | ||
30 | - * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
31 | - */ | ||
32 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
33 | - ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
34 | + if (sve_supported) { | ||
35 | + /* | ||
36 | + * There is a range of kernels between kernel commit 73433762fcae | ||
37 | + * and f81cb2c3ad41 which have a bug where the kernel doesn't | ||
38 | + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has | ||
39 | + * enabled SVE support, which resulted in an error rather than RAZ. | ||
40 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
41 | + */ | ||
42 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
43 | + ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
44 | + } | ||
45 | } | ||
46 | |||
47 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
48 | -- | ||
49 | 2.25.1 | diff view generated by jsdifflib |