| 1 | Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code. | 1 | v1->v2: fix up format string issues in aspeed_i3c.c |
|---|---|---|---|
| 2 | 2 | ||
| 3 | -- PMM | 3 | -- PMM |
| 4 | 4 | ||
| 5 | The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236: | 5 | The following changes since commit b10d00d8811fa4eed4862963273d7353ce310c82: |
| 6 | 6 | ||
| 7 | Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700) | 7 | Merge remote-tracking branch 'remotes/kraxel/tags/seabios-20220118-pull-request' into staging (2022-01-19 18:46:28 +0000) |
| 8 | 8 | ||
| 9 | are available in the Git repository at: | 9 | are available in the Git repository at: |
| 10 | 10 | ||
| 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801 | 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220120-1 |
| 12 | 12 | ||
| 13 | for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc: | 13 | for you to fetch changes up to b9d383ab797f54ae5fa8746117770709921dc529: |
| 14 | 14 | ||
| 15 | target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100) | 15 | hw/intc/arm_gicv3: Check for !MEMTX_OK instead of MEMTX_ERROR (2022-01-20 16:04:58 +0000) |
| 16 | 16 | ||
| 17 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
| 18 | target-arm queue: | 18 | target-arm: |
| 19 | * Fix KVM SVE ID register probe code | 19 | * hw/intc/arm_gicv3_its: Fix various minor bugs |
| 20 | * hw/arm/aspeed: Add the i3c device to the AST2600 SoC | ||
| 21 | * hw/arm: kudo: add lm75s behind bus 1 switch at 75 | ||
| 22 | * hw/arm/virt: Fix support for running guests on hosts | ||
| 23 | with restricted IPA ranges | ||
| 24 | * hw/intc/arm_gic: Allow reset of the running priority | ||
| 25 | * hw/intc/arm_gic: Implement read of GICC_IIDR | ||
| 26 | * hw/arm/virt: Support for virtio-mem-pci | ||
| 27 | * hw/arm/virt: Support CPU cluster on ARM virt machine | ||
| 28 | * docs/can: convert to restructuredText | ||
| 29 | * hw/net: Move MV88W8618 network device out of hw/arm/ directory | ||
| 30 | * hw/arm/virt: KVM: Enable PAuth when supported by the host | ||
| 20 | 31 | ||
| 21 | ---------------------------------------------------------------- | 32 | ---------------------------------------------------------------- |
| 22 | Richard Henderson (3): | 33 | Gavin Shan (2): |
| 23 | target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features | 34 | virtio-mem: Correct default THP size for ARM64 |
| 24 | target/arm: Set KVM_ARM_VCPU_SVE while probing the host | 35 | hw/arm/virt: Support for virtio-mem-pci |
| 25 | target/arm: Move sve probe inside kvm >= 4.15 branch | ||
| 26 | 36 | ||
| 27 | target/arm/kvm64.c | 45 ++++++++++++++++++++++----------------------- | 37 | Lucas Ramage (1): |
| 28 | 1 file changed, 22 insertions(+), 23 deletions(-) | 38 | docs/can: convert to restructuredText |
| 39 | |||
| 40 | Marc Zyngier (7): | ||
| 41 | hw/arm/virt: KVM: Enable PAuth when supported by the host | ||
| 42 | hw/arm/virt: Add a control for the the highmem PCIe MMIO | ||
| 43 | hw/arm/virt: Add a control for the the highmem redistributors | ||
| 44 | hw/arm/virt: Honor highmem setting when computing the memory map | ||
| 45 | hw/arm/virt: Use the PA range to compute the memory map | ||
| 46 | hw/arm/virt: Disable highmem devices that don't fit in the PA range | ||
| 47 | hw/arm/virt: Drop superfluous checks against highmem | ||
| 48 | |||
| 49 | Patrick Venture (1): | ||
| 50 | hw/arm: kudo add lm75s behind bus 1 switch at 75 | ||
| 51 | |||
| 52 | Peter Maydell (13): | ||
| 53 | hw/intc/arm_gicv3_its: Fix event ID bounds checks | ||
| 54 | hw/intc/arm_gicv3_its: Convert int ID check to num_intids convention | ||
| 55 | hw/intc/arm_gicv3_its: Fix handling of process_its_cmd() return value | ||
| 56 | hw/intc/arm_gicv3_its: Don't use data if reading command failed | ||
| 57 | hw/intc/arm_gicv3_its: Use enum for return value of process_* functions | ||
| 58 | hw/intc/arm_gicv3_its: Fix return codes in process_its_cmd() | ||
| 59 | hw/intc/arm_gicv3_its: Refactor process_its_cmd() to reduce nesting | ||
| 60 | hw/intc/arm_gicv3_its: Fix return codes in process_mapti() | ||
| 61 | hw/intc/arm_gicv3_its: Fix return codes in process_mapc() | ||
| 62 | hw/intc/arm_gicv3_its: Fix return codes in process_mapd() | ||
| 63 | hw/intc/arm_gicv3_its: Factor out "find address of table entry" code | ||
| 64 | hw/intc/arm_gicv3_its: Check indexes before use, not after | ||
| 65 | hw/intc/arm_gicv3_its: Range-check ICID before indexing into collection table | ||
| 66 | |||
| 67 | Petr Pavlu (2): | ||
| 68 | hw/intc/arm_gic: Implement read of GICC_IIDR | ||
| 69 | hw/intc/arm_gic: Allow reset of the running priority | ||
| 70 | |||
| 71 | Philippe Mathieu-Daudé (4): | ||
| 72 | hw: Move MARVELL_88W8618 Kconfig from audio/ to arm/ | ||
| 73 | hw/arm/musicpal: Fix coding style of code related to MV88W8618 device | ||
| 74 | hw/net: Move MV88W8618 network device out of hw/arm/ directory | ||
| 75 | hw/intc/arm_gicv3: Check for !MEMTX_OK instead of MEMTX_ERROR | ||
| 76 | |||
| 77 | Troy Lee (2): | ||
| 78 | hw/misc/aspeed_i3c.c: Introduce a dummy AST2600 I3C model. | ||
| 79 | hw/arm/aspeed: Add the i3c device to the AST2600 SoC | ||
| 80 | |||
| 81 | Yanan Wang (6): | ||
| 82 | hw/arm/virt: Support CPU cluster on ARM virt machine | ||
| 83 | hw/arm/virt: Support cluster level in DT cpu-map | ||
| 84 | hw/acpi/aml-build: Improve scalability of PPTT generation | ||
| 85 | tests/acpi/bios-tables-test: Allow changes to virt/PPTT file | ||
| 86 | hw/acpi/aml-build: Support cluster level in PPTT generation | ||
| 87 | tests/acpi/bios-table-test: Update expected virt/PPTT file | ||
| 88 | |||
| 89 | docs/system/arm/cpu-features.rst | 4 - | ||
| 90 | docs/system/device-emulation.rst | 1 + | ||
| 91 | docs/{can.txt => system/devices/can.rst} | 90 +++--- | ||
| 92 | include/hw/arm/aspeed_soc.h | 3 + | ||
| 93 | include/hw/arm/virt.h | 5 +- | ||
| 94 | include/hw/misc/aspeed_i3c.h | 48 +++ | ||
| 95 | include/hw/net/mv88w8618_eth.h | 12 + | ||
| 96 | target/arm/cpu.h | 1 + | ||
| 97 | hw/acpi/aml-build.c | 68 +++-- | ||
| 98 | hw/arm/aspeed_ast2600.c | 16 + | ||
| 99 | hw/arm/musicpal.c | 381 +----------------------- | ||
| 100 | hw/arm/npcm7xx_boards.c | 10 +- | ||
| 101 | hw/arm/virt-acpi-build.c | 10 +- | ||
| 102 | hw/arm/virt.c | 184 ++++++++++-- | ||
| 103 | hw/intc/arm_gic.c | 11 + | ||
| 104 | hw/intc/arm_gicv3_its.c | 492 ++++++++++++++----------------- | ||
| 105 | hw/intc/arm_gicv3_redist.c | 4 +- | ||
| 106 | hw/misc/aspeed_i3c.c | 384 ++++++++++++++++++++++++ | ||
| 107 | hw/net/mv88w8618_eth.c | 403 +++++++++++++++++++++++++ | ||
| 108 | hw/virtio/virtio-mem.c | 36 ++- | ||
| 109 | target/arm/cpu.c | 16 +- | ||
| 110 | target/arm/cpu64.c | 31 +- | ||
| 111 | target/arm/kvm64.c | 21 ++ | ||
| 112 | MAINTAINERS | 2 + | ||
| 113 | hw/arm/Kconfig | 4 + | ||
| 114 | hw/audio/Kconfig | 3 - | ||
| 115 | hw/misc/meson.build | 1 + | ||
| 116 | hw/misc/trace-events | 6 + | ||
| 117 | hw/net/meson.build | 1 + | ||
| 118 | qemu-options.hx | 10 + | ||
| 119 | tests/data/acpi/virt/PPTT | Bin 76 -> 96 bytes | ||
| 120 | 31 files changed, 1476 insertions(+), 782 deletions(-) | ||
| 121 | rename docs/{can.txt => system/devices/can.rst} (68%) | ||
| 122 | create mode 100644 include/hw/misc/aspeed_i3c.h | ||
| 123 | create mode 100644 include/hw/net/mv88w8618_eth.h | ||
| 124 | create mode 100644 hw/misc/aspeed_i3c.c | ||
| 125 | create mode 100644 hw/net/mv88w8618_eth.c | ||
| 126 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Indication for support for SVE will not depend on whether we | ||
| 4 | perform the query on the main kvm_state or the temp vcpu. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-2-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 2 +- | ||
| 12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | } | ||
| 20 | } | ||
| 21 | |||
| 22 | - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; | ||
| 23 | + sve_supported = kvm_arm_sve_supported(); | ||
| 24 | |||
| 25 | /* Add feature bits that can't appear until after VCPU init. */ | ||
| 26 | if (sve_supported) { | ||
| 27 | -- | ||
| 28 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Because we weren't setting this flag, our probe of ID_AA64ZFR0 | ||
| 4 | was always returning zero. This also obviates the adjustment | ||
| 5 | of ID_AA64PFR0, which had sanitized the SVE field. | ||
| 6 | |||
| 7 | The effects of the bug are not visible, because the only thing that | ||
| 8 | ID_AA64ZFR0 is used for within qemu at present is tcg translation. | ||
| 9 | The other tests for SVE within KVM are via ID_AA64PFR0.SVE. | ||
| 10 | |||
| 11 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Message-id: 20220726045828.53697-3-richard.henderson@linaro.org | ||
| 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | --- | ||
| 17 | target/arm/kvm64.c | 27 +++++++++++++-------------- | ||
| 18 | 1 file changed, 13 insertions(+), 14 deletions(-) | ||
| 19 | |||
| 20 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/target/arm/kvm64.c | ||
| 23 | +++ b/target/arm/kvm64.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 25 | bool sve_supported; | ||
| 26 | bool pmu_supported = false; | ||
| 27 | uint64_t features = 0; | ||
| 28 | - uint64_t t; | ||
| 29 | int err; | ||
| 30 | |||
| 31 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | ||
| 32 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 33 | struct kvm_vcpu_init init = { .target = -1, }; | ||
| 34 | |||
| 35 | /* | ||
| 36 | - * Ask for Pointer Authentication if supported. We can't play the | ||
| 37 | - * SVE trick of synthesising the ID reg as KVM won't tell us | ||
| 38 | - * whether we have the architected or IMPDEF version of PAuth, so | ||
| 39 | - * we have to use the actual ID regs. | ||
| 40 | + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, | ||
| 41 | + * which is otherwise RAZ. | ||
| 42 | + */ | ||
| 43 | + sve_supported = kvm_arm_sve_supported(); | ||
| 44 | + if (sve_supported) { | ||
| 45 | + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; | ||
| 46 | + } | ||
| 47 | + | ||
| 48 | + /* | ||
| 49 | + * Ask for Pointer Authentication if supported, so that we get | ||
| 50 | + * the unsanitized field values for AA64ISAR1_EL1. | ||
| 51 | */ | ||
| 52 | if (kvm_arm_pauth_supported()) { | ||
| 53 | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | | ||
| 54 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 55 | } | ||
| 56 | } | ||
| 57 | |||
| 58 | - sve_supported = kvm_arm_sve_supported(); | ||
| 59 | - | ||
| 60 | - /* Add feature bits that can't appear until after VCPU init. */ | ||
| 61 | if (sve_supported) { | ||
| 62 | - t = ahcf->isar.id_aa64pfr0; | ||
| 63 | - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
| 64 | - ahcf->isar.id_aa64pfr0 = t; | ||
| 65 | - | ||
| 66 | /* | ||
| 67 | * There is a range of kernels between kernel commit 73433762fcae | ||
| 68 | * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 69 | * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 70 | - * SVE support, so we only read it here, rather than together with all | ||
| 71 | - * the other ID registers earlier. | ||
| 72 | + * SVE support, which resulted in an error rather than RAZ. | ||
| 73 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 74 | */ | ||
| 75 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 76 | ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 77 | -- | ||
| 78 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The test for the IF block indicates no ID registers are exposed, much | ||
| 4 | less host support for SVE. Move the SVE probe into the ELSE block. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-4-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 22 +++++++++++----------- | ||
| 12 | 1 file changed, 11 insertions(+), 11 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, | ||
| 20 | ARM64_SYS_REG(3, 3, 9, 12, 0)); | ||
| 21 | } | ||
| 22 | - } | ||
| 23 | |||
| 24 | - if (sve_supported) { | ||
| 25 | - /* | ||
| 26 | - * There is a range of kernels between kernel commit 73433762fcae | ||
| 27 | - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 28 | - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 29 | - * SVE support, which resulted in an error rather than RAZ. | ||
| 30 | - * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 31 | - */ | ||
| 32 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 33 | - ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 34 | + if (sve_supported) { | ||
| 35 | + /* | ||
| 36 | + * There is a range of kernels between kernel commit 73433762fcae | ||
| 37 | + * and f81cb2c3ad41 which have a bug where the kernel doesn't | ||
| 38 | + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has | ||
| 39 | + * enabled SVE support, which resulted in an error rather than RAZ. | ||
| 40 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 41 | + */ | ||
| 42 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 43 | + ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 44 | + } | ||
| 45 | } | ||
| 46 | |||
| 47 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
| 48 | -- | ||
| 49 | 2.25.1 | diff view generated by jsdifflib |