| 1 | Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code. | 1 | v1->v2: fix format string nit in ITS patches (%lu used when PRIu64 needed) |
|---|---|---|---|
| 2 | 2 | ||
| 3 | -- PMM | 3 | The following changes since commit eae587e8e3694b1aceab23239493fb4c7e1a80f5: |
| 4 | 4 | ||
| 5 | The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236: | 5 | Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-13' into staging (2021-09-13 11:00:30 +0100) |
| 6 | |||
| 7 | Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700) | ||
| 8 | 6 | ||
| 9 | are available in the Git repository at: | 7 | are available in the Git repository at: |
| 10 | 8 | ||
| 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801 | 9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913-1 |
| 12 | 10 | ||
| 13 | for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc: | 11 | for you to fetch changes up to 925e3b205bb17af52ac06c7bdd9d84b27345a4e9: |
| 14 | 12 | ||
| 15 | target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100) | 13 | hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 19:36:50 +0100) |
| 16 | 14 | ||
| 17 | ---------------------------------------------------------------- | 15 | ---------------------------------------------------------------- |
| 18 | target-arm queue: | 16 | target-arm queue: |
| 19 | * Fix KVM SVE ID register probe code | 17 | * mark MPS2/MPS3 board-internal i2c buses as 'full' so that command |
| 18 | line user-created devices are not plugged into them | ||
| 19 | * Take an exception if PSTATE.IL is set | ||
| 20 | * Support an emulated ITS in the virt board | ||
| 21 | * Add support for kudo-bmc board | ||
| 22 | * Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM | ||
| 23 | * cadence_uart: Fix clock handling issues that prevented | ||
| 24 | u-boot from running | ||
| 20 | 25 | ||
| 21 | ---------------------------------------------------------------- | 26 | ---------------------------------------------------------------- |
| 22 | Richard Henderson (3): | 27 | Bin Meng (6): |
| 23 | target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features | 28 | hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase |
| 24 | target/arm: Set KVM_ARM_VCPU_SVE while probing the host | 29 | hw/char: cadence_uart: Disable transmit when input clock is disabled |
| 25 | target/arm: Move sve probe inside kvm >= 4.15 branch | 30 | hw/char: cadence_uart: Move clock/reset check to uart_can_receive() |
| 31 | hw/char: cadence_uart: Convert to memop_with_attrs() ops | ||
| 32 | hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() | ||
| 33 | hw/char: cadence_uart: Log a guest error when device is unclocked or in reset | ||
| 26 | 34 | ||
| 27 | target/arm/kvm64.c | 45 ++++++++++++++++++++++----------------------- | 35 | Chris Rauer (1): |
| 28 | 1 file changed, 22 insertions(+), 23 deletions(-) | 36 | hw/arm: Add support for kudo-bmc board. |
| 37 | |||
| 38 | Marc Zyngier (1): | ||
| 39 | hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM | ||
| 40 | |||
| 41 | Peter Maydell (5): | ||
| 42 | target/arm: Take an exception if PSTATE.IL is set | ||
| 43 | qdev: Support marking individual buses as 'full' | ||
| 44 | hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn | ||
| 45 | hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full' | ||
| 46 | hw/arm/mps2.c: Mark internal-only I2C buses as 'full' | ||
| 47 | |||
| 48 | Richard Henderson (1): | ||
| 49 | target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn | ||
| 50 | |||
| 51 | Shashi Mallela (9): | ||
| 52 | hw/intc: GICv3 ITS initial framework | ||
| 53 | hw/intc: GICv3 ITS register definitions added | ||
| 54 | hw/intc: GICv3 ITS command queue framework | ||
| 55 | hw/intc: GICv3 ITS Command processing | ||
| 56 | hw/intc: GICv3 ITS Feature enablement | ||
| 57 | hw/intc: GICv3 redistributor ITS processing | ||
| 58 | tests/data/acpi/virt: Add IORT files for ITS | ||
| 59 | hw/arm/virt: add ITS support in virt GIC | ||
| 60 | tests/data/acpi/virt: Update IORT files for ITS | ||
| 61 | |||
| 62 | docs/system/arm/nuvoton.rst | 1 + | ||
| 63 | hw/intc/gicv3_internal.h | 188 ++++- | ||
| 64 | include/hw/arm/virt.h | 2 + | ||
| 65 | include/hw/intc/arm_gicv3_common.h | 13 + | ||
| 66 | include/hw/intc/arm_gicv3_its_common.h | 32 +- | ||
| 67 | include/hw/qdev-core.h | 24 + | ||
| 68 | target/arm/cpu.h | 1 + | ||
| 69 | target/arm/kvm_arm.h | 4 +- | ||
| 70 | target/arm/syndrome.h | 5 + | ||
| 71 | target/arm/translate.h | 2 + | ||
| 72 | hw/arm/mps2-tz.c | 92 ++- | ||
| 73 | hw/arm/mps2.c | 12 +- | ||
| 74 | hw/arm/npcm7xx_boards.c | 34 + | ||
| 75 | hw/arm/virt.c | 29 +- | ||
| 76 | hw/char/cadence_uart.c | 61 +- | ||
| 77 | hw/intc/arm_gicv3.c | 14 + | ||
| 78 | hw/intc/arm_gicv3_common.c | 13 + | ||
| 79 | hw/intc/arm_gicv3_cpuif.c | 7 +- | ||
| 80 | hw/intc/arm_gicv3_dist.c | 5 +- | ||
| 81 | hw/intc/arm_gicv3_its.c | 1322 ++++++++++++++++++++++++++++++++ | ||
| 82 | hw/intc/arm_gicv3_its_common.c | 7 +- | ||
| 83 | hw/intc/arm_gicv3_its_kvm.c | 2 +- | ||
| 84 | hw/intc/arm_gicv3_redist.c | 153 +++- | ||
| 85 | hw/misc/zynq_slcr.c | 31 +- | ||
| 86 | softmmu/qdev-monitor.c | 7 +- | ||
| 87 | target/arm/helper-a64.c | 1 + | ||
| 88 | target/arm/helper.c | 8 + | ||
| 89 | target/arm/kvm.c | 7 +- | ||
| 90 | target/arm/translate-a64.c | 255 +++--- | ||
| 91 | target/arm/translate.c | 21 + | ||
| 92 | hw/intc/meson.build | 1 + | ||
| 93 | tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes | ||
| 94 | tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes | ||
| 95 | tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes | ||
| 96 | tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes | ||
| 97 | 35 files changed, 2144 insertions(+), 210 deletions(-) | ||
| 98 | create mode 100644 hw/intc/arm_gicv3_its.c | ||
| 99 | create mode 100644 tests/data/acpi/virt/IORT | ||
| 100 | create mode 100644 tests/data/acpi/virt/IORT.memhp | ||
| 101 | create mode 100644 tests/data/acpi/virt/IORT.numamem | ||
| 102 | create mode 100644 tests/data/acpi/virt/IORT.pxb | ||
| 103 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Indication for support for SVE will not depend on whether we | ||
| 4 | perform the query on the main kvm_state or the temp vcpu. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-2-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 2 +- | ||
| 12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | } | ||
| 20 | } | ||
| 21 | |||
| 22 | - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; | ||
| 23 | + sve_supported = kvm_arm_sve_supported(); | ||
| 24 | |||
| 25 | /* Add feature bits that can't appear until after VCPU init. */ | ||
| 26 | if (sve_supported) { | ||
| 27 | -- | ||
| 28 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Because we weren't setting this flag, our probe of ID_AA64ZFR0 | ||
| 4 | was always returning zero. This also obviates the adjustment | ||
| 5 | of ID_AA64PFR0, which had sanitized the SVE field. | ||
| 6 | |||
| 7 | The effects of the bug are not visible, because the only thing that | ||
| 8 | ID_AA64ZFR0 is used for within qemu at present is tcg translation. | ||
| 9 | The other tests for SVE within KVM are via ID_AA64PFR0.SVE. | ||
| 10 | |||
| 11 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Message-id: 20220726045828.53697-3-richard.henderson@linaro.org | ||
| 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | --- | ||
| 17 | target/arm/kvm64.c | 27 +++++++++++++-------------- | ||
| 18 | 1 file changed, 13 insertions(+), 14 deletions(-) | ||
| 19 | |||
| 20 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/target/arm/kvm64.c | ||
| 23 | +++ b/target/arm/kvm64.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 25 | bool sve_supported; | ||
| 26 | bool pmu_supported = false; | ||
| 27 | uint64_t features = 0; | ||
| 28 | - uint64_t t; | ||
| 29 | int err; | ||
| 30 | |||
| 31 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | ||
| 32 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 33 | struct kvm_vcpu_init init = { .target = -1, }; | ||
| 34 | |||
| 35 | /* | ||
| 36 | - * Ask for Pointer Authentication if supported. We can't play the | ||
| 37 | - * SVE trick of synthesising the ID reg as KVM won't tell us | ||
| 38 | - * whether we have the architected or IMPDEF version of PAuth, so | ||
| 39 | - * we have to use the actual ID regs. | ||
| 40 | + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, | ||
| 41 | + * which is otherwise RAZ. | ||
| 42 | + */ | ||
| 43 | + sve_supported = kvm_arm_sve_supported(); | ||
| 44 | + if (sve_supported) { | ||
| 45 | + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; | ||
| 46 | + } | ||
| 47 | + | ||
| 48 | + /* | ||
| 49 | + * Ask for Pointer Authentication if supported, so that we get | ||
| 50 | + * the unsanitized field values for AA64ISAR1_EL1. | ||
| 51 | */ | ||
| 52 | if (kvm_arm_pauth_supported()) { | ||
| 53 | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | | ||
| 54 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 55 | } | ||
| 56 | } | ||
| 57 | |||
| 58 | - sve_supported = kvm_arm_sve_supported(); | ||
| 59 | - | ||
| 60 | - /* Add feature bits that can't appear until after VCPU init. */ | ||
| 61 | if (sve_supported) { | ||
| 62 | - t = ahcf->isar.id_aa64pfr0; | ||
| 63 | - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
| 64 | - ahcf->isar.id_aa64pfr0 = t; | ||
| 65 | - | ||
| 66 | /* | ||
| 67 | * There is a range of kernels between kernel commit 73433762fcae | ||
| 68 | * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 69 | * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 70 | - * SVE support, so we only read it here, rather than together with all | ||
| 71 | - * the other ID registers earlier. | ||
| 72 | + * SVE support, which resulted in an error rather than RAZ. | ||
| 73 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 74 | */ | ||
| 75 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 76 | ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 77 | -- | ||
| 78 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The test for the IF block indicates no ID registers are exposed, much | ||
| 4 | less host support for SVE. Move the SVE probe into the ELSE block. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-4-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 22 +++++++++++----------- | ||
| 12 | 1 file changed, 11 insertions(+), 11 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, | ||
| 20 | ARM64_SYS_REG(3, 3, 9, 12, 0)); | ||
| 21 | } | ||
| 22 | - } | ||
| 23 | |||
| 24 | - if (sve_supported) { | ||
| 25 | - /* | ||
| 26 | - * There is a range of kernels between kernel commit 73433762fcae | ||
| 27 | - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 28 | - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 29 | - * SVE support, which resulted in an error rather than RAZ. | ||
| 30 | - * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 31 | - */ | ||
| 32 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 33 | - ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 34 | + if (sve_supported) { | ||
| 35 | + /* | ||
| 36 | + * There is a range of kernels between kernel commit 73433762fcae | ||
| 37 | + * and f81cb2c3ad41 which have a bug where the kernel doesn't | ||
| 38 | + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has | ||
| 39 | + * enabled SVE support, which resulted in an error rather than RAZ. | ||
| 40 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 41 | + */ | ||
| 42 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 43 | + ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 44 | + } | ||
| 45 | } | ||
| 46 | |||
| 47 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
| 48 | -- | ||
| 49 | 2.25.1 | diff view generated by jsdifflib |