[PULL 0/3] target-arm queue
[PULL v2 00/39] target-arm queue
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Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code.
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v2: fix format-string issue in a test case.
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-- PMM
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-- PMM
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The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236:
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The following changes since commit 6f34661b6c97a37a5efc27d31c037ddeda4547e2:
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Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700)
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Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pull-request' into staging (2021-03-11 18:55:27 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210314
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for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc:
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for you to fetch changes up to 6500ac13ff8e5c64ca69f5ef5d456028cfda6139:
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target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100)
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hw/display/pxa2xx: Inline template header (2021-03-14 13:14:56 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* Fix KVM SVE ID register probe code
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* versal: Support XRAMs and XRAM controller
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* smmu: Various minor bug fixes
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* SVE emulation: fix bugs handling odd vector lengths
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* allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register value
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* tests/acceptance: fix orangepi-pc acceptance tests
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* hw/timer/sse-timer: Propagate eventual error in sse_timer_realize()
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* hw/arm/virt: KVM: The IPA lower bound is 32
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* npcm7xx: support MFT module
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* pl110, pxa2xx_lcd: tidy up template headers
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (3):
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Andrew Jones (2):
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target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
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accel: kvm: Fix kvm_type invocation
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target/arm: Set KVM_ARM_VCPU_SVE while probing the host
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hw/arm/virt: KVM: The IPA lower bound is 32
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target/arm: Move sve probe inside kvm >= 4.15 branch
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target/arm/kvm64.c | 45 ++++++++++++++++++++++-----------------------
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Edgar E. Iglesias (2):
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1 file changed, 22 insertions(+), 23 deletions(-)
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hw/misc: versal: Add a model of the XRAM controller
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hw/arm: versal: Add support for the XRAMs
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Eric Auger (7):
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intel_iommu: Fix mask may be uninitialized in vtd_context_device_invalidate
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dma: Introduce dma_aligned_pow2_mask()
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virtio-iommu: Handle non power of 2 range invalidations
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hw/arm/smmu-common: Fix smmu_iotlb_inv_iova when asid is not set
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hw/arm/smmuv3: Enforce invalidation on a power of two range
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hw/arm/smmuv3: Fix SMMU_CMD_CFGI_STE_RANGE handling
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hw/arm/smmuv3: Uniformize sid traces
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Hao Wu (5):
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hw/misc: Add GPIOs for duty in NPCM7xx PWM
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hw/misc: Add NPCM7XX MFT Module
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hw/arm: Add MFT device to NPCM7xx Soc
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hw/arm: Connect PWM fans in NPCM7XX boards
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tests/qtest: Test PWM fan RPM using MFT in PWM test
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Niek Linnenbank (5):
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hw/net/allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register value
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tests/acceptance/boot_linux_console: remove Armbian 19.11.3 bionic test for orangepi-pc machine
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tests/acceptance/boot_linux_console: change URL for test_arm_orangepi_bionic_20_08
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tests/acceptance: update sunxi kernel from armbian to 5.10.16
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tests/acceptance: drop ARMBIAN_ARTIFACTS_CACHED condition for orangepi-pc, cubieboard tests
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Peter Maydell (9):
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hw/display/pl110: Remove dead code for non-32-bpp surfaces
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hw/display/pl110: Pull included-once parts of template header into pl110.c
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hw/display/pl110: Remove use of BITS from pl110_template.h
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hw/display/pxa2xx_lcd: Remove dead code for non-32-bpp surfaces
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hw/display/pxa2xx_lcd: Remove dest_width state field
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hw/display/pxa2xx: Remove use of BITS in pxa2xx_template.h
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hw/display/pxa2xx: Apply brace-related coding style fixes to template header
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hw/display/pxa2xx: Apply whitespace-only coding style fixes to template header
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hw/display/pxa2xx: Inline template header
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Philippe Mathieu-Daudé (1):
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hw/timer/sse-timer: Propagate eventual error in sse_timer_realize()
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Richard Henderson (8):
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target/arm: Fix sve_uzp_p vs odd vector lengths
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target/arm: Fix sve_zip_p vs odd vector lengths
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target/arm: Fix sve_punpk_p vs odd vector lengths
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target/arm: Update find_last_active for PREDDESC
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target/arm: Update BRKA, BRKB, BRKN for PREDDESC
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target/arm: Update CNTP for PREDDESC
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target/arm: Update WHILE for PREDDESC
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target/arm: Update sve reduction vs simd_desc
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docs/system/arm/nuvoton.rst | 2 +-
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docs/system/arm/xlnx-versal-virt.rst | 1 +
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hw/arm/smmu-internal.h | 5 +
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hw/display/pl110_template.h | 120 +-------
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hw/display/pxa2xx_template.h | 447 ---------------------------
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include/hw/arm/npcm7xx.h | 13 +-
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include/hw/arm/xlnx-versal.h | 13 +
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include/hw/boards.h | 1 +
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include/hw/misc/npcm7xx_mft.h | 70 +++++
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include/hw/misc/npcm7xx_pwm.h | 4 +-
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include/hw/misc/xlnx-versal-xramc.h | 97 ++++++
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include/sysemu/dma.h | 12 +
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target/arm/kvm_arm.h | 6 +-
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accel/kvm/kvm-all.c | 2 +
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hw/arm/npcm7xx.c | 45 ++-
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hw/arm/npcm7xx_boards.c | 99 ++++++
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hw/arm/smmu-common.c | 32 +-
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hw/arm/smmuv3.c | 58 ++--
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hw/arm/virt.c | 23 +-
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hw/arm/xlnx-versal.c | 36 +++
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hw/display/pl110.c | 123 +++++---
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hw/display/pxa2xx_lcd.c | 520 ++++++++++++++++++++++++++-----
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hw/i386/intel_iommu.c | 32 +-
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hw/misc/npcm7xx_mft.c | 540 +++++++++++++++++++++++++++++++++
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hw/misc/npcm7xx_pwm.c | 4 +
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hw/misc/xlnx-versal-xramc.c | 253 +++++++++++++++
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hw/net/allwinner-sun8i-emac.c | 62 ++--
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hw/timer/sse-timer.c | 1 +
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hw/virtio/virtio-iommu.c | 19 +-
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softmmu/dma-helpers.c | 26 ++
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target/arm/kvm.c | 4 +-
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target/arm/sve_helper.c | 107 ++++---
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target/arm/translate-sve.c | 26 +-
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tests/qtest/npcm7xx_pwm-test.c | 205 ++++++++++++-
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hw/arm/trace-events | 24 +-
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hw/misc/meson.build | 2 +
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hw/misc/trace-events | 8 +
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tests/acceptance/boot_linux_console.py | 120 +++-----
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tests/acceptance/replay_kernel.py | 10 +-
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39 files changed, 2235 insertions(+), 937 deletions(-)
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delete mode 100644 hw/display/pxa2xx_template.h
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create mode 100644 include/hw/misc/npcm7xx_mft.h
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create mode 100644 include/hw/misc/xlnx-versal-xramc.h
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create mode 100644 hw/misc/npcm7xx_mft.c
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create mode 100644 hw/misc/xlnx-versal-xramc.c
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diff view generated by jsdifflib
[PULL 1/3] target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Indication for support for SVE will not depend on whether we
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perform the query on the main kvm_state or the temp vcpu.
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-2-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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}
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}
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- sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
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+ sve_supported = kvm_arm_sve_supported();
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/* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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--
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2.25.1
diff view generated by jsdifflib
[PULL 2/3] target/arm: Set KVM_ARM_VCPU_SVE while probing the host
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Because we weren't setting this flag, our probe of ID_AA64ZFR0
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was always returning zero. This also obviates the adjustment
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of ID_AA64PFR0, which had sanitized the SVE field.
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The effects of the bug are not visible, because the only thing that
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ID_AA64ZFR0 is used for within qemu at present is tcg translation.
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The other tests for SVE within KVM are via ID_AA64PFR0.SVE.
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Reported-by: Zenghui Yu <yuzenghui@huawei.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-3-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 27 +++++++++++++--------------
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1 file changed, 13 insertions(+), 14 deletions(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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bool sve_supported;
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bool pmu_supported = false;
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uint64_t features = 0;
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- uint64_t t;
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int err;
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/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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struct kvm_vcpu_init init = { .target = -1, };
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/*
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- * Ask for Pointer Authentication if supported. We can't play the
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- * SVE trick of synthesising the ID reg as KVM won't tell us
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- * whether we have the architected or IMPDEF version of PAuth, so
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- * we have to use the actual ID regs.
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+ * Ask for SVE if supported, so that we can query ID_AA64ZFR0,
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+ * which is otherwise RAZ.
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+ */
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+ sve_supported = kvm_arm_sve_supported();
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+ if (sve_supported) {
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+ init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
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+ }
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+
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+ /*
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+ * Ask for Pointer Authentication if supported, so that we get
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+ * the unsanitized field values for AA64ISAR1_EL1.
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*/
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if (kvm_arm_pauth_supported()) {
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init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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}
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}
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- sve_supported = kvm_arm_sve_supported();
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-
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- /* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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- t = ahcf->isar.id_aa64pfr0;
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- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
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- ahcf->isar.id_aa64pfr0 = t;
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-
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/*
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* There is a range of kernels between kernel commit 73433762fcae
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* and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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* SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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- * SVE support, so we only read it here, rather than together with all
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- * the other ID registers earlier.
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+ * SVE support, which resulted in an error rather than RAZ.
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+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
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*/
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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ARM64_SYS_REG(3, 0, 0, 4, 4));
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--
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2.25.1
diff view generated by jsdifflib
[PULL 3/3] target/arm: Move sve probe inside kvm >= 4.15 branch
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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1
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The test for the IF block indicates no ID registers are exposed, much
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less host support for SVE. Move the SVE probe into the ELSE block.
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-4-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 22 +++++++++++-----------
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1 file changed, 11 insertions(+), 11 deletions(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
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ARM64_SYS_REG(3, 3, 9, 12, 0));
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}
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- }
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- if (sve_supported) {
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- /*
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- * There is a range of kernels between kernel commit 73433762fcae
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- * and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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- * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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- * SVE support, which resulted in an error rather than RAZ.
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- * So only read the register if we set KVM_ARM_VCPU_SVE above.
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- */
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- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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- ARM64_SYS_REG(3, 0, 0, 4, 4));
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+ if (sve_supported) {
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+ /*
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+ * There is a range of kernels between kernel commit 73433762fcae
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+ * and f81cb2c3ad41 which have a bug where the kernel doesn't
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+ * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
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+ * enabled SVE support, which resulted in an error rather than RAZ.
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+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
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+ */
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+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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+ ARM64_SYS_REG(3, 0, 0, 4, 4));
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+ }
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}
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kvm_arm_destroy_scratch_host_vcpu(fdarray);
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--
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2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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