| 1 | Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code. | 1 | v1->v2: fix format-string errors on 32-bit hosts in xilinx csu dma model. |
|---|---|---|---|
| 2 | 2 | ||
| 3 | -- PMM | 3 | -- PMM |
| 4 | 4 | ||
| 5 | The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236: | 5 | The following changes since commit 0436c55edf6b357ff56e2a5bf688df8636f83456: |
| 6 | 6 | ||
| 7 | Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700) | 7 | Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2021-03-08 13:51:41 +0000) |
| 8 | 8 | ||
| 9 | are available in the Git repository at: | 9 | are available in the Git repository at: |
| 10 | 10 | ||
| 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801 | 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210310 |
| 12 | 12 | ||
| 13 | for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc: | 13 | for you to fetch changes up to 81b3ddaf8772ec6f88d372e52f9b433cfa46bc46: |
| 14 | 14 | ||
| 15 | target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100) | 15 | hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt() (2021-03-10 13:54:51 +0000) |
| 16 | 16 | ||
| 17 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
| 18 | target-arm queue: | 18 | target-arm queue: |
| 19 | * Fix KVM SVE ID register probe code | 19 | * Add new mps3-an547 board |
| 20 | * target/arm: Restrict v7A TCG cpus to TCG accel | ||
| 21 | * Implement a Xilinx CSU DMA model | ||
| 22 | * hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt() | ||
| 20 | 23 | ||
| 21 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
| 22 | Richard Henderson (3): | 25 | Peter Maydell (48): |
| 23 | target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features | 26 | clock: Add ClockEvent parameter to callbacks |
| 24 | target/arm: Set KVM_ARM_VCPU_SVE while probing the host | 27 | clock: Add ClockPreUpdate callback event type |
| 25 | target/arm: Move sve probe inside kvm >= 4.15 branch | 28 | clock: Add clock_ns_to_ticks() function |
| 29 | hw/timer/npcm7xx_timer: Use new clock_ns_to_ticks() | ||
| 30 | hw/arm/armsse: Introduce SSE subsystem version property | ||
| 31 | hw/misc/iotkit-sysctl: Remove is_sse200 flag | ||
| 32 | hw/misc/iotkit-secctl.c: Implement SSE-300 PID register values | ||
| 33 | hw/misc/iotkit-sysinfo.c: Implement SSE-300 PID register values | ||
| 34 | hw/arm/armsse.c: Use correct SYS_CONFIG0 register value for SSE-300 | ||
| 35 | hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDR | ||
| 36 | hw/timer/sse-counter: Model the SSE Subsystem System Counter | ||
| 37 | hw/timer/sse-timer: Model the SSE Subsystem System Timer | ||
| 38 | hw/misc/iotkit-sysctl: Add SSE-300 cases which match SSE-200 behaviour | ||
| 39 | hw/misc/iotkit-sysctl: Handle CPU_WAIT, NMI_ENABLE for SSE-300 | ||
| 40 | hw/misc/iotkit-sysctl: Handle INITSVTOR* for SSE-300 | ||
| 41 | hw/misc/iotkit-sysctl: Implement dummy version of SSE-300 PWRCTRL register | ||
| 42 | hw/misc/iotkit-sysctl: Handle SSE-300 changes to PDCM_PD_*_SENSE registers | ||
| 43 | hw/misc/iotkit-sysctl: Implement SSE-200 and SSE-300 PID register values | ||
| 44 | hw/arm/Kconfig: Move ARMSSE_CPUID and ARMSSE_MHU stanzas to hw/misc | ||
| 45 | hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU<N>_PWRCTRL register block | ||
| 46 | hw/arm/armsse: Use an array for apb_ppc fields in the state structure | ||
| 47 | hw/arm/armsse: Add a define for number of IRQs used by the SSE itself | ||
| 48 | hw/arm/armsse: Add framework for data-driven device placement | ||
| 49 | hw/arm/armsse: Move dual-timer device into data-driven framework | ||
| 50 | hw/arm/armsse: Move watchdogs into data-driven framework | ||
| 51 | hw/arm/armsse: Move s32ktimer into data-driven framework | ||
| 52 | hw/arm/armsse: Move sysinfo register block into data-driven framework | ||
| 53 | hw/arm/armsse: Move sysctl register block into data-driven framework | ||
| 54 | hw/arm/armsse: Move PPUs into data-driven framework | ||
| 55 | hw/arm/armsse: Add missing SSE-200 SYS_PPU | ||
| 56 | hw/arm/armsse: Indirect irq_is_common[] through ARMSSEInfo | ||
| 57 | hw/arm/armsse: Add support for SSE variants with a system counter | ||
| 58 | hw/arm/armsse: Add support for TYPE_SSE_TIMER in ARMSSEDeviceInfo | ||
| 59 | hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL block | ||
| 60 | hw/arm/armsse: Add SSE-300 support | ||
| 61 | hw/arm/mps2-tz: Make UART overflow IRQ board-specific | ||
| 62 | hw/misc/mps2-fpgaio: Fold counters subsection into main vmstate | ||
| 63 | hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register | ||
| 64 | hw/misc/mps2-scc: Implement changes for AN547 | ||
| 65 | hw/arm/mps2-tz: Support running APB peripherals on different clock | ||
| 66 | hw/arm/mps2-tz: Make initsvtor0 setting board-specific | ||
| 67 | hw/arm/mps2-tz: Add new mps3-an547 board | ||
| 68 | docs/system/arm/mps2.rst: Document the new mps3-an547 board | ||
| 69 | tests/qtest/sse-timer-test: Add simple test of the SSE counter | ||
| 70 | tests/qtest/sse-timer-test: Test the system timer | ||
| 71 | tests/qtest/sse-timer-test: Test counter scaling changes | ||
| 72 | hw/timer/renesas_tmr: Prefix constants for CSS values with CSS_ | ||
| 73 | hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt() | ||
| 26 | 74 | ||
| 27 | target/arm/kvm64.c | 45 ++++++++++++++++++++++----------------------- | 75 | Philippe Mathieu-Daudé (1): |
| 28 | 1 file changed, 22 insertions(+), 23 deletions(-) | 76 | target/arm: Restrict v7A TCG cpus to TCG accel |
| 77 | |||
| 78 | Xuzhou Cheng (5): | ||
| 79 | hw/dma: Implement a Xilinx CSU DMA model | ||
| 80 | hw/arm: xlnx-zynqmp: Clean up coding convention issues | ||
| 81 | hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI | ||
| 82 | hw/ssi: xilinx_spips: Clean up coding convention issues | ||
| 83 | hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips | ||
| 84 | |||
| 85 | docs/devel/clocks.rst | 71 ++- | ||
| 86 | docs/system/arm/mps2.rst | 6 +- | ||
| 87 | include/hw/arm/armsse-version.h | 42 ++ | ||
| 88 | include/hw/arm/armsse.h | 40 +- | ||
| 89 | include/hw/arm/xlnx-zynqmp.h | 5 +- | ||
| 90 | include/hw/clock.h | 63 ++- | ||
| 91 | include/hw/dma/xlnx_csu_dma.h | 52 ++ | ||
| 92 | include/hw/misc/armsse-cpu-pwrctrl.h | 40 ++ | ||
| 93 | include/hw/misc/iotkit-secctl.h | 2 + | ||
| 94 | include/hw/misc/iotkit-sysctl.h | 13 +- | ||
| 95 | include/hw/misc/iotkit-sysinfo.h | 2 + | ||
| 96 | include/hw/misc/mps2-fpgaio.h | 2 + | ||
| 97 | include/hw/qdev-clock.h | 17 +- | ||
| 98 | include/hw/ssi/xilinx_spips.h | 2 +- | ||
| 99 | include/hw/timer/sse-counter.h | 105 ++++ | ||
| 100 | include/hw/timer/sse-timer.h | 53 ++ | ||
| 101 | hw/adc/npcm7xx_adc.c | 2 +- | ||
| 102 | hw/arm/armsse.c | 1008 +++++++++++++++++++++++++--------- | ||
| 103 | hw/arm/mps2-tz.c | 168 +++++- | ||
| 104 | hw/arm/xlnx-zynqmp.c | 21 +- | ||
| 105 | hw/char/cadence_uart.c | 4 +- | ||
| 106 | hw/char/ibex_uart.c | 4 +- | ||
| 107 | hw/char/pl011.c | 5 +- | ||
| 108 | hw/core/clock.c | 24 +- | ||
| 109 | hw/core/qdev-clock.c | 8 +- | ||
| 110 | hw/dma/xlnx_csu_dma.c | 745 +++++++++++++++++++++++++ | ||
| 111 | hw/mips/cps.c | 2 +- | ||
| 112 | hw/misc/armsse-cpu-pwrctrl.c | 149 +++++ | ||
| 113 | hw/misc/bcm2835_cprman.c | 23 +- | ||
| 114 | hw/misc/iotkit-secctl.c | 50 +- | ||
| 115 | hw/misc/iotkit-sysctl.c | 522 +++++++++++++++--- | ||
| 116 | hw/misc/iotkit-sysinfo.c | 51 +- | ||
| 117 | hw/misc/mps2-fpgaio.c | 52 +- | ||
| 118 | hw/misc/mps2-scc.c | 15 +- | ||
| 119 | hw/misc/npcm7xx_clk.c | 26 +- | ||
| 120 | hw/misc/npcm7xx_pwm.c | 2 +- | ||
| 121 | hw/misc/zynq_slcr.c | 5 +- | ||
| 122 | hw/ssi/xilinx_spips.c | 33 +- | ||
| 123 | hw/timer/cmsdk-apb-dualtimer.c | 5 +- | ||
| 124 | hw/timer/cmsdk-apb-timer.c | 4 +- | ||
| 125 | hw/timer/npcm7xx_timer.c | 6 +- | ||
| 126 | hw/timer/renesas_tmr.c | 33 +- | ||
| 127 | hw/timer/sse-counter.c | 474 ++++++++++++++++ | ||
| 128 | hw/timer/sse-timer.c | 470 ++++++++++++++++ | ||
| 129 | hw/watchdog/cmsdk-apb-watchdog.c | 5 +- | ||
| 130 | target/arm/cpu.c | 335 ----------- | ||
| 131 | target/arm/cpu_tcg.c | 318 +++++++++++ | ||
| 132 | target/mips/cpu.c | 2 +- | ||
| 133 | tests/qtest/sse-timer-test.c | 240 ++++++++ | ||
| 134 | MAINTAINERS | 7 + | ||
| 135 | hw/arm/Kconfig | 10 +- | ||
| 136 | hw/dma/Kconfig | 4 + | ||
| 137 | hw/dma/meson.build | 1 + | ||
| 138 | hw/misc/Kconfig | 9 + | ||
| 139 | hw/misc/meson.build | 1 + | ||
| 140 | hw/misc/trace-events | 4 + | ||
| 141 | hw/timer/Kconfig | 6 + | ||
| 142 | hw/timer/meson.build | 2 + | ||
| 143 | hw/timer/trace-events | 12 + | ||
| 144 | tests/qtest/meson.build | 1 + | ||
| 145 | 60 files changed, 4537 insertions(+), 846 deletions(-) | ||
| 146 | create mode 100644 include/hw/arm/armsse-version.h | ||
| 147 | create mode 100644 include/hw/dma/xlnx_csu_dma.h | ||
| 148 | create mode 100644 include/hw/misc/armsse-cpu-pwrctrl.h | ||
| 149 | create mode 100644 include/hw/timer/sse-counter.h | ||
| 150 | create mode 100644 include/hw/timer/sse-timer.h | ||
| 151 | create mode 100644 hw/dma/xlnx_csu_dma.c | ||
| 152 | create mode 100644 hw/misc/armsse-cpu-pwrctrl.c | ||
| 153 | create mode 100644 hw/timer/sse-counter.c | ||
| 154 | create mode 100644 hw/timer/sse-timer.c | ||
| 155 | create mode 100644 tests/qtest/sse-timer-test.c | ||
| 156 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Indication for support for SVE will not depend on whether we | ||
| 4 | perform the query on the main kvm_state or the temp vcpu. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-2-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 2 +- | ||
| 12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | } | ||
| 20 | } | ||
| 21 | |||
| 22 | - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; | ||
| 23 | + sve_supported = kvm_arm_sve_supported(); | ||
| 24 | |||
| 25 | /* Add feature bits that can't appear until after VCPU init. */ | ||
| 26 | if (sve_supported) { | ||
| 27 | -- | ||
| 28 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Because we weren't setting this flag, our probe of ID_AA64ZFR0 | ||
| 4 | was always returning zero. This also obviates the adjustment | ||
| 5 | of ID_AA64PFR0, which had sanitized the SVE field. | ||
| 6 | |||
| 7 | The effects of the bug are not visible, because the only thing that | ||
| 8 | ID_AA64ZFR0 is used for within qemu at present is tcg translation. | ||
| 9 | The other tests for SVE within KVM are via ID_AA64PFR0.SVE. | ||
| 10 | |||
| 11 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Message-id: 20220726045828.53697-3-richard.henderson@linaro.org | ||
| 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | --- | ||
| 17 | target/arm/kvm64.c | 27 +++++++++++++-------------- | ||
| 18 | 1 file changed, 13 insertions(+), 14 deletions(-) | ||
| 19 | |||
| 20 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/target/arm/kvm64.c | ||
| 23 | +++ b/target/arm/kvm64.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 25 | bool sve_supported; | ||
| 26 | bool pmu_supported = false; | ||
| 27 | uint64_t features = 0; | ||
| 28 | - uint64_t t; | ||
| 29 | int err; | ||
| 30 | |||
| 31 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | ||
| 32 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 33 | struct kvm_vcpu_init init = { .target = -1, }; | ||
| 34 | |||
| 35 | /* | ||
| 36 | - * Ask for Pointer Authentication if supported. We can't play the | ||
| 37 | - * SVE trick of synthesising the ID reg as KVM won't tell us | ||
| 38 | - * whether we have the architected or IMPDEF version of PAuth, so | ||
| 39 | - * we have to use the actual ID regs. | ||
| 40 | + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, | ||
| 41 | + * which is otherwise RAZ. | ||
| 42 | + */ | ||
| 43 | + sve_supported = kvm_arm_sve_supported(); | ||
| 44 | + if (sve_supported) { | ||
| 45 | + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; | ||
| 46 | + } | ||
| 47 | + | ||
| 48 | + /* | ||
| 49 | + * Ask for Pointer Authentication if supported, so that we get | ||
| 50 | + * the unsanitized field values for AA64ISAR1_EL1. | ||
| 51 | */ | ||
| 52 | if (kvm_arm_pauth_supported()) { | ||
| 53 | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | | ||
| 54 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 55 | } | ||
| 56 | } | ||
| 57 | |||
| 58 | - sve_supported = kvm_arm_sve_supported(); | ||
| 59 | - | ||
| 60 | - /* Add feature bits that can't appear until after VCPU init. */ | ||
| 61 | if (sve_supported) { | ||
| 62 | - t = ahcf->isar.id_aa64pfr0; | ||
| 63 | - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
| 64 | - ahcf->isar.id_aa64pfr0 = t; | ||
| 65 | - | ||
| 66 | /* | ||
| 67 | * There is a range of kernels between kernel commit 73433762fcae | ||
| 68 | * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 69 | * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 70 | - * SVE support, so we only read it here, rather than together with all | ||
| 71 | - * the other ID registers earlier. | ||
| 72 | + * SVE support, which resulted in an error rather than RAZ. | ||
| 73 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 74 | */ | ||
| 75 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 76 | ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 77 | -- | ||
| 78 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The test for the IF block indicates no ID registers are exposed, much | ||
| 4 | less host support for SVE. Move the SVE probe into the ELSE block. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-4-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 22 +++++++++++----------- | ||
| 12 | 1 file changed, 11 insertions(+), 11 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, | ||
| 20 | ARM64_SYS_REG(3, 3, 9, 12, 0)); | ||
| 21 | } | ||
| 22 | - } | ||
| 23 | |||
| 24 | - if (sve_supported) { | ||
| 25 | - /* | ||
| 26 | - * There is a range of kernels between kernel commit 73433762fcae | ||
| 27 | - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 28 | - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 29 | - * SVE support, which resulted in an error rather than RAZ. | ||
| 30 | - * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 31 | - */ | ||
| 32 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 33 | - ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 34 | + if (sve_supported) { | ||
| 35 | + /* | ||
| 36 | + * There is a range of kernels between kernel commit 73433762fcae | ||
| 37 | + * and f81cb2c3ad41 which have a bug where the kernel doesn't | ||
| 38 | + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has | ||
| 39 | + * enabled SVE support, which resulted in an error rather than RAZ. | ||
| 40 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 41 | + */ | ||
| 42 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 43 | + ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 44 | + } | ||
| 45 | } | ||
| 46 | |||
| 47 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
| 48 | -- | ||
| 49 | 2.25.1 | diff view generated by jsdifflib |