| 1 | Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code. | 1 | v2: don't delete is_surface_bgr() definition, the ppc patches |
|---|---|---|---|
| 2 | that drop use of it from sm501 haven't hit master yet. | ||
| 2 | 3 | ||
| 3 | -- PMM | 4 | -- PMM |
| 4 | 5 | ||
| 5 | The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236: | 6 | The following changes since commit 9a7beaad3dbba982f7a461d676b55a5c3851d312: |
| 6 | 7 | ||
| 7 | Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700) | 8 | Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210304' into staging (2021-03-05 10:47:46 +0000) |
| 8 | 9 | ||
| 9 | are available in the Git repository at: | 10 | are available in the Git repository at: |
| 10 | 11 | ||
| 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210306 |
| 12 | 13 | ||
| 13 | for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc: | 14 | for you to fetch changes up to d2d837d68f7c493e4bc306a237d7f72db88a0201: |
| 14 | 15 | ||
| 15 | target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100) | 16 | hw/arm/mps2: Update old infocenter.arm.com URLs (2021-03-06 13:30:40 +0000) |
| 16 | 17 | ||
| 17 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
| 18 | target-arm queue: | 19 | * sbsa-ref: remove cortex-a53 from list of supported cpus |
| 19 | * Fix KVM SVE ID register probe code | 20 | * sbsa-ref: add 'max' to list of allowed cpus |
| 21 | * target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe | ||
| 22 | * npcm7xx: add EMC model | ||
| 23 | * xlnx-zynqmp: Remove obsolete 'has_rpu' property | ||
| 24 | * target/arm: Speed up aarch64 TBL/TBX | ||
| 25 | * virtio-mmio: improve virtio-mmio get_dev_path alog | ||
| 26 | * target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks | ||
| 27 | * target/arm: Restrict v8M IDAU to TCG | ||
| 28 | * target/arm/cpu: Update coding style to make checkpatch.pl happy | ||
| 29 | * musicpal, tc6393xb, omap_lcdc, tcx: drop dead code for non-32-bit-RGB surfaces | ||
| 30 | * Add new board: mps3-an524 | ||
| 20 | 31 | ||
| 21 | ---------------------------------------------------------------- | 32 | ---------------------------------------------------------------- |
| 22 | Richard Henderson (3): | 33 | Doug Evans (3): |
| 23 | target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features | 34 | hw/net: Add npcm7xx emc model |
| 24 | target/arm: Set KVM_ARM_VCPU_SVE while probing the host | 35 | hw/arm: Add npcm7xx emc model |
| 25 | target/arm: Move sve probe inside kvm >= 4.15 branch | 36 | tests/qtests: Add npcm7xx emc model test |
| 26 | 37 | ||
| 27 | target/arm/kvm64.c | 45 ++++++++++++++++++++++----------------------- | 38 | Marcin Juszkiewicz (2): |
| 28 | 1 file changed, 22 insertions(+), 23 deletions(-) | 39 | sbsa-ref: remove cortex-a53 from list of supported cpus |
| 40 | sbsa-ref: add 'max' to list of allowed cpus | ||
| 41 | |||
| 42 | Peter Collingbourne (1): | ||
| 43 | target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks | ||
| 44 | |||
| 45 | Peter Maydell (34): | ||
| 46 | hw/arm/musicpal: Remove dead code for non-32-bit-RGB surfaces | ||
| 47 | hw/display/tc6393xb: Remove dead code for handling non-32bpp surfaces | ||
| 48 | hw/display/tc6393xb: Expand out macros in template header | ||
| 49 | hw/display/tc6393xb: Inline tc6393xb_draw_graphic32() at its callsite | ||
| 50 | hw/display/omap_lcdc: Expand out macros in template header | ||
| 51 | hw/display/omap_lcdc: Drop broken bigendian ifdef | ||
| 52 | hw/display/omap_lcdc: Fix coding style issues in template header | ||
| 53 | hw/display/omap_lcdc: Inline template header into C file | ||
| 54 | hw/display/omap_lcdc: Delete unnecessary macro | ||
| 55 | hw/display/tcx: Drop unnecessary code for handling BGR format outputs | ||
| 56 | hw/arm/mps2-tz: Make SYSCLK frequency board-specific | ||
| 57 | hw/misc/mps2-scc: Support configurable number of OSCCLK values | ||
| 58 | hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511 | ||
| 59 | hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board | ||
| 60 | hw/misc/mps2-fpgaio: Make number of LEDs configurable by board | ||
| 61 | hw/misc/mps2-fpgaio: Support SWITCH register | ||
| 62 | hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board | ||
| 63 | hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type | ||
| 64 | hw/arm/mps2-tz: Make number of IRQs board-specific | ||
| 65 | hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524 | ||
| 66 | hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI | ||
| 67 | hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts | ||
| 68 | hw/arm/mps2-tz: Move device IRQ info to data structures | ||
| 69 | hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs | ||
| 70 | hw/arm/mps2-tz: Allow boards to have different PPCInfo data | ||
| 71 | hw/arm/mps2-tz: Make RAM arrangement board-specific | ||
| 72 | hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data | ||
| 73 | hw/arm/mps2-tz: Support ROMs as well as RAMs | ||
| 74 | hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo | ||
| 75 | hw/arm/mps2-tz: Add new mps3-an524 board | ||
| 76 | hw/arm/mps2-tz: Stub out USB controller for mps3-an524 | ||
| 77 | hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524 | ||
| 78 | docs/system/arm/mps2.rst: Document the new mps3-an524 board | ||
| 79 | hw/arm/mps2: Update old infocenter.arm.com URLs | ||
| 80 | |||
| 81 | Philippe Mathieu-Daudé (4): | ||
| 82 | hw/arm/xlnx-zynqmp: Remove obsolete 'has_rpu' property | ||
| 83 | hw/i2c/npcm7xx_smbus: Simplify npcm7xx_smbus_init() | ||
| 84 | target/arm: Restrict v8M IDAU to TCG | ||
| 85 | target/arm/cpu: Update coding style to make checkpatch.pl happy | ||
| 86 | |||
| 87 | Rebecca Cran (3): | ||
| 88 | target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe | ||
| 89 | target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU | ||
| 90 | target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU | ||
| 91 | |||
| 92 | Richard Henderson (1): | ||
| 93 | target/arm: Speed up aarch64 TBL/TBX | ||
| 94 | |||
| 95 | schspa (1): | ||
| 96 | virtio-mmio: improve virtio-mmio get_dev_path alog | ||
| 97 | |||
| 98 | docs/system/arm/mps2.rst | 24 +- | ||
| 99 | docs/system/arm/nuvoton.rst | 3 +- | ||
| 100 | hw/display/omap_lcd_template.h | 169 -------- | ||
| 101 | hw/display/tc6393xb_template.h | 72 ---- | ||
| 102 | include/hw/arm/armsse.h | 4 +- | ||
| 103 | include/hw/arm/npcm7xx.h | 2 + | ||
| 104 | include/hw/arm/xlnx-zynqmp.h | 2 - | ||
| 105 | include/hw/misc/armsse-cpuid.h | 2 +- | ||
| 106 | include/hw/misc/armsse-mhu.h | 2 +- | ||
| 107 | include/hw/misc/iotkit-secctl.h | 2 +- | ||
| 108 | include/hw/misc/iotkit-sysctl.h | 2 +- | ||
| 109 | include/hw/misc/iotkit-sysinfo.h | 2 +- | ||
| 110 | include/hw/misc/mps2-fpgaio.h | 8 +- | ||
| 111 | include/hw/misc/mps2-scc.h | 10 +- | ||
| 112 | include/hw/net/npcm7xx_emc.h | 286 +++++++++++++ | ||
| 113 | target/arm/cpu.h | 15 +- | ||
| 114 | target/arm/helper-a64.h | 2 +- | ||
| 115 | target/arm/internals.h | 6 + | ||
| 116 | hw/arm/mps2-tz.c | 632 +++++++++++++++++++++++----- | ||
| 117 | hw/arm/mps2.c | 5 + | ||
| 118 | hw/arm/musicpal.c | 64 ++- | ||
| 119 | hw/arm/npcm7xx.c | 50 ++- | ||
| 120 | hw/arm/sbsa-ref.c | 2 +- | ||
| 121 | hw/arm/xlnx-zynqmp.c | 6 - | ||
| 122 | hw/display/omap_lcdc.c | 129 +++++- | ||
| 123 | hw/display/tc6393xb.c | 48 +-- | ||
| 124 | hw/display/tcx.c | 31 +- | ||
| 125 | hw/i2c/npcm7xx_smbus.c | 1 - | ||
| 126 | hw/misc/armsse-cpuid.c | 2 +- | ||
| 127 | hw/misc/armsse-mhu.c | 2 +- | ||
| 128 | hw/misc/iotkit-sysctl.c | 2 +- | ||
| 129 | hw/misc/iotkit-sysinfo.c | 2 +- | ||
| 130 | hw/misc/mps2-fpgaio.c | 43 +- | ||
| 131 | hw/misc/mps2-scc.c | 93 ++++- | ||
| 132 | hw/net/npcm7xx_emc.c | 857 ++++++++++++++++++++++++++++++++++++++ | ||
| 133 | hw/virtio/virtio-mmio.c | 13 +- | ||
| 134 | target/arm/cpu.c | 23 +- | ||
| 135 | target/arm/cpu64.c | 5 + | ||
| 136 | target/arm/cpu_tcg.c | 8 + | ||
| 137 | target/arm/helper-a64.c | 32 -- | ||
| 138 | target/arm/helper.c | 39 +- | ||
| 139 | target/arm/mte_helper.c | 13 +- | ||
| 140 | target/arm/translate-a64.c | 70 +--- | ||
| 141 | target/arm/vec_helper.c | 48 +++ | ||
| 142 | tests/qtest/npcm7xx_emc-test.c | 862 +++++++++++++++++++++++++++++++++++++++ | ||
| 143 | hw/net/meson.build | 1 + | ||
| 144 | hw/net/trace-events | 17 + | ||
| 145 | tests/qtest/meson.build | 3 +- | ||
| 146 | 48 files changed, 3098 insertions(+), 618 deletions(-) | ||
| 147 | delete mode 100644 hw/display/omap_lcd_template.h | ||
| 148 | delete mode 100644 hw/display/tc6393xb_template.h | ||
| 149 | create mode 100644 include/hw/net/npcm7xx_emc.h | ||
| 150 | create mode 100644 hw/net/npcm7xx_emc.c | ||
| 151 | create mode 100644 tests/qtest/npcm7xx_emc-test.c | ||
| 152 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Indication for support for SVE will not depend on whether we | ||
| 4 | perform the query on the main kvm_state or the temp vcpu. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-2-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 2 +- | ||
| 12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | } | ||
| 20 | } | ||
| 21 | |||
| 22 | - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; | ||
| 23 | + sve_supported = kvm_arm_sve_supported(); | ||
| 24 | |||
| 25 | /* Add feature bits that can't appear until after VCPU init. */ | ||
| 26 | if (sve_supported) { | ||
| 27 | -- | ||
| 28 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Because we weren't setting this flag, our probe of ID_AA64ZFR0 | ||
| 4 | was always returning zero. This also obviates the adjustment | ||
| 5 | of ID_AA64PFR0, which had sanitized the SVE field. | ||
| 6 | |||
| 7 | The effects of the bug are not visible, because the only thing that | ||
| 8 | ID_AA64ZFR0 is used for within qemu at present is tcg translation. | ||
| 9 | The other tests for SVE within KVM are via ID_AA64PFR0.SVE. | ||
| 10 | |||
| 11 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Message-id: 20220726045828.53697-3-richard.henderson@linaro.org | ||
| 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | --- | ||
| 17 | target/arm/kvm64.c | 27 +++++++++++++-------------- | ||
| 18 | 1 file changed, 13 insertions(+), 14 deletions(-) | ||
| 19 | |||
| 20 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/target/arm/kvm64.c | ||
| 23 | +++ b/target/arm/kvm64.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 25 | bool sve_supported; | ||
| 26 | bool pmu_supported = false; | ||
| 27 | uint64_t features = 0; | ||
| 28 | - uint64_t t; | ||
| 29 | int err; | ||
| 30 | |||
| 31 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | ||
| 32 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 33 | struct kvm_vcpu_init init = { .target = -1, }; | ||
| 34 | |||
| 35 | /* | ||
| 36 | - * Ask for Pointer Authentication if supported. We can't play the | ||
| 37 | - * SVE trick of synthesising the ID reg as KVM won't tell us | ||
| 38 | - * whether we have the architected or IMPDEF version of PAuth, so | ||
| 39 | - * we have to use the actual ID regs. | ||
| 40 | + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, | ||
| 41 | + * which is otherwise RAZ. | ||
| 42 | + */ | ||
| 43 | + sve_supported = kvm_arm_sve_supported(); | ||
| 44 | + if (sve_supported) { | ||
| 45 | + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; | ||
| 46 | + } | ||
| 47 | + | ||
| 48 | + /* | ||
| 49 | + * Ask for Pointer Authentication if supported, so that we get | ||
| 50 | + * the unsanitized field values for AA64ISAR1_EL1. | ||
| 51 | */ | ||
| 52 | if (kvm_arm_pauth_supported()) { | ||
| 53 | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | | ||
| 54 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 55 | } | ||
| 56 | } | ||
| 57 | |||
| 58 | - sve_supported = kvm_arm_sve_supported(); | ||
| 59 | - | ||
| 60 | - /* Add feature bits that can't appear until after VCPU init. */ | ||
| 61 | if (sve_supported) { | ||
| 62 | - t = ahcf->isar.id_aa64pfr0; | ||
| 63 | - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
| 64 | - ahcf->isar.id_aa64pfr0 = t; | ||
| 65 | - | ||
| 66 | /* | ||
| 67 | * There is a range of kernels between kernel commit 73433762fcae | ||
| 68 | * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 69 | * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 70 | - * SVE support, so we only read it here, rather than together with all | ||
| 71 | - * the other ID registers earlier. | ||
| 72 | + * SVE support, which resulted in an error rather than RAZ. | ||
| 73 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 74 | */ | ||
| 75 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 76 | ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 77 | -- | ||
| 78 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The test for the IF block indicates no ID registers are exposed, much | ||
| 4 | less host support for SVE. Move the SVE probe into the ELSE block. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-4-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 22 +++++++++++----------- | ||
| 12 | 1 file changed, 11 insertions(+), 11 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, | ||
| 20 | ARM64_SYS_REG(3, 3, 9, 12, 0)); | ||
| 21 | } | ||
| 22 | - } | ||
| 23 | |||
| 24 | - if (sve_supported) { | ||
| 25 | - /* | ||
| 26 | - * There is a range of kernels between kernel commit 73433762fcae | ||
| 27 | - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 28 | - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 29 | - * SVE support, which resulted in an error rather than RAZ. | ||
| 30 | - * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 31 | - */ | ||
| 32 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 33 | - ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 34 | + if (sve_supported) { | ||
| 35 | + /* | ||
| 36 | + * There is a range of kernels between kernel commit 73433762fcae | ||
| 37 | + * and f81cb2c3ad41 which have a bug where the kernel doesn't | ||
| 38 | + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has | ||
| 39 | + * enabled SVE support, which resulted in an error rather than RAZ. | ||
| 40 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 41 | + */ | ||
| 42 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 43 | + ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 44 | + } | ||
| 45 | } | ||
| 46 | |||
| 47 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
| 48 | -- | ||
| 49 | 2.25.1 | diff view generated by jsdifflib |