[PULL 0/3] target-arm queue
[PULL v2 00/21] target-arm queue
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Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code.
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no changes to v1, except adding the CVE identifier to one of the commit
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messages.
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-- PMM
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-- PMM
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The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236:
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The following changes since commit cf7ca7d5b9faca13f1f8e3ea92cfb2f741eb0c0e:
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Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700)
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Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/tracing-pull-request' into staging (2021-02-01 16:28:00 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210203
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for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc:
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for you to fetch changes up to fd8f71b95da86f530aae3d02a14b0ccd9e024772:
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target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100)
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hw/arm: Display CPU type in machine description (2021-02-03 10:15:51 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* Fix KVM SVE ID register probe code
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* hw/intc/arm_gic: Allow to use QTest without crashing
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* hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
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* hw/char/exynos4210_uart: Fix missing call to report ready for input
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* hw/arm/smmuv3: Fix addr_mask for range-based invalidation
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* hw/ssi/imx_spi: Fix various minor bugs
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* hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
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* hw/arm: Add missing Kconfig dependencies
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* hw/arm: Display CPU type in machine description
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (3):
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Bin Meng (5):
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target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
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hw/ssi: imx_spi: Use a macro for number of chip selects supported
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target/arm: Set KVM_ARM_VCPU_SVE while probing the host
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hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset()
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target/arm: Move sve probe inside kvm >= 4.15 branch
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hw/ssi: imx_spi: Round up the burst length to be multiple of 8
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hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic
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hw/ssi: imx_spi: Correct tx and rx fifo endianness
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target/arm/kvm64.c | 45 ++++++++++++++++++++++-----------------------
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Iris Johnson (2):
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1 file changed, 22 insertions(+), 23 deletions(-)
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hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
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hw/char/exynos4210_uart: Fix missing call to report ready for input
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Philippe Mathieu-Daudé (12):
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hw/intc/arm_gic: Allow to use QTest without crashing
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hw/ssi: imx_spi: Remove pointless variable initialization
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hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value
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hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled
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hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled
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hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
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hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ
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hw/arm/exynos4210: Add missing dependency on OR_IRQ
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hw/arm/xlnx-versal: Versal SoC requires ZDMA
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hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals
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hw/net/can: ZynqMP CAN device requires PTIMER
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hw/arm: Display CPU type in machine description
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Xuzhou Cheng (1):
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hw/ssi: imx_spi: Disable chip selects when controller is disabled
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Zenghui Yu (1):
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hw/arm/smmuv3: Fix addr_mask for range-based invalidation
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include/hw/ssi/imx_spi.h | 5 +-
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hw/arm/digic_boards.c | 2 +-
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hw/arm/microbit.c | 2 +-
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hw/arm/netduino2.c | 2 +-
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hw/arm/netduinoplus2.c | 2 +-
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hw/arm/orangepi.c | 2 +-
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hw/arm/smmuv3.c | 4 +-
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hw/arm/stellaris.c | 4 +-
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hw/char/exynos4210_uart.c | 7 ++-
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hw/intc/arm_gic.c | 5 +-
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hw/ssi/imx_spi.c | 153 +++++++++++++++++++++++++++++-----------------
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hw/Kconfig | 1 +
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hw/arm/Kconfig | 5 ++
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hw/dma/Kconfig | 3 +
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hw/dma/meson.build | 2 +-
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15 files changed, 130 insertions(+), 69 deletions(-)
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diff view generated by jsdifflib
[PULL 1/3] target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Indication for support for SVE will not depend on whether we
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perform the query on the main kvm_state or the temp vcpu.
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-2-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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}
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}
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- sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
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+ sve_supported = kvm_arm_sve_supported();
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/* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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--
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2.25.1
diff view generated by jsdifflib
[PULL 2/3] target/arm: Set KVM_ARM_VCPU_SVE while probing the host
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Because we weren't setting this flag, our probe of ID_AA64ZFR0
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was always returning zero. This also obviates the adjustment
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of ID_AA64PFR0, which had sanitized the SVE field.
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The effects of the bug are not visible, because the only thing that
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ID_AA64ZFR0 is used for within qemu at present is tcg translation.
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The other tests for SVE within KVM are via ID_AA64PFR0.SVE.
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Reported-by: Zenghui Yu <yuzenghui@huawei.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-3-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 27 +++++++++++++--------------
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1 file changed, 13 insertions(+), 14 deletions(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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bool sve_supported;
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bool pmu_supported = false;
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uint64_t features = 0;
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- uint64_t t;
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int err;
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/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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struct kvm_vcpu_init init = { .target = -1, };
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/*
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- * Ask for Pointer Authentication if supported. We can't play the
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- * SVE trick of synthesising the ID reg as KVM won't tell us
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- * whether we have the architected or IMPDEF version of PAuth, so
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- * we have to use the actual ID regs.
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+ * Ask for SVE if supported, so that we can query ID_AA64ZFR0,
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+ * which is otherwise RAZ.
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+ */
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+ sve_supported = kvm_arm_sve_supported();
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+ if (sve_supported) {
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+ init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
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+ }
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+
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+ /*
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+ * Ask for Pointer Authentication if supported, so that we get
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+ * the unsanitized field values for AA64ISAR1_EL1.
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*/
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if (kvm_arm_pauth_supported()) {
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init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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}
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}
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- sve_supported = kvm_arm_sve_supported();
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-
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- /* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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- t = ahcf->isar.id_aa64pfr0;
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- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
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- ahcf->isar.id_aa64pfr0 = t;
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-
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/*
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* There is a range of kernels between kernel commit 73433762fcae
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* and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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* SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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- * SVE support, so we only read it here, rather than together with all
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- * the other ID registers earlier.
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+ * SVE support, which resulted in an error rather than RAZ.
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+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
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*/
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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ARM64_SYS_REG(3, 0, 0, 4, 4));
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--
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2.25.1
diff view generated by jsdifflib
[PULL 3/3] target/arm: Move sve probe inside kvm >= 4.15 branch
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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The test for the IF block indicates no ID registers are exposed, much
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less host support for SVE. Move the SVE probe into the ELSE block.
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-4-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 22 +++++++++++-----------
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1 file changed, 11 insertions(+), 11 deletions(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
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ARM64_SYS_REG(3, 3, 9, 12, 0));
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}
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- }
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- if (sve_supported) {
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- /*
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- * There is a range of kernels between kernel commit 73433762fcae
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- * and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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- * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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- * SVE support, which resulted in an error rather than RAZ.
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- * So only read the register if we set KVM_ARM_VCPU_SVE above.
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- */
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- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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- ARM64_SYS_REG(3, 0, 0, 4, 4));
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+ if (sve_supported) {
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+ /*
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+ * There is a range of kernels between kernel commit 73433762fcae
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+ * and f81cb2c3ad41 which have a bug where the kernel doesn't
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+ * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
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+ * enabled SVE support, which resulted in an error rather than RAZ.
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+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
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+ */
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+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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+ ARM64_SYS_REG(3, 0, 0, 4, 4));
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+ }
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}
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kvm_arm_destroy_scratch_host_vcpu(fdarray);
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--
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2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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