| 1 | Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code. | 1 | v2: dropped linux-user bti series. |
|---|---|---|---|
| 2 | 2 | ||
| 3 | -- PMM | 3 | The following changes since commit 4c41341af76cfc85b5a6c0f87de4838672ab9f89: |
| 4 | 4 | ||
| 5 | The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236: | 5 | Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20201020' into staging (2020-10-20 11:20:36 +0100) |
| 6 | |||
| 7 | Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700) | ||
| 8 | 6 | ||
| 9 | are available in the Git repository at: | 7 | are available in the Git repository at: |
| 10 | 8 | ||
| 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801 | 9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201020-1 |
| 12 | 10 | ||
| 13 | for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc: | 11 | for you to fetch changes up to 8128c8e8cc9489a8387c74075974f86dc0222e7f: |
| 14 | 12 | ||
| 15 | target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100) | 13 | target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension (2020-10-20 16:12:01 +0100) |
| 16 | 14 | ||
| 17 | ---------------------------------------------------------------- | 15 | ---------------------------------------------------------------- |
| 18 | target-arm queue: | 16 | target-arm queue: |
| 19 | * Fix KVM SVE ID register probe code | 17 | * Fix AArch32 SMLAD incorrect setting of Q bit |
| 18 | * AArch32 VCVT fixed-point to float is always round-to-nearest | ||
| 19 | * strongarm: Fix 'time to transmit a char' unit comment | ||
| 20 | * Restrict APEI tables generation to the 'virt' machine | ||
| 21 | * bcm2835: minor code cleanups | ||
| 22 | * bcm2835: connect all IRQs from SYS_timer device | ||
| 23 | * correctly flush TLBs when TBI is enabled | ||
| 24 | * tests/qtest: Add npcm7xx timer test | ||
| 25 | * loads-stores.rst: add footnote that clarifies GETPC usage | ||
| 26 | * Fix reported EL for mte_check_fail | ||
| 27 | * Ignore HCR_EL2.ATA when {E2H,TGE} != 11 | ||
| 28 | * microbit_i2c: Fix coredump when dump-vmstate | ||
| 29 | * nseries: Fix loading kernel image on n8x0 machines | ||
| 30 | * Implement v8.1M low-overhead-loops | ||
| 20 | 31 | ||
| 21 | ---------------------------------------------------------------- | 32 | ---------------------------------------------------------------- |
| 22 | Richard Henderson (3): | 33 | Emanuele Giuseppe Esposito (1): |
| 23 | target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features | 34 | loads-stores.rst: add footnote that clarifies GETPC usage |
| 24 | target/arm: Set KVM_ARM_VCPU_SVE while probing the host | ||
| 25 | target/arm: Move sve probe inside kvm >= 4.15 branch | ||
| 26 | 35 | ||
| 27 | target/arm/kvm64.c | 45 ++++++++++++++++++++++----------------------- | 36 | Havard Skinnemoen (1): |
| 28 | 1 file changed, 22 insertions(+), 23 deletions(-) | 37 | tests/qtest: Add npcm7xx timer test |
| 38 | |||
| 39 | Peng Liang (1): | ||
| 40 | microbit_i2c: Fix coredump when dump-vmstate | ||
| 41 | |||
| 42 | Peter Maydell (12): | ||
| 43 | target/arm: Fix SMLAD incorrect setting of Q bit | ||
| 44 | target/arm: AArch32 VCVT fixed-point to float is always round-to-nearest | ||
| 45 | decodetree: Fix codegen for non-overlapping group inside overlapping group | ||
| 46 | target/arm: Implement v8.1M NOCP handling | ||
| 47 | target/arm: Implement v8.1M conditional-select insns | ||
| 48 | target/arm: Make the t32 insn[25:23]=111 group non-overlapping | ||
| 49 | target/arm: Don't allow BLX imm for M-profile | ||
| 50 | target/arm: Implement v8.1M branch-future insns (as NOPs) | ||
| 51 | target/arm: Implement v8.1M low-overhead-loop instructions | ||
| 52 | target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile | ||
| 53 | target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16 | ||
| 54 | target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension | ||
| 55 | |||
| 56 | Philippe Mathieu-Daudé (9): | ||
| 57 | hw/arm/strongarm: Fix 'time to transmit a char' unit comment | ||
| 58 | hw/arm: Restrict APEI tables generation to the 'virt' machine | ||
| 59 | hw/timer/bcm2835: Introduce BCM2835_SYSTIMER_COUNT definition | ||
| 60 | hw/timer/bcm2835: Rename variable holding CTRL_STATUS register | ||
| 61 | hw/timer/bcm2835: Support the timer COMPARE registers | ||
| 62 | hw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQs | ||
| 63 | hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers | ||
| 64 | hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers | ||
| 65 | hw/arm/nseries: Fix loading kernel image on n8x0 machines | ||
| 66 | |||
| 67 | Richard Henderson (5): | ||
| 68 | accel/tcg: Add tlb_flush_page_bits_by_mmuidx* | ||
| 69 | target/arm: Use tlb_flush_page_bits_by_mmuidx* | ||
| 70 | target/arm: Remove redundant mmu_idx lookup | ||
| 71 | target/arm: Fix reported EL for mte_check_fail | ||
| 72 | target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11 | ||
| 73 | |||
| 74 | docs/devel/loads-stores.rst | 8 +- | ||
| 75 | default-configs/devices/arm-softmmu.mak | 1 - | ||
| 76 | include/exec/exec-all.h | 36 ++ | ||
| 77 | include/hw/timer/bcm2835_systmr.h | 17 +- | ||
| 78 | target/arm/cpu.h | 8 + | ||
| 79 | target/arm/helper.h | 13 + | ||
| 80 | target/arm/internals.h | 9 +- | ||
| 81 | target/arm/m-nocp.decode | 10 +- | ||
| 82 | target/arm/t32.decode | 50 ++- | ||
| 83 | accel/tcg/cputlb.c | 275 +++++++++++++++- | ||
| 84 | hw/arm/bcm2835_peripherals.c | 13 +- | ||
| 85 | hw/arm/nseries.c | 1 + | ||
| 86 | hw/arm/strongarm.c | 2 +- | ||
| 87 | hw/i2c/microbit_i2c.c | 1 + | ||
| 88 | hw/intc/bcm2835_ic.c | 4 +- | ||
| 89 | hw/intc/bcm2836_control.c | 8 +- | ||
| 90 | hw/timer/bcm2835_systmr.c | 57 ++-- | ||
| 91 | target/arm/cpu.c | 38 ++- | ||
| 92 | target/arm/helper.c | 55 +++- | ||
| 93 | target/arm/mte_helper.c | 13 +- | ||
| 94 | target/arm/translate.c | 239 +++++++++++++- | ||
| 95 | target/arm/vfp_helper.c | 76 +++-- | ||
| 96 | tests/qtest/npcm7xx_timer-test.c | 562 ++++++++++++++++++++++++++++++++ | ||
| 97 | hw/arm/Kconfig | 1 + | ||
| 98 | hw/intc/trace-events | 4 + | ||
| 99 | hw/timer/trace-events | 6 +- | ||
| 100 | scripts/decodetree.py | 2 +- | ||
| 101 | target/arm/translate-vfp.c.inc | 41 ++- | ||
| 102 | tests/qtest/meson.build | 1 + | ||
| 103 | 29 files changed, 1404 insertions(+), 147 deletions(-) | ||
| 104 | create mode 100644 tests/qtest/npcm7xx_timer-test.c | ||
| 105 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Indication for support for SVE will not depend on whether we | ||
| 4 | perform the query on the main kvm_state or the temp vcpu. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-2-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 2 +- | ||
| 12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | } | ||
| 20 | } | ||
| 21 | |||
| 22 | - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; | ||
| 23 | + sve_supported = kvm_arm_sve_supported(); | ||
| 24 | |||
| 25 | /* Add feature bits that can't appear until after VCPU init. */ | ||
| 26 | if (sve_supported) { | ||
| 27 | -- | ||
| 28 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Because we weren't setting this flag, our probe of ID_AA64ZFR0 | ||
| 4 | was always returning zero. This also obviates the adjustment | ||
| 5 | of ID_AA64PFR0, which had sanitized the SVE field. | ||
| 6 | |||
| 7 | The effects of the bug are not visible, because the only thing that | ||
| 8 | ID_AA64ZFR0 is used for within qemu at present is tcg translation. | ||
| 9 | The other tests for SVE within KVM are via ID_AA64PFR0.SVE. | ||
| 10 | |||
| 11 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Message-id: 20220726045828.53697-3-richard.henderson@linaro.org | ||
| 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | --- | ||
| 17 | target/arm/kvm64.c | 27 +++++++++++++-------------- | ||
| 18 | 1 file changed, 13 insertions(+), 14 deletions(-) | ||
| 19 | |||
| 20 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/target/arm/kvm64.c | ||
| 23 | +++ b/target/arm/kvm64.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 25 | bool sve_supported; | ||
| 26 | bool pmu_supported = false; | ||
| 27 | uint64_t features = 0; | ||
| 28 | - uint64_t t; | ||
| 29 | int err; | ||
| 30 | |||
| 31 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | ||
| 32 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 33 | struct kvm_vcpu_init init = { .target = -1, }; | ||
| 34 | |||
| 35 | /* | ||
| 36 | - * Ask for Pointer Authentication if supported. We can't play the | ||
| 37 | - * SVE trick of synthesising the ID reg as KVM won't tell us | ||
| 38 | - * whether we have the architected or IMPDEF version of PAuth, so | ||
| 39 | - * we have to use the actual ID regs. | ||
| 40 | + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, | ||
| 41 | + * which is otherwise RAZ. | ||
| 42 | + */ | ||
| 43 | + sve_supported = kvm_arm_sve_supported(); | ||
| 44 | + if (sve_supported) { | ||
| 45 | + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; | ||
| 46 | + } | ||
| 47 | + | ||
| 48 | + /* | ||
| 49 | + * Ask for Pointer Authentication if supported, so that we get | ||
| 50 | + * the unsanitized field values for AA64ISAR1_EL1. | ||
| 51 | */ | ||
| 52 | if (kvm_arm_pauth_supported()) { | ||
| 53 | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | | ||
| 54 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 55 | } | ||
| 56 | } | ||
| 57 | |||
| 58 | - sve_supported = kvm_arm_sve_supported(); | ||
| 59 | - | ||
| 60 | - /* Add feature bits that can't appear until after VCPU init. */ | ||
| 61 | if (sve_supported) { | ||
| 62 | - t = ahcf->isar.id_aa64pfr0; | ||
| 63 | - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
| 64 | - ahcf->isar.id_aa64pfr0 = t; | ||
| 65 | - | ||
| 66 | /* | ||
| 67 | * There is a range of kernels between kernel commit 73433762fcae | ||
| 68 | * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 69 | * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 70 | - * SVE support, so we only read it here, rather than together with all | ||
| 71 | - * the other ID registers earlier. | ||
| 72 | + * SVE support, which resulted in an error rather than RAZ. | ||
| 73 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 74 | */ | ||
| 75 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 76 | ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 77 | -- | ||
| 78 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The test for the IF block indicates no ID registers are exposed, much | ||
| 4 | less host support for SVE. Move the SVE probe into the ELSE block. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-4-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 22 +++++++++++----------- | ||
| 12 | 1 file changed, 11 insertions(+), 11 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, | ||
| 20 | ARM64_SYS_REG(3, 3, 9, 12, 0)); | ||
| 21 | } | ||
| 22 | - } | ||
| 23 | |||
| 24 | - if (sve_supported) { | ||
| 25 | - /* | ||
| 26 | - * There is a range of kernels between kernel commit 73433762fcae | ||
| 27 | - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 28 | - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 29 | - * SVE support, which resulted in an error rather than RAZ. | ||
| 30 | - * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 31 | - */ | ||
| 32 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 33 | - ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 34 | + if (sve_supported) { | ||
| 35 | + /* | ||
| 36 | + * There is a range of kernels between kernel commit 73433762fcae | ||
| 37 | + * and f81cb2c3ad41 which have a bug where the kernel doesn't | ||
| 38 | + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has | ||
| 39 | + * enabled SVE support, which resulted in an error rather than RAZ. | ||
| 40 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 41 | + */ | ||
| 42 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 43 | + ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 44 | + } | ||
| 45 | } | ||
| 46 | |||
| 47 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
| 48 | -- | ||
| 49 | 2.25.1 | diff view generated by jsdifflib |