| 1 | Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code. | 1 | v2: added Property array terminator (which caused crashes on |
|---|---|---|---|
| 2 | various non-x86 host architectures). | ||
| 2 | 3 | ||
| 3 | -- PMM | 4 | The following changes since commit ae3aa5da96f4ccf0c2a28851449d92db9fcfad71: |
| 4 | 5 | ||
| 5 | The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236: | 6 | Merge remote-tracking branch 'remotes/berrange/tags/socket-next-pull-request' into staging (2020-05-21 16:47:28 +0100) |
| 6 | |||
| 7 | Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700) | ||
| 8 | 7 | ||
| 9 | are available in the Git repository at: | 8 | are available in the Git repository at: |
| 10 | 9 | ||
| 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801 | 10 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200521-1 |
| 12 | 11 | ||
| 13 | for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc: | 12 | for you to fetch changes up to fafe7229272f39500c14845bc7ea60a8504a5a20: |
| 14 | 13 | ||
| 15 | target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100) | 14 | linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 (2020-05-21 22:05:27 +0100) |
| 16 | 15 | ||
| 17 | ---------------------------------------------------------------- | 16 | ---------------------------------------------------------------- |
| 18 | target-arm queue: | 17 | target-arm queue: |
| 19 | * Fix KVM SVE ID register probe code | 18 | * tests/acceptance: Add a test for the canon-a1100 machine |
| 19 | * docs/system: Document some of the Arm development boards | ||
| 20 | * linux-user: make BKPT insn cause SIGTRAP, not be a syscall | ||
| 21 | * target/arm: Remove unused GEN_NEON_INTEGER_OP macro | ||
| 22 | * fsl-imx25, fsl-imx31, fsl-imx6, fsl-imx6ul, fsl-imx7: implement watchdog | ||
| 23 | * hw/arm: Use qemu_log_mask() instead of hw_error() in various places | ||
| 24 | * ARM: PL061: Introduce N_GPIOS | ||
| 25 | * target/arm: Improve clear_vec_high() usage | ||
| 26 | * target/arm: Allow user-mode code to write CPSR.E via MSR | ||
| 27 | * linux-user/arm: Reset CPSR_E when entering a signal handler | ||
| 28 | * linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 | ||
| 20 | 29 | ||
| 21 | ---------------------------------------------------------------- | 30 | ---------------------------------------------------------------- |
| 22 | Richard Henderson (3): | 31 | Amanieu d'Antras (1): |
| 23 | target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features | 32 | linux-user/arm: Reset CPSR_E when entering a signal handler |
| 24 | target/arm: Set KVM_ARM_VCPU_SVE while probing the host | ||
| 25 | target/arm: Move sve probe inside kvm >= 4.15 branch | ||
| 26 | 33 | ||
| 27 | target/arm/kvm64.c | 45 ++++++++++++++++++++++----------------------- | 34 | Geert Uytterhoeven (1): |
| 28 | 1 file changed, 22 insertions(+), 23 deletions(-) | 35 | ARM: PL061: Introduce N_GPIOS |
| 36 | |||
| 37 | Guenter Roeck (8): | ||
| 38 | hw: Move i.MX watchdog driver to hw/watchdog | ||
| 39 | hw/watchdog: Implement full i.MX watchdog support | ||
| 40 | hw/arm/fsl-imx25: Wire up watchdog | ||
| 41 | hw/arm/fsl-imx31: Wire up watchdog | ||
| 42 | hw/arm/fsl-imx6: Connect watchdog interrupts | ||
| 43 | hw/arm/fsl-imx6ul: Connect watchdog interrupts | ||
| 44 | hw/arm/fsl-imx7: Instantiate various unimplemented devices | ||
| 45 | hw/arm/fsl-imx7: Connect watchdog interrupts | ||
| 46 | |||
| 47 | Peter Maydell (12): | ||
| 48 | docs/system: Add 'Arm' to the Integrator/CP document title | ||
| 49 | docs/system: Sort Arm board index into alphabetical order | ||
| 50 | docs/system: Document Arm Versatile Express boards | ||
| 51 | docs/system: Document the various MPS2 models | ||
| 52 | docs/system: Document Musca boards | ||
| 53 | linux-user/arm: BKPT should cause SIGTRAP, not be a syscall | ||
| 54 | linux-user/arm: Remove bogus SVC 0xf0002 handling | ||
| 55 | linux-user/arm: Handle invalid arm-specific syscalls correctly | ||
| 56 | linux-user/arm: Fix identification of syscall numbers | ||
| 57 | target/arm: Remove unused GEN_NEON_INTEGER_OP macro | ||
| 58 | target/arm: Allow user-mode code to write CPSR.E via MSR | ||
| 59 | linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 | ||
| 60 | |||
| 61 | Philippe Mathieu-Daudé (4): | ||
| 62 | hw/arm/integratorcp: Replace hw_error() by qemu_log_mask() | ||
| 63 | hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask() | ||
| 64 | hw/char/xilinx_uartlite: Replace hw_error() by qemu_log_mask() | ||
| 65 | hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask() | ||
| 66 | |||
| 67 | Richard Henderson (2): | ||
| 68 | target/arm: Use tcg_gen_gvec_mov for clear_vec_high | ||
| 69 | target/arm: Use clear_vec_high more effectively | ||
| 70 | |||
| 71 | Thomas Huth (1): | ||
| 72 | tests/acceptance: Add a test for the canon-a1100 machine | ||
| 73 | |||
| 74 | docs/system/arm/integratorcp.rst | 4 +- | ||
| 75 | docs/system/arm/mps2.rst | 29 +++ | ||
| 76 | docs/system/arm/musca.rst | 31 +++ | ||
| 77 | docs/system/arm/vexpress.rst | 60 ++++++ | ||
| 78 | docs/system/target-arm.rst | 20 +- | ||
| 79 | include/hw/arm/fsl-imx25.h | 5 + | ||
| 80 | include/hw/arm/fsl-imx31.h | 4 + | ||
| 81 | include/hw/arm/fsl-imx6.h | 2 +- | ||
| 82 | include/hw/arm/fsl-imx6ul.h | 2 +- | ||
| 83 | include/hw/arm/fsl-imx7.h | 23 ++- | ||
| 84 | include/hw/misc/imx2_wdt.h | 33 ---- | ||
| 85 | include/hw/watchdog/wdt_imx2.h | 90 +++++++++ | ||
| 86 | target/arm/cpu.h | 2 +- | ||
| 87 | hw/arm/fsl-imx25.c | 10 + | ||
| 88 | hw/arm/fsl-imx31.c | 6 + | ||
| 89 | hw/arm/fsl-imx6.c | 9 + | ||
| 90 | hw/arm/fsl-imx6ul.c | 10 + | ||
| 91 | hw/arm/fsl-imx7.c | 35 ++++ | ||
| 92 | hw/arm/integratorcp.c | 23 ++- | ||
| 93 | hw/arm/pxa2xx_gpio.c | 7 +- | ||
| 94 | hw/char/xilinx_uartlite.c | 5 +- | ||
| 95 | hw/display/pxa2xx_lcd.c | 8 +- | ||
| 96 | hw/dma/pxa2xx_dma.c | 14 +- | ||
| 97 | hw/gpio/pl061.c | 12 +- | ||
| 98 | hw/misc/imx2_wdt.c | 90 --------- | ||
| 99 | hw/timer/exynos4210_mct.c | 12 +- | ||
| 100 | hw/watchdog/wdt_imx2.c | 304 +++++++++++++++++++++++++++++ | ||
| 101 | linux-user/arm/cpu_loop.c | 145 ++++++++------ | ||
| 102 | linux-user/arm/signal.c | 15 +- | ||
| 103 | target/arm/translate-a64.c | 63 +++--- | ||
| 104 | target/arm/translate.c | 23 --- | ||
| 105 | MAINTAINERS | 6 + | ||
| 106 | hw/arm/Kconfig | 5 + | ||
| 107 | hw/misc/Makefile.objs | 1 - | ||
| 108 | hw/watchdog/Kconfig | 3 + | ||
| 109 | hw/watchdog/Makefile.objs | 1 + | ||
| 110 | tests/acceptance/machine_arm_canona1100.py | 35 ++++ | ||
| 111 | 37 files changed, 855 insertions(+), 292 deletions(-) | ||
| 112 | create mode 100644 docs/system/arm/mps2.rst | ||
| 113 | create mode 100644 docs/system/arm/musca.rst | ||
| 114 | create mode 100644 docs/system/arm/vexpress.rst | ||
| 115 | delete mode 100644 include/hw/misc/imx2_wdt.h | ||
| 116 | create mode 100644 include/hw/watchdog/wdt_imx2.h | ||
| 117 | delete mode 100644 hw/misc/imx2_wdt.c | ||
| 118 | create mode 100644 hw/watchdog/wdt_imx2.c | ||
| 119 | create mode 100644 tests/acceptance/machine_arm_canona1100.py | ||
| 120 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Indication for support for SVE will not depend on whether we | ||
| 4 | perform the query on the main kvm_state or the temp vcpu. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-2-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 2 +- | ||
| 12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | } | ||
| 20 | } | ||
| 21 | |||
| 22 | - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; | ||
| 23 | + sve_supported = kvm_arm_sve_supported(); | ||
| 24 | |||
| 25 | /* Add feature bits that can't appear until after VCPU init. */ | ||
| 26 | if (sve_supported) { | ||
| 27 | -- | ||
| 28 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Because we weren't setting this flag, our probe of ID_AA64ZFR0 | ||
| 4 | was always returning zero. This also obviates the adjustment | ||
| 5 | of ID_AA64PFR0, which had sanitized the SVE field. | ||
| 6 | |||
| 7 | The effects of the bug are not visible, because the only thing that | ||
| 8 | ID_AA64ZFR0 is used for within qemu at present is tcg translation. | ||
| 9 | The other tests for SVE within KVM are via ID_AA64PFR0.SVE. | ||
| 10 | |||
| 11 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Message-id: 20220726045828.53697-3-richard.henderson@linaro.org | ||
| 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | --- | ||
| 17 | target/arm/kvm64.c | 27 +++++++++++++-------------- | ||
| 18 | 1 file changed, 13 insertions(+), 14 deletions(-) | ||
| 19 | |||
| 20 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/target/arm/kvm64.c | ||
| 23 | +++ b/target/arm/kvm64.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 25 | bool sve_supported; | ||
| 26 | bool pmu_supported = false; | ||
| 27 | uint64_t features = 0; | ||
| 28 | - uint64_t t; | ||
| 29 | int err; | ||
| 30 | |||
| 31 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | ||
| 32 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 33 | struct kvm_vcpu_init init = { .target = -1, }; | ||
| 34 | |||
| 35 | /* | ||
| 36 | - * Ask for Pointer Authentication if supported. We can't play the | ||
| 37 | - * SVE trick of synthesising the ID reg as KVM won't tell us | ||
| 38 | - * whether we have the architected or IMPDEF version of PAuth, so | ||
| 39 | - * we have to use the actual ID regs. | ||
| 40 | + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, | ||
| 41 | + * which is otherwise RAZ. | ||
| 42 | + */ | ||
| 43 | + sve_supported = kvm_arm_sve_supported(); | ||
| 44 | + if (sve_supported) { | ||
| 45 | + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; | ||
| 46 | + } | ||
| 47 | + | ||
| 48 | + /* | ||
| 49 | + * Ask for Pointer Authentication if supported, so that we get | ||
| 50 | + * the unsanitized field values for AA64ISAR1_EL1. | ||
| 51 | */ | ||
| 52 | if (kvm_arm_pauth_supported()) { | ||
| 53 | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | | ||
| 54 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 55 | } | ||
| 56 | } | ||
| 57 | |||
| 58 | - sve_supported = kvm_arm_sve_supported(); | ||
| 59 | - | ||
| 60 | - /* Add feature bits that can't appear until after VCPU init. */ | ||
| 61 | if (sve_supported) { | ||
| 62 | - t = ahcf->isar.id_aa64pfr0; | ||
| 63 | - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
| 64 | - ahcf->isar.id_aa64pfr0 = t; | ||
| 65 | - | ||
| 66 | /* | ||
| 67 | * There is a range of kernels between kernel commit 73433762fcae | ||
| 68 | * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 69 | * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 70 | - * SVE support, so we only read it here, rather than together with all | ||
| 71 | - * the other ID registers earlier. | ||
| 72 | + * SVE support, which resulted in an error rather than RAZ. | ||
| 73 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 74 | */ | ||
| 75 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 76 | ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 77 | -- | ||
| 78 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The test for the IF block indicates no ID registers are exposed, much | ||
| 4 | less host support for SVE. Move the SVE probe into the ELSE block. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-4-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 22 +++++++++++----------- | ||
| 12 | 1 file changed, 11 insertions(+), 11 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, | ||
| 20 | ARM64_SYS_REG(3, 3, 9, 12, 0)); | ||
| 21 | } | ||
| 22 | - } | ||
| 23 | |||
| 24 | - if (sve_supported) { | ||
| 25 | - /* | ||
| 26 | - * There is a range of kernels between kernel commit 73433762fcae | ||
| 27 | - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 28 | - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 29 | - * SVE support, which resulted in an error rather than RAZ. | ||
| 30 | - * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 31 | - */ | ||
| 32 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 33 | - ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 34 | + if (sve_supported) { | ||
| 35 | + /* | ||
| 36 | + * There is a range of kernels between kernel commit 73433762fcae | ||
| 37 | + * and f81cb2c3ad41 which have a bug where the kernel doesn't | ||
| 38 | + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has | ||
| 39 | + * enabled SVE support, which resulted in an error rather than RAZ. | ||
| 40 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 41 | + */ | ||
| 42 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 43 | + ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 44 | + } | ||
| 45 | } | ||
| 46 | |||
| 47 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
| 48 | -- | ||
| 49 | 2.25.1 | diff view generated by jsdifflib |