| 1 | Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code. | 1 | v2: |
|---|---|---|---|
| 2 | * dropped target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[] | ||
| 3 | * renamed CLOCK_SECOND to CLOCK_PERIOD_1SEC | ||
| 2 | 4 | ||
| 3 | -- PMM | ||
| 4 | 5 | ||
| 5 | The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236: | 6 | The following changes since commit 648db19685b7030aa558a4ddbd3a8e53d8c9a062: |
| 6 | 7 | ||
| 7 | Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700) | 8 | Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-04-29' into staging (2020-04-29 15:07:33 +0100) |
| 8 | 9 | ||
| 9 | are available in the Git repository at: | 10 | are available in the Git repository at: |
| 10 | 11 | ||
| 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200430-1 |
| 12 | 13 | ||
| 13 | for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc: | 14 | for you to fetch changes up to 6f7b6947a6639fff15c6a0956adf0f5ec004b789: |
| 14 | 15 | ||
| 15 | target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100) | 16 | hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes (2020-04-30 15:35:41 +0100) |
| 16 | 17 | ||
| 17 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
| 18 | target-arm queue: | 19 | target-arm queue: |
| 19 | * Fix KVM SVE ID register probe code | 20 | * xlnx-zdma: Fix endianness handling of descriptor loading |
| 21 | * nrf51: Fix last GPIO CNF address | ||
| 22 | * gicv3: Use gicr_typer in arm_gicv3_icc_reset | ||
| 23 | * msf2: Add EMAC block to SmartFusion2 SoC | ||
| 24 | * New clock modelling framework | ||
| 25 | * hw/arm: versal: Setup the ADMA with 128bit bus-width | ||
| 26 | * Cadence: gem: fix wraparound in 64bit descriptors | ||
| 27 | * cadence_gem: clear RX control descriptor | ||
| 28 | * target/arm: Vectorize integer comparison vs zero | ||
| 29 | * hw/arm/virt: dt: add kaslr-seed property | ||
| 30 | * hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes | ||
| 20 | 31 | ||
| 21 | ---------------------------------------------------------------- | 32 | ---------------------------------------------------------------- |
| 22 | Richard Henderson (3): | 33 | Cameron Esfahani (1): |
| 23 | target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features | 34 | nrf51: Fix last GPIO CNF address |
| 24 | target/arm: Set KVM_ARM_VCPU_SVE while probing the host | ||
| 25 | target/arm: Move sve probe inside kvm >= 4.15 branch | ||
| 26 | 35 | ||
| 27 | target/arm/kvm64.c | 45 ++++++++++++++++++++++----------------------- | 36 | Damien Hedde (7): |
| 28 | 1 file changed, 22 insertions(+), 23 deletions(-) | 37 | hw/core/clock-vmstate: define a vmstate entry for clock state |
| 38 | qdev: add clock input&output support to devices. | ||
| 39 | qdev-clock: introduce an init array to ease the device construction | ||
| 40 | hw/misc/zynq_slcr: add clock generation for uarts | ||
| 41 | hw/char/cadence_uart: add clock support | ||
| 42 | hw/arm/xilinx_zynq: connect uart clocks to slcr | ||
| 43 | qdev-monitor: print the device's clock with info qtree | ||
| 44 | |||
| 45 | Edgar E. Iglesias (7): | ||
| 46 | dma/xlnx-zdma: Fix descriptor loading (MEM) wrt endianness | ||
| 47 | dma/xlnx-zdma: Fix descriptor loading (REG) wrt endianness | ||
| 48 | hw/arm: versal: Setup the ADMA with 128bit bus-width | ||
| 49 | device_tree: Allow name wildcards in qemu_fdt_node_path() | ||
| 50 | device_tree: Constify compat in qemu_fdt_node_path() | ||
| 51 | hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102 | ||
| 52 | hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes | ||
| 53 | |||
| 54 | Jerome Forissier (2): | ||
| 55 | hw/arm/virt: dt: move creation of /secure-chosen to create_fdt() | ||
| 56 | hw/arm/virt: dt: add kaslr-seed property | ||
| 57 | |||
| 58 | Keqian Zhu (2): | ||
| 59 | bugfix: Use gicr_typer in arm_gicv3_icc_reset | ||
| 60 | Typo: Correct the name of CPU hotplug memory region | ||
| 61 | |||
| 62 | Peter Maydell (2): | ||
| 63 | hw/core/clock: introduce clock object | ||
| 64 | docs/clocks: add device's clock documentation | ||
| 65 | |||
| 66 | Philippe Mathieu-Daudé (2): | ||
| 67 | target/arm: Restrict the Address Translate write operation to TCG accel | ||
| 68 | target/arm/cpu: Update coding style to make checkpatch.pl happy | ||
| 69 | |||
| 70 | Ramon Fried (2): | ||
| 71 | Cadence: gem: fix wraparound in 64bit descriptors | ||
| 72 | net: cadence_gem: clear RX control descriptor | ||
| 73 | |||
| 74 | Richard Henderson (1): | ||
| 75 | target/arm: Vectorize integer comparison vs zero | ||
| 76 | |||
| 77 | Subbaraya Sundeep (3): | ||
| 78 | hw/net: Add Smartfusion2 emac block | ||
| 79 | msf2: Add EMAC block to SmartFusion2 SoC | ||
| 80 | tests/boot_linux_console: Add ethernet test to SmartFusion2 | ||
| 81 | |||
| 82 | Thomas Huth (1): | ||
| 83 | target/arm: Make cpu_register() available for other files | ||
| 84 | |||
| 85 | hw/core/Makefile.objs | 2 + | ||
| 86 | hw/net/Makefile.objs | 1 + | ||
| 87 | tests/Makefile.include | 1 + | ||
| 88 | include/hw/arm/msf2-soc.h | 2 + | ||
| 89 | include/hw/char/cadence_uart.h | 1 + | ||
| 90 | include/hw/clock.h | 225 +++++++++++++ | ||
| 91 | include/hw/gpio/nrf51_gpio.h | 2 +- | ||
| 92 | include/hw/net/msf2-emac.h | 53 +++ | ||
| 93 | include/hw/qdev-clock.h | 159 +++++++++ | ||
| 94 | include/hw/qdev-core.h | 12 + | ||
| 95 | include/sysemu/device_tree.h | 5 +- | ||
| 96 | target/arm/cpu-qom.h | 9 +- | ||
| 97 | target/arm/helper.h | 27 +- | ||
| 98 | target/arm/translate.h | 5 + | ||
| 99 | device_tree.c | 4 +- | ||
| 100 | hw/acpi/cpu.c | 2 +- | ||
| 101 | hw/arm/msf2-soc.c | 26 +- | ||
| 102 | hw/arm/virt.c | 20 +- | ||
| 103 | hw/arm/xilinx_zynq.c | 57 +++- | ||
| 104 | hw/arm/xlnx-versal.c | 2 + | ||
| 105 | hw/arm/xlnx-zcu102.c | 39 ++- | ||
| 106 | hw/char/cadence_uart.c | 73 +++- | ||
| 107 | hw/core/clock-vmstate.c | 25 ++ | ||
| 108 | hw/core/clock.c | 130 ++++++++ | ||
| 109 | hw/core/qdev-clock.c | 185 +++++++++++ | ||
| 110 | hw/core/qdev.c | 12 + | ||
| 111 | hw/dma/xlnx-zdma.c | 25 +- | ||
| 112 | hw/intc/arm_gicv3_kvm.c | 4 +- | ||
| 113 | hw/misc/zynq_slcr.c | 172 +++++++++- | ||
| 114 | hw/net/cadence_gem.c | 16 +- | ||
| 115 | hw/net/msf2-emac.c | 589 +++++++++++++++++++++++++++++++++ | ||
| 116 | qdev-monitor.c | 9 + | ||
| 117 | target/arm/cpu.c | 19 +- | ||
| 118 | target/arm/cpu64.c | 8 +- | ||
| 119 | target/arm/helper.c | 17 + | ||
| 120 | target/arm/neon_helper.c | 24 -- | ||
| 121 | target/arm/translate-a64.c | 64 +--- | ||
| 122 | target/arm/translate.c | 256 ++++++++++++-- | ||
| 123 | target/arm/vec_helper.c | 25 ++ | ||
| 124 | MAINTAINERS | 2 + | ||
| 125 | docs/devel/clocks.rst | 391 ++++++++++++++++++++++ | ||
| 126 | docs/devel/index.rst | 1 + | ||
| 127 | hw/char/trace-events | 3 + | ||
| 128 | hw/core/trace-events | 7 + | ||
| 129 | tests/acceptance/boot_linux_console.py | 15 +- | ||
| 130 | 45 files changed, 2533 insertions(+), 193 deletions(-) | ||
| 131 | create mode 100644 include/hw/clock.h | ||
| 132 | create mode 100644 include/hw/net/msf2-emac.h | ||
| 133 | create mode 100644 include/hw/qdev-clock.h | ||
| 134 | create mode 100644 hw/core/clock-vmstate.c | ||
| 135 | create mode 100644 hw/core/clock.c | ||
| 136 | create mode 100644 hw/core/qdev-clock.c | ||
| 137 | create mode 100644 hw/net/msf2-emac.c | ||
| 138 | create mode 100644 docs/devel/clocks.rst | ||
| 139 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Indication for support for SVE will not depend on whether we | ||
| 4 | perform the query on the main kvm_state or the temp vcpu. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-2-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 2 +- | ||
| 12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | } | ||
| 20 | } | ||
| 21 | |||
| 22 | - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; | ||
| 23 | + sve_supported = kvm_arm_sve_supported(); | ||
| 24 | |||
| 25 | /* Add feature bits that can't appear until after VCPU init. */ | ||
| 26 | if (sve_supported) { | ||
| 27 | -- | ||
| 28 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Because we weren't setting this flag, our probe of ID_AA64ZFR0 | ||
| 4 | was always returning zero. This also obviates the adjustment | ||
| 5 | of ID_AA64PFR0, which had sanitized the SVE field. | ||
| 6 | |||
| 7 | The effects of the bug are not visible, because the only thing that | ||
| 8 | ID_AA64ZFR0 is used for within qemu at present is tcg translation. | ||
| 9 | The other tests for SVE within KVM are via ID_AA64PFR0.SVE. | ||
| 10 | |||
| 11 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Message-id: 20220726045828.53697-3-richard.henderson@linaro.org | ||
| 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | --- | ||
| 17 | target/arm/kvm64.c | 27 +++++++++++++-------------- | ||
| 18 | 1 file changed, 13 insertions(+), 14 deletions(-) | ||
| 19 | |||
| 20 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/target/arm/kvm64.c | ||
| 23 | +++ b/target/arm/kvm64.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 25 | bool sve_supported; | ||
| 26 | bool pmu_supported = false; | ||
| 27 | uint64_t features = 0; | ||
| 28 | - uint64_t t; | ||
| 29 | int err; | ||
| 30 | |||
| 31 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | ||
| 32 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 33 | struct kvm_vcpu_init init = { .target = -1, }; | ||
| 34 | |||
| 35 | /* | ||
| 36 | - * Ask for Pointer Authentication if supported. We can't play the | ||
| 37 | - * SVE trick of synthesising the ID reg as KVM won't tell us | ||
| 38 | - * whether we have the architected or IMPDEF version of PAuth, so | ||
| 39 | - * we have to use the actual ID regs. | ||
| 40 | + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, | ||
| 41 | + * which is otherwise RAZ. | ||
| 42 | + */ | ||
| 43 | + sve_supported = kvm_arm_sve_supported(); | ||
| 44 | + if (sve_supported) { | ||
| 45 | + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; | ||
| 46 | + } | ||
| 47 | + | ||
| 48 | + /* | ||
| 49 | + * Ask for Pointer Authentication if supported, so that we get | ||
| 50 | + * the unsanitized field values for AA64ISAR1_EL1. | ||
| 51 | */ | ||
| 52 | if (kvm_arm_pauth_supported()) { | ||
| 53 | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | | ||
| 54 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 55 | } | ||
| 56 | } | ||
| 57 | |||
| 58 | - sve_supported = kvm_arm_sve_supported(); | ||
| 59 | - | ||
| 60 | - /* Add feature bits that can't appear until after VCPU init. */ | ||
| 61 | if (sve_supported) { | ||
| 62 | - t = ahcf->isar.id_aa64pfr0; | ||
| 63 | - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
| 64 | - ahcf->isar.id_aa64pfr0 = t; | ||
| 65 | - | ||
| 66 | /* | ||
| 67 | * There is a range of kernels between kernel commit 73433762fcae | ||
| 68 | * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 69 | * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 70 | - * SVE support, so we only read it here, rather than together with all | ||
| 71 | - * the other ID registers earlier. | ||
| 72 | + * SVE support, which resulted in an error rather than RAZ. | ||
| 73 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 74 | */ | ||
| 75 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 76 | ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 77 | -- | ||
| 78 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The test for the IF block indicates no ID registers are exposed, much | ||
| 4 | less host support for SVE. Move the SVE probe into the ELSE block. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-4-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 22 +++++++++++----------- | ||
| 12 | 1 file changed, 11 insertions(+), 11 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, | ||
| 20 | ARM64_SYS_REG(3, 3, 9, 12, 0)); | ||
| 21 | } | ||
| 22 | - } | ||
| 23 | |||
| 24 | - if (sve_supported) { | ||
| 25 | - /* | ||
| 26 | - * There is a range of kernels between kernel commit 73433762fcae | ||
| 27 | - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 28 | - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 29 | - * SVE support, which resulted in an error rather than RAZ. | ||
| 30 | - * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 31 | - */ | ||
| 32 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 33 | - ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 34 | + if (sve_supported) { | ||
| 35 | + /* | ||
| 36 | + * There is a range of kernels between kernel commit 73433762fcae | ||
| 37 | + * and f81cb2c3ad41 which have a bug where the kernel doesn't | ||
| 38 | + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has | ||
| 39 | + * enabled SVE support, which resulted in an error rather than RAZ. | ||
| 40 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 41 | + */ | ||
| 42 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 43 | + ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 44 | + } | ||
| 45 | } | ||
| 46 | |||
| 47 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
| 48 | -- | ||
| 49 | 2.25.1 | diff view generated by jsdifflib |