[PULL 0/3] target-arm queue
[PULL v4 00/20] target-arm queue
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Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code.
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v1->v2: add system/index to docs/index.rst
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v2->v3: fix format string issues for OSX
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v3->v4: actually fix format string issues, somehow
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I failed to actually put the change into git :-(
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-- PMM
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The following changes since commit b7c359c748a2e3ccb97a184b9739feb2cd48de2f:
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The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236:
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Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.0-pull-request' into staging (2020-01-23 14:38:43 +0000)
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Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200123-4
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for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc:
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for you to fetch changes up to e9d20b55b2e4c8400143554f0e83e4e1fcb9bd0f:
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target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100)
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hw/arm/exynos4210: Connect serial port DMA busy signals with pl330 (2020-01-23 16:34:15 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* Fix KVM SVE ID register probe code
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* fix bug in PAuth emulation
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* add PMU to Cortex-R5, Cortex-R5F
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* qemu-nbd: Convert documentation to rST
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* qemu-block-drivers: Convert documentation to rST
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* Fix Exynos4210 UART DMA support
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* Various minor code cleanups
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----------------------------------------------------------------
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----------------------------------------------------------------
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Andrew Jones (1):
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target/arm/arch_dump: Add SVE notes
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Clement Deschamps (1):
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target/arm: add PMU feature to cortex-r5 and cortex-r5f
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Guenter Roeck (8):
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dma/pl330: Convert to support tracing
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hw/core/or-irq: Increase limit of or-lines to 48
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hw/arm/exynos4210: Fix DMA initialization
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hw/char/exynos4210_uart: Convert to support tracing
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hw/char/exynos4210_uart: Implement post_load function
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hw/char/exynos4210_uart: Implement Rx FIFO level triggers and timeouts
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hw/char/exynos4210_uart: Add receive DMA support
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hw/arm/exynos4210: Connect serial port DMA busy signals with pl330
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Keqian Zhu (2):
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hw/acpi: Remove extra indent in ACPI GED hotplug cb
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hw/arm: Use helper function to trigger hotplug handler plug
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Peter Maydell (3):
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qemu-nbd: Convert invocation documentation to rST
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docs: Create stub system manual
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qemu-block-drivers: Convert to rST
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Philippe Mathieu-Daudé (1):
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hw/misc/stm32f4xx_syscfg: Fix copy/paste error
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Richard Henderson (3):
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Richard Henderson (3):
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target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
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tests/tcg/aarch64: Fix compilation parameters for pauth-%
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target/arm: Set KVM_ARM_VCPU_SVE while probing the host
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tests/tcg/aarch64: Add pauth-3
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target/arm: Move sve probe inside kvm >= 4.15 branch
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tests/tcg/aarch64: Add pauth-4
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target/arm/kvm64.c | 45 ++++++++++++++++++++++-----------------------
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Vincent Dehors (1):
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1 file changed, 22 insertions(+), 23 deletions(-)
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target/arm: Fix PAuth sbox functions
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Makefile | 37 +-
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tests/tcg/aarch64/Makefile.softmmu-target | 5 +-
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tests/tcg/aarch64/Makefile.target | 3 +-
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include/elf.h | 1 +
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include/hw/arm/exynos4210.h | 4 +
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include/hw/or-irq.h | 2 +-
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target/arm/cpu.h | 25 +
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hw/acpi/generic_event_device.c | 2 +-
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hw/arm/exynos4210.c | 77 ++-
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hw/arm/virt.c | 6 +-
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hw/char/exynos4210_uart.c | 245 +++++---
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hw/dma/pl330.c | 88 +--
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hw/misc/stm32f4xx_syscfg.c | 2 +-
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target/arm/arch_dump.c | 124 +++-
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target/arm/cpu.c | 1 +
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target/arm/kvm64.c | 24 -
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target/arm/pauth_helper.c | 4 +-
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tests/tcg/aarch64/pauth-1.c | 2 -
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tests/tcg/aarch64/pauth-2.c | 2 -
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tests/tcg/aarch64/pauth-4.c | 25 +
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tests/tcg/aarch64/system/pauth-3.c | 40 ++
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MAINTAINERS | 1 +
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docs/index.html.in | 1 +
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docs/index.rst | 2 +-
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docs/interop/conf.py | 4 +-
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docs/interop/index.rst | 1 +
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docs/interop/qemu-nbd.rst | 263 ++++++++
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docs/interop/qemu-option-trace.rst.inc | 30 +
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docs/qemu-block-drivers.texi | 889 ---------------------------
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docs/system/conf.py | 22 +
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docs/system/index.rst | 17 +
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docs/system/qemu-block-drivers.rst | 985 ++++++++++++++++++++++++++++++
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hw/char/trace-events | 20 +
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hw/dma/trace-events | 24 +
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qemu-doc.texi | 18 -
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qemu-nbd.texi | 214 -------
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qemu-option-trace.texi | 4 +
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qemu-options.hx | 2 +-
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38 files changed, 1898 insertions(+), 1318 deletions(-)
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create mode 100644 tests/tcg/aarch64/pauth-4.c
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create mode 100644 tests/tcg/aarch64/system/pauth-3.c
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create mode 100644 docs/interop/qemu-nbd.rst
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create mode 100644 docs/interop/qemu-option-trace.rst.inc
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delete mode 100644 docs/qemu-block-drivers.texi
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create mode 100644 docs/system/conf.py
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create mode 100644 docs/system/index.rst
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create mode 100644 docs/system/qemu-block-drivers.rst
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delete mode 100644 qemu-nbd.texi
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diff view generated by jsdifflib
[PULL 1/3] target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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1
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Indication for support for SVE will not depend on whether we
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perform the query on the main kvm_state or the temp vcpu.
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-2-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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}
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}
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- sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
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+ sve_supported = kvm_arm_sve_supported();
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/* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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--
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2.25.1
diff view generated by jsdifflib
[PULL 2/3] target/arm: Set KVM_ARM_VCPU_SVE while probing the host
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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1
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Because we weren't setting this flag, our probe of ID_AA64ZFR0
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was always returning zero. This also obviates the adjustment
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of ID_AA64PFR0, which had sanitized the SVE field.
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The effects of the bug are not visible, because the only thing that
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ID_AA64ZFR0 is used for within qemu at present is tcg translation.
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The other tests for SVE within KVM are via ID_AA64PFR0.SVE.
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Reported-by: Zenghui Yu <yuzenghui@huawei.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-3-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 27 +++++++++++++--------------
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1 file changed, 13 insertions(+), 14 deletions(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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bool sve_supported;
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bool pmu_supported = false;
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uint64_t features = 0;
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- uint64_t t;
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int err;
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/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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struct kvm_vcpu_init init = { .target = -1, };
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/*
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- * Ask for Pointer Authentication if supported. We can't play the
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- * SVE trick of synthesising the ID reg as KVM won't tell us
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- * whether we have the architected or IMPDEF version of PAuth, so
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- * we have to use the actual ID regs.
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+ * Ask for SVE if supported, so that we can query ID_AA64ZFR0,
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+ * which is otherwise RAZ.
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+ */
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+ sve_supported = kvm_arm_sve_supported();
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+ if (sve_supported) {
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+ init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
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+ }
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+
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+ /*
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+ * Ask for Pointer Authentication if supported, so that we get
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+ * the unsanitized field values for AA64ISAR1_EL1.
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*/
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if (kvm_arm_pauth_supported()) {
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init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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}
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}
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- sve_supported = kvm_arm_sve_supported();
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-
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- /* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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- t = ahcf->isar.id_aa64pfr0;
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- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
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- ahcf->isar.id_aa64pfr0 = t;
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-
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/*
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* There is a range of kernels between kernel commit 73433762fcae
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* and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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* SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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- * SVE support, so we only read it here, rather than together with all
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- * the other ID registers earlier.
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+ * SVE support, which resulted in an error rather than RAZ.
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+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
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*/
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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ARM64_SYS_REG(3, 0, 0, 4, 4));
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--
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2.25.1
diff view generated by jsdifflib
[PULL 3/3] target/arm: Move sve probe inside kvm >= 4.15 branch
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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1
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The test for the IF block indicates no ID registers are exposed, much
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less host support for SVE. Move the SVE probe into the ELSE block.
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-4-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 22 +++++++++++-----------
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1 file changed, 11 insertions(+), 11 deletions(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
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ARM64_SYS_REG(3, 3, 9, 12, 0));
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}
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- }
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- if (sve_supported) {
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- /*
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- * There is a range of kernels between kernel commit 73433762fcae
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- * and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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- * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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- * SVE support, which resulted in an error rather than RAZ.
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- * So only read the register if we set KVM_ARM_VCPU_SVE above.
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- */
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- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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- ARM64_SYS_REG(3, 0, 0, 4, 4));
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+ if (sve_supported) {
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+ /*
36
+ * There is a range of kernels between kernel commit 73433762fcae
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+ * and f81cb2c3ad41 which have a bug where the kernel doesn't
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+ * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
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+ * enabled SVE support, which resulted in an error rather than RAZ.
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+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
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+ */
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+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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+ ARM64_SYS_REG(3, 0, 0, 4, 4));
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+ }
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}
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kvm_arm_destroy_scratch_host_vcpu(fdarray);
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--
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2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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