[PULL 0/3] target-arm queue
[PULL v2 00/19] target-arm queue
1
Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code.
1
Changes v1->v2: dropped rth's patchset as it causes an
2
assert with the qemu-armeb binary.
2
3
4
I expect I'll do another pullreq at the end of the week.
5
6
thanks
3
-- PMM
7
-- PMM
4
8
5
The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236:
9
The following changes since commit f9bec781379dd7ccf9d01b4b6a79a9ec82c192e5:
6
10
7
Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700)
11
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20191022' into staging (2019-10-22 13:45:09 +0100)
8
12
9
are available in the Git repository at:
13
are available in the Git repository at:
10
14
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801
15
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191022-1
12
16
13
for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc:
17
for you to fetch changes up to f9c1fe62a16f32c3d6fe34c2856475052b7efdaf:
14
18
15
target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100)
19
hw/arm/digic4: Inline digic4_board_setup_ram() function (2019-10-22 16:50:38 +0100)
16
20
17
----------------------------------------------------------------
21
----------------------------------------------------------------
18
target-arm queue:
22
target-arm queue:
19
* Fix KVM SVE ID register probe code
23
* Fix sign-extension for SMLAL* instructions
24
* aspeed: Add an AST2600 eval board
25
* Various ptimer device conversions to new transaction API
26
* Add a dummy Samsung SDHCI controller model to exynos4 boards
27
* Minor refactorings of RAM creation for some arm boards
20
28
21
----------------------------------------------------------------
29
----------------------------------------------------------------
22
Richard Henderson (3):
30
Cédric Le Goater (1):
23
target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
31
aspeed: Add an AST2600 eval board
24
target/arm: Set KVM_ARM_VCPU_SVE while probing the host
25
target/arm: Move sve probe inside kvm >= 4.15 branch
26
32
27
target/arm/kvm64.c | 45 ++++++++++++++++++++++-----------------------
33
Guenter Roeck (1):
28
1 file changed, 22 insertions(+), 23 deletions(-)
34
hw/timer/exynos4210_mct: Initialize ptimer before starting it
35
36
Peter Maydell (7):
37
hw/timer/arm_mptimer.c: Undo accidental rename of arm_mptimer_init()
38
hw/timer/puv3_ost.c: Switch to transaction-based ptimer API
39
hw/timer/sh_timer: Switch to transaction-based ptimer API
40
hw/timer/lm32_timer: Switch to transaction-based ptimer API
41
hw/timer/altera_timer.c: Switch to transaction-based ptimer API
42
hw/watchdog/etraxfs_timer.c: Switch to transaction-based ptimer API
43
hw/m68k/mcf5208.c: Switch to transaction-based ptimer API
44
45
Philippe Mathieu-Daudé (9):
46
hw/sd/sdhci: Add a comment to distinct the i.MX eSDHC functions
47
hw/sd/sdhci: Add dummy Samsung SDHCI controller
48
hw/arm/exynos4210: Use the Samsung s3c SDHCI controller
49
hw/arm/xilinx_zynq: Use the IEC binary prefix definitions
50
hw/arm/mps2: Use the IEC binary prefix definitions
51
hw/arm/collie: Create the RAM in the board
52
hw/arm/omap2: Create the RAM in the board
53
hw/arm/omap1: Create the RAM in the board
54
hw/arm/digic4: Inline digic4_board_setup_ram() function
55
56
Richard Henderson (1):
57
target/arm: Fix sign-extension for SMLAL*
58
59
hw/arm/strongarm.h | 4 +--
60
include/hw/arm/aspeed.h | 1 +
61
include/hw/arm/omap.h | 10 +++----
62
include/hw/sd/sdhci.h | 2 ++
63
hw/arm/aspeed.c | 23 ++++++++++++++++
64
hw/arm/collie.c | 8 ++++--
65
hw/arm/digic_boards.c | 9 ++-----
66
hw/arm/exynos4210.c | 2 +-
67
hw/arm/mps2-tz.c | 3 ++-
68
hw/arm/mps2.c | 3 ++-
69
hw/arm/nseries.c | 10 ++++---
70
hw/arm/omap1.c | 12 ++++-----
71
hw/arm/omap2.c | 13 ++++-----
72
hw/arm/omap_sx1.c | 8 ++++--
73
hw/arm/palm.c | 8 ++++--
74
hw/arm/strongarm.c | 7 +----
75
hw/arm/xilinx_zynq.c | 3 ++-
76
hw/m68k/mcf5208.c | 9 ++++---
77
hw/sd/sdhci.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++-
78
hw/timer/altera_timer.c | 13 ++++++---
79
hw/timer/arm_mptimer.c | 4 +--
80
hw/timer/etraxfs_timer.c | 23 +++++++++-------
81
hw/timer/exynos4210_mct.c | 2 +-
82
hw/timer/lm32_timer.c | 13 ++++++---
83
hw/timer/puv3_ost.c | 9 ++++---
84
hw/timer/sh_timer.c | 13 ++++++---
85
target/arm/translate.c | 4 ++-
86
27 files changed, 198 insertions(+), 86 deletions(-)
87
diff view generated by jsdifflib
[PULL 1/3] target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Indication for support for SVE will not depend on whether we
4
perform the query on the main kvm_state or the temp vcpu.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220726045828.53697-2-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/kvm64.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/kvm64.c
17
+++ b/target/arm/kvm64.c
18
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
19
}
20
}
21
22
- sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
23
+ sve_supported = kvm_arm_sve_supported();
24
25
/* Add feature bits that can't appear until after VCPU init. */
26
if (sve_supported) {
27
--
28
2.25.1
diff view generated by jsdifflib
[PULL 2/3] target/arm: Set KVM_ARM_VCPU_SVE while probing the host
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Because we weren't setting this flag, our probe of ID_AA64ZFR0
4
was always returning zero. This also obviates the adjustment
5
of ID_AA64PFR0, which had sanitized the SVE field.
6
7
The effects of the bug are not visible, because the only thing that
8
ID_AA64ZFR0 is used for within qemu at present is tcg translation.
9
The other tests for SVE within KVM are via ID_AA64PFR0.SVE.
10
11
Reported-by: Zenghui Yu <yuzenghui@huawei.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20220726045828.53697-3-richard.henderson@linaro.org
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/kvm64.c | 27 +++++++++++++--------------
18
1 file changed, 13 insertions(+), 14 deletions(-)
19
20
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/kvm64.c
23
+++ b/target/arm/kvm64.c
24
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
25
bool sve_supported;
26
bool pmu_supported = false;
27
uint64_t features = 0;
28
- uint64_t t;
29
int err;
30
31
/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
32
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
33
struct kvm_vcpu_init init = { .target = -1, };
34
35
/*
36
- * Ask for Pointer Authentication if supported. We can't play the
37
- * SVE trick of synthesising the ID reg as KVM won't tell us
38
- * whether we have the architected or IMPDEF version of PAuth, so
39
- * we have to use the actual ID regs.
40
+ * Ask for SVE if supported, so that we can query ID_AA64ZFR0,
41
+ * which is otherwise RAZ.
42
+ */
43
+ sve_supported = kvm_arm_sve_supported();
44
+ if (sve_supported) {
45
+ init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
46
+ }
47
+
48
+ /*
49
+ * Ask for Pointer Authentication if supported, so that we get
50
+ * the unsanitized field values for AA64ISAR1_EL1.
51
*/
52
if (kvm_arm_pauth_supported()) {
53
init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
54
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
55
}
56
}
57
58
- sve_supported = kvm_arm_sve_supported();
59
-
60
- /* Add feature bits that can't appear until after VCPU init. */
61
if (sve_supported) {
62
- t = ahcf->isar.id_aa64pfr0;
63
- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
64
- ahcf->isar.id_aa64pfr0 = t;
65
-
66
/*
67
* There is a range of kernels between kernel commit 73433762fcae
68
* and f81cb2c3ad41 which have a bug where the kernel doesn't expose
69
* SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
70
- * SVE support, so we only read it here, rather than together with all
71
- * the other ID registers earlier.
72
+ * SVE support, which resulted in an error rather than RAZ.
73
+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
74
*/
75
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
76
ARM64_SYS_REG(3, 0, 0, 4, 4));
77
--
78
2.25.1
diff view generated by jsdifflib
[PULL 3/3] target/arm: Move sve probe inside kvm >= 4.15 branch
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
The test for the IF block indicates no ID registers are exposed, much
4
less host support for SVE. Move the SVE probe into the ELSE block.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220726045828.53697-4-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/kvm64.c | 22 +++++++++++-----------
12
1 file changed, 11 insertions(+), 11 deletions(-)
13
14
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/kvm64.c
17
+++ b/target/arm/kvm64.c
18
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
19
err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
20
ARM64_SYS_REG(3, 3, 9, 12, 0));
21
}
22
- }
23
24
- if (sve_supported) {
25
- /*
26
- * There is a range of kernels between kernel commit 73433762fcae
27
- * and f81cb2c3ad41 which have a bug where the kernel doesn't expose
28
- * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
29
- * SVE support, which resulted in an error rather than RAZ.
30
- * So only read the register if we set KVM_ARM_VCPU_SVE above.
31
- */
32
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
33
- ARM64_SYS_REG(3, 0, 0, 4, 4));
34
+ if (sve_supported) {
35
+ /*
36
+ * There is a range of kernels between kernel commit 73433762fcae
37
+ * and f81cb2c3ad41 which have a bug where the kernel doesn't
38
+ * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
39
+ * enabled SVE support, which resulted in an error rather than RAZ.
40
+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
41
+ */
42
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
43
+ ARM64_SYS_REG(3, 0, 0, 4, 4));
44
+ }
45
}
46
47
kvm_arm_destroy_scratch_host_vcpu(fdarray);
48
--
49
2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.