1
Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code.
1
v1->v2 changes: dropped the patch adding the new ast2600
2
2
board, as it doesn't pass "make check" on 32-bit hosts or
3
low-memory hosts.
4
5
thanks
3
-- PMM
6
-- PMM
4
7
5
The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236:
8
The following changes since commit 3af78db68176a049e2570822f64604e0692c1447:
6
9
7
Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700)
10
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2019-10-15 13:25:05 +0100)
8
11
9
are available in the Git repository at:
12
are available in the Git repository at:
10
13
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191015
12
15
13
for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc:
16
for you to fetch changes up to 19845504da1bdee4be7d0fba33da5be9efa4c11b:
14
17
15
target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100)
18
hw/misc/bcm2835_mbox: Add trace events (2019-10-15 18:09:05 +0100)
16
19
17
----------------------------------------------------------------
20
----------------------------------------------------------------
18
target-arm queue:
21
target-arm queue:
19
* Fix KVM SVE ID register probe code
22
* Add Aspeed AST2600 SoC support (but no new board model yet)
23
* aspeed/wdt: Check correct register for clock source
24
* bcm2835: code cleanups, better logging, trace events
25
* implement v2.0 of the Arm semihosting specification
26
* provide new 'transaction-based' ptimer API and use it
27
for the Arm devices that use ptimers
28
* ARM: KVM: support more than 256 CPUs
20
29
21
----------------------------------------------------------------
30
----------------------------------------------------------------
22
Richard Henderson (3):
31
Amithash Prasad (1):
23
target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
32
aspeed/wdt: Check correct register for clock source
24
target/arm: Set KVM_ARM_VCPU_SVE while probing the host
33
25
target/arm: Move sve probe inside kvm >= 4.15 branch
34
Cédric Le Goater (14):
26
35
aspeed/timer: Introduce an object class per SoC
27
target/arm/kvm64.c | 45 ++++++++++++++++++++++-----------------------
36
aspeed/timer: Add support for control register 3
28
1 file changed, 22 insertions(+), 23 deletions(-)
37
aspeed/timer: Add AST2600 support
38
aspeed/timer: Add support for IRQ status register on the AST2600
39
aspeed/sdmc: Introduce an object class per SoC
40
watchdog/aspeed: Introduce an object class per SoC
41
aspeed/smc: Introduce segment operations
42
aspeed/smc: Add AST2600 support
43
aspeed/i2c: Introduce an object class per SoC
44
aspeed/i2c: Add AST2600 support
45
aspeed: Introduce an object class per SoC
46
aspeed/soc: Add AST2600 support
47
m25p80: Add support for w25q512jv
48
aspeed: add support for the Aspeed MII controller of the AST2600
49
50
Eddie James (1):
51
hw/sd/aspeed_sdhci: New device
52
53
Eric Auger (3):
54
linux headers: update against v5.4-rc1
55
intc/arm_gic: Support IRQ injection for more than 256 vpus
56
ARM: KVM: Check KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 for smp_cpus > 256
57
58
Joel Stanley (5):
59
hw: aspeed_scu: Add AST2600 support
60
aspeed/sdmc: Add AST2600 support
61
hw: wdt_aspeed: Add AST2600 support
62
aspeed: Parameterise number of MACs
63
aspeed/soc: Add ASPEED Video stub
64
65
Peter Maydell (36):
66
ptimer: Rename ptimer_init() to ptimer_init_with_bh()
67
ptimer: Provide new transaction-based API
68
tests/ptimer-test: Switch to transaction-based ptimer API
69
hw/timer/arm_timer.c: Switch to transaction-based ptimer API
70
hw/arm/musicpal.c: Switch to transaction-based ptimer API
71
hw/timer/allwinner-a10-pit.c: Switch to transaction-based ptimer API
72
hw/timer/arm_mptimer.c: Switch to transaction-based ptimer API
73
hw/timer/cmsdk-apb-dualtimer.c: Switch to transaction-based ptimer API
74
hw/timer/cmsdk-apb-timer.c: Switch to transaction-based ptimer API
75
hw/timer/digic-timer.c: Switch to transaction-based ptimer API
76
hw/timer/exynos4210_mct.c: Switch GFRC to transaction-based ptimer API
77
hw/timer/exynos4210_mct.c: Switch LFRC to transaction-based ptimer API
78
hw/timer/exynos4210_mct.c: Switch ltick to transaction-based ptimer API
79
hw/timer/exynos4210_pwm.c: Switch to transaction-based ptimer API
80
hw/timer/exynos4210_rtc.c: Switch 1Hz ptimer to transaction-based API
81
hw/timer/exynos4210_rtc.c: Switch main ptimer to transaction-based API
82
hw/timer/imx_epit.c: Switch to transaction-based ptimer API
83
hw/timer/imx_gpt.c: Switch to transaction-based ptimer API
84
hw/timer/mss-timerc: Switch to transaction-based ptimer API
85
hw/watchdog/cmsdk-apb-watchdog.c: Switch to transaction-based ptimer API
86
hw/net/lan9118.c: Switch to transaction-based ptimer API
87
target/arm/arm-semi: Capture errno in softmmu version of set_swi_errno()
88
target/arm/arm-semi: Always set some kind of errno for failed calls
89
target/arm/arm-semi: Correct comment about gdb syscall races
90
target/arm/arm-semi: Make semihosting code hand out its own file descriptors
91
target/arm/arm-semi: Restrict use of TaskState*
92
target/arm/arm-semi: Use set_swi_errno() in gdbstub callback functions
93
target/arm/arm-semi: Factor out implementation of SYS_CLOSE
94
target/arm/arm-semi: Factor out implementation of SYS_WRITE
95
target/arm/arm-semi: Factor out implementation of SYS_READ
96
target/arm/arm-semi: Factor out implementation of SYS_ISTTY
97
target/arm/arm-semi: Factor out implementation of SYS_SEEK
98
target/arm/arm-semi: Factor out implementation of SYS_FLEN
99
target/arm/arm-semi: Implement support for semihosting feature detection
100
target/arm/arm-semi: Implement SH_EXT_EXIT_EXTENDED extension
101
target/arm/arm-semi: Implement SH_EXT_STDOUT_STDERR extension
102
103
Philippe Mathieu-Daudé (6):
104
hw/arm/raspi: Use the IEC binary prefix definitions
105
hw/arm/bcm2835_peripherals: Improve logging
106
hw/arm/bcm2835_peripherals: Name various address spaces
107
hw/arm/bcm2835: Rename some definitions
108
hw/arm/bcm2835: Add various unimplemented peripherals
109
hw/misc/bcm2835_mbox: Add trace events
110
111
Rashmica Gupta (1):
112
hw/gpio: Add in AST2600 specific implementation
113
114
hw/arm/Makefile.objs | 2 +-
115
hw/sd/Makefile.objs | 1 +
116
include/hw/arm/aspeed_soc.h | 29 +-
117
include/hw/arm/bcm2835_peripherals.h | 15 +
118
include/hw/arm/raspi_platform.h | 24 +-
119
include/hw/i2c/aspeed_i2c.h | 20 +-
120
include/hw/misc/aspeed_scu.h | 7 +-
121
include/hw/misc/aspeed_sdmc.h | 20 +-
122
include/hw/net/ftgmac100.h | 17 +
123
include/hw/ptimer.h | 83 ++-
124
include/hw/sd/aspeed_sdhci.h | 34 ++
125
include/hw/ssi/aspeed_smc.h | 4 +
126
include/hw/timer/aspeed_timer.h | 18 +
127
include/hw/timer/mss-timer.h | 1 -
128
include/hw/watchdog/wdt_aspeed.h | 19 +-
129
include/standard-headers/asm-x86/bootparam.h | 2 +
130
include/standard-headers/asm-x86/kvm_para.h | 1 +
131
include/standard-headers/linux/ethtool.h | 24 +
132
include/standard-headers/linux/pci_regs.h | 19 +-
133
include/standard-headers/linux/virtio_fs.h | 19 +
134
include/standard-headers/linux/virtio_ids.h | 2 +
135
include/standard-headers/linux/virtio_iommu.h | 165 ++++++
136
include/standard-headers/linux/virtio_pmem.h | 6 +-
137
linux-headers/asm-arm/kvm.h | 16 +-
138
linux-headers/asm-arm/unistd-common.h | 2 +
139
linux-headers/asm-arm64/kvm.h | 21 +-
140
linux-headers/asm-generic/mman-common.h | 18 +-
141
linux-headers/asm-generic/mman.h | 10 +-
142
linux-headers/asm-generic/unistd.h | 10 +-
143
linux-headers/asm-mips/mman.h | 3 +
144
linux-headers/asm-mips/unistd_n32.h | 1 +
145
linux-headers/asm-mips/unistd_n64.h | 1 +
146
linux-headers/asm-mips/unistd_o32.h | 1 +
147
linux-headers/asm-powerpc/mman.h | 6 +-
148
linux-headers/asm-powerpc/unistd_32.h | 2 +
149
linux-headers/asm-powerpc/unistd_64.h | 2 +
150
linux-headers/asm-s390/kvm.h | 6 +
151
linux-headers/asm-s390/unistd_32.h | 2 +
152
linux-headers/asm-s390/unistd_64.h | 2 +
153
linux-headers/asm-x86/kvm.h | 28 +-
154
linux-headers/asm-x86/unistd.h | 2 +-
155
linux-headers/asm-x86/unistd_32.h | 2 +
156
linux-headers/asm-x86/unistd_64.h | 2 +
157
linux-headers/asm-x86/unistd_x32.h | 2 +
158
linux-headers/linux/kvm.h | 12 +-
159
linux-headers/linux/psp-sev.h | 5 +-
160
linux-headers/linux/vfio.h | 71 ++-
161
target/arm/kvm_arm.h | 1 +
162
hw/arm/aspeed.c | 19 +-
163
hw/arm/aspeed_ast2600.c | 523 +++++++++++++++++++
164
hw/arm/aspeed_soc.c | 199 +++++---
165
hw/arm/bcm2835_peripherals.c | 38 +-
166
hw/arm/bcm2836.c | 2 +-
167
hw/arm/musicpal.c | 16 +-
168
hw/arm/raspi.c | 4 +-
169
hw/block/m25p80.c | 1 +
170
hw/char/bcm2835_aux.c | 5 +-
171
hw/core/ptimer.c | 154 +++++-
172
hw/display/bcm2835_fb.c | 2 +-
173
hw/dma/bcm2835_dma.c | 10 +-
174
hw/dma/xilinx_axidma.c | 2 +-
175
hw/gpio/aspeed_gpio.c | 142 +++++-
176
hw/i2c/aspeed_i2c.c | 106 +++-
177
hw/intc/arm_gic_kvm.c | 7 +-
178
hw/intc/bcm2836_control.c | 7 +-
179
hw/m68k/mcf5206.c | 2 +-
180
hw/m68k/mcf5208.c | 2 +-
181
hw/misc/aspeed_scu.c | 194 ++++++-
182
hw/misc/aspeed_sdmc.c | 250 ++++++---
183
hw/misc/bcm2835_mbox.c | 14 +-
184
hw/misc/bcm2835_property.c | 20 +-
185
hw/net/fsl_etsec/etsec.c | 2 +-
186
hw/net/ftgmac100.c | 162 ++++++
187
hw/net/lan9118.c | 11 +-
188
hw/sd/aspeed_sdhci.c | 198 ++++++++
189
hw/ssi/aspeed_smc.c | 177 ++++++-
190
hw/timer/allwinner-a10-pit.c | 12 +-
191
hw/timer/altera_timer.c | 2 +-
192
hw/timer/arm_mptimer.c | 18 +-
193
hw/timer/arm_timer.c | 16 +-
194
hw/timer/aspeed_timer.c | 213 +++++++-
195
hw/timer/cmsdk-apb-dualtimer.c | 14 +-
196
hw/timer/cmsdk-apb-timer.c | 15 +-
197
hw/timer/digic-timer.c | 16 +-
198
hw/timer/etraxfs_timer.c | 6 +-
199
hw/timer/exynos4210_mct.c | 107 +++-
200
hw/timer/exynos4210_pwm.c | 17 +-
201
hw/timer/exynos4210_rtc.c | 22 +-
202
hw/timer/grlib_gptimer.c | 2 +-
203
hw/timer/imx_epit.c | 32 +-
204
hw/timer/imx_gpt.c | 21 +-
205
hw/timer/lm32_timer.c | 2 +-
206
hw/timer/milkymist-sysctl.c | 4 +-
207
hw/timer/mss-timer.c | 11 +-
208
hw/timer/puv3_ost.c | 2 +-
209
hw/timer/sh_timer.c | 2 +-
210
hw/timer/slavio_timer.c | 2 +-
211
hw/timer/xilinx_timer.c | 2 +-
212
hw/watchdog/cmsdk-apb-watchdog.c | 13 +-
213
hw/watchdog/wdt_aspeed.c | 153 +++---
214
target/arm/arm-semi.c | 707 +++++++++++++++++++++-----
215
target/arm/cpu.c | 10 +-
216
target/arm/kvm.c | 22 +-
217
tests/ptimer-test.c | 106 +++-
218
hw/misc/trace-events | 6 +
219
105 files changed, 3934 insertions(+), 650 deletions(-)
220
create mode 100644 include/hw/sd/aspeed_sdhci.h
221
create mode 100644 include/standard-headers/linux/virtio_fs.h
222
create mode 100644 include/standard-headers/linux/virtio_iommu.h
223
create mode 100644 hw/arm/aspeed_ast2600.c
224
create mode 100644 hw/sd/aspeed_sdhci.c
225
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Indication for support for SVE will not depend on whether we
4
perform the query on the main kvm_state or the temp vcpu.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220726045828.53697-2-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/kvm64.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/kvm64.c
17
+++ b/target/arm/kvm64.c
18
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
19
}
20
}
21
22
- sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
23
+ sve_supported = kvm_arm_sve_supported();
24
25
/* Add feature bits that can't appear until after VCPU init. */
26
if (sve_supported) {
27
--
28
2.25.1
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Because we weren't setting this flag, our probe of ID_AA64ZFR0
4
was always returning zero. This also obviates the adjustment
5
of ID_AA64PFR0, which had sanitized the SVE field.
6
7
The effects of the bug are not visible, because the only thing that
8
ID_AA64ZFR0 is used for within qemu at present is tcg translation.
9
The other tests for SVE within KVM are via ID_AA64PFR0.SVE.
10
11
Reported-by: Zenghui Yu <yuzenghui@huawei.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20220726045828.53697-3-richard.henderson@linaro.org
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/kvm64.c | 27 +++++++++++++--------------
18
1 file changed, 13 insertions(+), 14 deletions(-)
19
20
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/kvm64.c
23
+++ b/target/arm/kvm64.c
24
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
25
bool sve_supported;
26
bool pmu_supported = false;
27
uint64_t features = 0;
28
- uint64_t t;
29
int err;
30
31
/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
32
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
33
struct kvm_vcpu_init init = { .target = -1, };
34
35
/*
36
- * Ask for Pointer Authentication if supported. We can't play the
37
- * SVE trick of synthesising the ID reg as KVM won't tell us
38
- * whether we have the architected or IMPDEF version of PAuth, so
39
- * we have to use the actual ID regs.
40
+ * Ask for SVE if supported, so that we can query ID_AA64ZFR0,
41
+ * which is otherwise RAZ.
42
+ */
43
+ sve_supported = kvm_arm_sve_supported();
44
+ if (sve_supported) {
45
+ init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
46
+ }
47
+
48
+ /*
49
+ * Ask for Pointer Authentication if supported, so that we get
50
+ * the unsanitized field values for AA64ISAR1_EL1.
51
*/
52
if (kvm_arm_pauth_supported()) {
53
init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
54
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
55
}
56
}
57
58
- sve_supported = kvm_arm_sve_supported();
59
-
60
- /* Add feature bits that can't appear until after VCPU init. */
61
if (sve_supported) {
62
- t = ahcf->isar.id_aa64pfr0;
63
- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
64
- ahcf->isar.id_aa64pfr0 = t;
65
-
66
/*
67
* There is a range of kernels between kernel commit 73433762fcae
68
* and f81cb2c3ad41 which have a bug where the kernel doesn't expose
69
* SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
70
- * SVE support, so we only read it here, rather than together with all
71
- * the other ID registers earlier.
72
+ * SVE support, which resulted in an error rather than RAZ.
73
+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
74
*/
75
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
76
ARM64_SYS_REG(3, 0, 0, 4, 4));
77
--
78
2.25.1
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
The test for the IF block indicates no ID registers are exposed, much
4
less host support for SVE. Move the SVE probe into the ELSE block.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220726045828.53697-4-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/kvm64.c | 22 +++++++++++-----------
12
1 file changed, 11 insertions(+), 11 deletions(-)
13
14
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/kvm64.c
17
+++ b/target/arm/kvm64.c
18
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
19
err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
20
ARM64_SYS_REG(3, 3, 9, 12, 0));
21
}
22
- }
23
24
- if (sve_supported) {
25
- /*
26
- * There is a range of kernels between kernel commit 73433762fcae
27
- * and f81cb2c3ad41 which have a bug where the kernel doesn't expose
28
- * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
29
- * SVE support, which resulted in an error rather than RAZ.
30
- * So only read the register if we set KVM_ARM_VCPU_SVE above.
31
- */
32
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
33
- ARM64_SYS_REG(3, 0, 0, 4, 4));
34
+ if (sve_supported) {
35
+ /*
36
+ * There is a range of kernels between kernel commit 73433762fcae
37
+ * and f81cb2c3ad41 which have a bug where the kernel doesn't
38
+ * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
39
+ * enabled SVE support, which resulted in an error rather than RAZ.
40
+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
41
+ */
42
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
43
+ ARM64_SYS_REG(3, 0, 0, 4, 4));
44
+ }
45
}
46
47
kvm_arm_destroy_scratch_host_vcpu(fdarray);
48
--
49
2.25.1
diff view generated by jsdifflib