| 1 | Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code. | 1 | v2: drop a couple of RTH's patches that he wants to rework. |
|---|---|---|---|
| 2 | 2 | ||
| 3 | -- PMM | 3 | The following changes since commit 0266c739abbed804deabb4ccde2aa449466ac3b4: |
| 4 | 4 | ||
| 5 | The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236: | 5 | Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-feb-14-2019' into staging (2019-02-14 18:33:00 +0000) |
| 6 | |||
| 7 | Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700) | ||
| 8 | 6 | ||
| 9 | are available in the Git repository at: | 7 | are available in the Git repository at: |
| 10 | 8 | ||
| 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801 | 9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190215 |
| 12 | 10 | ||
| 13 | for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc: | 11 | for you to fetch changes up to 0f8b09b22234460cb5b8766a25066cf6b5f06842: |
| 14 | 12 | ||
| 15 | target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100) | 13 | gdbstub: Send a reply to the vKill packet. (2019-02-15 09:56:41 +0000) |
| 16 | 14 | ||
| 17 | ---------------------------------------------------------------- | 15 | ---------------------------------------------------------------- |
| 18 | target-arm queue: | 16 | target-arm queue: |
| 19 | * Fix KVM SVE ID register probe code | 17 | * gdbstub: Send a reply to the vKill packet |
| 18 | * Improve codegen for neon min/max and saturating arithmetic | ||
| 19 | * Fix a bug in clearing FPSCR exception status bits | ||
| 20 | * hw/arm/armsse: Fix miswiring of expansion IRQs | ||
| 21 | * hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 | ||
| 22 | * MAINTAINERS: Remove Peter Crosthwaite from various entries | ||
| 23 | * arm: Allow system registers for KVM guests to be changed by QEMU code | ||
| 24 | * linux-user: support HWCAP_CPUID which exposes ID registers to user code | ||
| 25 | * Fix bug in 128-bit cmpxchg for BE Arm guests | ||
| 26 | * Implement (no-op) HACR_EL2 | ||
| 27 | * Fix CRn to be 14 for PMEVTYPER/PMEVCNTR | ||
| 20 | 28 | ||
| 21 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
| 22 | Richard Henderson (3): | 30 | Aaron Lindsay OS (1): |
| 23 | target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features | 31 | target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR |
| 24 | target/arm: Set KVM_ARM_VCPU_SVE while probing the host | ||
| 25 | target/arm: Move sve probe inside kvm >= 4.15 branch | ||
| 26 | 32 | ||
| 27 | target/arm/kvm64.c | 45 ++++++++++++++++++++++----------------------- | 33 | Alex Bennée (5): |
| 28 | 1 file changed, 22 insertions(+), 23 deletions(-) | 34 | target/arm: relax permission checks for HWCAP_CPUID registers |
| 35 | target/arm: expose CPUID registers to userspace | ||
| 36 | target/arm: expose MPIDR_EL1 to userspace | ||
| 37 | target/arm: expose remaining CPUID registers as RAZ | ||
| 38 | linux-user/elfload: enable HWCAP_CPUID for AArch64 | ||
| 39 | |||
| 40 | Catherine Ho (1): | ||
| 41 | target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be | ||
| 42 | |||
| 43 | Peter Maydell (5): | ||
| 44 | target/arm: Implement HACR_EL2 | ||
| 45 | arm: Allow system registers for KVM guests to be changed by QEMU code | ||
| 46 | MAINTAINERS: Remove Peter Crosthwaite from various entries | ||
| 47 | hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 | ||
| 48 | hw/arm/armsse: Fix miswiring of expansion IRQs | ||
| 49 | |||
| 50 | Richard Henderson (12): | ||
| 51 | target/arm: Rely on optimization within tcg_gen_gvec_or | ||
| 52 | target/arm: Use vector minmax expanders for aarch64 | ||
| 53 | target/arm: Use vector minmax expanders for aarch32 | ||
| 54 | target/arm: Use tcg integer min/max primitives for neon | ||
| 55 | target/arm: Remove neon min/max helpers | ||
| 56 | target/arm: Fix vfp_gdb_get/set_reg vs FPSCR | ||
| 57 | target/arm: Fix arm_cpu_dump_state vs FPSCR | ||
| 58 | target/arm: Split out flags setting from vfp compares | ||
| 59 | target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR] | ||
| 60 | target/arm: Split out FPSCR.QC to a vector field | ||
| 61 | target/arm: Use vector operations for saturation | ||
| 62 | target/arm: Add missing clear_tail calls | ||
| 63 | |||
| 64 | Sandra Loosemore (1): | ||
| 65 | gdbstub: Send a reply to the vKill packet. | ||
| 66 | |||
| 67 | target/arm/cpu.h | 50 +++++++++- | ||
| 68 | target/arm/helper.h | 45 ++++++--- | ||
| 69 | target/arm/translate.h | 4 + | ||
| 70 | gdbstub.c | 1 + | ||
| 71 | hw/arm/armsse.c | 2 +- | ||
| 72 | hw/intc/armv7m_nvic.c | 4 +- | ||
| 73 | linux-user/elfload.c | 1 + | ||
| 74 | target/arm/helper-a64.c | 4 +- | ||
| 75 | target/arm/helper.c | 228 ++++++++++++++++++++++++++++++++++++--------- | ||
| 76 | target/arm/kvm32.c | 20 +--- | ||
| 77 | target/arm/kvm64.c | 2 + | ||
| 78 | target/arm/machine.c | 2 +- | ||
| 79 | target/arm/neon_helper.c | 14 +-- | ||
| 80 | target/arm/translate-a64.c | 77 ++++++--------- | ||
| 81 | target/arm/translate-sve.c | 6 +- | ||
| 82 | target/arm/translate.c | 219 ++++++++++++++++++++++++++++++++++--------- | ||
| 83 | target/arm/vec_helper.c | 134 +++++++++++++++++++++++++- | ||
| 84 | MAINTAINERS | 4 - | ||
| 85 | 18 files changed, 622 insertions(+), 195 deletions(-) | ||
| 86 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Indication for support for SVE will not depend on whether we | ||
| 4 | perform the query on the main kvm_state or the temp vcpu. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-2-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 2 +- | ||
| 12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | } | ||
| 20 | } | ||
| 21 | |||
| 22 | - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; | ||
| 23 | + sve_supported = kvm_arm_sve_supported(); | ||
| 24 | |||
| 25 | /* Add feature bits that can't appear until after VCPU init. */ | ||
| 26 | if (sve_supported) { | ||
| 27 | -- | ||
| 28 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Because we weren't setting this flag, our probe of ID_AA64ZFR0 | ||
| 4 | was always returning zero. This also obviates the adjustment | ||
| 5 | of ID_AA64PFR0, which had sanitized the SVE field. | ||
| 6 | |||
| 7 | The effects of the bug are not visible, because the only thing that | ||
| 8 | ID_AA64ZFR0 is used for within qemu at present is tcg translation. | ||
| 9 | The other tests for SVE within KVM are via ID_AA64PFR0.SVE. | ||
| 10 | |||
| 11 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Message-id: 20220726045828.53697-3-richard.henderson@linaro.org | ||
| 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | --- | ||
| 17 | target/arm/kvm64.c | 27 +++++++++++++-------------- | ||
| 18 | 1 file changed, 13 insertions(+), 14 deletions(-) | ||
| 19 | |||
| 20 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/target/arm/kvm64.c | ||
| 23 | +++ b/target/arm/kvm64.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 25 | bool sve_supported; | ||
| 26 | bool pmu_supported = false; | ||
| 27 | uint64_t features = 0; | ||
| 28 | - uint64_t t; | ||
| 29 | int err; | ||
| 30 | |||
| 31 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | ||
| 32 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 33 | struct kvm_vcpu_init init = { .target = -1, }; | ||
| 34 | |||
| 35 | /* | ||
| 36 | - * Ask for Pointer Authentication if supported. We can't play the | ||
| 37 | - * SVE trick of synthesising the ID reg as KVM won't tell us | ||
| 38 | - * whether we have the architected or IMPDEF version of PAuth, so | ||
| 39 | - * we have to use the actual ID regs. | ||
| 40 | + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, | ||
| 41 | + * which is otherwise RAZ. | ||
| 42 | + */ | ||
| 43 | + sve_supported = kvm_arm_sve_supported(); | ||
| 44 | + if (sve_supported) { | ||
| 45 | + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; | ||
| 46 | + } | ||
| 47 | + | ||
| 48 | + /* | ||
| 49 | + * Ask for Pointer Authentication if supported, so that we get | ||
| 50 | + * the unsanitized field values for AA64ISAR1_EL1. | ||
| 51 | */ | ||
| 52 | if (kvm_arm_pauth_supported()) { | ||
| 53 | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | | ||
| 54 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 55 | } | ||
| 56 | } | ||
| 57 | |||
| 58 | - sve_supported = kvm_arm_sve_supported(); | ||
| 59 | - | ||
| 60 | - /* Add feature bits that can't appear until after VCPU init. */ | ||
| 61 | if (sve_supported) { | ||
| 62 | - t = ahcf->isar.id_aa64pfr0; | ||
| 63 | - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
| 64 | - ahcf->isar.id_aa64pfr0 = t; | ||
| 65 | - | ||
| 66 | /* | ||
| 67 | * There is a range of kernels between kernel commit 73433762fcae | ||
| 68 | * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 69 | * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 70 | - * SVE support, so we only read it here, rather than together with all | ||
| 71 | - * the other ID registers earlier. | ||
| 72 | + * SVE support, which resulted in an error rather than RAZ. | ||
| 73 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 74 | */ | ||
| 75 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 76 | ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 77 | -- | ||
| 78 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The test for the IF block indicates no ID registers are exposed, much | ||
| 4 | less host support for SVE. Move the SVE probe into the ELSE block. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-4-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 22 +++++++++++----------- | ||
| 12 | 1 file changed, 11 insertions(+), 11 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, | ||
| 20 | ARM64_SYS_REG(3, 3, 9, 12, 0)); | ||
| 21 | } | ||
| 22 | - } | ||
| 23 | |||
| 24 | - if (sve_supported) { | ||
| 25 | - /* | ||
| 26 | - * There is a range of kernels between kernel commit 73433762fcae | ||
| 27 | - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 28 | - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 29 | - * SVE support, which resulted in an error rather than RAZ. | ||
| 30 | - * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 31 | - */ | ||
| 32 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 33 | - ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 34 | + if (sve_supported) { | ||
| 35 | + /* | ||
| 36 | + * There is a range of kernels between kernel commit 73433762fcae | ||
| 37 | + * and f81cb2c3ad41 which have a bug where the kernel doesn't | ||
| 38 | + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has | ||
| 39 | + * enabled SVE support, which resulted in an error rather than RAZ. | ||
| 40 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 41 | + */ | ||
| 42 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 43 | + ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 44 | + } | ||
| 45 | } | ||
| 46 | |||
| 47 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
| 48 | -- | ||
| 49 | 2.25.1 | diff view generated by jsdifflib |