| 1 | Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code. | 1 | target-arm queue: this clears out a bunch of patches I'd sent over |
|---|---|---|---|
| 2 | the last coupled of weeks that have now got reviewed. Mostly | ||
| 3 | this is MPS2 device support improvements, put there is also | ||
| 4 | more of the incremental work towards supporting AArch32 Hyp mode, | ||
| 5 | a floating point bugfix, and the raspi framebuffer viewport support. | ||
| 2 | 6 | ||
| 7 | v2 fixes a "variable used uninitialized" error in a15mpcore.c. | ||
| 8 | |||
| 9 | thanks | ||
| 3 | -- PMM | 10 | -- PMM |
| 4 | 11 | ||
| 5 | The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236: | ||
| 6 | 12 | ||
| 7 | Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700) | 13 | The following changes since commit 6b699ae1be9f257478d5eca7ef65dcea270a2796: |
| 14 | |||
| 15 | tests/vm: Increase timeout waiting for VM to boot to 5 minutes (2018-08-24 11:31:28 +0100) | ||
| 8 | 16 | ||
| 9 | are available in the Git repository at: | 17 | are available in the Git repository at: |
| 10 | 18 | ||
| 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801 | 19 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180824-1 |
| 12 | 20 | ||
| 13 | for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc: | 21 | for you to fetch changes up to 239cb6feb298a31faa40b7e97ced107bf9c2f2bf: |
| 14 | 22 | ||
| 15 | target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100) | 23 | hw/arm/mps2: Fix ID register errors on AN511 and AN385 (2018-08-24 13:17:50 +0100) |
| 16 | 24 | ||
| 17 | ---------------------------------------------------------------- | 25 | ---------------------------------------------------------------- |
| 18 | target-arm queue: | 26 | target-arm queue: |
| 19 | * Fix KVM SVE ID register probe code | 27 | * Fix rounding errors in scaling float-to-int and int-to-float operations |
| 28 | * Connect virtualization-related IRQs and memory regions of GICv2 | ||
| 29 | in boards that use Cortex-A7 or Cortex-A15 | ||
| 30 | * Support taking exceptions to AArch32 Hyp mode | ||
| 31 | * Clear CPSR.IL and CPSR.J on 32-bit exception entry | ||
| 32 | (a minor bug fix that won't affect non-buggy guest code) | ||
| 33 | * mps2-an505: Implement various missing devices: | ||
| 34 | dual timer, watchdogs, counters in the FPGAIO registers, | ||
| 35 | some missing ID/control registers, TrustZone Master Security | ||
| 36 | Controllers, PL081 DMA controllers, PL022 SPI controllers | ||
| 37 | * correct ID register values for mps2-an385, -an511, -an505 | ||
| 38 | * fix some hardcoded tabs in untouched backwaters of the | ||
| 39 | target/arm codebase | ||
| 40 | * raspi: Refactor framebuffer property handling code and implement | ||
| 41 | support for the virtual framebuffer/viewport | ||
| 20 | 42 | ||
| 21 | ---------------------------------------------------------------- | 43 | ---------------------------------------------------------------- |
| 22 | Richard Henderson (3): | 44 | Peter Maydell (48): |
| 23 | target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features | 45 | hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes large |
| 24 | target/arm: Set KVM_ARM_VCPU_SVE while probing the host | 46 | hw/arm/vexpress: Connect VIRQ and VFIQ |
| 25 | target/arm: Move sve probe inside kvm >= 4.15 branch | 47 | hw/arm/highbank: Connect VIRQ and VFIQ |
| 48 | hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ | ||
| 49 | hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ | ||
| 50 | hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up | ||
| 51 | hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3 | ||
| 52 | hw/arm/vexpress: Add "virtualization" property controlling presence of EL2 | ||
| 53 | target/arm: Implement RAZ/WI HACTLR2 | ||
| 54 | target/arm: Implement AArch32 HCR and HCR2 | ||
| 55 | target/arm: Factor out code for taking an AArch32 exception | ||
| 56 | target/arm: Implement support for taking exceptions to Hyp mode | ||
| 57 | target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry | ||
| 58 | hw/arm/boot: AArch32 kernels should be started in Hyp mode if available | ||
| 59 | hw/misc/mps2-fpgaio: Implement 1Hz and 100Hz counters | ||
| 60 | hw/misc/mps2-fpgaio: Implement PSCNTR and COUNTER | ||
| 61 | hw/timer/cmsdk-apb-dualtimer: Implement CMSDK dual timer module | ||
| 62 | hw/arm/iotkit: Wire up the dualtimer | ||
| 63 | hw/arm/mps2: Wire up dual-timer in mps2-an385 and mps2-an511 | ||
| 64 | hw/arm/iotkit: Wire up the watchdogs | ||
| 65 | hw/arm/iotkit: Wire up the S32KTIMER | ||
| 66 | hw/misc/iotkit-sysctl: Implement IoTKit system control element | ||
| 67 | hw/misc/iotkit-sysinfo: Implement IoTKit system information block | ||
| 68 | hw/misc/iotkit: Wire up the sysctl and sysinfo register blocks | ||
| 69 | hw/misc/tz-msc: Model TrustZone Master Security Controller | ||
| 70 | hw/misc/iotkit-secctl: Wire up registers for controlling MSCs | ||
| 71 | hw/arm/iotkit: Wire up the lines for MSCs | ||
| 72 | hw/arm/mps2-tz: Create PL081s and MSCs | ||
| 73 | hw/ssi/pl022: Allow use as embedded-struct device | ||
| 74 | hw/ssi/pl022: Set up reset function in class init | ||
| 75 | hw/ssi/pl022: Don't directly call vmstate_register() | ||
| 76 | hw/ssi/pl022: Use DeviceState::realize rather than SysBusDevice::init | ||
| 77 | hw/ssi/pl022: Correct wrong value for PL022_INT_RT | ||
| 78 | hw/ssi/pl022: Correct wrong DMACR and ICR handling | ||
| 79 | hw/arm/mps2-tz: Instantiate SPI controllers | ||
| 80 | hw/arm/mps2-tz: Fix MPS2 SCC config register values | ||
| 81 | target/arm: Untabify translate.c | ||
| 82 | target/arm: Untabify iwmmxt_helper.c | ||
| 83 | target/arm: Remove a handful of stray tabs | ||
| 84 | hw/misc/bcm2835_fb: Move config fields to their own struct | ||
| 85 | hw/misc/bcm2835_property: Track fb settings using BCM2835FBConfig | ||
| 86 | hw/display/bcm2835_fb: Drop unused size and pitch fields | ||
| 87 | hw/display/bcm2835_fb: Reset resolution, etc correctly | ||
| 88 | hw/display/bcm2835_fb: Abstract out calculation of pitch, size | ||
| 89 | hw/display/bcm2835_fb: Fix handling of virtual framebuffer | ||
| 90 | hw/display/bcm2835_fb: Validate config settings | ||
| 91 | hw/display/bcm2835_fb: Validate bcm2835_fb_mbox_push() config | ||
| 92 | hw/arm/mps2: Fix ID register errors on AN511 and AN385 | ||
| 26 | 93 | ||
| 27 | target/arm/kvm64.c | 45 ++++++++++++++++++++++----------------------- | 94 | Richard Henderson (4): |
| 28 | 1 file changed, 22 insertions(+), 23 deletions(-) | 95 | softfloat: Add scaling int-to-float routines |
| 96 | softfloat: Add scaling float-to-int routines | ||
| 97 | target/arm: Use the int-to-float-scale softfloat routines | ||
| 98 | target/arm: Use the float-to-int-scale softfloat routines | ||
| 99 | |||
| 100 | hw/misc/Makefile.objs | 3 + | ||
| 101 | hw/timer/Makefile.objs | 1 + | ||
| 102 | include/fpu/softfloat.h | 169 +++++++--- | ||
| 103 | include/hw/arm/iotkit.h | 25 +- | ||
| 104 | include/hw/display/bcm2835_fb.h | 59 +++- | ||
| 105 | include/hw/misc/iotkit-secctl.h | 14 + | ||
| 106 | include/hw/misc/iotkit-sysctl.h | 49 +++ | ||
| 107 | include/hw/misc/iotkit-sysinfo.h | 37 +++ | ||
| 108 | include/hw/misc/mps2-fpgaio.h | 10 + | ||
| 109 | include/hw/misc/tz-msc.h | 79 +++++ | ||
| 110 | include/hw/ssi/pl022.h | 51 +++ | ||
| 111 | include/hw/timer/cmsdk-apb-dualtimer.h | 72 ++++ | ||
| 112 | target/arm/cpu.h | 16 +- | ||
| 113 | fpu/softfloat.c | 579 ++++++++++++++++++++++++++------- | ||
| 114 | hw/arm/boot.c | 11 + | ||
| 115 | hw/arm/fsl-imx6ul.c | 4 + | ||
| 116 | hw/arm/fsl-imx7.c | 4 + | ||
| 117 | hw/arm/highbank.c | 6 + | ||
| 118 | hw/arm/iotkit.c | 114 ++++++- | ||
| 119 | hw/arm/mps2-tz.c | 142 +++++++- | ||
| 120 | hw/arm/mps2.c | 17 +- | ||
| 121 | hw/arm/vexpress.c | 64 +++- | ||
| 122 | hw/cpu/a15mpcore.c | 31 +- | ||
| 123 | hw/display/bcm2835_fb.c | 218 ++++++++----- | ||
| 124 | hw/intc/arm_gic.c | 2 +- | ||
| 125 | hw/misc/bcm2835_property.c | 123 ++++--- | ||
| 126 | hw/misc/iotkit-secctl.c | 73 ++++- | ||
| 127 | hw/misc/iotkit-sysctl.c | 261 +++++++++++++++ | ||
| 128 | hw/misc/iotkit-sysinfo.c | 128 ++++++++ | ||
| 129 | hw/misc/mps2-fpgaio.c | 146 ++++++++- | ||
| 130 | hw/misc/tz-msc.c | 308 ++++++++++++++++++ | ||
| 131 | hw/ssi/pl022.c | 57 ++-- | ||
| 132 | hw/timer/cmsdk-apb-dualtimer.c | 515 +++++++++++++++++++++++++++++ | ||
| 133 | target/arm/arm-semi.c | 2 +- | ||
| 134 | target/arm/helper.c | 342 +++++++++++++------ | ||
| 135 | target/arm/iwmmxt_helper.c | 234 ++++++------- | ||
| 136 | target/arm/translate.c | 122 +++---- | ||
| 137 | MAINTAINERS | 10 + | ||
| 138 | default-configs/arm-softmmu.mak | 4 + | ||
| 139 | hw/misc/trace-events | 16 + | ||
| 140 | hw/timer/trace-events | 5 + | ||
| 141 | 41 files changed, 3405 insertions(+), 718 deletions(-) | ||
| 142 | create mode 100644 include/hw/misc/iotkit-sysctl.h | ||
| 143 | create mode 100644 include/hw/misc/iotkit-sysinfo.h | ||
| 144 | create mode 100644 include/hw/misc/tz-msc.h | ||
| 145 | create mode 100644 include/hw/ssi/pl022.h | ||
| 146 | create mode 100644 include/hw/timer/cmsdk-apb-dualtimer.h | ||
| 147 | create mode 100644 hw/misc/iotkit-sysctl.c | ||
| 148 | create mode 100644 hw/misc/iotkit-sysinfo.c | ||
| 149 | create mode 100644 hw/misc/tz-msc.c | ||
| 150 | create mode 100644 hw/timer/cmsdk-apb-dualtimer.c | ||
| 151 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Indication for support for SVE will not depend on whether we | ||
| 4 | perform the query on the main kvm_state or the temp vcpu. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-2-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 2 +- | ||
| 12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | } | ||
| 20 | } | ||
| 21 | |||
| 22 | - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; | ||
| 23 | + sve_supported = kvm_arm_sve_supported(); | ||
| 24 | |||
| 25 | /* Add feature bits that can't appear until after VCPU init. */ | ||
| 26 | if (sve_supported) { | ||
| 27 | -- | ||
| 28 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Because we weren't setting this flag, our probe of ID_AA64ZFR0 | ||
| 4 | was always returning zero. This also obviates the adjustment | ||
| 5 | of ID_AA64PFR0, which had sanitized the SVE field. | ||
| 6 | |||
| 7 | The effects of the bug are not visible, because the only thing that | ||
| 8 | ID_AA64ZFR0 is used for within qemu at present is tcg translation. | ||
| 9 | The other tests for SVE within KVM are via ID_AA64PFR0.SVE. | ||
| 10 | |||
| 11 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Message-id: 20220726045828.53697-3-richard.henderson@linaro.org | ||
| 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | --- | ||
| 17 | target/arm/kvm64.c | 27 +++++++++++++-------------- | ||
| 18 | 1 file changed, 13 insertions(+), 14 deletions(-) | ||
| 19 | |||
| 20 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/target/arm/kvm64.c | ||
| 23 | +++ b/target/arm/kvm64.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 25 | bool sve_supported; | ||
| 26 | bool pmu_supported = false; | ||
| 27 | uint64_t features = 0; | ||
| 28 | - uint64_t t; | ||
| 29 | int err; | ||
| 30 | |||
| 31 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | ||
| 32 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 33 | struct kvm_vcpu_init init = { .target = -1, }; | ||
| 34 | |||
| 35 | /* | ||
| 36 | - * Ask for Pointer Authentication if supported. We can't play the | ||
| 37 | - * SVE trick of synthesising the ID reg as KVM won't tell us | ||
| 38 | - * whether we have the architected or IMPDEF version of PAuth, so | ||
| 39 | - * we have to use the actual ID regs. | ||
| 40 | + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, | ||
| 41 | + * which is otherwise RAZ. | ||
| 42 | + */ | ||
| 43 | + sve_supported = kvm_arm_sve_supported(); | ||
| 44 | + if (sve_supported) { | ||
| 45 | + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; | ||
| 46 | + } | ||
| 47 | + | ||
| 48 | + /* | ||
| 49 | + * Ask for Pointer Authentication if supported, so that we get | ||
| 50 | + * the unsanitized field values for AA64ISAR1_EL1. | ||
| 51 | */ | ||
| 52 | if (kvm_arm_pauth_supported()) { | ||
| 53 | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | | ||
| 54 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 55 | } | ||
| 56 | } | ||
| 57 | |||
| 58 | - sve_supported = kvm_arm_sve_supported(); | ||
| 59 | - | ||
| 60 | - /* Add feature bits that can't appear until after VCPU init. */ | ||
| 61 | if (sve_supported) { | ||
| 62 | - t = ahcf->isar.id_aa64pfr0; | ||
| 63 | - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
| 64 | - ahcf->isar.id_aa64pfr0 = t; | ||
| 65 | - | ||
| 66 | /* | ||
| 67 | * There is a range of kernels between kernel commit 73433762fcae | ||
| 68 | * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 69 | * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 70 | - * SVE support, so we only read it here, rather than together with all | ||
| 71 | - * the other ID registers earlier. | ||
| 72 | + * SVE support, which resulted in an error rather than RAZ. | ||
| 73 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 74 | */ | ||
| 75 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 76 | ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 77 | -- | ||
| 78 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The test for the IF block indicates no ID registers are exposed, much | ||
| 4 | less host support for SVE. Move the SVE probe into the ELSE block. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220726045828.53697-4-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/kvm64.c | 22 +++++++++++----------- | ||
| 12 | 1 file changed, 11 insertions(+), 11 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/kvm64.c | ||
| 17 | +++ b/target/arm/kvm64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 19 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, | ||
| 20 | ARM64_SYS_REG(3, 3, 9, 12, 0)); | ||
| 21 | } | ||
| 22 | - } | ||
| 23 | |||
| 24 | - if (sve_supported) { | ||
| 25 | - /* | ||
| 26 | - * There is a range of kernels between kernel commit 73433762fcae | ||
| 27 | - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose | ||
| 28 | - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled | ||
| 29 | - * SVE support, which resulted in an error rather than RAZ. | ||
| 30 | - * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 31 | - */ | ||
| 32 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 33 | - ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 34 | + if (sve_supported) { | ||
| 35 | + /* | ||
| 36 | + * There is a range of kernels between kernel commit 73433762fcae | ||
| 37 | + * and f81cb2c3ad41 which have a bug where the kernel doesn't | ||
| 38 | + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has | ||
| 39 | + * enabled SVE support, which resulted in an error rather than RAZ. | ||
| 40 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 41 | + */ | ||
| 42 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 43 | + ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 44 | + } | ||
| 45 | } | ||
| 46 | |||
| 47 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
| 48 | -- | ||
| 49 | 2.25.1 | diff view generated by jsdifflib |