[PULL 0/3] target-arm queue
[Qemu-devel] [PULL v2 00/13] target-arm queue
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Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code.
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A random mix of items here, nothing very major. v2 is just
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squashing in the fix for the clang unused-function error.
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thanks
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-- PMM
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-- PMM
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The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236:
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Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700)
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The following changes since commit d0dff238a87fa81393ed72754d4dc8b09e50b08b:
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are available in the Git repository at:
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Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170206' into staging (2017-02-07 15:29:26 +0000)
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801
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are available in the git repository at:
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for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170207-1
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target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100)
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for you to fetch changes up to aecfbbc97a2e52bbee34a53c32f961a182046a95:
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stellaris: Use the 'unimplemented' device for parts we don't implement (2017-02-07 18:55:15 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm:
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* Fix KVM SVE ID register probe code
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* new "unimplemented" device for stubbing out devices in a
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system model so accesses can be logged
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* stellaris: document the SoC memory map
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* arm: create instruction syndromes for AArch32 data aborts
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* arm: Correctly handle watchpoints for BE32 CPUs
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* Fix Thumb-1 BE32 execution and disassembly
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* arm: Add cfgend parameter for ARM CPU selection
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* sd: sdhci: check data length during dma_memory_read
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* aspeed: add a watchdog controller
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* integratorcp: adding vmstate for save/restore
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (3):
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Cédric Le Goater (2):
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target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
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wdt: Add Aspeed watchdog device model
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target/arm: Set KVM_ARM_VCPU_SVE while probing the host
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aspeed: add a watchdog controller
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target/arm: Move sve probe inside kvm >= 4.15 branch
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target/arm/kvm64.c | 45 ++++++++++++++++++++++-----------------------
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Julian Brown (4):
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1 file changed, 22 insertions(+), 23 deletions(-)
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hw/arm/integratorcp: Support specifying features via -cpu
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target/arm: Add cfgend parameter for ARM CPU selection.
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Fix Thumb-1 BE32 execution and disassembly.
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arm: Correctly handle watchpoints for BE32 CPUs
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Pavel Dovgalyuk (1):
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integratorcp: adding vmstate for save/restore
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Peter Maydell (5):
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target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
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target/arm: A32, T32: Create Instruction Syndromes for Data Aborts
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stellaris: Document memory map and which SoC devices are unimplemented
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hw/misc: New "unimplemented" sysbus device
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stellaris: Use the 'unimplemented' device for parts we don't implement
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Prasad J Pandit (1):
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sd: sdhci: check data length during dma_memory_read
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hw/misc/Makefile.objs | 2 +
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hw/watchdog/Makefile.objs | 1 +
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include/disas/bfd.h | 7 ++
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include/hw/arm/aspeed_soc.h | 2 +
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include/hw/misc/unimp.h | 39 +++++++
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include/hw/watchdog/wdt_aspeed.h | 32 ++++++
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include/qom/cpu.h | 3 +
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target/arm/arm_ldst.h | 10 +-
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target/arm/cpu.h | 7 ++
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target/arm/internals.h | 5 +
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target/arm/translate.h | 14 +++
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disas.c | 1 +
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exec.c | 1 +
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hw/arm/aspeed_soc.c | 13 +++
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hw/arm/integratorcp.c | 78 +++++++++++++-
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hw/arm/stellaris.c | 48 +++++++++
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hw/misc/unimp.c | 107 +++++++++++++++++++
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hw/sd/sdhci.c | 2 +-
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hw/watchdog/wdt_aspeed.c | 225 +++++++++++++++++++++++++++++++++++++++
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qom/cpu.c | 6 ++
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target/arm/cpu.c | 39 +++++++
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target/arm/op_helper.c | 22 ++++
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target/arm/translate-a64.c | 14 ---
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target/arm/translate.c | 193 ++++++++++++++++++++++++---------
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24 files changed, 801 insertions(+), 70 deletions(-)
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create mode 100644 include/hw/misc/unimp.h
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create mode 100644 include/hw/watchdog/wdt_aspeed.h
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create mode 100644 hw/misc/unimp.c
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create mode 100644 hw/watchdog/wdt_aspeed.c
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diff view generated by jsdifflib
[PULL 1/3] target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Indication for support for SVE will not depend on whether we
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perform the query on the main kvm_state or the temp vcpu.
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-2-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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}
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}
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- sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
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+ sve_supported = kvm_arm_sve_supported();
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/* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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--
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2.25.1
diff view generated by jsdifflib
[PULL 2/3] target/arm: Set KVM_ARM_VCPU_SVE while probing the host
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Because we weren't setting this flag, our probe of ID_AA64ZFR0
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was always returning zero. This also obviates the adjustment
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of ID_AA64PFR0, which had sanitized the SVE field.
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The effects of the bug are not visible, because the only thing that
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ID_AA64ZFR0 is used for within qemu at present is tcg translation.
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The other tests for SVE within KVM are via ID_AA64PFR0.SVE.
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Reported-by: Zenghui Yu <yuzenghui@huawei.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-3-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 27 +++++++++++++--------------
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1 file changed, 13 insertions(+), 14 deletions(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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bool sve_supported;
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bool pmu_supported = false;
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uint64_t features = 0;
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- uint64_t t;
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int err;
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/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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struct kvm_vcpu_init init = { .target = -1, };
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/*
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- * Ask for Pointer Authentication if supported. We can't play the
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- * SVE trick of synthesising the ID reg as KVM won't tell us
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- * whether we have the architected or IMPDEF version of PAuth, so
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- * we have to use the actual ID regs.
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+ * Ask for SVE if supported, so that we can query ID_AA64ZFR0,
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+ * which is otherwise RAZ.
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+ */
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+ sve_supported = kvm_arm_sve_supported();
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+ if (sve_supported) {
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+ init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
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+ }
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+
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+ /*
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+ * Ask for Pointer Authentication if supported, so that we get
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+ * the unsanitized field values for AA64ISAR1_EL1.
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*/
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if (kvm_arm_pauth_supported()) {
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init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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}
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}
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- sve_supported = kvm_arm_sve_supported();
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-
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- /* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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- t = ahcf->isar.id_aa64pfr0;
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- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
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- ahcf->isar.id_aa64pfr0 = t;
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-
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/*
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* There is a range of kernels between kernel commit 73433762fcae
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* and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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* SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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- * SVE support, so we only read it here, rather than together with all
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- * the other ID registers earlier.
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+ * SVE support, which resulted in an error rather than RAZ.
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+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
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*/
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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ARM64_SYS_REG(3, 0, 0, 4, 4));
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--
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2.25.1
diff view generated by jsdifflib
[PULL 3/3] target/arm: Move sve probe inside kvm >= 4.15 branch
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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The test for the IF block indicates no ID registers are exposed, much
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less host support for SVE. Move the SVE probe into the ELSE block.
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-4-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 22 +++++++++++-----------
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1 file changed, 11 insertions(+), 11 deletions(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
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ARM64_SYS_REG(3, 3, 9, 12, 0));
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}
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- }
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- if (sve_supported) {
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- /*
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- * There is a range of kernels between kernel commit 73433762fcae
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- * and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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- * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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- * SVE support, which resulted in an error rather than RAZ.
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- * So only read the register if we set KVM_ARM_VCPU_SVE above.
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- */
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- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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- ARM64_SYS_REG(3, 0, 0, 4, 4));
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+ if (sve_supported) {
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+ /*
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+ * There is a range of kernels between kernel commit 73433762fcae
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+ * and f81cb2c3ad41 which have a bug where the kernel doesn't
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+ * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
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+ * enabled SVE support, which resulted in an error rather than RAZ.
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+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
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+ */
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+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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+ ARM64_SYS_REG(3, 0, 0, 4, 4));
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+ }
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}
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kvm_arm_destroy_scratch_host_vcpu(fdarray);
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--
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2.25.1
diff view generated by jsdifflib

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