Since below KVM commit, KVM hided BTS as it's not supported yet.
b9181c8ef356 ("KVM: x86/pmu: Avoid exposing Intel BTS feature")

After below KVM commit, it gave control of MSR_IA32_MISC_ENABLES to userspace.
9fc222967a39 ("KVM: x86: Give host userspace full control of MSR_IA32_MISC_ENABLES")

So qemu takes the responsibility to hide BTS.
Without fix, we get below error in guest kernel:

[] unchecked MSR access error: WRMSR to 0x1d9 (tried to write 0x00000000000001c0) at rIP: 0xffffffffaa070644 (native_write_msr+0x4/0x20)
[] Call Trace:
[]  <TASK>
[]  intel_pmu_enable_bts+0x5d/0x70
[]  bts_event_add+0x77/0x90
[]  event_sched_in.isra.135+0x99/0x1e0

Also setup MISC_ENABLE_EMON bit based on pmu property for consistency.

Tested-by: Xiangfei Ma <xiangfeix.ma@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
---
v2: Some changes based on Like's comments

 target/i386/cpu.c | 7 ++++++-
 target/i386/cpu.h | 6 ++++--
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6a57ef13af86..16cf72f992a3 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5955,7 +5955,12 @@ static void x86_cpu_reset(DeviceState *dev)
         env->tsc = 0;
     }
 
-    env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
+    /* Disable BTS feature which is unsupported on KVM */
+    env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT |
+                                MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
+    if (cpu->enable_pmu) {
+        env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_EMON;
+    }
     if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
         env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
     }
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 82004b65b944..7221488f84bc 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -434,8 +434,10 @@ typedef enum X86Seg {
 
 #define MSR_IA32_MISC_ENABLE            0x1a0
 /* Indicates good rep/movs microcode on some processors: */
-#define MSR_IA32_MISC_ENABLE_DEFAULT    1
-#define MSR_IA32_MISC_ENABLE_MWAIT      (1ULL << 18)
+#define MSR_IA32_MISC_ENABLE_DEFAULT     (1ULL << 0)
+#define MSR_IA32_MISC_ENABLE_EMON        (1ULL << 7)
+#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11)
+#define MSR_IA32_MISC_ENABLE_MWAIT       (1ULL << 18)
 
 #define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))
 #define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)
-- 
2.25.1