Some arm patches before softfreeze. These are all bug fixes.

-- PMM

The following changes since commit 0ebf76aae58324b8f7bf6af798696687f5f4c2a9:

Merge tag 'nvme-next-pull-request' of git://git.infradead.org/qemu-nvme into staging (2022-07-15 15:38:13 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220718

for you to fetch changes up to 004c8a8bc569c8b18fca6fc90ffe3223daaf17b7:

Align Raspberry Pi DMA interrupts with Linux DTS (2022-07-18 13:25:13 +0100)

* hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high

* target/arm: Fill in VL for tbflags when SME enabled and SVE disabled

* target/arm: Fix aarch64_sve_change_el for SME

* linux-user/aarch64: Do not clear PROT_MTE on mprotect

* target/arm: Honour VTCR_EL2 bits in Secure EL2

* hw/adc: Fix CONV bit in NPCM7XX ADC CON register

* hw/adc: Make adci[*] R/W in NPCM7XX ADC

* target/arm: Don't set syndrome ISS for loads and stores with writeback

* Align Raspberry Pi DMA interrupts with Linux DTS

Andrey Makarov (1):

Align Raspberry Pi DMA interrupts with Linux DTS

Hao Wu (2):

hw/adc: Fix CONV bit in NPCM7XX ADC CON register

hw/adc: Make adci[*] R/W in NPCM7XX ADC

In the M-profile Arm ARM, rule R_CVJS defines when an interrupt should

be set to the Pending state:

A) when the input line is high and the interrupt is not Active

B) when the input line transitions from low to high and the interrupt

is Active

(Note that the first of these is an ongoing condition, and the

second is a point-in-time event.)

This can be rephrased as:

1 when the line goes from low to high, set Pending

2 when Active goes from 1 to 0, if line is high then set Pending

3 ignore attempts to clear Pending when the line is high

and Active is 0

where 1 covers both B and one of the "transition into condition A"

cases, 2 deals with the other "transition into condition A"

possibility, and 3 is "don't drop Pending if we're already in

condition A". Transitions out of condition A don't affect Pending

state.

We handle case 1 in set_irq_level(). For an interrupt (as opposed

to other kinds of exception) the only place where we clear Active

is in armv7m_nvic_complete_irq(), where we handle case 2 by

checking for whether we need to re-pend the exception. For case 3,

the only places where we clear Pending state on an interrupt are in

armv7m_nvic_acknowledge_irq() (where we are setting Active so it

doesn't count) and for writes to NVIC_ICPRn.

It is the "write to NVIC_ICPRn" case that we missed: we must ignore

this if the input line is high and the interrupt is not Active.

(This required behaviour is differently and perhaps more clearly

stated in the v7M Arm ARM, which has pseudocode in section B3.4.1

that implies it.)

Reported-by: Igor Kotrasiński <i.kotrasinsk@samsung.com>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20220628154724.3297442-1-peter.maydell@linaro.org

---

hw/intc/armv7m_nvic.c | 9 ++++++++-

1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

--- a/hw/intc/armv7m_nvic.c

+++ b/hw/intc/armv7m_nvic.c

@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,

startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */

for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {

+ /*

+ * Note that if the input line is still held high and the interrupt

+ * is not active then rule R_CVJS requires that the Pending state

+ * remains set; in that case we mustn't let it be cleared.

+ */

if (value & (1 << i) &&

- (attrs.secure || s->itns[startvec + i])) {

+ (attrs.secure || s->itns[startvec + i]) &&

+ !(setval == 0 && s->vectors[startvec + i].level &&

+ !s->vectors[startvec + i].active)) {

s->vectors[startvec + i].pending = setval;

}

2.25.1