Choose some instructions to test:
- FCMP.cond.S
- cond: ceq clt cle cne seq slt sle sne
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
tests/tcg/loongarch64/Makefile.target | 1 +
tests/tcg/loongarch64/test_fpcom.c | 37 +++++++++++++++++++++++++++
2 files changed, 38 insertions(+)
create mode 100644 tests/tcg/loongarch64/test_fpcom.c
diff --git a/tests/tcg/loongarch64/Makefile.target b/tests/tcg/loongarch64/Makefile.target
index 59d564725a..b320d9fd9c 100644
--- a/tests/tcg/loongarch64/Makefile.target
+++ b/tests/tcg/loongarch64/Makefile.target
@@ -13,5 +13,6 @@ LDFLAGS+=-lm
LOONGARCH64_TESTS = test_bit
LOONGARCH64_TESTS += test_div
LOONGARCH64_TESTS += test_fclass
+LOONGARCH64_TESTS += test_fpcom
TESTS += $(LOONGARCH64_TESTS)
diff --git a/tests/tcg/loongarch64/test_fpcom.c b/tests/tcg/loongarch64/test_fpcom.c
new file mode 100644
index 0000000000..9e81f767f9
--- /dev/null
+++ b/tests/tcg/loongarch64/test_fpcom.c
@@ -0,0 +1,37 @@
+#include <assert.h>
+
+#define TEST_COMP(N) \
+void test_##N(float fj, float fk) \
+{ \
+ int rd = 0; \
+ \
+ asm volatile("fcmp."#N".s $fcc6,%1,%2\n" \
+ "movcf2gr %0, $fcc6\n" \
+ : "=r"(rd) \
+ : "f"(fj), "f"(fk) \
+ : ); \
+ assert(rd == 1); \
+}
+
+TEST_COMP(ceq)
+TEST_COMP(clt)
+TEST_COMP(cle)
+TEST_COMP(cne)
+TEST_COMP(seq)
+TEST_COMP(slt)
+TEST_COMP(sle)
+TEST_COMP(sne)
+
+int main()
+{
+ test_ceq(0xff700102, 0xff700102);
+ test_clt(0x00730007, 0xff730007);
+ test_cle(0xff70130a, 0xff70130b);
+ test_cne(0x1238acde, 0xff71111f);
+ test_seq(0xff766618, 0xff766619);
+ test_slt(0xff78881c, 0xff78901d);
+ test_sle(0xff780b22, 0xff790b22);
+ test_sne(0xff7bcd25, 0xff7a26cf);
+
+ return 0;
+}
--
2.31.1