On 7/3/22 05:42, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit d495e432c04a6394126c35cf96517749708b410f:
>
> Merge tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu into staging (2022-06-30 22:04:12 +0530)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220703-1
>
> for you to fetch changes up to 435774992e82d2d16f025afbb20b4f7be9b242b0:
>
> target/riscv: Update default priority table for local interrupts (2022-07-03 10:03:20 +1000)
>
> ----------------------------------------------------------------
> Fifth RISC-V PR for QEMU 7.1
>
> * Fix register zero guarding for auipc and lui
> * Ensure bins (mtval) is set correctly
> * Minimize the calls to decode_save_opc
> * Guard against PMP ranges with a negative size
> * Implement mcountinhibit CSR
> * Add support for hpmcounters/hpmevents
> * Improve PMU implenentation
> * Support mcycle/minstret write operation
> * Fixup MSECCFG minimum priv check
> * Ibex (OpenTitan) fixup priv version
> * Fix bug resulting in always using latest priv spec
> * Reduce FDT address alignment constraints
> * Set minumum priv spec version for mcountinhibit
> * AIA update to v0.3 of the spec
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate.
r~
>
> ----------------------------------------------------------------
> Alistair Francis (3):
> target/riscv: Fixup MSECCFG minimum priv check
> target/riscv: Ibex: Support priv version 1.11
> hw/riscv: boot: Reduce FDT address alignment constraints
>
> Anup Patel (4):
> target/riscv: Don't force update priv spec version to latest
> target/riscv: Set minumum priv spec version for mcountinhibit
> target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits
> target/riscv: Update default priority table for local interrupts
>
> Atish Patra (7):
> target/riscv: Fix PMU CSR predicate function
> target/riscv: Implement PMU CSR predicate function for S-mode
> target/riscv: pmu: Rename the counters extension to pmu
> target/riscv: pmu: Make number of counters configurable
> target/riscv: Implement mcountinhibit CSR
> target/riscv: Add support for hpmcounters/hpmevents
> target/riscv: Support mcycle/minstret write operation
>
> Nicolas Pitre (1):
> target/riscv/pmp: guard against PMP ranges with a negative size
>
> Richard Henderson (3):
> target/riscv: Set env->bins in gen_exception_illegal
> target/riscv: Remove generate_exception_mtval
> target/riscv: Minimize the calls to decode_save_opc
>
> Víctor Colombo (1):
> target/riscv: Remove condition guarding register zero for auipc and lui
>
> target/riscv/cpu.h | 24 +-
> target/riscv/cpu_bits.h | 30 +-
> target/riscv/pmu.h | 28 +
> hw/riscv/boot.c | 4 +-
> target/riscv/cpu.c | 17 +-
> target/riscv/cpu_helper.c | 134 ++--
> target/riscv/csr.c | 857 +++++++++++++++----------
> target/riscv/machine.c | 25 +
> target/riscv/pmp.c | 3 +
> target/riscv/pmu.c | 32 +
> target/riscv/translate.c | 31 +-
> target/riscv/insn_trans/trans_privileged.c.inc | 4 +
> target/riscv/insn_trans/trans_rvh.c.inc | 2 +
> target/riscv/insn_trans/trans_rvi.c.inc | 10 +-
> target/riscv/meson.build | 3 +-
> tests/tcg/riscv64/Makefile.softmmu-target | 21 +
> tests/tcg/riscv64/issue1060.S | 53 ++
> tests/tcg/riscv64/semihost.ld | 21 +
> 18 files changed, 843 insertions(+), 456 deletions(-)
> create mode 100644 target/riscv/pmu.h
> create mode 100644 target/riscv/pmu.c
> create mode 100644 tests/tcg/riscv64/Makefile.softmmu-target
> create mode 100644 tests/tcg/riscv64/issue1060.S
> create mode 100644 tests/tcg/riscv64/semihost.ld
>