From: Martin Liška <mliska@suse.cz>

Fixes the following Sphinx warning (treated as error) starting

with 5.0 release:

Warning, treated as error:

Invalid configuration value found: 'language = None'. Update your configuration to a valid langauge code. Falling back to 'en' (English).

Signed-off-by: Martin Liska <mliska@suse.cz>

Message-id: e91e51ee-48ac-437e-6467-98b56ee40042@suse.cz

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

docs/conf.py | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/conf.py b/docs/conf.py

index XXXXXXX..XXXXXXX 100644

--- a/docs/conf.py

+++ b/docs/conf.py

@@ -XXX,XX +XXX,XX @@

#

# This is also used if you do content translation via gettext catalogs.

# Usually you set "language" from the command line for these cases.

-language = None

+language = 'en'

# List of patterns, relative to source directory, that match files and

# directories to ignore when looking for source files.

--

2.25.1

From: Alexander Graf <agraf@csgraf.de>

We need to fetch the name of the current accelerator in flexible error

messages more going forward. Let's create a helper that gives it to us

without casting in the target code.

Signed-off-by: Alexander Graf <agraf@csgraf.de>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20220620192242.70573-1-agraf@csgraf.de

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

include/qemu/accel.h | 1 +

accel/accel-common.c | 8 ++++++++

softmmu/vl.c | 3 +--

3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/include/qemu/accel.h b/include/qemu/accel.h

index XXXXXXX..XXXXXXX 100644

--- a/include/qemu/accel.h

+++ b/include/qemu/accel.h

@@ -XXX,XX +XXX,XX @@ typedef struct AccelClass {

AccelClass *accel_find(const char *opt_name);

AccelState *current_accel(void);

+const char *current_accel_name(void);

void accel_init_interfaces(AccelClass *ac);

diff --git a/accel/accel-common.c b/accel/accel-common.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/accel-common.c

+++ b/accel/accel-common.c

@@ -XXX,XX +XXX,XX @@ AccelClass *accel_find(const char *opt_name)

return ac;

}

+/* Return the name of the current accelerator */

+const char *current_accel_name(void)

+{

+ AccelClass *ac = ACCEL_GET_CLASS(current_accel());

+

+ return ac->name;

+}

+

static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque)

{

CPUClass *cc = CPU_CLASS(klass);

diff --git a/softmmu/vl.c b/softmmu/vl.c

index XXXXXXX..XXXXXXX 100644

--- a/softmmu/vl.c

+++ b/softmmu/vl.c

@@ -XXX,XX +XXX,XX @@ static void configure_accelerators(const char *progname)

}

if (init_failed && !qtest_chrdev) {

- AccelClass *ac = ACCEL_GET_CLASS(current_accel());

- error_report("falling back to %s", ac->name);

+ error_report("falling back to %s", current_accel_name());

}

if (icount_enabled() && !tcg_enabled()) {

--

2.25.1

From: Alexander Graf <agraf@csgraf.de>

Some features such as running in EL3 or running M profile code are

incompatible with virtualization as QEMU implements it today. To prevent

users from picking invalid configurations on other virt solutions like

Hvf, let's run the same checks there too.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1073

Signed-off-by: Alexander Graf <agraf@csgraf.de>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20220620192242.70573-2-agraf@csgraf.de

[PMM: Allow qtest accelerator too; tweak comment]

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu.c | 16 ++++++++++++----

1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@

#include "hw/boards.h"

#endif

#include "sysemu/tcg.h"

+#include "sysemu/qtest.h"

#include "sysemu/hw_accel.h"

#include "kvm_arm.h"

#include "disas/capstone.h"

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)

}

}

- if (kvm_enabled()) {

+ if (!tcg_enabled() && !qtest_enabled()) {

/*

+ * We assume that no accelerator except TCG (and the "not really an

+ * accelerator" qtest) can handle these features, because Arm hardware

+ * virtualization can't virtualize them.

+ *

* Catch all the cases which might cause us to create more than one

* address space for the CPU (otherwise we will assert() later in

* cpu_address_space_init()).

*/

if (arm_feature(env, ARM_FEATURE_M)) {

error_setg(errp,

- "Cannot enable KVM when using an M-profile guest CPU");

+ "Cannot enable %s when using an M-profile guest CPU",

+ current_accel_name());

return;

}

if (cpu->has_el3) {

error_setg(errp,

- "Cannot enable KVM when guest CPU has EL3 enabled");

+ "Cannot enable %s when guest CPU has EL3 enabled",

+ current_accel_name());

return;

}

if (cpu->tag_memory) {

error_setg(errp,

- "Cannot enable KVM when guest CPUs has MTE enabled");

+ "Cannot enable %s when guest CPUs has MTE enabled",

+ current_accel_name());

return;

}

}

--

2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This register is part of SME, but isn't closely related to the

rest of the extension.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20220620175235.60881-2-richard.henderson@linaro.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu.h | 1 +

target/arm/helper.c | 32 ++++++++++++++++++++++++++++++++

2 files changed, 33 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {

};

uint64_t tpidr_el[4];

};

+ uint64_t tpidr2_el0;

/* The secure banks of these registers don't map anywhere */

uint64_t tpidrurw_s;

uint64_t tpidrprw_s;

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo zcr_reginfo[] = {

.writefn = zcr_write, .raw_writefn = raw_write },

};

+#ifdef TARGET_AARCH64

+static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri,

+ bool isread)

+{

+ int el = arm_current_el(env);

+

+ if (el == 0) {

+ uint64_t sctlr = arm_sctlr(env, el);

+ if (!(sctlr & SCTLR_EnTP2)) {

+ return CP_ACCESS_TRAP;

+ }

+ }

+ /* TODO: FEAT_FGT */

+ if (el < 3

+ && arm_feature(env, ARM_FEATURE_EL3)

+ && !(env->cp15.scr_el3 & SCR_ENTP2)) {

+ return CP_ACCESS_TRAP_EL3;

+ }

+ return CP_ACCESS_OK;

+}

+

+static const ARMCPRegInfo sme_reginfo[] = {

+ { .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64,

+ .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5,

+ .access = PL0_RW, .accessfn = access_tpidr2,

+ .fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) },

+};

+#endif /* TARGET_AARCH64 */

+

void hw_watchpoint_update(ARMCPU *cpu, int n)

{

CPUARMState *env = &cpu->env;

@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)

}

#ifdef TARGET_AARCH64

+ if (cpu_isar_feature(aa64_sme, cpu)) {

+ define_arm_cp_regs(cpu, sme_reginfo);

+ }

if (cpu_isar_feature(aa64_pauth, cpu)) {

define_arm_cp_regs(cpu, pauth_reginfo);

}

--

2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This is CheckSMEAccess, which is the basis for a set of

related tests for various SME cpregs and instructions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20220620175235.60881-3-richard.henderson@linaro.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu.h | 2 ++

target/arm/translate.h | 1 +

target/arm/helper.c | 52 ++++++++++++++++++++++++++++++++++++++

target/arm/translate-a64.c | 1 +

4 files changed, 56 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ void aarch64_sync_64_to_32(CPUARMState *env);

int fp_exception_el(CPUARMState *env, int cur_el);

int sve_exception_el(CPUARMState *env, int cur_el);

+int sme_exception_el(CPUARMState *env, int cur_el);

/**

* sve_vqm1_for_el:

@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, ATA, 15, 1)

FIELD(TBFLAG_A64, TCMA, 16, 2)

FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)

FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)

+FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)

/*

* Helpers for using the above.

diff --git a/target/arm/translate.h b/target/arm/translate.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.h

+++ b/target/arm/translate.h

@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {

bool ns; /* Use non-secure CPREG bank on access */

int fp_excp_el; /* FP exception EL or 0 if enabled */

int sve_excp_el; /* SVE exception EL or 0 if enabled */

+ int sme_excp_el; /* SME exception EL or 0 if enabled */

int vl; /* current vector length in bytes */

bool vfp_enabled; /* FP enabled via FPSCR.EN */

int vec_len;

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)

return 0;

}

+/*

+ * Return the exception level to which exceptions should be taken for SME.

+ * C.f. the ARM pseudocode function CheckSMEAccess.

+ */

+int sme_exception_el(CPUARMState *env, int el)

+{

+#ifndef CONFIG_USER_ONLY

+ if (el <= 1 && !el_is_in_host(env, el)) {

+ switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, SMEN)) {

+ case 1:

+ if (el != 0) {

+ break;

+ }

+ /* fall through */

+ case 0:

+ case 2:

+ return 1;

+ }

+ }

+

+ if (el <= 2 && arm_is_el2_enabled(env)) {

+ /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */

+ if (env->cp15.hcr_el2 & HCR_E2H) {

+ switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, SMEN)) {

+ case 1:

+ if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) {

+ break;

+ }

+ /* fall through */

+ case 0:

+ case 2:

+ return 2;

+ }

+ } else {

+ if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TSM)) {

+ return 2;

+ }

+ }

+ }

+

+ /* CPTR_EL3. Since ESM is negative we must check for EL3. */

+ if (arm_feature(env, ARM_FEATURE_EL3)

+ && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) {

+ return 3;

+ }

+#endif

+ return 0;

+}

+

/*

* Given that SVE is enabled, return the vector length for EL.

*/

@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,

}

DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el);

}

+ if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {

+ DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el));

+ }

sctlr = regime_sctlr(env, stage1);

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,

dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);

dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);

dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);

+ dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);

dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16;

dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE);

dc->bt = EX_TBFLAG_A64(tb_flags, BT);

--

2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This will be used for raising various traps for SME.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20220620175235.60881-4-richard.henderson@linaro.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/syndrome.h | 14 ++++++++++++++

1 file changed, 14 insertions(+)

diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/syndrome.h

+++ b/target/arm/syndrome.h

@@ -XXX,XX +XXX,XX @@ enum arm_exception_class {

EC_AA64_SMC = 0x17,

EC_SYSTEMREGISTERTRAP = 0x18,

EC_SVEACCESSTRAP = 0x19,

+ EC_SMETRAP = 0x1d,

EC_INSNABORT = 0x20,

EC_INSNABORT_SAME_EL = 0x21,

EC_PCALIGNMENT = 0x22,

@@ -XXX,XX +XXX,XX @@ enum arm_exception_class {

EC_AA64_BKPT = 0x3c,

};

+typedef enum {

+ SME_ET_AccessTrap,

+ SME_ET_Streaming,

+ SME_ET_NotStreaming,

+ SME_ET_InactiveZA,

+} SMEExceptionType;

+

#define ARM_EL_EC_SHIFT 26

#define ARM_EL_IL_SHIFT 25

#define ARM_EL_ISV_SHIFT 24

@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_sve_access_trap(void)

return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT;

}

+static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit)

+{

+ return (EC_SMETRAP << ARM_EL_EC_SHIFT)

+ | (is_16bit ? 0 : ARM_EL_IL) | etype;

+}

+

static inline uint32_t syn_pactrap(void)

{

return EC_PACTRAP << ARM_EL_EC_SHIFT;

--

2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This will be used for controlling access to SME cpregs.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20220620175235.60881-5-richard.henderson@linaro.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpregs.h | 5 +++++

target/arm/translate-a64.c | 18 ++++++++++++++++++

2 files changed, 23 insertions(+)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpregs.h

+++ b/target/arm/cpregs.h

@@ -XXX,XX +XXX,XX @@ enum {

ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16,

ARM_CP_EL3_NO_EL2_KEEP = 1 << 17,

ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18,

+ /*

+ * Flag: Access check for this sysreg is constrained by the

+ * ARM pseudocode function CheckSMEAccess().

+ */

+ ARM_CP_SME = 1 << 19,

};

/*

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ bool sve_access_check(DisasContext *s)

return fp_access_check(s);

}

+/*

+ * Check that SME access is enabled, raise an exception if not.

+ * Note that this function corresponds to CheckSMEAccess and is

+ * only used directly for cpregs.

+ */

+static bool sme_access_check(DisasContext *s)

+{

+ if (s->sme_excp_el) {

+ gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,

+ syn_smetrap(SME_ET_AccessTrap, false),

+ s->sme_excp_el);

+ return false;

+ }

+ return true;

+}

+

/*

* This utility function is for doing register extension with an

* optional shift. You will likely want to pass a temporary for the

@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,

return;

} else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) {

return;

+ } else if ((ri->type & ARM_CP_SME) && !sme_access_check(s)) {

+ return;

}

if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {

--

2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This cpreg is used to access two new bits of PSTATE

that are not visible via any other mechanism.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20220620175235.60881-6-richard.henderson@linaro.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu.h | 6 ++++++

target/arm/helper.c | 13 +++++++++++++

2 files changed, 19 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {

* nRW (also known as M[4]) is kept, inverted, in env->aarch64

* DAIF (exception masks) are kept in env->daif

* BTYPE is kept in env->btype

+ * SM and ZA are kept in env->svcr

* all other bits are stored in their correct places in env->pstate

*/

uint32_t pstate;

@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {

uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */

uint32_t btype; /* BTI branch type. spsr[11:10]. */

uint64_t daif; /* exception masks, in the bits they are in PSTATE */

+ uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */

uint64_t elr_el[4]; /* AArch64 exception link regs */

uint64_t sp_el[4]; /* AArch64 banked stack pointers */

@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TCPAC, 31, 1)

#define PSTATE_MODE_EL1t 4

#define PSTATE_MODE_EL0t 0

+/* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */

+FIELD(SVCR, SM, 0, 1)

+FIELD(SVCR, ZA, 1, 1)

+

/* Write a new value to v7m.exception, thus transitioning into or out

* of Handler mode; this may result in a change of active stack pointer.

*/

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri,

return CP_ACCESS_OK;

}

+static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,

+ uint64_t value)

+{

+ value &= R_SVCR_SM_MASK | R_SVCR_ZA_MASK;

+ /* TODO: Side effects. */

+ env->svcr = value;

+}

+

static const ARMCPRegInfo sme_reginfo[] = {

{ .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64,

.opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5,

.access = PL0_RW, .accessfn = access_tpidr2,

.fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) },

+ { .name = "SVCR", .state = ARM_CP_STATE_AA64,

+ .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2,

+ .access = PL0_RW, .type = ARM_CP_SME,

+ .fieldoffset = offsetof(CPUARMState, svcr),

+ .writefn = svcr_write, .raw_writefn = raw_write },

};

#endif /* TARGET_AARCH64 */

--

2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

These cpregs control the streaming vector length and whether the

full a64 instruction set is allowed while in streaming mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20220620175235.60881-7-richard.henderson@linaro.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu.h | 8 ++++++--

target/arm/helper.c | 41 +++++++++++++++++++++++++++++++++++++++++

2 files changed, 47 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {

float_status standard_fp_status;

float_status standard_fp_status_f16;

- /* ZCR_EL[1-3] */

- uint64_t zcr_el[4];

+ uint64_t zcr_el[4]; /* ZCR_EL[1-3] */

+ uint64_t smcr_el[4]; /* SMCR_EL[1-3] */

} vfp;

uint64_t exclusive_addr;

uint64_t exclusive_val;

@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TCPAC, 31, 1)

FIELD(SVCR, SM, 0, 1)

FIELD(SVCR, ZA, 1, 1)

+/* Fields for SMCR_ELx. */

+FIELD(SMCR, LEN, 0, 4)

+FIELD(SMCR, FA64, 31, 1)

+

/* Write a new value to v7m.exception, thus transitioning into or out

* of Handler mode; this may result in a change of active stack pointer.

*/

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)

*/

{ K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),

"ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve },

+ { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6),

+ "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme },

{ K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),

"TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },

@@ -XXX,XX +XXX,XX @@ static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,

env->svcr = value;

}

+static void smcr_write(CPUARMState *env, const ARMCPRegInfo *ri,

+ uint64_t value)

+{

+ int cur_el = arm_current_el(env);

+ int old_len = sve_vqm1_for_el(env, cur_el);

+ int new_len;

+

+ QEMU_BUILD_BUG_ON(ARM_MAX_VQ > R_SMCR_LEN_MASK + 1);

+ value &= R_SMCR_LEN_MASK | R_SMCR_FA64_MASK;

+ raw_write(env, ri, value);

+

+ /*

+ * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage

+ * when SVL is widened (old values kept, or zeros). Choose to keep the

+ * current values for simplicity. But for QEMU internals, we must still

+ * apply the narrower SVL to the Zregs and Pregs -- see the comment

+ * above aarch64_sve_narrow_vq.

+ */

+ new_len = sve_vqm1_for_el(env, cur_el);

+ if (new_len < old_len) {

+ aarch64_sve_narrow_vq(env, new_len + 1);

+ }

+}

+

static const ARMCPRegInfo sme_reginfo[] = {

{ .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64,

.opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5,

@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = {

.access = PL0_RW, .type = ARM_CP_SME,

.fieldoffset = offsetof(CPUARMState, svcr),

.writefn = svcr_write, .raw_writefn = raw_write },

+ { .name = "SMCR_EL1", .state = ARM_CP_STATE_AA64,

+ .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 6,

+ .access = PL1_RW, .type = ARM_CP_SME,

+ .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[1]),

+ .writefn = smcr_write, .raw_writefn = raw_write },

+ { .name = "SMCR_EL2", .state = ARM_CP_STATE_AA64,

+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 6,

+ .access = PL2_RW, .type = ARM_CP_SME,

+ .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[2]),

+ .writefn = smcr_write, .raw_writefn = raw_write },

+ { .name = "SMCR_EL3", .state = ARM_CP_STATE_AA64,

+ .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 6,

+ .access = PL3_RW, .type = ARM_CP_SME,

+ .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[3]),

+ .writefn = smcr_write, .raw_writefn = raw_write },

};

#endif /* TARGET_AARCH64 */

--

2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Implement the streaming mode identification register, and the

two streaming priority registers. For QEMU, they are all RES0.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20220620175235.60881-8-richard.henderson@linaro.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/helper.c | 33 +++++++++++++++++++++++++++++++++

1 file changed, 33 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri,

return CP_ACCESS_OK;

}

+static CPAccessResult access_esm(CPUARMState *env, const ARMCPRegInfo *ri,

+ bool isread)

+{

+ /* TODO: FEAT_FGT for SMPRI_EL1 but not SMPRIMAP_EL2 */

+ if (arm_current_el(env) < 3

+ && arm_feature(env, ARM_FEATURE_EL3)

+ && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) {

+ return CP_ACCESS_TRAP_EL3;

+ }

+ return CP_ACCESS_OK;

+}

+

static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,

uint64_t value)

{

@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = {

.access = PL3_RW, .type = ARM_CP_SME,

.fieldoffset = offsetof(CPUARMState, vfp.smcr_el[3]),

.writefn = smcr_write, .raw_writefn = raw_write },

+ { .name = "SMIDR_EL1", .state = ARM_CP_STATE_AA64,

+ .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 6,

+ .access = PL1_R, .accessfn = access_aa64_tid1,

+ /*

+ * IMPLEMENTOR = 0 (software)

+ * REVISION = 0 (implementation defined)

+ * SMPS = 0 (no streaming execution priority in QEMU)

+ * AFFINITY = 0 (streaming sve mode not shared with other PEs)

+ */

+ .type = ARM_CP_CONST, .resetvalue = 0, },

+ /*

+ * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0.

+ */

+ { .name = "SMPRI_EL1", .state = ARM_CP_STATE_AA64,

+ .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 4,

+ .access = PL1_RW, .accessfn = access_esm,

+ .type = ARM_CP_CONST, .resetvalue = 0 },

+ { .name = "SMPRIMAP_EL2", .state = ARM_CP_STATE_AA64,

+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5,

+ .access = PL2_RW, .accessfn = access_esm,

+ .type = ARM_CP_CONST, .resetvalue = 0 },

};

#endif /* TARGET_AARCH64 */

--

2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

These are required to determine if various insns

are allowed to issue.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20220620175235.60881-9-richard.henderson@linaro.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu.h | 2 ++

target/arm/translate.h | 4 ++++

target/arm/helper.c | 4 ++++

target/arm/translate-a64.c | 2 ++

4 files changed, 12 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, TCMA, 16, 2)

FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)

FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)

FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)

+FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)

+FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)

/*

* Helpers for using the above.

diff --git a/target/arm/translate.h b/target/arm/translate.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.h

+++ b/target/arm/translate.h

@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {

bool align_mem;

/* True if PSTATE.IL is set */

bool pstate_il;

+ /* True if PSTATE.SM is set. */

+ bool pstate_sm;

+ /* True if PSTATE.ZA is set. */

+ bool pstate_za;

/* True if MVE insns are definitely not predicated by VPR or LTPSIZE */

bool mve_no_pred;

/*

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,

}

if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {

DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el));

+ if (FIELD_EX64(env->svcr, SVCR, SM)) {

+ DP_TBFLAG_A64(flags, PSTATE_SM, 1);

+ }

+ DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA));

}

sctlr = regime_sctlr(env, stage1);

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,

dc->ata = EX_TBFLAG_A64(tb_flags, ATA);

dc->mte_active[0] = EX_TBFLAG_A64(tb_flags, MTE_ACTIVE);

dc->mte_active[1] = EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE);

+ dc->pstate_sm = EX_TBFLAG_A64(tb_flags, PSTATE_SM);

+ dc->pstate_za = EX_TBFLAG_A64(tb_flags, PSTATE_ZA);

dc->vec_len = 0;

dc->vec_stride = 0;

dc->cp_regs = arm_cpu->cp_regs;

--

2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Place this late in the resettable section of the structure,

to keep the most common element offsets from being > 64k.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20220620175235.60881-10-richard.henderson@linaro.org

[PMM: expanded comment on zarray[] format]

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu.h | 22 ++++++++++++++++++++++

target/arm/machine.c | 34 ++++++++++++++++++++++++++++++++++

2 files changed, 56 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {

} keys;

uint64_t scxtnum_el[4];

+

+ /*

+ * SME ZA storage -- 256 x 256 byte array, with bytes in host word order,

+ * as we do with vfp.zregs[]. This corresponds to the architectural ZA

+ * array, where ZA[N] is in the least-significant bytes of env->zarray[N].

+ * When SVL is less than the architectural maximum, the accessible

+ * storage is restricted, such that if the SVL is X bytes the guest can

+ * see only the bottom X elements of zarray[], and only the least

+ * significant X bytes of each element of the array. (In other words,

+ * the observable part is always square.)

+ *

+ * The ZA storage can also be considered as a set of square tiles of

+ * elements of different sizes. The mapping from tiles to the ZA array

+ * is architecturally defined, such that for tiles of elements of esz

+ * bytes, the Nth row (or "horizontal slice") of tile T is in

+ * ZA[T + N * esz]. Note that this means that each tile is not contiguous

+ * in the ZA storage, because its rows are striped through the ZA array.

+ *

+ * Because this is so large, keep this toward the end of the reset area,

+ * to keep the offsets into the rest of the structure smaller.

+ */

+ ARMVectorReg zarray[ARM_MAX_VQ * 16];

#endif

#if defined(CONFIG_USER_ONLY)

diff --git a/target/arm/machine.c b/target/arm/machine.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/machine.c

+++ b/target/arm/machine.c

@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_sve = {

VMSTATE_END_OF_LIST()

}

};

+

+static const VMStateDescription vmstate_vreg = {

+ .name = "vreg",

+ .version_id = 1,

+ .minimum_version_id = 1,

+ .fields = (VMStateField[]) {

+ VMSTATE_UINT64_ARRAY(d, ARMVectorReg, ARM_MAX_VQ * 2),

+ VMSTATE_END_OF_LIST()

+ }

+};

+

+static bool za_needed(void *opaque)

+{

+ ARMCPU *cpu = opaque;

+

+ /*

+ * When ZA storage is disabled, its contents are discarded.

+ * It will be zeroed when ZA storage is re-enabled.

+ */

+ return FIELD_EX64(cpu->env.svcr, SVCR, ZA);

+}

+

+static const VMStateDescription vmstate_za = {

+ .name = "cpu/sme",

+ .version_id = 1,

+ .minimum_version_id = 1,

+ .needed = za_needed,

+ .fields = (VMStateField[]) {

+ VMSTATE_STRUCT_ARRAY(env.zarray, ARMCPU, ARM_MAX_VQ * 16, 0,

+ vmstate_vreg, ARMVectorReg),

+ VMSTATE_END_OF_LIST()

+ }

+};

#endif /* AARCH64 */

static bool serror_needed(void *opaque)

@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_arm_cpu = {

&vmstate_m_security,

#ifdef TARGET_AARCH64

&vmstate_sve,

+ &vmstate_za,

#endif

&vmstate_serror,

&vmstate_irq_line_state,

--

2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

These two instructions are aliases of MSR (immediate).

Use the two helpers to properly implement svcr_write.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20220620175235.60881-11-richard.henderson@linaro.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu.h | 1 +

target/arm/helper-sme.h | 21 +++++++++++++

target/arm/helper.h | 1 +

target/arm/helper.c | 6 ++--

target/arm/sme_helper.c | 61 ++++++++++++++++++++++++++++++++++++++

target/arm/translate-a64.c | 24 +++++++++++++++

target/arm/meson.build | 1 +

7 files changed, 112 insertions(+), 3 deletions(-)

create mode 100644 target/arm/helper-sme.h

create mode 100644 target/arm/sme_helper.c

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,

int new_el, bool el0_a64);

void aarch64_add_sve_properties(Object *obj);

void aarch64_add_pauth_properties(Object *obj);

+void arm_reset_sve_state(CPUARMState *env);

/*

* SVE registers are encoded in KVM's memory in an endianness-invariant format.

diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/target/arm/helper-sme.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * AArch64 SME specific helper definitions

+ *

+ * Copyright (c) 2022 Linaro, Ltd

+ *

+ * This library is free software; you can redistribute it and/or

+ * modify it under the terms of the GNU Lesser General Public

+ * License as published by the Free Software Foundation; either

+ * version 2.1 of the License, or (at your option) any later version.

+ *

+ * This library is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU

+ * Lesser General Public License for more details.

+ *

+ * You should have received a copy of the GNU Lesser General Public

+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.

+ */

+

+DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32)

+DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32)

diff --git a/target/arm/helper.h b/target/arm/helper.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.h

+++ b/target/arm/helper.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG,

#ifdef TARGET_AARCH64

#include "helper-a64.h"

#include "helper-sve.h"

+#include "helper-sme.h"

#endif

#include "helper-mve.h"

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_esm(CPUARMState *env, const ARMCPRegInfo *ri,

static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,

uint64_t value)

{

- value &= R_SVCR_SM_MASK | R_SVCR_ZA_MASK;

- /* TODO: Side effects. */

- env->svcr = value;

+ helper_set_pstate_sm(env, FIELD_EX64(value, SVCR, SM));

+ helper_set_pstate_za(env, FIELD_EX64(value, SVCR, ZA));

+ arm_rebuild_hflags(env);

}

static void smcr_write(CPUARMState *env, const ARMCPRegInfo *ri,

diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/target/arm/sme_helper.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * ARM SME Operations

+ *

+ * Copyright (c) 2022 Linaro, Ltd.

+ *

+ * This library is free software; you can redistribute it and/or

+ * modify it under the terms of the GNU Lesser General Public

+ * License as published by the Free Software Foundation; either

+ * version 2.1 of the License, or (at your option) any later version.

+ *

+ * This library is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU

+ * Lesser General Public License for more details.

+ *

+ * You should have received a copy of the GNU Lesser General Public

+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.

+ */

+

+#include "qemu/osdep.h"

+#include "cpu.h"

+#include "internals.h"

+#include "exec/helper-proto.h"

+

+/* ResetSVEState */

+void arm_reset_sve_state(CPUARMState *env)

+{

+ memset(env->vfp.zregs, 0, sizeof(env->vfp.zregs));

+ /* Recall that FFR is stored as pregs[16]. */

+ memset(env->vfp.pregs, 0, sizeof(env->vfp.pregs));

+ vfp_set_fpcr(env, 0x0800009f);

+}

+

+void helper_set_pstate_sm(CPUARMState *env, uint32_t i)

+{

+ if (i == FIELD_EX64(env->svcr, SVCR, SM)) {

+ return;

+ }

+ env->svcr ^= R_SVCR_SM_MASK;

+ arm_reset_sve_state(env);

+}

+

+void helper_set_pstate_za(CPUARMState *env, uint32_t i)

+{

+ if (i == FIELD_EX64(env->svcr, SVCR, ZA)) {

+ return;

+ }

+ env->svcr ^= R_SVCR_ZA_MASK;

+

+ /*

+ * ResetSMEState.

+ *

+ * SetPSTATE_ZA zeros on enable and disable. We can zero this only

+ * on enable: while disabled, the storage is inaccessible and the

+ * value does not matter. We're not saving the storage in vmstate

+ * when disabled either.

+ */

+ if (i) {

+ memset(env->zarray, 0, sizeof(env->zarray));

+ }

+}

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn,

}

break;

+ case 0x1b: /* SVCR* */

+ if (!dc_isar_feature(aa64_sme, s) || crm < 2 || crm > 7) {

+ goto do_unallocated;

+ }

+ if (sme_access_check(s)) {

+ bool i = crm & 1;

+ bool changed = false;

+

+ if ((crm & 2) && i != s->pstate_sm) {

+ gen_helper_set_pstate_sm(cpu_env, tcg_constant_i32(i));

+ changed = true;

+ }

+ if ((crm & 4) && i != s->pstate_za) {

+ gen_helper_set_pstate_za(cpu_env, tcg_constant_i32(i));

+ changed = true;

+ }

+ if (changed) {

+ gen_rebuild_hflags(s);

+ } else {

+ s->base.is_jmp = DISAS_NEXT;

+ }

+ }

+ break;

+

default: