aspeed/hace: Accumulative mode supported

[PATCH] aspeed/hace: Accumulative mode supported

Joel Stanley posted 1 patch 3 years, 7 months ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20220627100816.125956-1-joel@jms.id.au

Maintainers: "Cédric Le Goater" <clg@kaod.org>, Peter Maydell <peter.maydell@linaro.org>, Andrew Jeffery <andrew@aj.id.au>, Joel Stanley <joel@jms.id.au>

hw/misc/aspeed_hace.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

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[PATCH] aspeed/hace: Accumulative mode supported

Posted by Joel Stanley 3 years, 7 months ago

While the HMAC mode is not modelled, the accumulative mode is.

Accumulative mode is enabled by setting one of the bits in the HMAC
engine command mode part of the register, so fix the unimplemented check
to only look at the upper of the two bits.

Fixes: 5cd7d8564a8b ("aspeed/hace: Support AST2600 HACE")
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 hw/misc/aspeed_hace.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 731234b78c4c..ac21be306c69 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -338,10 +338,10 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,
         int algo;
         data &= ahc->hash_mask;
 
-        if ((data & HASH_HMAC_MASK)) {
+        if ((data & HASH_DIGEST_HMAC)) {
             qemu_log_mask(LOG_UNIMP,
-                          "%s: HMAC engine command mode %"PRIx64" not implemented\n",
-                          __func__, (data & HASH_HMAC_MASK) >> 8);
+                          "%s: HMAC mode not implemented\n",
+                          __func__);
         }
         if (data & BIT(1)) {
             qemu_log_mask(LOG_UNIMP,
-- 
2.35.1

Re: [PATCH] aspeed/hace: Accumulative mode supported

Posted by Cédric Le Goater 3 years, 7 months ago

On 6/27/22 12:08, Joel Stanley wrote:
> While the HMAC mode is not modelled, the accumulative mode is.
> 
> Accumulative mode is enabled by setting one of the bits in the HMAC
> engine command mode part of the register, so fix the unimplemented check
> to only look at the upper of the two bits.
> 
> Fixes: 5cd7d8564a8b ("aspeed/hace: Support AST2600 HACE")
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Thanks,

C.

>   hw/misc/aspeed_hace.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
> index 731234b78c4c..ac21be306c69 100644
> --- a/hw/misc/aspeed_hace.c
> +++ b/hw/misc/aspeed_hace.c
> @@ -338,10 +338,10 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,
>           int algo;
>           data &= ahc->hash_mask;
>   
> -        if ((data & HASH_HMAC_MASK)) {
> +        if ((data & HASH_DIGEST_HMAC)) {
>               qemu_log_mask(LOG_UNIMP,
> -                          "%s: HMAC engine command mode %"PRIx64" not implemented\n",
> -                          __func__, (data & HASH_HMAC_MASK) >> 8);
> +                          "%s: HMAC mode not implemented\n",
> +                          __func__);
>           }
>           if (data & BIT(1)) {
>               qemu_log_mask(LOG_UNIMP,