The unified pnv-phb-root-port can be used instead. The phb4-root-port
device isn't exposed to the user in any official QEMU release so there's
no ABI breakage in removing it.

Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
 hw/pci-host/pnv_phb.c          |  4 +-
 hw/pci-host/pnv_phb4.c         | 85 ----------------------------------
 hw/pci-host/pnv_phb4_pec.c     |  4 +-
 hw/ppc/pnv.c                   |  2 +
 include/hw/pci-host/pnv_phb4.h |  9 ----
 5 files changed, 6 insertions(+), 98 deletions(-)

diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index cdddc6a389..da729e89e7 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -38,11 +38,11 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
         break;
     case 4:
         phb_typename = g_strdup(TYPE_PNV_PHB4);
-        phb_rootport_typename = g_strdup(TYPE_PNV_PHB4_ROOT_PORT);
+        phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
         break;
     case 5:
         phb_typename = g_strdup(TYPE_PNV_PHB5);
-        phb_rootport_typename = g_strdup(TYPE_PNV_PHB5_ROOT_PORT);
+        phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
         break;
     default:
         g_assert_not_reached();
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 74cf62dc1a..fefdd3ad89 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1741,94 +1741,9 @@ static const TypeInfo pnv_phb4_root_bus_info = {
     .class_init = pnv_phb4_root_bus_class_init,
 };
 
-static void pnv_phb4_root_port_reset(DeviceState *dev)
-{
-    PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
-    PCIDevice *d = PCI_DEVICE(dev);
-    uint8_t *conf = d->config;
-
-    rpc->parent_reset(dev);
-
-    pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
-                               PCI_IO_RANGE_MASK & 0xff);
-    pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
-                                 PCI_IO_RANGE_MASK & 0xff);
-    pci_set_word(conf + PCI_MEMORY_BASE, 0);
-    pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0);
-    pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1);
-    pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1);
-    pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */
-    pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff);
-    pci_config_set_interrupt_pin(conf, 0);
-}
-
-static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp)
-{
-    PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
-    Error *local_err = NULL;
-
-    rpc->parent_realize(dev, &local_err);
-    if (local_err) {
-        error_propagate(errp, local_err);
-        return;
-    }
-}
-
-static void pnv_phb4_root_port_class_init(ObjectClass *klass, void *data)
-{
-    DeviceClass *dc = DEVICE_CLASS(klass);
-    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-    PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
-
-    dc->desc     = "IBM PHB4 PCIE Root Port";
-    dc->user_creatable = false;
-
-    device_class_set_parent_realize(dc, pnv_phb4_root_port_realize,
-                                    &rpc->parent_realize);
-    device_class_set_parent_reset(dc, pnv_phb4_root_port_reset,
-                                  &rpc->parent_reset);
-
-    k->vendor_id = PCI_VENDOR_ID_IBM;
-    k->device_id = PNV_PHB4_DEVICE_ID;
-    k->revision  = 0;
-
-    rpc->exp_offset = 0x48;
-    rpc->aer_offset = 0x100;
-
-    dc->reset = &pnv_phb4_root_port_reset;
-}
-
-static const TypeInfo pnv_phb4_root_port_info = {
-    .name          = TYPE_PNV_PHB4_ROOT_PORT,
-    .parent        = TYPE_PCIE_ROOT_PORT,
-    .instance_size = sizeof(PnvPHB4RootPort),
-    .class_init    = pnv_phb4_root_port_class_init,
-};
-
-static void pnv_phb5_root_port_class_init(ObjectClass *klass, void *data)
-{
-    DeviceClass *dc = DEVICE_CLASS(klass);
-    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
-    dc->desc     = "IBM PHB5 PCIE Root Port";
-    dc->user_creatable = false;
-
-    k->vendor_id = PCI_VENDOR_ID_IBM;
-    k->device_id = PNV_PHB5_DEVICE_ID;
-}
-
-static const TypeInfo pnv_phb5_root_port_info = {
-    .name          = TYPE_PNV_PHB5_ROOT_PORT,
-    .parent        = TYPE_PNV_PHB4_ROOT_PORT,
-    .instance_size = sizeof(PnvPHB4RootPort),
-    .class_init    = pnv_phb5_root_port_class_init,
-};
-
 static void pnv_phb4_register_types(void)
 {
     type_register_static(&pnv_phb4_root_bus_info);
-    type_register_static(&pnv_phb5_root_port_info);
-    type_register_static(&pnv_phb4_root_port_info);
     type_register_static(&pnv_phb4_type_info);
     type_register_static(&pnv_phb5_type_info);
     type_register_static(&pnv_phb4_iommu_memory_region_info);
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index 4a0a9fbe8b..0ef66b9a9b 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -260,7 +260,7 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data)
     pecc->version = PNV_PHB4_VERSION;
     pecc->phb_type = TYPE_PNV_PHB4;
     pecc->num_phbs = pnv_pec_num_phbs;
-    pecc->rp_model = TYPE_PNV_PHB4_ROOT_PORT;
+    pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT;
 }
 
 static const TypeInfo pnv_pec_type_info = {
@@ -313,7 +313,7 @@ static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data)
     pecc->version = PNV_PHB5_VERSION;
     pecc->phb_type = TYPE_PNV_PHB5;
     pecc->num_phbs = pnv_phb5_pec_num_stacks;
-    pecc->rp_model = TYPE_PNV_PHB5_ROOT_PORT;
+    pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT;
 }
 
 static const TypeInfo pnv_phb5_pec_type_info = {
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index d82c66ca6f..159899103e 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -2132,6 +2132,7 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
 
     static GlobalProperty phb_compat[] = {
         { TYPE_PNV_PHB, "version", "4" },
+        { TYPE_PNV_PHB_ROOT_PORT, "version", "4" },
     };
 
     mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
@@ -2156,6 +2157,7 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
 
     static GlobalProperty phb_compat[] = {
         { TYPE_PNV_PHB, "version", "5" },
+        { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
     };
 
     mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index f22253358f..29c49ac79c 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -45,16 +45,7 @@ typedef struct PnvPhb4DMASpace {
     QLIST_ENTRY(PnvPhb4DMASpace) list;
 } PnvPhb4DMASpace;
 
-/*
- * PHB4 PCIe Root port
- */
 #define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root"
-#define TYPE_PNV_PHB4_ROOT_PORT "pnv-phb4-root-port"
-#define TYPE_PNV_PHB5_ROOT_PORT "pnv-phb5-root-port"
-
-typedef struct PnvPHB4RootPort {
-    PCIESlot parent_obj;
-} PnvPHB4RootPort;
 
 /*
  * PHB4 PCIe Host Bridge for PowerNV machines (POWER9)
-- 
2.36.1

On 24/06/2022 10:49, Daniel Henrique Barboza wrote:
> The unified pnv-phb-root-port can be used instead. The phb4-root-port
> device isn't exposed to the user in any official QEMU release so there's
> no ABI breakage in removing it.
> 
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> ---


Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>

   Fred


>   hw/pci-host/pnv_phb.c          |  4 +-
>   hw/pci-host/pnv_phb4.c         | 85 ----------------------------------
>   hw/pci-host/pnv_phb4_pec.c     |  4 +-
>   hw/ppc/pnv.c                   |  2 +
>   include/hw/pci-host/pnv_phb4.h |  9 ----
>   5 files changed, 6 insertions(+), 98 deletions(-)
> 
> diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
> index cdddc6a389..da729e89e7 100644
> --- a/hw/pci-host/pnv_phb.c
> +++ b/hw/pci-host/pnv_phb.c
> @@ -38,11 +38,11 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
>           break;
>       case 4:
>           phb_typename = g_strdup(TYPE_PNV_PHB4);
> -        phb_rootport_typename = g_strdup(TYPE_PNV_PHB4_ROOT_PORT);
> +        phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
>           break;
>       case 5:
>           phb_typename = g_strdup(TYPE_PNV_PHB5);
> -        phb_rootport_typename = g_strdup(TYPE_PNV_PHB5_ROOT_PORT);
> +        phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
>           break;
>       default:
>           g_assert_not_reached();
> diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
> index 74cf62dc1a..fefdd3ad89 100644
> --- a/hw/pci-host/pnv_phb4.c
> +++ b/hw/pci-host/pnv_phb4.c
> @@ -1741,94 +1741,9 @@ static const TypeInfo pnv_phb4_root_bus_info = {
>       .class_init = pnv_phb4_root_bus_class_init,
>   };
>   
> -static void pnv_phb4_root_port_reset(DeviceState *dev)
> -{
> -    PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
> -    PCIDevice *d = PCI_DEVICE(dev);
> -    uint8_t *conf = d->config;
> -
> -    rpc->parent_reset(dev);
> -
> -    pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
> -                               PCI_IO_RANGE_MASK & 0xff);
> -    pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
> -                                 PCI_IO_RANGE_MASK & 0xff);
> -    pci_set_word(conf + PCI_MEMORY_BASE, 0);
> -    pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0);
> -    pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1);
> -    pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1);
> -    pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */
> -    pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff);
> -    pci_config_set_interrupt_pin(conf, 0);
> -}
> -
> -static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp)
> -{
> -    PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
> -    Error *local_err = NULL;
> -
> -    rpc->parent_realize(dev, &local_err);
> -    if (local_err) {
> -        error_propagate(errp, local_err);
> -        return;
> -    }
> -}
> -
> -static void pnv_phb4_root_port_class_init(ObjectClass *klass, void *data)
> -{
> -    DeviceClass *dc = DEVICE_CLASS(klass);
> -    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> -    PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
> -
> -    dc->desc     = "IBM PHB4 PCIE Root Port";
> -    dc->user_creatable = false;
> -
> -    device_class_set_parent_realize(dc, pnv_phb4_root_port_realize,
> -                                    &rpc->parent_realize);
> -    device_class_set_parent_reset(dc, pnv_phb4_root_port_reset,
> -                                  &rpc->parent_reset);
> -
> -    k->vendor_id = PCI_VENDOR_ID_IBM;
> -    k->device_id = PNV_PHB4_DEVICE_ID;
> -    k->revision  = 0;
> -
> -    rpc->exp_offset = 0x48;
> -    rpc->aer_offset = 0x100;
> -
> -    dc->reset = &pnv_phb4_root_port_reset;
> -}
> -
> -static const TypeInfo pnv_phb4_root_port_info = {
> -    .name          = TYPE_PNV_PHB4_ROOT_PORT,
> -    .parent        = TYPE_PCIE_ROOT_PORT,
> -    .instance_size = sizeof(PnvPHB4RootPort),
> -    .class_init    = pnv_phb4_root_port_class_init,
> -};
> -
> -static void pnv_phb5_root_port_class_init(ObjectClass *klass, void *data)
> -{
> -    DeviceClass *dc = DEVICE_CLASS(klass);
> -    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> -
> -    dc->desc     = "IBM PHB5 PCIE Root Port";
> -    dc->user_creatable = false;
> -
> -    k->vendor_id = PCI_VENDOR_ID_IBM;
> -    k->device_id = PNV_PHB5_DEVICE_ID;
> -}
> -
> -static const TypeInfo pnv_phb5_root_port_info = {
> -    .name          = TYPE_PNV_PHB5_ROOT_PORT,
> -    .parent        = TYPE_PNV_PHB4_ROOT_PORT,
> -    .instance_size = sizeof(PnvPHB4RootPort),
> -    .class_init    = pnv_phb5_root_port_class_init,
> -};
> -
>   static void pnv_phb4_register_types(void)
>   {
>       type_register_static(&pnv_phb4_root_bus_info);
> -    type_register_static(&pnv_phb5_root_port_info);
> -    type_register_static(&pnv_phb4_root_port_info);
>       type_register_static(&pnv_phb4_type_info);
>       type_register_static(&pnv_phb5_type_info);
>       type_register_static(&pnv_phb4_iommu_memory_region_info);
> diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
> index 4a0a9fbe8b..0ef66b9a9b 100644
> --- a/hw/pci-host/pnv_phb4_pec.c
> +++ b/hw/pci-host/pnv_phb4_pec.c
> @@ -260,7 +260,7 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data)
>       pecc->version = PNV_PHB4_VERSION;
>       pecc->phb_type = TYPE_PNV_PHB4;
>       pecc->num_phbs = pnv_pec_num_phbs;
> -    pecc->rp_model = TYPE_PNV_PHB4_ROOT_PORT;
> +    pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT;
>   }
>   
>   static const TypeInfo pnv_pec_type_info = {
> @@ -313,7 +313,7 @@ static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data)
>       pecc->version = PNV_PHB5_VERSION;
>       pecc->phb_type = TYPE_PNV_PHB5;
>       pecc->num_phbs = pnv_phb5_pec_num_stacks;
> -    pecc->rp_model = TYPE_PNV_PHB5_ROOT_PORT;
> +    pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT;
>   }
>   
>   static const TypeInfo pnv_phb5_pec_type_info = {
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index d82c66ca6f..159899103e 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -2132,6 +2132,7 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
>   
>       static GlobalProperty phb_compat[] = {
>           { TYPE_PNV_PHB, "version", "4" },
> +        { TYPE_PNV_PHB_ROOT_PORT, "version", "4" },
>       };
>   
>       mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
> @@ -2156,6 +2157,7 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
>   
>       static GlobalProperty phb_compat[] = {
>           { TYPE_PNV_PHB, "version", "5" },
> +        { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
>       };
>   
>       mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
> diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
> index f22253358f..29c49ac79c 100644
> --- a/include/hw/pci-host/pnv_phb4.h
> +++ b/include/hw/pci-host/pnv_phb4.h
> @@ -45,16 +45,7 @@ typedef struct PnvPhb4DMASpace {
>       QLIST_ENTRY(PnvPhb4DMASpace) list;
>   } PnvPhb4DMASpace;
>   
> -/*
> - * PHB4 PCIe Root port
> - */
>   #define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root"
> -#define TYPE_PNV_PHB4_ROOT_PORT "pnv-phb4-root-port"
> -#define TYPE_PNV_PHB5_ROOT_PORT "pnv-phb5-root-port"
> -
> -typedef struct PnvPHB4RootPort {
> -    PCIESlot parent_obj;
> -} PnvPHB4RootPort;
>   
>   /*
>    * PHB4 PCIe Host Bridge for PowerNV machines (POWER9)