1 | Just flushing my target-arm queue since I won't be working next week :-) | 1 | The following changes since commit 003ba52a8b327180e284630b289c6ece5a3e08b9: |
---|---|---|---|
2 | 2 | ||
3 | -- PMM | 3 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-02-16 11:16:39 +0000) |
4 | |||
5 | The following changes since commit b3cd3b5a66f0dddfe3d5ba2bef13cd4f5b89cde9: | ||
6 | |||
7 | Merge tag 'pull-riscv-to-apply-20220610' of github.com:alistair23/qemu into staging (2022-06-09 22:08:27 -0700) | ||
8 | 4 | ||
9 | are available in the Git repository at: | 5 | are available in the Git repository at: |
10 | 6 | ||
11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220610 | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230216 |
12 | 8 | ||
13 | for you to fetch changes up to 90c072e063737e9e8f431489bbd334452f89056e: | 9 | for you to fetch changes up to caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8: |
14 | 10 | ||
15 | semihosting/config: Merge --semihosting-config option groups (2022-06-10 14:32:36 +0100) | 11 | tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG (2023-02-16 16:28:53 +0000) |
16 | 12 | ||
17 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
18 | * refactor exception routing code | 14 | target-arm queue: |
19 | * fix SCR_EL3 RAO/RAZ bits | 15 | * Some mostly M-profile-related code cleanups |
20 | * gdbstub: Don't use GDB syscalls if no GDB is attached | 16 | * avocado: Retire the boot_linux.py AArch64 TCG tests |
21 | * semihosting/config: Merge --semihosting-config option groups | 17 | * hw/arm/smmuv3: Add GBPA register |
22 | * tests/qtest: Reduce npcm7xx_sdhci test image size | 18 | * arm/virt: don't try to spell out the accelerator |
19 | * hw/arm: Attach PSPI module to NPCM7XX SoC | ||
20 | * Some cleanup/refactoring patches aiming towards | ||
21 | allowing building Arm targets without CONFIG_TCG | ||
23 | 22 | ||
24 | ---------------------------------------------------------------- | 23 | ---------------------------------------------------------------- |
25 | Hao Wu (1): | 24 | Alex Bennée (1): |
26 | tests/qtest: Reduce npcm7xx_sdhci test image size | 25 | tests/avocado: retire the Aarch64 TCG tests from boot_linux.py |
27 | 26 | ||
28 | Peter Maydell (2): | 27 | Claudio Fontana (3): |
29 | gdbstub: Don't use GDB syscalls if no GDB is attached | 28 | target/arm: rename handle_semihosting to tcg_handle_semihosting |
30 | semihosting/config: Merge --semihosting-config option groups | 29 | target/arm: wrap psci call with tcg_enabled |
30 | target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() | ||
31 | 31 | ||
32 | Richard Henderson (25): | 32 | Cornelia Huck (1): |
33 | target/arm: Mark exception helpers as noreturn | 33 | arm/virt: don't try to spell out the accelerator |
34 | target/arm: Add coproc parameter to syn_fp_access_trap | ||
35 | target/arm: Move exception_target_el out of line | ||
36 | target/arm: Move arm_singlestep_active out of line | ||
37 | target/arm: Move arm_generate_debug_exceptions out of line | ||
38 | target/arm: Use is_a64 in arm_generate_debug_exceptions | ||
39 | target/arm: Move exception_bkpt_insn to debug_helper.c | ||
40 | target/arm: Move arm_debug_exception_fsr to debug_helper.c | ||
41 | target/arm: Rename helper_exception_with_syndrome | ||
42 | target/arm: Introduce gen_exception_insn_el_v | ||
43 | target/arm: Rename gen_exception_insn to gen_exception_insn_el | ||
44 | target/arm: Introduce gen_exception_insn | ||
45 | target/arm: Create helper_exception_swstep | ||
46 | target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_EL | ||
47 | target/arm: Move gen_exception to translate.c | ||
48 | target/arm: Rename gen_exception to gen_exception_el | ||
49 | target/arm: Introduce gen_exception | ||
50 | target/arm: Introduce gen_exception_el_v | ||
51 | target/arm: Introduce helper_exception_with_syndrome | ||
52 | target/arm: Remove default_exception_el | ||
53 | target/arm: Create raise_exception_debug | ||
54 | target/arm: Move arm_debug_target_el to debug_helper.c | ||
55 | target/arm: Fix Secure PL1 tests in fp_exception_el | ||
56 | target/arm: Adjust format test in scr_write | ||
57 | target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12] | ||
58 | 34 | ||
59 | target/arm/cpu.h | 133 ++--------------------- | 35 | Fabiano Rosas (7): |
60 | target/arm/helper.h | 8 +- | 36 | target/arm: Move PC alignment check |
61 | target/arm/internals.h | 43 +------- | 37 | target/arm: Move cpregs code out of cpu.h |
62 | target/arm/syndrome.h | 7 +- | 38 | tests/avocado: Skip tests that require a missing accelerator |
63 | target/arm/translate.h | 43 ++------ | 39 | tests/avocado: Tag TCG tests with accel:tcg |
64 | gdbstub.c | 14 ++- | 40 | target/arm: Use "max" as default cpu for the virt machine with KVM |
65 | semihosting/config.c | 1 + | 41 | tests/qtest: arm-cpu-features: Match tests to required accelerators |
66 | target/arm/debug_helper.c | 220 +++++++++++++++++++++++++++++++++++++-- | 42 | tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG |
67 | target/arm/helper.c | 53 ++++------ | 43 | |
68 | target/arm/op_helper.c | 52 +++++---- | 44 | Hao Wu (3): |
69 | target/arm/translate-a64.c | 34 +++--- | 45 | MAINTAINERS: Add myself to maintainers and remove Havard |
70 | target/arm/translate-m-nocp.c | 15 ++- | 46 | hw/ssi: Add Nuvoton PSPI Module |
71 | target/arm/translate-mve.c | 3 +- | 47 | hw/arm: Attach PSPI module to NPCM7XX SoC |
72 | target/arm/translate-vfp.c | 18 +++- | 48 | |
73 | target/arm/translate.c | 106 ++++++++++--------- | 49 | Jean-Philippe Brucker (2): |
74 | tests/qtest/npcm7xx_sdhci-test.c | 2 +- | 50 | hw/arm/smmu-common: Support 64-bit addresses |
75 | 16 files changed, 390 insertions(+), 362 deletions(-) | 51 | hw/arm/smmu-common: Fix TTB1 handling |
52 | |||
53 | Mostafa Saleh (1): | ||
54 | hw/arm/smmuv3: Add GBPA register | ||
55 | |||
56 | Philippe Mathieu-Daudé (12): | ||
57 | hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro | ||
58 | target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation | ||
59 | target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope | ||
60 | target/arm: Constify ID_PFR1 on user emulation | ||
61 | target/arm: Convert CPUARMState::eabi to boolean | ||
62 | target/arm: Avoid resetting CPUARMState::eabi field | ||
63 | target/arm: Restrict CPUARMState::gicv3state to sysemu | ||
64 | target/arm: Restrict CPUARMState::arm_boot_info to sysemu | ||
65 | target/arm: Restrict CPUARMState::nvic to sysemu | ||
66 | target/arm: Store CPUARMState::nvic as NVICState* | ||
67 | target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h' | ||
68 | hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency | ||
69 | |||
70 | MAINTAINERS | 8 +- | ||
71 | docs/system/arm/nuvoton.rst | 2 +- | ||
72 | hw/arm/smmuv3-internal.h | 7 + | ||
73 | include/hw/arm/npcm7xx.h | 2 + | ||
74 | include/hw/arm/smmu-common.h | 2 - | ||
75 | include/hw/arm/smmuv3.h | 1 + | ||
76 | include/hw/intc/armv7m_nvic.h | 128 +++++++++++++++++- | ||
77 | include/hw/ssi/npcm_pspi.h | 53 ++++++++ | ||
78 | linux-user/user-internals.h | 2 +- | ||
79 | target/arm/cpregs.h | 98 ++++++++++++++ | ||
80 | target/arm/cpu.h | 228 ++------------------------------- | ||
81 | target/arm/internals.h | 14 -- | ||
82 | hw/arm/npcm7xx.c | 25 +++- | ||
83 | hw/arm/smmu-common.c | 4 +- | ||
84 | hw/arm/smmuv3.c | 43 ++++++- | ||
85 | hw/arm/virt.c | 10 +- | ||
86 | hw/intc/armv7m_nvic.c | 38 ++---- | ||
87 | hw/ssi/npcm_pspi.c | 221 ++++++++++++++++++++++++++++++++ | ||
88 | linux-user/arm/cpu_loop.c | 4 +- | ||
89 | target/arm/cpu.c | 5 +- | ||
90 | target/arm/cpu_tcg.c | 3 + | ||
91 | target/arm/helper.c | 31 +++-- | ||
92 | target/arm/m_helper.c | 86 +++++++------ | ||
93 | target/arm/machine.c | 18 +-- | ||
94 | tests/qtest/arm-cpu-features.c | 28 ++-- | ||
95 | hw/arm/Kconfig | 1 + | ||
96 | hw/ssi/meson.build | 2 +- | ||
97 | hw/ssi/trace-events | 5 + | ||
98 | tests/avocado/avocado_qemu/__init__.py | 4 + | ||
99 | tests/avocado/boot_linux.py | 48 ++----- | ||
100 | tests/avocado/boot_linux_console.py | 1 + | ||
101 | tests/avocado/machine_aarch64_virt.py | 63 ++++++++- | ||
102 | tests/avocado/reverse_debugging.py | 8 ++ | ||
103 | tests/qtest/meson.build | 4 +- | ||
104 | 34 files changed, 798 insertions(+), 399 deletions(-) | ||
105 | create mode 100644 include/hw/ssi/npcm_pspi.h | ||
106 | create mode 100644 hw/ssi/npcm_pspi.c | ||
107 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro, | ||
4 | similarly to automatic conversion from commit 8063396bf3 | ||
5 | ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible"). | ||
6 | |||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20230206223502.25122-2-philmd@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/intc/armv7m_nvic.h | 5 +---- | ||
13 | 1 file changed, 1 insertion(+), 4 deletions(-) | ||
14 | |||
15 | diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/intc/armv7m_nvic.h | ||
18 | +++ b/include/hw/intc/armv7m_nvic.h | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | #include "qom/object.h" | ||
21 | |||
22 | #define TYPE_NVIC "armv7m_nvic" | ||
23 | - | ||
24 | -typedef struct NVICState NVICState; | ||
25 | -DECLARE_INSTANCE_CHECKER(NVICState, NVIC, | ||
26 | - TYPE_NVIC) | ||
27 | +OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC) | ||
28 | |||
29 | /* Highest permitted number of exceptions (architectural limit) */ | ||
30 | #define NVIC_MAX_VECTORS 512 | ||
31 | -- | ||
32 | 2.34.1 | ||
33 | |||
34 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Split out a common helper function for gen_exception_el | 3 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> |
4 | and gen_exception_insn_el_v. | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Message-id: 20230206223502.25122-3-philmd@linaro.org |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220609202901.1177572-19-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 8 | --- |
11 | target/arm/translate.c | 13 ++++++++----- | 9 | target/arm/m_helper.c | 11 ++++++++--- |
12 | 1 file changed, 8 insertions(+), 5 deletions(-) | 10 | 1 file changed, 8 insertions(+), 3 deletions(-) |
13 | 11 | ||
14 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 12 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c |
15 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/translate.c | 14 | --- a/target/arm/m_helper.c |
17 | +++ b/target/arm/translate.c | 15 | +++ b/target/arm/m_helper.c |
18 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) | 16 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) |
19 | s->base.is_jmp = DISAS_NORETURN; | 17 | return 0; |
20 | } | 18 | } |
21 | 19 | ||
22 | -static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) | 20 | -#else |
23 | +static void gen_exception_el_v(int excp, uint32_t syndrome, TCGv_i32 tcg_el) | 21 | +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
24 | { | 22 | +{ |
25 | gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), | 23 | + return ARMMMUIdx_MUser; |
26 | - tcg_constant_i32(syndrome), | ||
27 | - tcg_constant_i32(target_el)); | ||
28 | + tcg_constant_i32(syndrome), tcg_el); | ||
29 | +} | 24 | +} |
30 | + | 25 | + |
31 | +static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) | 26 | +#else /* !CONFIG_USER_ONLY */ |
32 | +{ | 27 | |
33 | + gen_exception_el_v(excp, syndrome, tcg_constant_i32(target_el)); | 28 | /* |
29 | * What kind of stack write are we doing? This affects how exceptions | ||
30 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) | ||
31 | return tt_resp; | ||
34 | } | 32 | } |
35 | 33 | ||
36 | static void gen_exception(DisasContext *s, int excp, uint32_t syndrome) | 34 | -#endif /* !CONFIG_USER_ONLY */ |
37 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, | 35 | - |
38 | gen_set_condexec(s); | 36 | ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, |
39 | gen_set_pc_im(s, pc); | 37 | bool secstate, bool priv, bool negpri) |
40 | } | 38 | { |
41 | - gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), | 39 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
42 | - tcg_constant_i32(syn), tcg_el); | 40 | |
43 | + gen_exception_el_v(excp, syn, tcg_el); | 41 | return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); |
44 | s->base.is_jmp = DISAS_NORETURN; | ||
45 | } | 42 | } |
46 | 43 | + | |
44 | +#endif /* !CONFIG_USER_ONLY */ | ||
47 | -- | 45 | -- |
48 | 2.25.1 | 46 | 2.34.1 |
47 | |||
48 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This function now now only used in debug_helper.c, so there is | 3 | arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv() |
4 | no reason to have a declaration in a header. | 4 | are only used for system emulation in m_helper.c. |
5 | Move the definitions to avoid prototype forward declarations. | ||
5 | 6 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220609202901.1177572-9-richard.henderson@linaro.org | 9 | Message-id: 20230206223502.25122-4-philmd@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 11 | --- |
11 | target/arm/internals.h | 25 ------------------------- | 12 | target/arm/internals.h | 14 -------- |
12 | target/arm/debug_helper.c | 26 ++++++++++++++++++++++++++ | 13 | target/arm/m_helper.c | 74 +++++++++++++++++++++--------------------- |
13 | 2 files changed, 26 insertions(+), 25 deletions(-) | 14 | 2 files changed, 37 insertions(+), 51 deletions(-) |
14 | 15 | ||
15 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 16 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
16 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/internals.h | 18 | --- a/target/arm/internals.h |
18 | +++ b/target/arm/internals.h | 19 | +++ b/target/arm/internals.h |
19 | @@ -XXX,XX +XXX,XX @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) | 20 | @@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) |
20 | return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; | 21 | |
22 | int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); | ||
23 | |||
24 | -/* | ||
25 | - * Return the MMU index for a v7M CPU with all relevant information | ||
26 | - * manually specified. | ||
27 | - */ | ||
28 | -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | ||
29 | - bool secstate, bool priv, bool negpri); | ||
30 | - | ||
31 | -/* | ||
32 | - * Return the MMU index for a v7M CPU in the specified security and | ||
33 | - * privilege state. | ||
34 | - */ | ||
35 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | ||
36 | - bool secstate, bool priv); | ||
37 | - | ||
38 | /* Return the MMU index for a v7M CPU in the specified security state */ | ||
39 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); | ||
40 | |||
41 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/target/arm/m_helper.c | ||
44 | +++ b/target/arm/m_helper.c | ||
45 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | ||
46 | |||
47 | #else /* !CONFIG_USER_ONLY */ | ||
48 | |||
49 | +static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | ||
50 | + bool secstate, bool priv, bool negpri) | ||
51 | +{ | ||
52 | + ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; | ||
53 | + | ||
54 | + if (priv) { | ||
55 | + mmu_idx |= ARM_MMU_IDX_M_PRIV; | ||
56 | + } | ||
57 | + | ||
58 | + if (negpri) { | ||
59 | + mmu_idx |= ARM_MMU_IDX_M_NEGPRI; | ||
60 | + } | ||
61 | + | ||
62 | + if (secstate) { | ||
63 | + mmu_idx |= ARM_MMU_IDX_M_S; | ||
64 | + } | ||
65 | + | ||
66 | + return mmu_idx; | ||
67 | +} | ||
68 | + | ||
69 | +static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | ||
70 | + bool secstate, bool priv) | ||
71 | +{ | ||
72 | + bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); | ||
73 | + | ||
74 | + return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); | ||
75 | +} | ||
76 | + | ||
77 | +/* Return the MMU index for a v7M CPU in the specified security state */ | ||
78 | +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | ||
79 | +{ | ||
80 | + bool priv = arm_v7m_is_handler_mode(env) || | ||
81 | + !(env->v7m.control[secstate] & 1); | ||
82 | + | ||
83 | + return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); | ||
84 | +} | ||
85 | + | ||
86 | /* | ||
87 | * What kind of stack write are we doing? This affects how exceptions | ||
88 | * generated during the stacking are treated. | ||
89 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) | ||
90 | return tt_resp; | ||
21 | } | 91 | } |
22 | 92 | ||
23 | -/* Return the FSR value for a debug exception (watchpoint, hardware | 93 | -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, |
24 | - * breakpoint or BKPT insn) targeting the specified exception level. | 94 | - bool secstate, bool priv, bool negpri) |
25 | - */ | ||
26 | -static inline uint32_t arm_debug_exception_fsr(CPUARMState *env) | ||
27 | -{ | 95 | -{ |
28 | - ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; | 96 | - ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; |
29 | - int target_el = arm_debug_target_el(env); | ||
30 | - bool using_lpae = false; | ||
31 | - | 97 | - |
32 | - if (target_el == 2 || arm_el_is_aa64(env, target_el)) { | 98 | - if (priv) { |
33 | - using_lpae = true; | 99 | - mmu_idx |= ARM_MMU_IDX_M_PRIV; |
34 | - } else { | ||
35 | - if (arm_feature(env, ARM_FEATURE_LPAE) && | ||
36 | - (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { | ||
37 | - using_lpae = true; | ||
38 | - } | ||
39 | - } | 100 | - } |
40 | - | 101 | - |
41 | - if (using_lpae) { | 102 | - if (negpri) { |
42 | - return arm_fi_to_lfsc(&fi); | 103 | - mmu_idx |= ARM_MMU_IDX_M_NEGPRI; |
43 | - } else { | ||
44 | - return arm_fi_to_sfsc(&fi); | ||
45 | - } | 104 | - } |
105 | - | ||
106 | - if (secstate) { | ||
107 | - mmu_idx |= ARM_MMU_IDX_M_S; | ||
108 | - } | ||
109 | - | ||
110 | - return mmu_idx; | ||
46 | -} | 111 | -} |
47 | - | 112 | - |
48 | /** | 113 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, |
49 | * arm_num_brps: Return number of implemented breakpoints. | 114 | - bool secstate, bool priv) |
50 | * Note that the ID register BRPS field is "number of bps - 1", | 115 | -{ |
51 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c | 116 | - bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); |
52 | index XXXXXXX..XXXXXXX 100644 | 117 | - |
53 | --- a/target/arm/debug_helper.c | 118 | - return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); |
54 | +++ b/target/arm/debug_helper.c | 119 | -} |
55 | @@ -XXX,XX +XXX,XX @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) | 120 | - |
56 | return check_watchpoints(cpu); | 121 | -/* Return the MMU index for a v7M CPU in the specified security state */ |
57 | } | 122 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
58 | 123 | -{ | |
59 | +/* | 124 | - bool priv = arm_v7m_is_handler_mode(env) || |
60 | + * Return the FSR value for a debug exception (watchpoint, hardware | 125 | - !(env->v7m.control[secstate] & 1); |
61 | + * breakpoint or BKPT insn) targeting the specified exception level. | 126 | - |
62 | + */ | 127 | - return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); |
63 | +static uint32_t arm_debug_exception_fsr(CPUARMState *env) | 128 | -} |
64 | +{ | 129 | - |
65 | + ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; | 130 | #endif /* !CONFIG_USER_ONLY */ |
66 | + int target_el = arm_debug_target_el(env); | ||
67 | + bool using_lpae = false; | ||
68 | + | ||
69 | + if (target_el == 2 || arm_el_is_aa64(env, target_el)) { | ||
70 | + using_lpae = true; | ||
71 | + } else { | ||
72 | + if (arm_feature(env, ARM_FEATURE_LPAE) && | ||
73 | + (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { | ||
74 | + using_lpae = true; | ||
75 | + } | ||
76 | + } | ||
77 | + | ||
78 | + if (using_lpae) { | ||
79 | + return arm_fi_to_lfsc(&fi); | ||
80 | + } else { | ||
81 | + return arm_fi_to_sfsc(&fi); | ||
82 | + } | ||
83 | +} | ||
84 | + | ||
85 | void arm_debug_excp_handler(CPUState *cs) | ||
86 | { | ||
87 | /* | ||
88 | -- | 131 | -- |
89 | 2.25.1 | 132 | 2.34.1 |
133 | |||
134 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | Message-id: 20220609202901.1177572-8-richard.henderson@linaro.org | 5 | Message-id: 20230206223502.25122-5-philmd@linaro.org |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 7 | --- |
8 | target/arm/debug_helper.c | 31 +++++++++++++++++++++++++++++++ | 8 | target/arm/helper.c | 12 ++++++++++-- |
9 | target/arm/op_helper.c | 29 ----------------------------- | 9 | 1 file changed, 10 insertions(+), 2 deletions(-) |
10 | 2 files changed, 31 insertions(+), 29 deletions(-) | ||
11 | 10 | ||
12 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c | 11 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
13 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/debug_helper.c | 13 | --- a/target/arm/helper.c |
15 | +++ b/target/arm/debug_helper.c | 14 | +++ b/target/arm/helper.c |
16 | @@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs) | 15 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) |
17 | } | 16 | } |
18 | } | 17 | } |
19 | 18 | ||
20 | +/* | 19 | +#ifndef CONFIG_USER_ONLY |
21 | + * Raise an EXCP_BKPT with the specified syndrome register value, | 20 | /* |
22 | + * targeting the correct exception level for debug exceptions. | 21 | * We don't know until after realize whether there's a GICv3 |
23 | + */ | 22 | * attached, and that is what registers the gicv3 sysregs. |
24 | +void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) | 23 | @@ -XXX,XX +XXX,XX @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) |
25 | +{ | 24 | return pfr1; |
26 | + int debug_el = arm_debug_target_el(env); | ||
27 | + int cur_el = arm_current_el(env); | ||
28 | + | ||
29 | + /* FSR will only be used if the debug target EL is AArch32. */ | ||
30 | + env->exception.fsr = arm_debug_exception_fsr(env); | ||
31 | + /* | ||
32 | + * FAR is UNKNOWN: clear vaddress to avoid potentially exposing | ||
33 | + * values to the guest that it shouldn't be able to see at its | ||
34 | + * exception/security level. | ||
35 | + */ | ||
36 | + env->exception.vaddress = 0; | ||
37 | + /* | ||
38 | + * Other kinds of architectural debug exception are ignored if | ||
39 | + * they target an exception level below the current one (in QEMU | ||
40 | + * this is checked by arm_generate_debug_exceptions()). Breakpoint | ||
41 | + * instructions are special because they always generate an exception | ||
42 | + * to somewhere: if they can't go to the configured debug exception | ||
43 | + * level they are taken to the current exception level. | ||
44 | + */ | ||
45 | + if (debug_el < cur_el) { | ||
46 | + debug_el = cur_el; | ||
47 | + } | ||
48 | + raise_exception(env, EXCP_BKPT, syndrome, debug_el); | ||
49 | +} | ||
50 | + | ||
51 | #if !defined(CONFIG_USER_ONLY) | ||
52 | |||
53 | vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) | ||
54 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/target/arm/op_helper.c | ||
57 | +++ b/target/arm/op_helper.c | ||
58 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, | ||
59 | raise_exception(env, excp, syndrome, target_el); | ||
60 | } | 25 | } |
61 | 26 | ||
62 | -/* Raise an EXCP_BKPT with the specified syndrome register value, | 27 | -#ifndef CONFIG_USER_ONLY |
63 | - * targeting the correct exception level for debug exceptions. | 28 | static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) |
64 | - */ | ||
65 | -void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) | ||
66 | -{ | ||
67 | - int debug_el = arm_debug_target_el(env); | ||
68 | - int cur_el = arm_current_el(env); | ||
69 | - | ||
70 | - /* FSR will only be used if the debug target EL is AArch32. */ | ||
71 | - env->exception.fsr = arm_debug_exception_fsr(env); | ||
72 | - /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing | ||
73 | - * values to the guest that it shouldn't be able to see at its | ||
74 | - * exception/security level. | ||
75 | - */ | ||
76 | - env->exception.vaddress = 0; | ||
77 | - /* | ||
78 | - * Other kinds of architectural debug exception are ignored if | ||
79 | - * they target an exception level below the current one (in QEMU | ||
80 | - * this is checked by arm_generate_debug_exceptions()). Breakpoint | ||
81 | - * instructions are special because they always generate an exception | ||
82 | - * to somewhere: if they can't go to the configured debug exception | ||
83 | - * level they are taken to the current exception level. | ||
84 | - */ | ||
85 | - if (debug_el < cur_el) { | ||
86 | - debug_el = cur_el; | ||
87 | - } | ||
88 | - raise_exception(env, EXCP_BKPT, syndrome, debug_el); | ||
89 | -} | ||
90 | - | ||
91 | uint32_t HELPER(cpsr_read)(CPUARMState *env) | ||
92 | { | 29 | { |
93 | return cpsr_read(env) & ~CPSR_EXEC; | 30 | ARMCPU *cpu = env_archcpu(env); |
31 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
32 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | ||
33 | .access = PL1_R, .type = ARM_CP_NO_RAW, | ||
34 | .accessfn = access_aa32_tid3, | ||
35 | +#ifdef CONFIG_USER_ONLY | ||
36 | + .type = ARM_CP_CONST, | ||
37 | + .resetvalue = cpu->isar.id_pfr1, | ||
38 | +#else | ||
39 | + .type = ARM_CP_NO_RAW, | ||
40 | + .accessfn = access_aa32_tid3, | ||
41 | .readfn = id_pfr1_read, | ||
42 | - .writefn = arm_cp_write_ignore }, | ||
43 | + .writefn = arm_cp_write_ignore | ||
44 | +#endif | ||
45 | + }, | ||
46 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, | ||
47 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | ||
48 | .access = PL1_R, .type = ARM_CP_CONST, | ||
94 | -- | 49 | -- |
95 | 2.25.1 | 50 | 2.34.1 |
51 | |||
52 | diff view generated by jsdifflib |
1 | In two places in gdbstub.c we look at gdbserver_state.init to decide | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | whether we're going to do a semihosting syscall via the gdb remote | ||
3 | protocol: | ||
4 | * when setting up, if the user didn't explicitly select either | ||
5 | native semihosting or gdb semihosting, we autoselect, with the | ||
6 | intended behaviour "use gdb if gdb is connected" | ||
7 | * when the semihosting layer attempts to do a syscall via gdb, we | ||
8 | silently ignore it if the gdbstub wasn't actually set up | ||
9 | 2 | ||
10 | However, if the user's commandline sets up the gdbstub but tells QEMU | 3 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> |
11 | to start rather than waiting for a GDB to connect (eg using '-s' but | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
12 | not '-S'), then we will have gdbserver_state.init true but no actual | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
13 | connection; an attempt to use gdb syscalls will then crash because we | 6 | Message-id: 20230206223502.25122-6-philmd@linaro.org |
14 | try to use gdbserver_state.c_cpu when it hasn't been set up: | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | ||
9 | linux-user/user-internals.h | 2 +- | ||
10 | target/arm/cpu.h | 2 +- | ||
11 | linux-user/arm/cpu_loop.c | 4 ++-- | ||
12 | 3 files changed, 4 insertions(+), 4 deletions(-) | ||
15 | 13 | ||
16 | #0 0x00007ffff6803ba8 in qemu_cpu_kick (cpu=0x0) at ../../softmmu/cpus.c:457 | 14 | diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h |
17 | #1 0x00007ffff6c03913 in gdb_do_syscallv (cb=0x7ffff6c19944 <common_semi_cb>, | ||
18 | fmt=0x7ffff7573b7e "", va=0x7ffff56294c0) at ../../gdbstub.c:2946 | ||
19 | #2 0x00007ffff6c19c3a in common_semi_gdb_syscall (cs=0x7ffff83fe060, | ||
20 | cb=0x7ffff6c19944 <common_semi_cb>, fmt=0x7ffff7573b75 "isatty,%x") | ||
21 | at ../../semihosting/arm-compat-semi.c:494 | ||
22 | #3 0x00007ffff6c1a064 in gdb_isattyfn (cs=0x7ffff83fe060, gf=0x7ffff86a3690) | ||
23 | at ../../semihosting/arm-compat-semi.c:636 | ||
24 | #4 0x00007ffff6c1b20f in do_common_semihosting (cs=0x7ffff83fe060) | ||
25 | at ../../semihosting/arm-compat-semi.c:967 | ||
26 | #5 0x00007ffff693a037 in handle_semihosting (cs=0x7ffff83fe060) | ||
27 | at ../../target/arm/helper.c:10316 | ||
28 | |||
29 | You can probably also get into this state via some odd | ||
30 | corner cases involving connecting a GDB and then telling it | ||
31 | to detach from all the vCPUs. | ||
32 | |||
33 | Abstract out the test into a new gdb_attached() function | ||
34 | which returns true only if there's actually a GDB connected | ||
35 | to the debug stub and attached to at least one vCPU. | ||
36 | |||
37 | Reported-by: Liviu Ionescu <ilg@livius.net> | ||
38 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
39 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
40 | Reviewed-by: Luc Michel <luc@lmichel.fr> | ||
41 | Message-id: 20220526190053.521505-2-peter.maydell@linaro.org | ||
42 | --- | ||
43 | gdbstub.c | 14 +++++++++++--- | ||
44 | 1 file changed, 11 insertions(+), 3 deletions(-) | ||
45 | |||
46 | diff --git a/gdbstub.c b/gdbstub.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
48 | --- a/gdbstub.c | 16 | --- a/linux-user/user-internals.h |
49 | +++ b/gdbstub.c | 17 | +++ b/linux-user/user-internals.h |
50 | @@ -XXX,XX +XXX,XX @@ static int get_char(void) | 18 | @@ -XXX,XX +XXX,XX @@ void print_termios(void *arg); |
19 | #ifdef TARGET_ARM | ||
20 | static inline int regpairs_aligned(CPUArchState *cpu_env, int num) | ||
21 | { | ||
22 | - return cpu_env->eabi == 1; | ||
23 | + return cpu_env->eabi; | ||
51 | } | 24 | } |
25 | #elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32) | ||
26 | static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; } | ||
27 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/cpu.h | ||
30 | +++ b/target/arm/cpu.h | ||
31 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
32 | |||
33 | #if defined(CONFIG_USER_ONLY) | ||
34 | /* For usermode syscall translation. */ | ||
35 | - int eabi; | ||
36 | + bool eabi; | ||
52 | #endif | 37 | #endif |
53 | 38 | ||
54 | +/* | 39 | struct CPUBreakpoint *cpu_breakpoint[16]; |
55 | + * Return true if there is a GDB currently connected to the stub | 40 | diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c |
56 | + * and attached to a CPU | 41 | index XXXXXXX..XXXXXXX 100644 |
57 | + */ | 42 | --- a/linux-user/arm/cpu_loop.c |
58 | +static bool gdb_attached(void) | 43 | +++ b/linux-user/arm/cpu_loop.c |
59 | +{ | 44 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) |
60 | + return gdbserver_state.init && gdbserver_state.c_cpu; | 45 | break; |
61 | +} | 46 | case EXCP_SWI: |
62 | + | 47 | { |
63 | static enum { | 48 | - env->eabi = 1; |
64 | GDB_SYS_UNKNOWN, | 49 | + env->eabi = true; |
65 | GDB_SYS_ENABLED, | 50 | /* system call */ |
66 | @@ -XXX,XX +XXX,XX @@ int use_gdb_syscalls(void) | 51 | if (env->thumb) { |
67 | /* -semihosting-config target=auto */ | 52 | /* Thumb is always EABI style with syscall number in r7 */ |
68 | /* On the first call check if gdb is connected and remember. */ | 53 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) |
69 | if (gdb_syscall_mode == GDB_SYS_UNKNOWN) { | 54 | * > 0xfffff and are handled below as out-of-range. |
70 | - gdb_syscall_mode = gdbserver_state.init ? | 55 | */ |
71 | - GDB_SYS_ENABLED : GDB_SYS_DISABLED; | 56 | n ^= ARM_SYSCALL_BASE; |
72 | + gdb_syscall_mode = gdb_attached() ? GDB_SYS_ENABLED : GDB_SYS_DISABLED; | 57 | - env->eabi = 0; |
73 | } | 58 | + env->eabi = false; |
74 | return gdb_syscall_mode == GDB_SYS_ENABLED; | 59 | } |
75 | } | 60 | } |
76 | @@ -XXX,XX +XXX,XX @@ void gdb_do_syscallv(gdb_syscall_complete_cb cb, const char *fmt, va_list va) | ||
77 | target_ulong addr; | ||
78 | uint64_t i64; | ||
79 | |||
80 | - if (!gdbserver_state.init) { | ||
81 | + if (!gdb_attached()) { | ||
82 | return; | ||
83 | } | ||
84 | 61 | ||
85 | -- | 62 | -- |
86 | 2.25.1 | 63 | 2.34.1 |
87 | 64 | ||
88 | 65 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | Although the 'eabi' field is only used in user emulation where | ||
4 | CPU reset doesn't occur, it doesn't belong to the area to reset. | ||
5 | Move it after the 'end_reset_fields' for consistency. | ||
6 | |||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Message-id: 20230206223502.25122-7-philmd@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/cpu.h | 9 ++++----- | ||
13 | 1 file changed, 4 insertions(+), 5 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/cpu.h | ||
18 | +++ b/target/arm/cpu.h | ||
19 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
20 | ARMVectorReg zarray[ARM_MAX_VQ * 16]; | ||
21 | #endif | ||
22 | |||
23 | -#if defined(CONFIG_USER_ONLY) | ||
24 | - /* For usermode syscall translation. */ | ||
25 | - bool eabi; | ||
26 | -#endif | ||
27 | - | ||
28 | struct CPUBreakpoint *cpu_breakpoint[16]; | ||
29 | struct CPUWatchpoint *cpu_watchpoint[16]; | ||
30 | |||
31 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
32 | const struct arm_boot_info *boot_info; | ||
33 | /* Store GICv3CPUState to access from this struct */ | ||
34 | void *gicv3state; | ||
35 | +#if defined(CONFIG_USER_ONLY) | ||
36 | + /* For usermode syscall translation. */ | ||
37 | + bool eabi; | ||
38 | +#endif /* CONFIG_USER_ONLY */ | ||
39 | |||
40 | #ifdef TARGET_TAGGED_ADDRESSES | ||
41 | /* Linux syscall tagged address support */ | ||
42 | -- | ||
43 | 2.34.1 | ||
44 | |||
45 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Since DDI0487F.a, the RW bit is RAO/WI. When specifically | 3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
4 | targeting such a cpu, e.g. cortex-a76, it is legitimate to | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | ignore the bit within the secure monitor. | 5 | Message-id: 20230206223502.25122-8-philmd@linaro.org |
6 | |||
7 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1062 | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20220609214657.1217913-3-richard.henderson@linaro.org | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 7 | --- |
13 | target/arm/cpu.h | 5 +++++ | 8 | target/arm/cpu.h | 3 ++- |
14 | target/arm/helper.c | 4 ++++ | 9 | 1 file changed, 2 insertions(+), 1 deletion(-) |
15 | 2 files changed, 9 insertions(+) | ||
16 | 10 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
18 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 13 | --- a/target/arm/cpu.h |
20 | +++ b/target/arm/cpu.h | 14 | +++ b/target/arm/cpu.h |
21 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) | 15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
22 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; | 16 | |
23 | } | 17 | void *nvic; |
24 | 18 | const struct arm_boot_info *boot_info; | |
25 | +static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) | 19 | +#if !defined(CONFIG_USER_ONLY) |
26 | +{ | 20 | /* Store GICv3CPUState to access from this struct */ |
27 | + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2; | 21 | void *gicv3state; |
28 | +} | 22 | -#if defined(CONFIG_USER_ONLY) |
29 | + | 23 | +#else /* CONFIG_USER_ONLY */ |
30 | static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) | 24 | /* For usermode syscall translation. */ |
31 | { | 25 | bool eabi; |
32 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; | 26 | #endif /* CONFIG_USER_ONLY */ |
33 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/helper.c | ||
36 | +++ b/target/arm/helper.c | ||
37 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
38 | value |= SCR_FW | SCR_AW; /* RES1 */ | ||
39 | valid_mask &= ~SCR_NET; /* RES0 */ | ||
40 | |||
41 | + if (!cpu_isar_feature(aa64_aa32_el1, cpu) && | ||
42 | + !cpu_isar_feature(aa64_aa32_el2, cpu)) { | ||
43 | + value |= SCR_RW; /* RAO/WI */ | ||
44 | + } | ||
45 | if (cpu_isar_feature(aa64_ras, cpu)) { | ||
46 | valid_mask |= SCR_TERR; | ||
47 | } | ||
48 | -- | 27 | -- |
49 | 2.25.1 | 28 | 2.34.1 |
29 | |||
30 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This function is no longer used outside debug_helper.c. | 3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
4 | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | |
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Message-id: 20230206223502.25122-9-philmd@linaro.org |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20220609202901.1177572-23-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 7 | --- |
10 | target/arm/cpu.h | 21 --------------------- | 8 | target/arm/cpu.h | 2 +- |
11 | target/arm/debug_helper.c | 21 +++++++++++++++++++++ | 9 | 1 file changed, 1 insertion(+), 1 deletion(-) |
12 | 2 files changed, 21 insertions(+), 21 deletions(-) | ||
13 | 10 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
15 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.h | 13 | --- a/target/arm/cpu.h |
17 | +++ b/target/arm/cpu.h | 14 | +++ b/target/arm/cpu.h |
18 | @@ -XXX,XX +XXX,XX @@ typedef enum ARMASIdx { | 15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
19 | ARMASIdx_TagS = 3, | 16 | } sau; |
20 | } ARMASIdx; | 17 | |
21 | 18 | void *nvic; | |
22 | -/* Return the Exception Level targeted by debug exceptions. */ | 19 | - const struct arm_boot_info *boot_info; |
23 | -static inline int arm_debug_target_el(CPUARMState *env) | 20 | #if !defined(CONFIG_USER_ONLY) |
24 | -{ | 21 | + const struct arm_boot_info *boot_info; |
25 | - bool secure = arm_is_secure(env); | 22 | /* Store GICv3CPUState to access from this struct */ |
26 | - bool route_to_el2 = false; | 23 | void *gicv3state; |
27 | - | 24 | #else /* CONFIG_USER_ONLY */ |
28 | - if (arm_is_el2_enabled(env)) { | ||
29 | - route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || | ||
30 | - env->cp15.mdcr_el2 & MDCR_TDE; | ||
31 | - } | ||
32 | - | ||
33 | - if (route_to_el2) { | ||
34 | - return 2; | ||
35 | - } else if (arm_feature(env, ARM_FEATURE_EL3) && | ||
36 | - !arm_el_is_aa64(env, 3) && secure) { | ||
37 | - return 3; | ||
38 | - } else { | ||
39 | - return 1; | ||
40 | - } | ||
41 | -} | ||
42 | - | ||
43 | static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) | ||
44 | { | ||
45 | /* If all the CLIDR.Ctypem bits are 0 there are no caches, and | ||
46 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/debug_helper.c | ||
49 | +++ b/target/arm/debug_helper.c | ||
50 | @@ -XXX,XX +XXX,XX @@ | ||
51 | #include "exec/helper-proto.h" | ||
52 | |||
53 | |||
54 | +/* Return the Exception Level targeted by debug exceptions. */ | ||
55 | +static int arm_debug_target_el(CPUARMState *env) | ||
56 | +{ | ||
57 | + bool secure = arm_is_secure(env); | ||
58 | + bool route_to_el2 = false; | ||
59 | + | ||
60 | + if (arm_is_el2_enabled(env)) { | ||
61 | + route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || | ||
62 | + env->cp15.mdcr_el2 & MDCR_TDE; | ||
63 | + } | ||
64 | + | ||
65 | + if (route_to_el2) { | ||
66 | + return 2; | ||
67 | + } else if (arm_feature(env, ARM_FEATURE_EL3) && | ||
68 | + !arm_el_is_aa64(env, 3) && secure) { | ||
69 | + return 3; | ||
70 | + } else { | ||
71 | + return 1; | ||
72 | + } | ||
73 | +} | ||
74 | + | ||
75 | /* | ||
76 | * Raise an exception to the debug target el. | ||
77 | * Modify syndrome to indicate when origin and target EL are the same. | ||
78 | -- | 25 | -- |
79 | 2.25.1 | 26 | 2.34.1 |
27 | |||
28 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We no longer need this value during translation, | 3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
4 | as it is now handled within the helpers. | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | 5 | Message-id: 20230206223502.25122-10-philmd@linaro.org | |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220609202901.1177572-15-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 7 | --- |
11 | target/arm/cpu.h | 6 ++---- | 8 | target/arm/cpu.h | 2 +- |
12 | target/arm/translate.h | 2 -- | 9 | 1 file changed, 1 insertion(+), 1 deletion(-) |
13 | target/arm/helper.c | 12 ++---------- | ||
14 | target/arm/translate-a64.c | 1 - | ||
15 | target/arm/translate.c | 1 - | ||
16 | 5 files changed, 4 insertions(+), 18 deletions(-) | ||
17 | 10 | ||
18 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
19 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/cpu.h | 13 | --- a/target/arm/cpu.h |
21 | +++ b/target/arm/cpu.h | 14 | +++ b/target/arm/cpu.h |
22 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, BE_DATA, 3, 1) | 15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
23 | FIELD(TBFLAG_ANY, MMUIDX, 4, 4) | 16 | uint32_t ctrl; |
24 | /* Target EL if we take a floating-point-disabled exception */ | 17 | } sau; |
25 | FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) | 18 | |
26 | -/* For A-profile only, target EL for debug exceptions. */ | 19 | - void *nvic; |
27 | -FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) | 20 | #if !defined(CONFIG_USER_ONLY) |
28 | /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ | 21 | + void *nvic; |
29 | -FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) | 22 | const struct arm_boot_info *boot_info; |
30 | -FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1) | 23 | /* Store GICv3CPUState to access from this struct */ |
31 | +FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) | 24 | void *gicv3state; |
32 | +FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) | ||
33 | |||
34 | /* | ||
35 | * Bit usage when in AArch32 state, both A- and M-profile. | ||
36 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/translate.h | ||
39 | +++ b/target/arm/translate.h | ||
40 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | ||
41 | */ | ||
42 | uint32_t svc_imm; | ||
43 | int current_el; | ||
44 | - /* Debug target exception level for single-step exceptions */ | ||
45 | - int debug_target_el; | ||
46 | GHashTable *cp_regs; | ||
47 | uint64_t features; /* CPU features bits */ | ||
48 | bool aarch64; | ||
49 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/target/arm/helper.c | ||
52 | +++ b/target/arm/helper.c | ||
53 | @@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, | ||
54 | return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); | ||
55 | } | ||
56 | |||
57 | -static CPUARMTBFlags rebuild_hflags_aprofile(CPUARMState *env) | ||
58 | -{ | ||
59 | - CPUARMTBFlags flags = {}; | ||
60 | - | ||
61 | - DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env)); | ||
62 | - return flags; | ||
63 | -} | ||
64 | - | ||
65 | static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, | ||
66 | ARMMMUIdx mmu_idx) | ||
67 | { | ||
68 | - CPUARMTBFlags flags = rebuild_hflags_aprofile(env); | ||
69 | + CPUARMTBFlags flags = {}; | ||
70 | int el = arm_current_el(env); | ||
71 | |||
72 | if (arm_sctlr(env, el) & SCTLR_A) { | ||
73 | @@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, | ||
74 | static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, | ||
75 | ARMMMUIdx mmu_idx) | ||
76 | { | ||
77 | - CPUARMTBFlags flags = rebuild_hflags_aprofile(env); | ||
78 | + CPUARMTBFlags flags = {}; | ||
79 | ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); | ||
80 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | ||
81 | uint64_t sctlr; | ||
82 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
83 | index XXXXXXX..XXXXXXX 100644 | ||
84 | --- a/target/arm/translate-a64.c | ||
85 | +++ b/target/arm/translate-a64.c | ||
86 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, | ||
87 | dc->ss_active = EX_TBFLAG_ANY(tb_flags, SS_ACTIVE); | ||
88 | dc->pstate_ss = EX_TBFLAG_ANY(tb_flags, PSTATE__SS); | ||
89 | dc->is_ldex = false; | ||
90 | - dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); | ||
91 | |||
92 | /* Bound the number of insns to execute to those left on the page. */ | ||
93 | bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; | ||
94 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
95 | index XXXXXXX..XXXXXXX 100644 | ||
96 | --- a/target/arm/translate.c | ||
97 | +++ b/target/arm/translate.c | ||
98 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) | ||
99 | dc->v7m_lspact = EX_TBFLAG_M32(tb_flags, LSPACT); | ||
100 | dc->mve_no_pred = EX_TBFLAG_M32(tb_flags, MVE_NO_PRED); | ||
101 | } else { | ||
102 | - dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); | ||
103 | dc->sctlr_b = EX_TBFLAG_A32(tb_flags, SCTLR__B); | ||
104 | dc->hstr_active = EX_TBFLAG_A32(tb_flags, HSTR_ACTIVE); | ||
105 | dc->ns = EX_TBFLAG_A32(tb_flags, NS); | ||
106 | -- | 25 | -- |
107 | 2.25.1 | 26 | 2.34.1 |
27 | |||
28 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Move the function to debug_helper.c, and the | 3 | There is no point in using a void pointer to access the NVIC. |
4 | declaration to internals.h. | 4 | Use the real type to avoid casting it while debugging. |
5 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220609202901.1177572-5-richard.henderson@linaro.org | 8 | Message-id: 20230206223502.25122-11-philmd@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | target/arm/cpu.h | 10 ---------- | 11 | target/arm/cpu.h | 46 ++++++++++++++++++++++--------------------- |
12 | target/arm/internals.h | 1 + | 12 | hw/intc/armv7m_nvic.c | 38 ++++++++++++----------------------- |
13 | target/arm/debug_helper.c | 12 ++++++++++++ | 13 | target/arm/cpu.c | 1 + |
14 | 3 files changed, 13 insertions(+), 10 deletions(-) | 14 | target/arm/m_helper.c | 2 +- |
15 | 4 files changed, 39 insertions(+), 48 deletions(-) | ||
15 | 16 | ||
16 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
17 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/cpu.h | 19 | --- a/target/arm/cpu.h |
19 | +++ b/target/arm/cpu.h | 20 | +++ b/target/arm/cpu.h |
20 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_generate_debug_exceptions(CPUARMState *env) | 21 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMTBFlags { |
22 | |||
23 | typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; | ||
24 | |||
25 | +typedef struct NVICState NVICState; | ||
26 | + | ||
27 | typedef struct CPUArchState { | ||
28 | /* Regs for current mode. */ | ||
29 | uint32_t regs[16]; | ||
30 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
31 | } sau; | ||
32 | |||
33 | #if !defined(CONFIG_USER_ONLY) | ||
34 | - void *nvic; | ||
35 | + NVICState *nvic; | ||
36 | const struct arm_boot_info *boot_info; | ||
37 | /* Store GICv3CPUState to access from this struct */ | ||
38 | void *gicv3state; | ||
39 | @@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | ||
40 | |||
41 | /* Interface between CPU and Interrupt controller. */ | ||
42 | #ifndef CONFIG_USER_ONLY | ||
43 | -bool armv7m_nvic_can_take_pending_exception(void *opaque); | ||
44 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s); | ||
45 | #else | ||
46 | -static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) | ||
47 | +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
48 | { | ||
49 | return true; | ||
50 | } | ||
51 | #endif | ||
52 | /** | ||
53 | * armv7m_nvic_set_pending: mark the specified exception as pending | ||
54 | - * @opaque: the NVIC | ||
55 | + * @s: the NVIC | ||
56 | * @irq: the exception number to mark pending | ||
57 | * @secure: false for non-banked exceptions or for the nonsecure | ||
58 | * version of a banked exception, true for the secure version of a banked | ||
59 | @@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) | ||
60 | * if @secure is true and @irq does not specify one of the fixed set | ||
61 | * of architecturally banked exceptions. | ||
62 | */ | ||
63 | -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); | ||
64 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); | ||
65 | /** | ||
66 | * armv7m_nvic_set_pending_derived: mark this derived exception as pending | ||
67 | - * @opaque: the NVIC | ||
68 | + * @s: the NVIC | ||
69 | * @irq: the exception number to mark pending | ||
70 | * @secure: false for non-banked exceptions or for the nonsecure | ||
71 | * version of a banked exception, true for the secure version of a banked | ||
72 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); | ||
73 | * exceptions (exceptions generated in the course of trying to take | ||
74 | * a different exception). | ||
75 | */ | ||
76 | -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); | ||
77 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | ||
78 | /** | ||
79 | * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | ||
80 | - * @opaque: the NVIC | ||
81 | + * @s: the NVIC | ||
82 | * @irq: the exception number to mark pending | ||
83 | * @secure: false for non-banked exceptions or for the nonsecure | ||
84 | * version of a banked exception, true for the secure version of a banked | ||
85 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); | ||
86 | * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
87 | * generated in the course of lazy stacking of FP registers. | ||
88 | */ | ||
89 | -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); | ||
90 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
91 | /** | ||
92 | * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
93 | * exception, and whether it targets Secure state | ||
94 | - * @opaque: the NVIC | ||
95 | + * @s: the NVIC | ||
96 | * @pirq: set to pending exception number | ||
97 | * @ptargets_secure: set to whether pending exception targets Secure | ||
98 | * | ||
99 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); | ||
100 | * to true if the current highest priority pending exception should | ||
101 | * be taken to Secure state, false for NS. | ||
102 | */ | ||
103 | -void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, | ||
104 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
105 | bool *ptargets_secure); | ||
106 | /** | ||
107 | * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
108 | - * @opaque: the NVIC | ||
109 | + * @s: the NVIC | ||
110 | * | ||
111 | * Move the current highest priority pending exception from the pending | ||
112 | * state to the active state, and update v7m.exception to indicate that | ||
113 | * it is the exception currently being handled. | ||
114 | */ | ||
115 | -void armv7m_nvic_acknowledge_irq(void *opaque); | ||
116 | +void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
117 | /** | ||
118 | * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
119 | - * @opaque: the NVIC | ||
120 | + * @s: the NVIC | ||
121 | * @irq: the exception number to complete | ||
122 | * @secure: true if this exception was secure | ||
123 | * | ||
124 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque); | ||
125 | * 0 if there is still an irq active after this one was completed | ||
126 | * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
127 | */ | ||
128 | -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); | ||
129 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
130 | /** | ||
131 | * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
132 | - * @opaque: the NVIC | ||
133 | + * @s: the NVIC | ||
134 | * @irq: the exception number to mark pending | ||
135 | * @secure: false for non-banked exceptions or for the nonsecure | ||
136 | * version of a banked exception, true for the secure version of a banked | ||
137 | @@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); | ||
138 | * interrupt the current execution priority. This controls whether the | ||
139 | * RDY bit for it in the FPCCR is set. | ||
140 | */ | ||
141 | -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); | ||
142 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
143 | /** | ||
144 | * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
145 | - * @opaque: the NVIC | ||
146 | + * @s: the NVIC | ||
147 | * | ||
148 | * Returns: the raw execution priority as defined by the v8M architecture. | ||
149 | * This is the execution priority minus the effects of AIRCR.PRIS, | ||
150 | * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
151 | * (v8M ARM ARM I_PKLD.) | ||
152 | */ | ||
153 | -int armv7m_nvic_raw_execution_priority(void *opaque); | ||
154 | +int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
155 | /** | ||
156 | * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
157 | * priority is negative for the specified security state. | ||
158 | - * @opaque: the NVIC | ||
159 | + * @s: the NVIC | ||
160 | * @secure: the security state to test | ||
161 | * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
162 | */ | ||
163 | #ifndef CONFIG_USER_ONLY | ||
164 | -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); | ||
165 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
166 | #else | ||
167 | -static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
168 | +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
169 | { | ||
170 | return false; | ||
171 | } | ||
172 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
173 | index XXXXXXX..XXXXXXX 100644 | ||
174 | --- a/hw/intc/armv7m_nvic.c | ||
175 | +++ b/hw/intc/armv7m_nvic.c | ||
176 | @@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s) | ||
177 | return MIN(running, s->exception_prio); | ||
178 | } | ||
179 | |||
180 | -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
181 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
182 | { | ||
183 | /* Return true if the requested execution priority is negative | ||
184 | * for the specified security state, ie that security state | ||
185 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
186 | * mean we don't allow FAULTMASK_NS to actually make the execution | ||
187 | * priority negative). Compare pseudocode IsReqExcPriNeg(). | ||
188 | */ | ||
189 | - NVICState *s = opaque; | ||
190 | - | ||
191 | if (s->cpu->env.v7m.faultmask[secure]) { | ||
192 | return true; | ||
21 | } | 193 | } |
22 | } | 194 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) |
23 | 195 | return false; | |
24 | -/* Is single-stepping active? (Note that the "is EL_D AArch64?" check | 196 | } |
25 | - * implicitly means this always returns false in pre-v8 CPUs.) | 197 | |
26 | - */ | 198 | -bool armv7m_nvic_can_take_pending_exception(void *opaque) |
27 | -static inline bool arm_singlestep_active(CPUARMState *env) | 199 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s) |
28 | -{ | 200 | { |
29 | - return extract32(env->cp15.mdscr_el1, 0, 1) | 201 | - NVICState *s = opaque; |
30 | - && arm_el_is_aa64(env, arm_debug_target_el(env)) | ||
31 | - && arm_generate_debug_exceptions(env); | ||
32 | -} | ||
33 | - | 202 | - |
34 | static inline bool arm_sctlr_b(CPUARMState *env) | 203 | return nvic_exec_prio(s) > nvic_pending_prio(s); |
35 | { | 204 | } |
36 | return | 205 | |
37 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 206 | -int armv7m_nvic_raw_execution_priority(void *opaque) |
207 | +int armv7m_nvic_raw_execution_priority(NVICState *s) | ||
208 | { | ||
209 | - NVICState *s = opaque; | ||
210 | - | ||
211 | return s->exception_prio; | ||
212 | } | ||
213 | |||
214 | @@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s) | ||
215 | * if @secure is true and @irq does not specify one of the fixed set | ||
216 | * of architecturally banked exceptions. | ||
217 | */ | ||
218 | -static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure) | ||
219 | +static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure) | ||
220 | { | ||
221 | - NVICState *s = (NVICState *)opaque; | ||
222 | VecInfo *vec; | ||
223 | |||
224 | assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); | ||
225 | @@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure, | ||
226 | } | ||
227 | } | ||
228 | |||
229 | -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure) | ||
230 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure) | ||
231 | { | ||
232 | - do_armv7m_nvic_set_pending(opaque, irq, secure, false); | ||
233 | + do_armv7m_nvic_set_pending(s, irq, secure, false); | ||
234 | } | ||
235 | |||
236 | -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure) | ||
237 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure) | ||
238 | { | ||
239 | - do_armv7m_nvic_set_pending(opaque, irq, secure, true); | ||
240 | + do_armv7m_nvic_set_pending(s, irq, secure, true); | ||
241 | } | ||
242 | |||
243 | -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
244 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure) | ||
245 | { | ||
246 | /* | ||
247 | * Pend an exception during lazy FP stacking. This differs | ||
248 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
249 | * whether we should escalate depends on the saved context | ||
250 | * in the FPCCR register, not on the current state of the CPU/NVIC. | ||
251 | */ | ||
252 | - NVICState *s = (NVICState *)opaque; | ||
253 | bool banked = exc_is_banked(irq); | ||
254 | VecInfo *vec; | ||
255 | bool targets_secure; | ||
256 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
257 | } | ||
258 | |||
259 | /* Make pending IRQ active. */ | ||
260 | -void armv7m_nvic_acknowledge_irq(void *opaque) | ||
261 | +void armv7m_nvic_acknowledge_irq(NVICState *s) | ||
262 | { | ||
263 | - NVICState *s = (NVICState *)opaque; | ||
264 | CPUARMState *env = &s->cpu->env; | ||
265 | const int pending = s->vectpending; | ||
266 | const int running = nvic_exec_prio(s); | ||
267 | @@ -XXX,XX +XXX,XX @@ static bool vectpending_targets_secure(NVICState *s) | ||
268 | exc_targets_secure(s, s->vectpending); | ||
269 | } | ||
270 | |||
271 | -void armv7m_nvic_get_pending_irq_info(void *opaque, | ||
272 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, | ||
273 | int *pirq, bool *ptargets_secure) | ||
274 | { | ||
275 | - NVICState *s = (NVICState *)opaque; | ||
276 | const int pending = s->vectpending; | ||
277 | bool targets_secure; | ||
278 | |||
279 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque, | ||
280 | *pirq = pending; | ||
281 | } | ||
282 | |||
283 | -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) | ||
284 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure) | ||
285 | { | ||
286 | - NVICState *s = (NVICState *)opaque; | ||
287 | VecInfo *vec = NULL; | ||
288 | int ret = 0; | ||
289 | |||
290 | @@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) | ||
291 | return ret; | ||
292 | } | ||
293 | |||
294 | -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
295 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure) | ||
296 | { | ||
297 | /* | ||
298 | * Return whether an exception is "ready", i.e. it is enabled and is | ||
299 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
300 | * for non-banked exceptions secure is always false; for banked exceptions | ||
301 | * it indicates which of the exceptions is required. | ||
302 | */ | ||
303 | - NVICState *s = (NVICState *)opaque; | ||
304 | bool banked = exc_is_banked(irq); | ||
305 | VecInfo *vec; | ||
306 | int running = nvic_exec_prio(s); | ||
307 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | 308 | index XXXXXXX..XXXXXXX 100644 |
39 | --- a/target/arm/internals.h | 309 | --- a/target/arm/cpu.c |
40 | +++ b/target/arm/internals.h | 310 | +++ b/target/arm/cpu.c |
41 | @@ -XXX,XX +XXX,XX @@ bool el_is_in_host(CPUARMState *env, int el); | 311 | @@ -XXX,XX +XXX,XX @@ |
42 | 312 | #if !defined(CONFIG_USER_ONLY) | |
43 | void aa32_max_features(ARMCPU *cpu); | 313 | #include "hw/loader.h" |
44 | int exception_target_el(CPUARMState *env); | 314 | #include "hw/boards.h" |
45 | +bool arm_singlestep_active(CPUARMState *env); | 315 | +#include "hw/intc/armv7m_nvic.h" |
46 | 316 | #endif | |
47 | /* Powers of 2 for sve_vq_map et al. */ | 317 | #include "sysemu/tcg.h" |
48 | #define SVE_VQ_POW2_MAP \ | 318 | #include "sysemu/qtest.h" |
49 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c | 319 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c |
50 | index XXXXXXX..XXXXXXX 100644 | 320 | index XXXXXXX..XXXXXXX 100644 |
51 | --- a/target/arm/debug_helper.c | 321 | --- a/target/arm/m_helper.c |
52 | +++ b/target/arm/debug_helper.c | 322 | +++ b/target/arm/m_helper.c |
53 | @@ -XXX,XX +XXX,XX @@ | 323 | @@ -XXX,XX +XXX,XX @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, |
54 | #include "exec/exec-all.h" | 324 | * that we will need later in order to do lazy FP reg stacking. |
55 | #include "exec/helper-proto.h" | 325 | */ |
56 | 326 | bool is_secure = env->v7m.secure; | |
57 | + | 327 | - void *nvic = env->nvic; |
58 | +/* | 328 | + NVICState *nvic = env->nvic; |
59 | + * Is single-stepping active? (Note that the "is EL_D AArch64?" check | 329 | /* |
60 | + * implicitly means this always returns false in pre-v8 CPUs.) | 330 | * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits |
61 | + */ | 331 | * are banked and we want to update the bit in the bank for the |
62 | +bool arm_singlestep_active(CPUARMState *env) | ||
63 | +{ | ||
64 | + return extract32(env->cp15.mdscr_el1, 0, 1) | ||
65 | + && arm_el_is_aa64(env, arm_debug_target_el(env)) | ||
66 | + && arm_generate_debug_exceptions(env); | ||
67 | +} | ||
68 | + | ||
69 | /* Return true if the linked breakpoint entry lbn passes its checks */ | ||
70 | static bool linked_bp_matches(ARMCPU *cpu, int lbn) | ||
71 | { | ||
72 | -- | 332 | -- |
73 | 2.25.1 | 333 | 2.34.1 |
334 | |||
335 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Handle the debug vs current el exception test in one place. | 3 | While dozens of files include "cpu.h", only 3 files require |
4 | Leave EXCP_BKPT alone, since that treats debug < current differently. | 4 | these NVIC helper declarations. |
5 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Message-id: 20220609202901.1177572-22-richard.henderson@linaro.org | 8 | Message-id: 20230206223502.25122-12-philmd@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | target/arm/debug_helper.c | 44 +++++++++++++++++++++------------------ | 11 | include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++ |
12 | 1 file changed, 24 insertions(+), 20 deletions(-) | 12 | target/arm/cpu.h | 123 ---------------------------------- |
13 | 13 | target/arm/cpu.c | 4 +- | |
14 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c | 14 | target/arm/cpu_tcg.c | 3 + |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | target/arm/m_helper.c | 3 + |
16 | --- a/target/arm/debug_helper.c | 16 | 5 files changed, 132 insertions(+), 124 deletions(-) |
17 | +++ b/target/arm/debug_helper.c | 17 | |
18 | diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/intc/armv7m_nvic.h | ||
21 | +++ b/include/hw/intc/armv7m_nvic.h | ||
22 | @@ -XXX,XX +XXX,XX @@ struct NVICState { | ||
23 | qemu_irq sysresetreq; | ||
24 | }; | ||
25 | |||
26 | +/* Interface between CPU and Interrupt controller. */ | ||
27 | +/** | ||
28 | + * armv7m_nvic_set_pending: mark the specified exception as pending | ||
29 | + * @s: the NVIC | ||
30 | + * @irq: the exception number to mark pending | ||
31 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
32 | + * version of a banked exception, true for the secure version of a banked | ||
33 | + * exception. | ||
34 | + * | ||
35 | + * Marks the specified exception as pending. Note that we will assert() | ||
36 | + * if @secure is true and @irq does not specify one of the fixed set | ||
37 | + * of architecturally banked exceptions. | ||
38 | + */ | ||
39 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); | ||
40 | +/** | ||
41 | + * armv7m_nvic_set_pending_derived: mark this derived exception as pending | ||
42 | + * @s: the NVIC | ||
43 | + * @irq: the exception number to mark pending | ||
44 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
45 | + * version of a banked exception, true for the secure version of a banked | ||
46 | + * exception. | ||
47 | + * | ||
48 | + * Similar to armv7m_nvic_set_pending(), but specifically for derived | ||
49 | + * exceptions (exceptions generated in the course of trying to take | ||
50 | + * a different exception). | ||
51 | + */ | ||
52 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | ||
53 | +/** | ||
54 | + * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | ||
55 | + * @s: the NVIC | ||
56 | + * @irq: the exception number to mark pending | ||
57 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
58 | + * version of a banked exception, true for the secure version of a banked | ||
59 | + * exception. | ||
60 | + * | ||
61 | + * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
62 | + * generated in the course of lazy stacking of FP registers. | ||
63 | + */ | ||
64 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
65 | +/** | ||
66 | + * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
67 | + * exception, and whether it targets Secure state | ||
68 | + * @s: the NVIC | ||
69 | + * @pirq: set to pending exception number | ||
70 | + * @ptargets_secure: set to whether pending exception targets Secure | ||
71 | + * | ||
72 | + * This function writes the number of the highest priority pending | ||
73 | + * exception (the one which would be made active by | ||
74 | + * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure | ||
75 | + * to true if the current highest priority pending exception should | ||
76 | + * be taken to Secure state, false for NS. | ||
77 | + */ | ||
78 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
79 | + bool *ptargets_secure); | ||
80 | +/** | ||
81 | + * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
82 | + * @s: the NVIC | ||
83 | + * | ||
84 | + * Move the current highest priority pending exception from the pending | ||
85 | + * state to the active state, and update v7m.exception to indicate that | ||
86 | + * it is the exception currently being handled. | ||
87 | + */ | ||
88 | +void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
89 | +/** | ||
90 | + * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
91 | + * @s: the NVIC | ||
92 | + * @irq: the exception number to complete | ||
93 | + * @secure: true if this exception was secure | ||
94 | + * | ||
95 | + * Returns: -1 if the irq was not active | ||
96 | + * 1 if completing this irq brought us back to base (no active irqs) | ||
97 | + * 0 if there is still an irq active after this one was completed | ||
98 | + * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
99 | + */ | ||
100 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
101 | +/** | ||
102 | + * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
103 | + * @s: the NVIC | ||
104 | + * @irq: the exception number to mark pending | ||
105 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
106 | + * version of a banked exception, true for the secure version of a banked | ||
107 | + * exception. | ||
108 | + * | ||
109 | + * Return whether an exception is "ready", i.e. whether the exception is | ||
110 | + * enabled and is configured at a priority which would allow it to | ||
111 | + * interrupt the current execution priority. This controls whether the | ||
112 | + * RDY bit for it in the FPCCR is set. | ||
113 | + */ | ||
114 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
115 | +/** | ||
116 | + * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
117 | + * @s: the NVIC | ||
118 | + * | ||
119 | + * Returns: the raw execution priority as defined by the v8M architecture. | ||
120 | + * This is the execution priority minus the effects of AIRCR.PRIS, | ||
121 | + * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
122 | + * (v8M ARM ARM I_PKLD.) | ||
123 | + */ | ||
124 | +int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
125 | +/** | ||
126 | + * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
127 | + * priority is negative for the specified security state. | ||
128 | + * @s: the NVIC | ||
129 | + * @secure: the security state to test | ||
130 | + * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
131 | + */ | ||
132 | +#ifndef CONFIG_USER_ONLY | ||
133 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
134 | +#else | ||
135 | +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
136 | +{ | ||
137 | + return false; | ||
138 | +} | ||
139 | +#endif | ||
140 | +#ifndef CONFIG_USER_ONLY | ||
141 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s); | ||
142 | +#else | ||
143 | +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
144 | +{ | ||
145 | + return true; | ||
146 | +} | ||
147 | +#endif | ||
148 | + | ||
149 | #endif | ||
150 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
151 | index XXXXXXX..XXXXXXX 100644 | ||
152 | --- a/target/arm/cpu.h | ||
153 | +++ b/target/arm/cpu.h | ||
154 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void); | ||
155 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | ||
156 | uint32_t cur_el, bool secure); | ||
157 | |||
158 | -/* Interface between CPU and Interrupt controller. */ | ||
159 | -#ifndef CONFIG_USER_ONLY | ||
160 | -bool armv7m_nvic_can_take_pending_exception(NVICState *s); | ||
161 | -#else | ||
162 | -static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
163 | -{ | ||
164 | - return true; | ||
165 | -} | ||
166 | -#endif | ||
167 | -/** | ||
168 | - * armv7m_nvic_set_pending: mark the specified exception as pending | ||
169 | - * @s: the NVIC | ||
170 | - * @irq: the exception number to mark pending | ||
171 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
172 | - * version of a banked exception, true for the secure version of a banked | ||
173 | - * exception. | ||
174 | - * | ||
175 | - * Marks the specified exception as pending. Note that we will assert() | ||
176 | - * if @secure is true and @irq does not specify one of the fixed set | ||
177 | - * of architecturally banked exceptions. | ||
178 | - */ | ||
179 | -void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); | ||
180 | -/** | ||
181 | - * armv7m_nvic_set_pending_derived: mark this derived exception as pending | ||
182 | - * @s: the NVIC | ||
183 | - * @irq: the exception number to mark pending | ||
184 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
185 | - * version of a banked exception, true for the secure version of a banked | ||
186 | - * exception. | ||
187 | - * | ||
188 | - * Similar to armv7m_nvic_set_pending(), but specifically for derived | ||
189 | - * exceptions (exceptions generated in the course of trying to take | ||
190 | - * a different exception). | ||
191 | - */ | ||
192 | -void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | ||
193 | -/** | ||
194 | - * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | ||
195 | - * @s: the NVIC | ||
196 | - * @irq: the exception number to mark pending | ||
197 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
198 | - * version of a banked exception, true for the secure version of a banked | ||
199 | - * exception. | ||
200 | - * | ||
201 | - * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
202 | - * generated in the course of lazy stacking of FP registers. | ||
203 | - */ | ||
204 | -void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
205 | -/** | ||
206 | - * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
207 | - * exception, and whether it targets Secure state | ||
208 | - * @s: the NVIC | ||
209 | - * @pirq: set to pending exception number | ||
210 | - * @ptargets_secure: set to whether pending exception targets Secure | ||
211 | - * | ||
212 | - * This function writes the number of the highest priority pending | ||
213 | - * exception (the one which would be made active by | ||
214 | - * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure | ||
215 | - * to true if the current highest priority pending exception should | ||
216 | - * be taken to Secure state, false for NS. | ||
217 | - */ | ||
218 | -void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
219 | - bool *ptargets_secure); | ||
220 | -/** | ||
221 | - * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
222 | - * @s: the NVIC | ||
223 | - * | ||
224 | - * Move the current highest priority pending exception from the pending | ||
225 | - * state to the active state, and update v7m.exception to indicate that | ||
226 | - * it is the exception currently being handled. | ||
227 | - */ | ||
228 | -void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
229 | -/** | ||
230 | - * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
231 | - * @s: the NVIC | ||
232 | - * @irq: the exception number to complete | ||
233 | - * @secure: true if this exception was secure | ||
234 | - * | ||
235 | - * Returns: -1 if the irq was not active | ||
236 | - * 1 if completing this irq brought us back to base (no active irqs) | ||
237 | - * 0 if there is still an irq active after this one was completed | ||
238 | - * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
239 | - */ | ||
240 | -int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
241 | -/** | ||
242 | - * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
243 | - * @s: the NVIC | ||
244 | - * @irq: the exception number to mark pending | ||
245 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
246 | - * version of a banked exception, true for the secure version of a banked | ||
247 | - * exception. | ||
248 | - * | ||
249 | - * Return whether an exception is "ready", i.e. whether the exception is | ||
250 | - * enabled and is configured at a priority which would allow it to | ||
251 | - * interrupt the current execution priority. This controls whether the | ||
252 | - * RDY bit for it in the FPCCR is set. | ||
253 | - */ | ||
254 | -bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
255 | -/** | ||
256 | - * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
257 | - * @s: the NVIC | ||
258 | - * | ||
259 | - * Returns: the raw execution priority as defined by the v8M architecture. | ||
260 | - * This is the execution priority minus the effects of AIRCR.PRIS, | ||
261 | - * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
262 | - * (v8M ARM ARM I_PKLD.) | ||
263 | - */ | ||
264 | -int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
265 | -/** | ||
266 | - * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
267 | - * priority is negative for the specified security state. | ||
268 | - * @s: the NVIC | ||
269 | - * @secure: the security state to test | ||
270 | - * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
271 | - */ | ||
272 | -#ifndef CONFIG_USER_ONLY | ||
273 | -bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
274 | -#else | ||
275 | -static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
276 | -{ | ||
277 | - return false; | ||
278 | -} | ||
279 | -#endif | ||
280 | - | ||
281 | /* Interface for defining coprocessor registers. | ||
282 | * Registers are defined in tables of arm_cp_reginfo structs | ||
283 | * which are passed to define_arm_cp_regs(). | ||
284 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
285 | index XXXXXXX..XXXXXXX 100644 | ||
286 | --- a/target/arm/cpu.c | ||
287 | +++ b/target/arm/cpu.c | ||
18 | @@ -XXX,XX +XXX,XX @@ | 288 | @@ -XXX,XX +XXX,XX @@ |
19 | #include "exec/helper-proto.h" | ||
20 | |||
21 | |||
22 | +/* | ||
23 | + * Raise an exception to the debug target el. | ||
24 | + * Modify syndrome to indicate when origin and target EL are the same. | ||
25 | + */ | ||
26 | +G_NORETURN static void | ||
27 | +raise_exception_debug(CPUARMState *env, uint32_t excp, uint32_t syndrome) | ||
28 | +{ | ||
29 | + int debug_el = arm_debug_target_el(env); | ||
30 | + int cur_el = arm_current_el(env); | ||
31 | + | ||
32 | + /* | ||
33 | + * If singlestep is targeting a lower EL than the current one, then | ||
34 | + * DisasContext.ss_active must be false and we can never get here. | ||
35 | + * Similarly for watchpoint and breakpoint matches. | ||
36 | + */ | ||
37 | + assert(debug_el >= cur_el); | ||
38 | + syndrome |= (debug_el == cur_el) << ARM_EL_EC_SHIFT; | ||
39 | + raise_exception(env, excp, syndrome, debug_el); | ||
40 | +} | ||
41 | + | ||
42 | /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ | ||
43 | static bool aa64_generate_debug_exceptions(CPUARMState *env) | ||
44 | { | ||
45 | @@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs) | ||
46 | if (wp_hit) { | ||
47 | if (wp_hit->flags & BP_CPU) { | ||
48 | bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0; | ||
49 | - bool same_el = arm_debug_target_el(env) == arm_current_el(env); | ||
50 | |||
51 | cs->watchpoint_hit = NULL; | ||
52 | |||
53 | env->exception.fsr = arm_debug_exception_fsr(env); | ||
54 | env->exception.vaddress = wp_hit->hitaddr; | ||
55 | - raise_exception(env, EXCP_DATA_ABORT, | ||
56 | - syn_watchpoint(same_el, 0, wnr), | ||
57 | - arm_debug_target_el(env)); | ||
58 | + raise_exception_debug(env, EXCP_DATA_ABORT, | ||
59 | + syn_watchpoint(0, 0, wnr)); | ||
60 | } | ||
61 | } else { | ||
62 | uint64_t pc = is_a64(env) ? env->pc : env->regs[15]; | ||
63 | - bool same_el = (arm_debug_target_el(env) == arm_current_el(env)); | ||
64 | |||
65 | /* | ||
66 | * (1) GDB breakpoints should be handled first. | ||
67 | @@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs) | ||
68 | * exception/security level. | ||
69 | */ | ||
70 | env->exception.vaddress = 0; | ||
71 | - raise_exception(env, EXCP_PREFETCH_ABORT, | ||
72 | - syn_breakpoint(same_el), | ||
73 | - arm_debug_target_el(env)); | ||
74 | + raise_exception_debug(env, EXCP_PREFETCH_ABORT, syn_breakpoint(0)); | ||
75 | } | ||
76 | } | ||
77 | |||
78 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) | ||
79 | |||
80 | void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome) | ||
81 | { | ||
82 | - int debug_el = arm_debug_target_el(env); | ||
83 | - int cur_el = arm_current_el(env); | ||
84 | - | ||
85 | - /* | ||
86 | - * If singlestep is targeting a lower EL than the current one, then | ||
87 | - * DisasContext.ss_active must be false and we can never get here. | ||
88 | - */ | ||
89 | - assert(debug_el >= cur_el); | ||
90 | - if (debug_el == cur_el) { | ||
91 | - syndrome |= 1 << ARM_EL_EC_SHIFT; | ||
92 | - } | ||
93 | - raise_exception(env, EXCP_UDEF, syndrome, debug_el); | ||
94 | + raise_exception_debug(env, EXCP_UDEF, syndrome); | ||
95 | } | ||
96 | |||
97 | #if !defined(CONFIG_USER_ONLY) | 289 | #if !defined(CONFIG_USER_ONLY) |
290 | #include "hw/loader.h" | ||
291 | #include "hw/boards.h" | ||
292 | +#ifdef CONFIG_TCG | ||
293 | #include "hw/intc/armv7m_nvic.h" | ||
294 | -#endif | ||
295 | +#endif /* CONFIG_TCG */ | ||
296 | +#endif /* !CONFIG_USER_ONLY */ | ||
297 | #include "sysemu/tcg.h" | ||
298 | #include "sysemu/qtest.h" | ||
299 | #include "sysemu/hw_accel.h" | ||
300 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
301 | index XXXXXXX..XXXXXXX 100644 | ||
302 | --- a/target/arm/cpu_tcg.c | ||
303 | +++ b/target/arm/cpu_tcg.c | ||
304 | @@ -XXX,XX +XXX,XX @@ | ||
305 | #include "hw/boards.h" | ||
306 | #endif | ||
307 | #include "cpregs.h" | ||
308 | +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) | ||
309 | +#include "hw/intc/armv7m_nvic.h" | ||
310 | +#endif | ||
311 | |||
312 | |||
313 | /* Share AArch32 -cpu max features with AArch64. */ | ||
314 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
315 | index XXXXXXX..XXXXXXX 100644 | ||
316 | --- a/target/arm/m_helper.c | ||
317 | +++ b/target/arm/m_helper.c | ||
318 | @@ -XXX,XX +XXX,XX @@ | ||
319 | #include "exec/cpu_ldst.h" | ||
320 | #include "semihosting/common-semi.h" | ||
321 | #endif | ||
322 | +#if !defined(CONFIG_USER_ONLY) | ||
323 | +#include "hw/intc/armv7m_nvic.h" | ||
324 | +#endif | ||
325 | |||
326 | static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, | ||
327 | uint32_t reg, uint32_t val) | ||
98 | -- | 328 | -- |
99 | 2.25.1 | 329 | 2.34.1 |
330 | |||
331 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This function is no longer used. At the same time, remove | 3 | The two TCG tests for GICv2 and GICv3 are very heavy weight distros |
4 | DisasContext.secure_routed_to_el3, as it in turn becomes unused. | 4 | that take a long time to boot up, especially for an --enable-debug |
5 | 5 | build. The total code coverage they give is: | |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Overall coverage rate: |
8 | Message-id: 20220609202901.1177572-21-richard.henderson@linaro.org | 8 | lines......: 11.2% (59584 of 530123 lines) |
9 | functions..: 15.0% (7436 of 49443 functions) | ||
10 | branches...: 6.3% (19273 of 303933 branches) | ||
11 | |||
12 | We already get pretty close to that with the machine_aarch64_virt | ||
13 | tests which only does one full boot (~120s vs ~600s) of alpine. We | ||
14 | expand the kernel+initrd boot (~8s) to test both GICs and also add an | ||
15 | RNG device and a block device to generate a few IRQs and exercise the | ||
16 | storage layer. With that we get to a coverage of: | ||
17 | |||
18 | Overall coverage rate: | ||
19 | lines......: 11.0% (58121 of 530123 lines) | ||
20 | functions..: 14.9% (7343 of 49443 functions) | ||
21 | branches...: 6.0% (18269 of 303933 branches) | ||
22 | |||
23 | which I feel is close enough given the massive time saving. If we want | ||
24 | to target any more sub-systems we can use lighter weight more directed | ||
25 | tests. | ||
26 | |||
27 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
28 | Reviewed-by: Fabiano Rosas <farosas@suse.de> | ||
29 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
30 | Message-id: 20230203181632.2919715-1-alex.bennee@linaro.org | ||
31 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 32 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 33 | --- |
11 | target/arm/translate.h | 16 ---------------- | 34 | tests/avocado/boot_linux.py | 48 ++++---------------- |
12 | target/arm/translate-a64.c | 5 ----- | 35 | tests/avocado/machine_aarch64_virt.py | 63 ++++++++++++++++++++++++--- |
13 | target/arm/translate.c | 5 ----- | 36 | 2 files changed, 65 insertions(+), 46 deletions(-) |
14 | 3 files changed, 26 deletions(-) | 37 | |
15 | 38 | diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py | |
16 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | 39 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/translate.h | 40 | --- a/tests/avocado/boot_linux.py |
19 | +++ b/target/arm/translate.h | 41 | +++ b/tests/avocado/boot_linux.py |
20 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | 42 | @@ -XXX,XX +XXX,XX @@ def test_pc_q35_kvm(self): |
21 | int fp_excp_el; /* FP exception EL or 0 if enabled */ | 43 | self.launch_and_wait(set_up_ssh_connection=False) |
22 | int sve_excp_el; /* SVE exception EL or 0 if enabled */ | 44 | |
23 | int vl; /* current vector length in bytes */ | 45 | |
24 | - /* Flag indicating that exceptions from secure mode are routed to EL3. */ | 46 | -# For Aarch64 we only boot KVM tests in CI as the TCG tests are very |
25 | - bool secure_routed_to_el3; | 47 | -# heavyweight. There are lighter weight distros which we use in the |
26 | bool vfp_enabled; /* FP enabled via FPSCR.EN */ | 48 | -# machine_aarch64_virt.py tests. |
27 | int vec_len; | 49 | +# For Aarch64 we only boot KVM tests in CI as booting the current |
28 | int vec_stride; | 50 | +# Fedora OS in TCG tests is very heavyweight. There are lighter weight |
29 | @@ -XXX,XX +XXX,XX @@ static inline int get_mem_index(DisasContext *s) | 51 | +# distros which we use in the machine_aarch64_virt.py tests. |
30 | return arm_to_core_mmu_idx(s->mmu_idx); | 52 | class BootLinuxAarch64(LinuxTest): |
31 | } | 53 | """ |
32 | 54 | :avocado: tags=arch:aarch64 | |
33 | -/* Function used to determine the target exception EL when otherwise not known | 55 | :avocado: tags=machine:virt |
34 | - * or default. | 56 | - :avocado: tags=machine:gic-version=2 |
35 | - */ | 57 | """ |
36 | -static inline int default_exception_el(DisasContext *s) | 58 | timeout = 720 |
37 | -{ | 59 | |
38 | - /* If we are coming from secure EL0 in a system with a 32-bit EL3, then | 60 | - def add_common_args(self): |
39 | - * there is no secure EL1, so we route exceptions to EL3. Otherwise, | 61 | - self.vm.add_args('-bios', |
40 | - * exceptions can only be routed to ELs above 1, so we target the higher of | 62 | - os.path.join(BUILD_DIR, 'pc-bios', |
41 | - * 1 or the current EL. | 63 | - 'edk2-aarch64-code.fd')) |
42 | - */ | 64 | - self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') |
43 | - return (s->mmu_idx == ARMMMUIdx_SE10_0 && s->secure_routed_to_el3) | 65 | - self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom') |
44 | - ? 3 : MAX(1, s->current_el); | 66 | - |
45 | -} | 67 | - @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') |
46 | - | 68 | - def test_fedora_cloud_tcg_gicv2(self): |
47 | static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) | 69 | - """ |
48 | { | 70 | - :avocado: tags=accel:tcg |
49 | /* We don't need to save all of the syndrome so we mask and shift | 71 | - :avocado: tags=cpu:max |
50 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 72 | - :avocado: tags=device:gicv2 |
73 | - """ | ||
74 | - self.require_accelerator("tcg") | ||
75 | - self.vm.add_args("-accel", "tcg") | ||
76 | - self.vm.add_args("-cpu", "max,lpa2=off") | ||
77 | - self.vm.add_args("-machine", "virt,gic-version=2") | ||
78 | - self.add_common_args() | ||
79 | - self.launch_and_wait(set_up_ssh_connection=False) | ||
80 | - | ||
81 | - @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') | ||
82 | - def test_fedora_cloud_tcg_gicv3(self): | ||
83 | - """ | ||
84 | - :avocado: tags=accel:tcg | ||
85 | - :avocado: tags=cpu:max | ||
86 | - :avocado: tags=device:gicv3 | ||
87 | - """ | ||
88 | - self.require_accelerator("tcg") | ||
89 | - self.vm.add_args("-accel", "tcg") | ||
90 | - self.vm.add_args("-cpu", "max,lpa2=off") | ||
91 | - self.vm.add_args("-machine", "virt,gic-version=3") | ||
92 | - self.add_common_args() | ||
93 | - self.launch_and_wait(set_up_ssh_connection=False) | ||
94 | - | ||
95 | def test_virt_kvm(self): | ||
96 | """ | ||
97 | :avocado: tags=accel:kvm | ||
98 | @@ -XXX,XX +XXX,XX @@ def test_virt_kvm(self): | ||
99 | self.require_accelerator("kvm") | ||
100 | self.vm.add_args("-accel", "kvm") | ||
101 | self.vm.add_args("-machine", "virt,gic-version=host") | ||
102 | - self.add_common_args() | ||
103 | + self.vm.add_args('-bios', | ||
104 | + os.path.join(BUILD_DIR, 'pc-bios', | ||
105 | + 'edk2-aarch64-code.fd')) | ||
106 | + self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') | ||
107 | + self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom') | ||
108 | self.launch_and_wait(set_up_ssh_connection=False) | ||
109 | |||
110 | |||
111 | diff --git a/tests/avocado/machine_aarch64_virt.py b/tests/avocado/machine_aarch64_virt.py | ||
51 | index XXXXXXX..XXXXXXX 100644 | 112 | index XXXXXXX..XXXXXXX 100644 |
52 | --- a/target/arm/translate-a64.c | 113 | --- a/tests/avocado/machine_aarch64_virt.py |
53 | +++ b/target/arm/translate-a64.c | 114 | +++ b/tests/avocado/machine_aarch64_virt.py |
54 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, | 115 | @@ -XXX,XX +XXX,XX @@ |
55 | dc->condjmp = 0; | 116 | |
56 | 117 | import time | |
57 | dc->aarch64 = true; | 118 | import os |
58 | - /* If we are coming from secure EL0 in a system with a 32-bit EL3, then | 119 | +import logging |
59 | - * there is no secure EL1, so we route exceptions to EL3. | 120 | |
60 | - */ | 121 | from avocado_qemu import QemuSystemTest |
61 | - dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && | 122 | from avocado_qemu import wait_for_console_pattern |
62 | - !arm_el_is_aa64(env, 3); | 123 | from avocado_qemu import exec_command |
63 | dc->thumb = false; | 124 | from avocado_qemu import BUILD_DIR |
64 | dc->sctlr_b = 0; | 125 | +from avocado.utils import process |
65 | dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; | 126 | +from avocado.utils.path import find_command |
66 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 127 | |
67 | index XXXXXXX..XXXXXXX 100644 | 128 | class Aarch64VirtMachine(QemuSystemTest): |
68 | --- a/target/arm/translate.c | 129 | KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 ' |
69 | +++ b/target/arm/translate.c | 130 | @@ -XXX,XX +XXX,XX @@ def test_alpine_virt_tcg_gic_max(self): |
70 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) | 131 | self.wait_for_console_pattern('Welcome to Alpine Linux 3.16') |
71 | dc->condjmp = 0; | 132 | |
72 | 133 | ||
73 | dc->aarch64 = false; | 134 | - def test_aarch64_virt(self): |
74 | - /* If we are coming from secure EL0 in a system with a 32-bit EL3, then | 135 | + def common_aarch64_virt(self, machine): |
75 | - * there is no secure EL1, so we route exceptions to EL3. | 136 | """ |
76 | - */ | 137 | - :avocado: tags=arch:aarch64 |
77 | - dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && | 138 | - :avocado: tags=machine:virt |
78 | - !arm_el_is_aa64(env, 3); | 139 | - :avocado: tags=accel:tcg |
79 | dc->thumb = EX_TBFLAG_AM32(tb_flags, THUMB); | 140 | - :avocado: tags=cpu:max |
80 | dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; | 141 | + Common code to launch basic virt machine with kernel+initrd |
81 | condexec = EX_TBFLAG_AM32(tb_flags, CONDEXEC); | 142 | + and a scratch disk. |
143 | """ | ||
144 | + logger = logging.getLogger('aarch64_virt') | ||
145 | + | ||
146 | kernel_url = ('https://fileserver.linaro.org/s/' | ||
147 | 'z6B2ARM7DQT3HWN/download') | ||
148 | - | ||
149 | kernel_hash = 'ed11daab50c151dde0e1e9c9cb8b2d9bd3215347' | ||
150 | kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) | ||
151 | |||
152 | @@ -XXX,XX +XXX,XX @@ def test_aarch64_virt(self): | ||
153 | 'console=ttyAMA0') | ||
154 | self.require_accelerator("tcg") | ||
155 | self.vm.add_args('-cpu', 'max,pauth-impdef=on', | ||
156 | + '-machine', machine, | ||
157 | '-accel', 'tcg', | ||
158 | '-kernel', kernel_path, | ||
159 | '-append', kernel_command_line) | ||
160 | + | ||
161 | + # A RNG offers an easy way to generate a few IRQs | ||
162 | + self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') | ||
163 | + self.vm.add_args('-object', | ||
164 | + 'rng-random,id=rng0,filename=/dev/urandom') | ||
165 | + | ||
166 | + # Also add a scratch block device | ||
167 | + logger.info('creating scratch qcow2 image') | ||
168 | + image_path = os.path.join(self.workdir, 'scratch.qcow2') | ||
169 | + qemu_img = os.path.join(BUILD_DIR, 'qemu-img') | ||
170 | + if not os.path.exists(qemu_img): | ||
171 | + qemu_img = find_command('qemu-img', False) | ||
172 | + if qemu_img is False: | ||
173 | + self.cancel('Could not find "qemu-img", which is required to ' | ||
174 | + 'create the temporary qcow2 image') | ||
175 | + cmd = '%s create -f qcow2 %s 8M' % (qemu_img, image_path) | ||
176 | + process.run(cmd) | ||
177 | + | ||
178 | + # Add the device | ||
179 | + self.vm.add_args('-blockdev', | ||
180 | + f"driver=qcow2,file.driver=file,file.filename={image_path},node-name=scratch") | ||
181 | + self.vm.add_args('-device', | ||
182 | + 'virtio-blk-device,drive=scratch') | ||
183 | + | ||
184 | self.vm.launch() | ||
185 | self.wait_for_console_pattern('Welcome to Buildroot') | ||
186 | time.sleep(0.1) | ||
187 | exec_command(self, 'root') | ||
188 | time.sleep(0.1) | ||
189 | + exec_command(self, 'dd if=/dev/hwrng of=/dev/vda bs=512 count=4') | ||
190 | + time.sleep(0.1) | ||
191 | + exec_command(self, 'md5sum /dev/vda') | ||
192 | + time.sleep(0.1) | ||
193 | + exec_command(self, 'cat /proc/interrupts') | ||
194 | + time.sleep(0.1) | ||
195 | exec_command(self, 'cat /proc/self/maps') | ||
196 | time.sleep(0.1) | ||
197 | + | ||
198 | + def test_aarch64_virt_gicv3(self): | ||
199 | + """ | ||
200 | + :avocado: tags=arch:aarch64 | ||
201 | + :avocado: tags=machine:virt | ||
202 | + :avocado: tags=accel:tcg | ||
203 | + :avocado: tags=cpu:max | ||
204 | + """ | ||
205 | + self.common_aarch64_virt("virt,gic_version=3") | ||
206 | + | ||
207 | + def test_aarch64_virt_gicv2(self): | ||
208 | + """ | ||
209 | + :avocado: tags=arch:aarch64 | ||
210 | + :avocado: tags=machine:virt | ||
211 | + :avocado: tags=accel:tcg | ||
212 | + :avocado: tags=cpu:max | ||
213 | + """ | ||
214 | + self.common_aarch64_virt("virt,gic-version=2") | ||
82 | -- | 215 | -- |
83 | 2.25.1 | 216 | 2.34.1 |
217 | |||
218 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Mostafa Saleh <smostafa@google.com> |
---|---|---|---|
2 | 2 | ||
3 | With the helper we can use exception_target_el at runtime, | 3 | GBPA register can be used to globally abort all |
4 | instead of default_exception_el at translate time. | 4 | transactions. |
5 | While we're at it, remove the DisasContext parameter from | ||
6 | gen_exception, as it is no longer used. | ||
7 | 5 | ||
6 | It is described in the SMMU manual in "6.3.14 SMMU_GBPA". | ||
7 | ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to | ||
8 | be zero(Do not abort incoming transactions). | ||
9 | |||
10 | Other fields have default values of Use Incoming. | ||
11 | |||
12 | If UPDATE is not set, the write is ignored. This is the only permitted | ||
13 | behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure) | ||
14 | |||
15 | As this patch adds a new state to the SMMU (GBPA), it is added | ||
16 | in a new subsection for forward migration compatibility. | ||
17 | GBPA is only migrated if its value is different from the reset value. | ||
18 | It does this to be backward migration compatible if SW didn't write | ||
19 | the register. | ||
20 | |||
21 | Signed-off-by: Mostafa Saleh <smostafa@google.com> | ||
22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
23 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
24 | Message-id: 20230214094009.2445653-1-smostafa@google.com | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 25 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20220609202901.1177572-20-richard.henderson@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 27 | --- |
13 | target/arm/helper.h | 1 + | 28 | hw/arm/smmuv3-internal.h | 7 +++++++ |
14 | target/arm/op_helper.c | 10 ++++++++++ | 29 | include/hw/arm/smmuv3.h | 1 + |
15 | target/arm/translate.c | 18 +++++++++++++----- | 30 | hw/arm/smmuv3.c | 43 +++++++++++++++++++++++++++++++++++++++- |
16 | 3 files changed, 24 insertions(+), 5 deletions(-) | 31 | 3 files changed, 50 insertions(+), 1 deletion(-) |
17 | 32 | ||
18 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 33 | diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h |
19 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/helper.h | 35 | --- a/hw/arm/smmuv3-internal.h |
21 | +++ b/target/arm/helper.h | 36 | +++ b/hw/arm/smmuv3-internal.h |
22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) | 37 | @@ -XXX,XX +XXX,XX @@ REG32(CR0ACK, 0x24) |
23 | DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, | 38 | REG32(CR1, 0x28) |
24 | i32, i32, i32, i32) | 39 | REG32(CR2, 0x2c) |
25 | DEF_HELPER_2(exception_internal, noreturn, env, i32) | 40 | REG32(STATUSR, 0x40) |
26 | +DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32) | 41 | +REG32(GBPA, 0x44) |
27 | DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) | 42 | + FIELD(GBPA, ABORT, 20, 1) |
28 | DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) | 43 | + FIELD(GBPA, UPDATE, 31, 1) |
29 | DEF_HELPER_2(exception_swstep, noreturn, env, i32) | 44 | + |
30 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | 45 | +/* Use incoming. */ |
46 | +#define SMMU_GBPA_RESET_VAL 0x1000 | ||
47 | + | ||
48 | REG32(IRQ_CTRL, 0x50) | ||
49 | FIELD(IRQ_CTRL, GERROR_IRQEN, 0, 1) | ||
50 | FIELD(IRQ_CTRL, PRI_IRQEN, 1, 1) | ||
51 | diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h | ||
31 | index XXXXXXX..XXXXXXX 100644 | 52 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/target/arm/op_helper.c | 53 | --- a/include/hw/arm/smmuv3.h |
33 | +++ b/target/arm/op_helper.c | 54 | +++ b/include/hw/arm/smmuv3.h |
34 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_with_syndrome_el)(CPUARMState *env, uint32_t excp, | 55 | @@ -XXX,XX +XXX,XX @@ struct SMMUv3State { |
35 | raise_exception(env, excp, syndrome, target_el); | 56 | uint32_t cr[3]; |
57 | uint32_t cr0ack; | ||
58 | uint32_t statusr; | ||
59 | + uint32_t gbpa; | ||
60 | uint32_t irq_ctrl; | ||
61 | uint32_t gerror; | ||
62 | uint32_t gerrorn; | ||
63 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c | ||
64 | index XXXXXXX..XXXXXXX 100644 | ||
65 | --- a/hw/arm/smmuv3.c | ||
66 | +++ b/hw/arm/smmuv3.c | ||
67 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s) | ||
68 | s->gerror = 0; | ||
69 | s->gerrorn = 0; | ||
70 | s->statusr = 0; | ||
71 | + s->gbpa = SMMU_GBPA_RESET_VAL; | ||
36 | } | 72 | } |
37 | 73 | ||
38 | +/* | 74 | static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, |
39 | + * Raise an exception with the specified syndrome register value | 75 | @@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, |
40 | + * to the default target el. | 76 | qemu_mutex_lock(&s->mutex); |
41 | + */ | 77 | |
42 | +void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, | 78 | if (!smmu_enabled(s)) { |
43 | + uint32_t syndrome) | 79 | - status = SMMU_TRANS_DISABLE; |
80 | + if (FIELD_EX32(s->gbpa, GBPA, ABORT)) { | ||
81 | + status = SMMU_TRANS_ABORT; | ||
82 | + } else { | ||
83 | + status = SMMU_TRANS_DISABLE; | ||
84 | + } | ||
85 | goto epilogue; | ||
86 | } | ||
87 | |||
88 | @@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, | ||
89 | case A_GERROR_IRQ_CFG2: | ||
90 | s->gerror_irq_cfg2 = data; | ||
91 | return MEMTX_OK; | ||
92 | + case A_GBPA: | ||
93 | + /* | ||
94 | + * If UPDATE is not set, the write is ignored. This is the only | ||
95 | + * permitted behavior in SMMUv3.2 and later. | ||
96 | + */ | ||
97 | + if (data & R_GBPA_UPDATE_MASK) { | ||
98 | + /* Ignore update bit as write is synchronous. */ | ||
99 | + s->gbpa = data & ~R_GBPA_UPDATE_MASK; | ||
100 | + } | ||
101 | + return MEMTX_OK; | ||
102 | case A_STRTAB_BASE: /* 64b */ | ||
103 | s->strtab_base = deposit64(s->strtab_base, 0, 32, data); | ||
104 | return MEMTX_OK; | ||
105 | @@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset, | ||
106 | case A_STATUSR: | ||
107 | *data = s->statusr; | ||
108 | return MEMTX_OK; | ||
109 | + case A_GBPA: | ||
110 | + *data = s->gbpa; | ||
111 | + return MEMTX_OK; | ||
112 | case A_IRQ_CTRL: | ||
113 | case A_IRQ_CTRL_ACK: | ||
114 | *data = s->irq_ctrl; | ||
115 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3_queue = { | ||
116 | }, | ||
117 | }; | ||
118 | |||
119 | +static bool smmuv3_gbpa_needed(void *opaque) | ||
44 | +{ | 120 | +{ |
45 | + raise_exception(env, excp, syndrome, exception_target_el(env)); | 121 | + SMMUv3State *s = opaque; |
122 | + | ||
123 | + /* Only migrate GBPA if it has different reset value. */ | ||
124 | + return s->gbpa != SMMU_GBPA_RESET_VAL; | ||
46 | +} | 125 | +} |
47 | + | 126 | + |
48 | uint32_t HELPER(cpsr_read)(CPUARMState *env) | 127 | +static const VMStateDescription vmstate_gbpa = { |
49 | { | 128 | + .name = "smmuv3/gbpa", |
50 | return cpsr_read(env) & ~CPSR_EXEC; | 129 | + .version_id = 1, |
51 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 130 | + .minimum_version_id = 1, |
52 | index XXXXXXX..XXXXXXX 100644 | 131 | + .needed = smmuv3_gbpa_needed, |
53 | --- a/target/arm/translate.c | 132 | + .fields = (VMStateField[]) { |
54 | +++ b/target/arm/translate.c | 133 | + VMSTATE_UINT32(gbpa, SMMUv3State), |
55 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) | 134 | + VMSTATE_END_OF_LIST() |
56 | gen_exception_el_v(excp, syndrome, tcg_constant_i32(target_el)); | ||
57 | } | ||
58 | |||
59 | -static void gen_exception(DisasContext *s, int excp, uint32_t syndrome) | ||
60 | +static void gen_exception(int excp, uint32_t syndrome) | ||
61 | { | ||
62 | - gen_exception_el(excp, syndrome, default_exception_el(s)); | ||
63 | + gen_helper_exception_with_syndrome(cpu_env, tcg_constant_i32(excp), | ||
64 | + tcg_constant_i32(syndrome)); | ||
65 | } | ||
66 | |||
67 | static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, | ||
68 | @@ -XXX,XX +XXX,XX @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, | ||
69 | |||
70 | void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn) | ||
71 | { | ||
72 | - gen_exception_insn_el(s, pc, excp, syn, default_exception_el(s)); | ||
73 | + if (s->aarch64) { | ||
74 | + gen_a64_set_pc_im(pc); | ||
75 | + } else { | ||
76 | + gen_set_condexec(s); | ||
77 | + gen_set_pc_im(s, pc); | ||
78 | + } | 135 | + } |
79 | + gen_exception(excp, syn); | 136 | +}; |
80 | + s->base.is_jmp = DISAS_NORETURN; | 137 | + |
81 | } | 138 | static const VMStateDescription vmstate_smmuv3 = { |
82 | 139 | .name = "smmuv3", | |
83 | static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) | 140 | .version_id = 1, |
84 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | 141 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = { |
85 | switch (dc->base.is_jmp) { | 142 | |
86 | case DISAS_SWI: | 143 | VMSTATE_END_OF_LIST(), |
87 | gen_ss_advance(dc); | 144 | }, |
88 | - gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); | 145 | + .subsections = (const VMStateDescription * []) { |
89 | + gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); | 146 | + &vmstate_gbpa, |
90 | break; | 147 | + NULL |
91 | case DISAS_HVC: | 148 | + } |
92 | gen_ss_advance(dc); | 149 | }; |
93 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | 150 | |
94 | gen_helper_yield(cpu_env); | 151 | static void smmuv3_instance_init(Object *obj) |
95 | break; | ||
96 | case DISAS_SWI: | ||
97 | - gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); | ||
98 | + gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); | ||
99 | break; | ||
100 | case DISAS_HVC: | ||
101 | gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); | ||
102 | -- | 152 | -- |
103 | 2.25.1 | 153 | 2.34.1 | diff view generated by jsdifflib |
1 | Currently we mishandle the --semihosting-config option if the | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | user specifies it on the command line more than once. For | ||
3 | example with: | ||
4 | --semihosting-config target=gdb --semihosting-config arg=foo,arg=bar | ||
5 | 2 | ||
6 | the function qemu_semihosting_config_options() is called twice, once | 3 | Since commit acc0b8b05a when running the ZynqMP ZCU102 board with |
7 | for each argument. But that function expects to be called only once, | 4 | a QEMU configured using --without-default-devices, we get: |
8 | and it always unconditionally sets the semihosting.enabled, | ||
9 | semihost_chardev and semihosting.target variables. This means that | ||
10 | if any of those options were set anywhere except the last | ||
11 | --semihosting-config option on the command line, those settings are | ||
12 | ignored. In the example above, 'target=gdb' in the first option is | ||
13 | overridden by an implied default 'target=auto' in the second. | ||
14 | 5 | ||
15 | The QemuOptsList machinery has a flag for handling this kind of | 6 | $ qemu-system-aarch64 -M xlnx-zcu102 |
16 | "option group is setting global state": by setting | 7 | qemu-system-aarch64: missing object type 'usb_dwc3' |
17 | .merge_lists = true; | 8 | Abort trap: 6 |
18 | we make the machinery merge all the --semihosting-config arguments | ||
19 | the user passes into a single set of options and call our | ||
20 | qemu_semihosting_config_options() just once. | ||
21 | 9 | ||
10 | Fix by adding the missing Kconfig dependency. | ||
11 | |||
12 | Fixes: acc0b8b05a ("hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers") | ||
13 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
14 | Message-id: 20230216092327.2203-1-philmd@linaro.org | ||
15 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | ||
22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
23 | Reviewed-by: Luc Michel <luc@lmichel.fr> | ||
24 | Message-id: 20220526190053.521505-3-peter.maydell@linaro.org | ||
25 | --- | 17 | --- |
26 | semihosting/config.c | 1 + | 18 | hw/arm/Kconfig | 1 + |
27 | 1 file changed, 1 insertion(+) | 19 | 1 file changed, 1 insertion(+) |
28 | 20 | ||
29 | diff --git a/semihosting/config.c b/semihosting/config.c | 21 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig |
30 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
31 | --- a/semihosting/config.c | 23 | --- a/hw/arm/Kconfig |
32 | +++ b/semihosting/config.c | 24 | +++ b/hw/arm/Kconfig |
33 | @@ -XXX,XX +XXX,XX @@ | 25 | @@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP_ARM |
34 | 26 | select XLNX_CSU_DMA | |
35 | QemuOptsList qemu_semihosting_config_opts = { | 27 | select XLNX_ZYNQMP |
36 | .name = "semihosting-config", | 28 | select XLNX_ZDMA |
37 | + .merge_lists = true, | 29 | + select USB_DWC3 |
38 | .implied_opt_name = "enable", | 30 | |
39 | .head = QTAILQ_HEAD_INITIALIZER(qemu_semihosting_config_opts.head), | 31 | config XLNX_VERSAL |
40 | .desc = { | 32 | bool |
41 | -- | 33 | -- |
42 | 2.25.1 | 34 | 2.34.1 |
35 | |||
36 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Cornelia Huck <cohuck@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | Create a new wrapper function that passes the default | 3 | Just use current_accel_name() directly. |
4 | exception target to gen_exception_insn_el. | ||
5 | 4 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Cornelia Huck <cohuck@redhat.com> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
8 | Message-id: 20220609202901.1177572-13-richard.henderson@linaro.org | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 9 | --- |
11 | target/arm/translate.h | 1 + | 10 | hw/arm/virt.c | 6 +++--- |
12 | target/arm/translate-a64.c | 15 ++++++--------- | 11 | 1 file changed, 3 insertions(+), 3 deletions(-) |
13 | target/arm/translate-m-nocp.c | 3 +-- | ||
14 | target/arm/translate-mve.c | 3 +-- | ||
15 | target/arm/translate.c | 29 +++++++++++++---------------- | ||
16 | 5 files changed, 22 insertions(+), 29 deletions(-) | ||
17 | 12 | ||
18 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 13 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
19 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/translate.h | 15 | --- a/hw/arm/virt.c |
21 | +++ b/target/arm/translate.h | 16 | +++ b/hw/arm/virt.c |
22 | @@ -XXX,XX +XXX,XX @@ MemOp pow2_align(unsigned i); | 17 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) |
23 | void unallocated_encoding(DisasContext *s); | 18 | if (vms->secure && (kvm_enabled() || hvf_enabled())) { |
24 | void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, | 19 | error_report("mach-virt: %s does not support providing " |
25 | uint32_t syn, uint32_t target_el); | 20 | "Security extensions (TrustZone) to the guest CPU", |
26 | +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn); | 21 | - kvm_enabled() ? "KVM" : "HVF"); |
27 | 22 | + current_accel_name()); | |
28 | /* Return state of Alternate Half-precision flag, caller frees result */ | 23 | exit(1); |
29 | static inline TCGv_i32 get_ahp_flag(void) | ||
30 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/translate-a64.c | ||
33 | +++ b/target/arm/translate-a64.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static void gen_sysreg_undef(DisasContext *s, bool isread, | ||
35 | } else { | ||
36 | syndrome = syn_uncategorized(); | ||
37 | } | 24 | } |
38 | - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syndrome, | 25 | |
39 | - default_exception_el(s)); | 26 | if (vms->virt && (kvm_enabled() || hvf_enabled())) { |
40 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome); | 27 | error_report("mach-virt: %s does not support providing " |
41 | } | 28 | "Virtualization extensions to the guest CPU", |
42 | 29 | - kvm_enabled() ? "KVM" : "HVF"); | |
43 | /* MRS - move from system register | 30 | + current_accel_name()); |
44 | @@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn) | 31 | exit(1); |
45 | switch (op2_ll) { | ||
46 | case 1: /* SVC */ | ||
47 | gen_ss_advance(s); | ||
48 | - gen_exception_insn_el(s, s->base.pc_next, EXCP_SWI, | ||
49 | - syn_aa64_svc(imm16), default_exception_el(s)); | ||
50 | + gen_exception_insn(s, s->base.pc_next, EXCP_SWI, | ||
51 | + syn_aa64_svc(imm16)); | ||
52 | break; | ||
53 | case 2: /* HVC */ | ||
54 | if (s->current_el == 0) { | ||
55 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
56 | * Illegal execution state. This has priority over BTI | ||
57 | * exceptions, but comes after instruction abort exceptions. | ||
58 | */ | ||
59 | - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | ||
60 | - syn_illegalstate(), default_exception_el(s)); | ||
61 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate()); | ||
62 | return; | ||
63 | } | 32 | } |
64 | 33 | ||
65 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | 34 | if (vms->mte && (kvm_enabled() || hvf_enabled())) { |
66 | if (s->btype != 0 | 35 | error_report("mach-virt: %s does not support providing " |
67 | && s->guarded_page | 36 | "MTE to the guest CPU", |
68 | && !btype_destination_ok(insn, s->bt, s->btype)) { | 37 | - kvm_enabled() ? "KVM" : "HVF"); |
69 | - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | 38 | + current_accel_name()); |
70 | - syn_btitrap(s->btype), | 39 | exit(1); |
71 | - default_exception_el(s)); | ||
72 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
73 | + syn_btitrap(s->btype)); | ||
74 | return; | ||
75 | } | ||
76 | } else { | ||
77 | diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c | ||
78 | index XXXXXXX..XXXXXXX 100644 | ||
79 | --- a/target/arm/translate-m-nocp.c | ||
80 | +++ b/target/arm/translate-m-nocp.c | ||
81 | @@ -XXX,XX +XXX,XX @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a) | ||
82 | } | 40 | } |
83 | 41 | ||
84 | if (a->cp != 10) { | ||
85 | - gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, | ||
86 | - syn_uncategorized(), default_exception_el(s)); | ||
87 | + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized()); | ||
88 | return true; | ||
89 | } | ||
90 | |||
91 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
92 | index XXXXXXX..XXXXXXX 100644 | ||
93 | --- a/target/arm/translate-mve.c | ||
94 | +++ b/target/arm/translate-mve.c | ||
95 | @@ -XXX,XX +XXX,XX @@ bool mve_eci_check(DisasContext *s) | ||
96 | return true; | ||
97 | default: | ||
98 | /* Reserved value: INVSTATE UsageFault */ | ||
99 | - gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
100 | - default_exception_el(s)); | ||
101 | + gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized()); | ||
102 | return false; | ||
103 | } | ||
104 | } | ||
105 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
106 | index XXXXXXX..XXXXXXX 100644 | ||
107 | --- a/target/arm/translate.c | ||
108 | +++ b/target/arm/translate.c | ||
109 | @@ -XXX,XX +XXX,XX @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, | ||
110 | gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el)); | ||
111 | } | ||
112 | |||
113 | +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn) | ||
114 | +{ | ||
115 | + gen_exception_insn_el(s, pc, excp, syn, default_exception_el(s)); | ||
116 | +} | ||
117 | + | ||
118 | static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) | ||
119 | { | ||
120 | gen_set_condexec(s); | ||
121 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) | ||
122 | void unallocated_encoding(DisasContext *s) | ||
123 | { | ||
124 | /* Unallocated and reserved encodings are uncategorized */ | ||
125 | - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), | ||
126 | - default_exception_el(s)); | ||
127 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized()); | ||
128 | } | ||
129 | |||
130 | /* Force a TB lookup after an instruction that changes the CPU state. */ | ||
131 | @@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, | ||
132 | * an exception and return false. Otherwise it will return true, | ||
133 | * and set *tgtmode and *regno appropriately. | ||
134 | */ | ||
135 | - int exc_target = default_exception_el(s); | ||
136 | - | ||
137 | /* These instructions are present only in ARMv8, or in ARMv7 with the | ||
138 | * Virtualization Extensions. | ||
139 | */ | ||
140 | @@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, | ||
141 | |||
142 | undef: | ||
143 | /* If we get here then some access check did not pass */ | ||
144 | - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | ||
145 | - syn_uncategorized(), exc_target); | ||
146 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized()); | ||
147 | return false; | ||
148 | } | ||
149 | |||
150 | @@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a) | ||
151 | tmp = load_cpu_field(v7m.ltpsize); | ||
152 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc); | ||
153 | tcg_temp_free_i32(tmp); | ||
154 | - gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
155 | - default_exception_el(s)); | ||
156 | + gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized()); | ||
157 | gen_set_label(skipexc); | ||
158 | } | ||
159 | |||
160 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
161 | * UsageFault exception. | ||
162 | */ | ||
163 | if (arm_dc_feature(s, ARM_FEATURE_M)) { | ||
164 | - gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
165 | - default_exception_el(s)); | ||
166 | + gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized()); | ||
167 | return; | ||
168 | } | ||
169 | |||
170 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
171 | * Illegal execution state. This has priority over BTI | ||
172 | * exceptions, but comes after instruction abort exceptions. | ||
173 | */ | ||
174 | - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | ||
175 | - syn_illegalstate(), default_exception_el(s)); | ||
176 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate()); | ||
177 | return; | ||
178 | } | ||
179 | |||
180 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
181 | * Illegal execution state. This has priority over BTI | ||
182 | * exceptions, but comes after instruction abort exceptions. | ||
183 | */ | ||
184 | - gen_exception_insn_el(dc, dc->pc_curr, EXCP_UDEF, | ||
185 | - syn_illegalstate(), default_exception_el(dc)); | ||
186 | + gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, syn_illegalstate()); | ||
187 | return; | ||
188 | } | ||
189 | |||
190 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
191 | */ | ||
192 | tcg_remove_ops_after(dc->insn_eci_rewind); | ||
193 | dc->condjmp = 0; | ||
194 | - gen_exception_insn_el(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
195 | - default_exception_el(dc)); | ||
196 | + gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE, | ||
197 | + syn_uncategorized()); | ||
198 | } | ||
199 | |||
200 | arm_post_translate_insn(dc); | ||
201 | -- | 42 | -- |
202 | 2.25.1 | 43 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | From: Hao Wu <wuhaotsh@google.com> |
---|---|---|---|
2 | 2 | ||
3 | Creating 1GB image for a simple qtest is unnecessary | 3 | Havard is no longer working on the Nuvoton systems for a while |
4 | and could lead to failures. We reduce the image size | 4 | and won't be able to do any work on it in the future. So I'll |
5 | to 1MB to reduce the test overhead. | 5 | take over maintaining the Nuvoton system from him. |
6 | 6 | ||
7 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | 7 | Signed-off-by: Hao Wu <wuhaotsh@google.com> |
8 | Message-id: 20220609214125.4192212-1-wuhaotsh@google.com | 8 | Acked-by: Havard Skinnemoen <hskinnemoen@google.com> |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> |
10 | Message-id: 20230208235433.3989937-2-wuhaotsh@google.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 12 | --- |
12 | tests/qtest/npcm7xx_sdhci-test.c | 2 +- | 13 | MAINTAINERS | 2 +- |
13 | 1 file changed, 1 insertion(+), 1 deletion(-) | 14 | 1 file changed, 1 insertion(+), 1 deletion(-) |
14 | 15 | ||
15 | diff --git a/tests/qtest/npcm7xx_sdhci-test.c b/tests/qtest/npcm7xx_sdhci-test.c | 16 | diff --git a/MAINTAINERS b/MAINTAINERS |
16 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/tests/qtest/npcm7xx_sdhci-test.c | 18 | --- a/MAINTAINERS |
18 | +++ b/tests/qtest/npcm7xx_sdhci-test.c | 19 | +++ b/MAINTAINERS |
19 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ F: include/hw/net/mv88w8618_eth.h |
20 | #define NPCM7XX_REG_SIZE 0x100 | 21 | F: docs/system/arm/musicpal.rst |
21 | #define NPCM7XX_MMC_BA 0xF0842000 | 22 | |
22 | #define NPCM7XX_BLK_SIZE 512 | 23 | Nuvoton NPCM7xx |
23 | -#define NPCM7XX_TEST_IMAGE_SIZE (1 << 30) | 24 | -M: Havard Skinnemoen <hskinnemoen@google.com> |
24 | +#define NPCM7XX_TEST_IMAGE_SIZE (1 << 20) | 25 | M: Tyrone Ting <kfting@nuvoton.com> |
25 | 26 | +M: Hao Wu <wuhaotsh@google.com> | |
26 | char *sd_path; | 27 | L: qemu-arm@nongnu.org |
27 | 28 | S: Supported | |
29 | F: hw/*/npcm7xx* | ||
28 | -- | 30 | -- |
29 | 2.25.1 | 31 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Hao Wu <wuhaotsh@google.com> |
---|---|---|---|
2 | 2 | ||
3 | Create a new wrapper function that passes the default | 3 | Nuvoton's PSPI is a general purpose SPI module which enables |
4 | exception target to gen_exception_el. | 4 | connections to SPI-based peripheral devices. |
5 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Hao Wu <wuhaotsh@google.com> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Chris Rauer <crauer@google.com> |
8 | Message-id: 20220609202901.1177572-18-richard.henderson@linaro.org | 8 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> |
9 | Message-id: 20230208235433.3989937-3-wuhaotsh@google.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 11 | --- |
11 | target/arm/translate.c | 11 +++++++---- | 12 | MAINTAINERS | 6 +- |
12 | 1 file changed, 7 insertions(+), 4 deletions(-) | 13 | include/hw/ssi/npcm_pspi.h | 53 +++++++++ |
14 | hw/ssi/npcm_pspi.c | 221 +++++++++++++++++++++++++++++++++++++ | ||
15 | hw/ssi/meson.build | 2 +- | ||
16 | hw/ssi/trace-events | 5 + | ||
17 | 5 files changed, 283 insertions(+), 4 deletions(-) | ||
18 | create mode 100644 include/hw/ssi/npcm_pspi.h | ||
19 | create mode 100644 hw/ssi/npcm_pspi.c | ||
13 | 20 | ||
14 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 21 | diff --git a/MAINTAINERS b/MAINTAINERS |
15 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/translate.c | 23 | --- a/MAINTAINERS |
17 | +++ b/target/arm/translate.c | 24 | +++ b/MAINTAINERS |
18 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) | 25 | @@ -XXX,XX +XXX,XX @@ M: Tyrone Ting <kfting@nuvoton.com> |
19 | tcg_constant_i32(target_el)); | 26 | M: Hao Wu <wuhaotsh@google.com> |
20 | } | 27 | L: qemu-arm@nongnu.org |
21 | 28 | S: Supported | |
22 | +static void gen_exception(DisasContext *s, int excp, uint32_t syndrome) | 29 | -F: hw/*/npcm7xx* |
23 | +{ | 30 | -F: include/hw/*/npcm7xx* |
24 | + gen_exception_el(excp, syndrome, default_exception_el(s)); | 31 | -F: tests/qtest/npcm7xx* |
25 | +} | 32 | +F: hw/*/npcm* |
26 | + | 33 | +F: include/hw/*/npcm* |
27 | static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, | 34 | +F: tests/qtest/npcm* |
28 | uint32_t syn, TCGv_i32 tcg_el) | 35 | F: pc-bios/npcm7xx_bootrom.bin |
29 | { | 36 | F: roms/vbootrom |
30 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | 37 | F: docs/system/arm/nuvoton.rst |
31 | switch (dc->base.is_jmp) { | 38 | diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h |
32 | case DISAS_SWI: | 39 | new file mode 100644 |
33 | gen_ss_advance(dc); | 40 | index XXXXXXX..XXXXXXX |
34 | - gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), | 41 | --- /dev/null |
35 | - default_exception_el(dc)); | 42 | +++ b/include/hw/ssi/npcm_pspi.h |
36 | + gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); | 43 | @@ -XXX,XX +XXX,XX @@ |
37 | break; | 44 | +/* |
38 | case DISAS_HVC: | 45 | + * Nuvoton Peripheral SPI Module |
39 | gen_ss_advance(dc); | 46 | + * |
40 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | 47 | + * Copyright 2023 Google LLC |
41 | gen_helper_yield(cpu_env); | 48 | + * |
42 | break; | 49 | + * This program is free software; you can redistribute it and/or modify it |
43 | case DISAS_SWI: | 50 | + * under the terms of the GNU General Public License as published by the |
44 | - gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), | 51 | + * Free Software Foundation; either version 2 of the License, or |
45 | - default_exception_el(dc)); | 52 | + * (at your option) any later version. |
46 | + gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); | 53 | + * |
47 | break; | 54 | + * This program is distributed in the hope that it will be useful, but WITHOUT |
48 | case DISAS_HVC: | 55 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
49 | gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); | 56 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
57 | + * for more details. | ||
58 | + */ | ||
59 | +#ifndef NPCM_PSPI_H | ||
60 | +#define NPCM_PSPI_H | ||
61 | + | ||
62 | +#include "hw/ssi/ssi.h" | ||
63 | +#include "hw/sysbus.h" | ||
64 | + | ||
65 | +/* | ||
66 | + * Number of registers in our device state structure. Don't change this without | ||
67 | + * incrementing the version_id in the vmstate. | ||
68 | + */ | ||
69 | +#define NPCM_PSPI_NR_REGS 3 | ||
70 | + | ||
71 | +/** | ||
72 | + * NPCMPSPIState - Device state for one Flash Interface Unit. | ||
73 | + * @parent: System bus device. | ||
74 | + * @mmio: Memory region for register access. | ||
75 | + * @spi: The SPI bus mastered by this controller. | ||
76 | + * @regs: Register contents. | ||
77 | + * @irq: The interrupt request queue for this module. | ||
78 | + * | ||
79 | + * Each PSPI has a shared bank of registers, and controls up to four chip | ||
80 | + * selects. Each chip select has a dedicated memory region which may be used to | ||
81 | + * read and write the flash connected to that chip select as if it were memory. | ||
82 | + */ | ||
83 | +typedef struct NPCMPSPIState { | ||
84 | + SysBusDevice parent; | ||
85 | + | ||
86 | + MemoryRegion mmio; | ||
87 | + | ||
88 | + SSIBus *spi; | ||
89 | + uint16_t regs[NPCM_PSPI_NR_REGS]; | ||
90 | + qemu_irq irq; | ||
91 | +} NPCMPSPIState; | ||
92 | + | ||
93 | +#define TYPE_NPCM_PSPI "npcm-pspi" | ||
94 | +OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI) | ||
95 | + | ||
96 | +#endif /* NPCM_PSPI_H */ | ||
97 | diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c | ||
98 | new file mode 100644 | ||
99 | index XXXXXXX..XXXXXXX | ||
100 | --- /dev/null | ||
101 | +++ b/hw/ssi/npcm_pspi.c | ||
102 | @@ -XXX,XX +XXX,XX @@ | ||
103 | +/* | ||
104 | + * Nuvoton NPCM Peripheral SPI Module (PSPI) | ||
105 | + * | ||
106 | + * Copyright 2023 Google LLC | ||
107 | + * | ||
108 | + * This program is free software; you can redistribute it and/or modify it | ||
109 | + * under the terms of the GNU General Public License as published by the | ||
110 | + * Free Software Foundation; either version 2 of the License, or | ||
111 | + * (at your option) any later version. | ||
112 | + * | ||
113 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
114 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
115 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
116 | + * for more details. | ||
117 | + */ | ||
118 | + | ||
119 | +#include "qemu/osdep.h" | ||
120 | + | ||
121 | +#include "hw/irq.h" | ||
122 | +#include "hw/registerfields.h" | ||
123 | +#include "hw/ssi/npcm_pspi.h" | ||
124 | +#include "migration/vmstate.h" | ||
125 | +#include "qapi/error.h" | ||
126 | +#include "qemu/error-report.h" | ||
127 | +#include "qemu/log.h" | ||
128 | +#include "qemu/module.h" | ||
129 | +#include "qemu/units.h" | ||
130 | + | ||
131 | +#include "trace.h" | ||
132 | + | ||
133 | +REG16(PSPI_DATA, 0x0) | ||
134 | +REG16(PSPI_CTL1, 0x2) | ||
135 | + FIELD(PSPI_CTL1, SPIEN, 0, 1) | ||
136 | + FIELD(PSPI_CTL1, MOD, 2, 1) | ||
137 | + FIELD(PSPI_CTL1, EIR, 5, 1) | ||
138 | + FIELD(PSPI_CTL1, EIW, 6, 1) | ||
139 | + FIELD(PSPI_CTL1, SCM, 7, 1) | ||
140 | + FIELD(PSPI_CTL1, SCIDL, 8, 1) | ||
141 | + FIELD(PSPI_CTL1, SCDV, 9, 7) | ||
142 | +REG16(PSPI_STAT, 0x4) | ||
143 | + FIELD(PSPI_STAT, BSY, 0, 1) | ||
144 | + FIELD(PSPI_STAT, RBF, 1, 1) | ||
145 | + | ||
146 | +static void npcm_pspi_update_irq(NPCMPSPIState *s) | ||
147 | +{ | ||
148 | + int level = 0; | ||
149 | + | ||
150 | + /* Only fire IRQ when the module is enabled. */ | ||
151 | + if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) { | ||
152 | + /* Update interrupt as BSY is cleared. */ | ||
153 | + if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) && | ||
154 | + FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) { | ||
155 | + level = 1; | ||
156 | + } | ||
157 | + | ||
158 | + /* Update interrupt as RBF is set. */ | ||
159 | + if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) && | ||
160 | + FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) { | ||
161 | + level = 1; | ||
162 | + } | ||
163 | + } | ||
164 | + qemu_set_irq(s->irq, level); | ||
165 | +} | ||
166 | + | ||
167 | +static uint16_t npcm_pspi_read_data(NPCMPSPIState *s) | ||
168 | +{ | ||
169 | + uint16_t value = s->regs[R_PSPI_DATA]; | ||
170 | + | ||
171 | + /* Clear stat bits as the value are read out. */ | ||
172 | + s->regs[R_PSPI_STAT] = 0; | ||
173 | + | ||
174 | + return value; | ||
175 | +} | ||
176 | + | ||
177 | +static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data) | ||
178 | +{ | ||
179 | + uint16_t value = 0; | ||
180 | + | ||
181 | + if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) { | ||
182 | + value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8; | ||
183 | + } | ||
184 | + value |= ssi_transfer(s->spi, extract16(data, 0, 8)); | ||
185 | + s->regs[R_PSPI_DATA] = value; | ||
186 | + | ||
187 | + /* Mark data as available */ | ||
188 | + s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK; | ||
189 | +} | ||
190 | + | ||
191 | +/* Control register read handler. */ | ||
192 | +static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr, | ||
193 | + unsigned int size) | ||
194 | +{ | ||
195 | + NPCMPSPIState *s = opaque; | ||
196 | + uint16_t value; | ||
197 | + | ||
198 | + switch (addr) { | ||
199 | + case A_PSPI_DATA: | ||
200 | + value = npcm_pspi_read_data(s); | ||
201 | + break; | ||
202 | + | ||
203 | + case A_PSPI_CTL1: | ||
204 | + value = s->regs[R_PSPI_CTL1]; | ||
205 | + break; | ||
206 | + | ||
207 | + case A_PSPI_STAT: | ||
208 | + value = s->regs[R_PSPI_STAT]; | ||
209 | + break; | ||
210 | + | ||
211 | + default: | ||
212 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
213 | + "%s: write to invalid offset 0x%" PRIx64 "\n", | ||
214 | + DEVICE(s)->canonical_path, addr); | ||
215 | + return 0; | ||
216 | + } | ||
217 | + trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value); | ||
218 | + npcm_pspi_update_irq(s); | ||
219 | + | ||
220 | + return value; | ||
221 | +} | ||
222 | + | ||
223 | +/* Control register write handler. */ | ||
224 | +static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v, | ||
225 | + unsigned int size) | ||
226 | +{ | ||
227 | + NPCMPSPIState *s = opaque; | ||
228 | + uint16_t value = v; | ||
229 | + | ||
230 | + trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value); | ||
231 | + | ||
232 | + switch (addr) { | ||
233 | + case A_PSPI_DATA: | ||
234 | + npcm_pspi_write_data(s, value); | ||
235 | + break; | ||
236 | + | ||
237 | + case A_PSPI_CTL1: | ||
238 | + s->regs[R_PSPI_CTL1] = value; | ||
239 | + break; | ||
240 | + | ||
241 | + case A_PSPI_STAT: | ||
242 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
243 | + "%s: write to read-only register PSPI_STAT: 0x%08" | ||
244 | + PRIx64 "\n", DEVICE(s)->canonical_path, v); | ||
245 | + break; | ||
246 | + | ||
247 | + default: | ||
248 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
249 | + "%s: write to invalid offset 0x%" PRIx64 "\n", | ||
250 | + DEVICE(s)->canonical_path, addr); | ||
251 | + return; | ||
252 | + } | ||
253 | + npcm_pspi_update_irq(s); | ||
254 | +} | ||
255 | + | ||
256 | +static const MemoryRegionOps npcm_pspi_ctrl_ops = { | ||
257 | + .read = npcm_pspi_ctrl_read, | ||
258 | + .write = npcm_pspi_ctrl_write, | ||
259 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
260 | + .valid = { | ||
261 | + .min_access_size = 1, | ||
262 | + .max_access_size = 2, | ||
263 | + .unaligned = false, | ||
264 | + }, | ||
265 | + .impl = { | ||
266 | + .min_access_size = 2, | ||
267 | + .max_access_size = 2, | ||
268 | + .unaligned = false, | ||
269 | + }, | ||
270 | +}; | ||
271 | + | ||
272 | +static void npcm_pspi_enter_reset(Object *obj, ResetType type) | ||
273 | +{ | ||
274 | + NPCMPSPIState *s = NPCM_PSPI(obj); | ||
275 | + | ||
276 | + trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type); | ||
277 | + memset(s->regs, 0, sizeof(s->regs)); | ||
278 | +} | ||
279 | + | ||
280 | +static void npcm_pspi_realize(DeviceState *dev, Error **errp) | ||
281 | +{ | ||
282 | + NPCMPSPIState *s = NPCM_PSPI(dev); | ||
283 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
284 | + Object *obj = OBJECT(dev); | ||
285 | + | ||
286 | + s->spi = ssi_create_bus(dev, "pspi"); | ||
287 | + memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s, | ||
288 | + "mmio", 4 * KiB); | ||
289 | + sysbus_init_mmio(sbd, &s->mmio); | ||
290 | + sysbus_init_irq(sbd, &s->irq); | ||
291 | +} | ||
292 | + | ||
293 | +static const VMStateDescription vmstate_npcm_pspi = { | ||
294 | + .name = "npcm-pspi", | ||
295 | + .version_id = 0, | ||
296 | + .minimum_version_id = 0, | ||
297 | + .fields = (VMStateField[]) { | ||
298 | + VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS), | ||
299 | + VMSTATE_END_OF_LIST(), | ||
300 | + }, | ||
301 | +}; | ||
302 | + | ||
303 | + | ||
304 | +static void npcm_pspi_class_init(ObjectClass *klass, void *data) | ||
305 | +{ | ||
306 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
307 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
308 | + | ||
309 | + dc->desc = "NPCM Peripheral SPI Module"; | ||
310 | + dc->realize = npcm_pspi_realize; | ||
311 | + dc->vmsd = &vmstate_npcm_pspi; | ||
312 | + rc->phases.enter = npcm_pspi_enter_reset; | ||
313 | +} | ||
314 | + | ||
315 | +static const TypeInfo npcm_pspi_types[] = { | ||
316 | + { | ||
317 | + .name = TYPE_NPCM_PSPI, | ||
318 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
319 | + .instance_size = sizeof(NPCMPSPIState), | ||
320 | + .class_init = npcm_pspi_class_init, | ||
321 | + }, | ||
322 | +}; | ||
323 | +DEFINE_TYPES(npcm_pspi_types); | ||
324 | diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build | ||
325 | index XXXXXXX..XXXXXXX 100644 | ||
326 | --- a/hw/ssi/meson.build | ||
327 | +++ b/hw/ssi/meson.build | ||
328 | @@ -XXX,XX +XXX,XX @@ | ||
329 | softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c')) | ||
330 | softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c')) | ||
331 | -softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c')) | ||
332 | +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'npcm_pspi.c')) | ||
333 | softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c')) | ||
334 | softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c')) | ||
335 | softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c')) | ||
336 | diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events | ||
337 | index XXXXXXX..XXXXXXX 100644 | ||
338 | --- a/hw/ssi/trace-events | ||
339 | +++ b/hw/ssi/trace-events | ||
340 | @@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset: | ||
341 | npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64 | ||
342 | npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64 | ||
343 | |||
344 | +# npcm_pspi.c | ||
345 | +npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d" | ||
346 | +npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16 | ||
347 | +npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16 | ||
348 | + | ||
349 | # ibex_spi_host.c | ||
350 | |||
351 | ibex_spi_host_reset(const char *msg) "%s" | ||
50 | -- | 352 | -- |
51 | 2.25.1 | 353 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Hao Wu <wuhaotsh@google.com> |
---|---|---|---|
2 | 2 | ||
3 | This function is not required by any other translation file. | 3 | Signed-off-by: Hao Wu <wuhaotsh@google.com> |
4 | 4 | Reviewed-by: Titus Rwantare <titusr@google.com> | |
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Message-id: 20230208235433.3989937-4-wuhaotsh@google.com |
7 | Message-id: 20220609202901.1177572-16-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 8 | --- |
10 | target/arm/translate.h | 8 -------- | 9 | docs/system/arm/nuvoton.rst | 2 +- |
11 | target/arm/translate.c | 7 +++++++ | 10 | include/hw/arm/npcm7xx.h | 2 ++ |
12 | 2 files changed, 7 insertions(+), 8 deletions(-) | 11 | hw/arm/npcm7xx.c | 25 +++++++++++++++++++++++-- |
12 | 3 files changed, 26 insertions(+), 3 deletions(-) | ||
13 | 13 | ||
14 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 14 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/translate.h | 16 | --- a/docs/system/arm/nuvoton.rst |
17 | +++ b/target/arm/translate.h | 17 | +++ b/docs/system/arm/nuvoton.rst |
18 | @@ -XXX,XX +XXX,XX @@ static inline void gen_ss_advance(DisasContext *s) | 18 | @@ -XXX,XX +XXX,XX @@ Supported devices |
19 | * SMBus controller (SMBF) | ||
20 | * Ethernet controller (EMC) | ||
21 | * Tachometer | ||
22 | + * Peripheral SPI controller (PSPI) | ||
23 | |||
24 | Missing devices | ||
25 | --------------- | ||
26 | @@ -XXX,XX +XXX,XX @@ Missing devices | ||
27 | |||
28 | * Ethernet controller (GMAC) | ||
29 | * USB device (USBD) | ||
30 | - * Peripheral SPI controller (PSPI) | ||
31 | * SD/MMC host | ||
32 | * PECI interface | ||
33 | * PCI and PCIe root complex and bridges | ||
34 | diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/include/hw/arm/npcm7xx.h | ||
37 | +++ b/include/hw/arm/npcm7xx.h | ||
38 | @@ -XXX,XX +XXX,XX @@ | ||
39 | #include "hw/nvram/npcm7xx_otp.h" | ||
40 | #include "hw/timer/npcm7xx_timer.h" | ||
41 | #include "hw/ssi/npcm7xx_fiu.h" | ||
42 | +#include "hw/ssi/npcm_pspi.h" | ||
43 | #include "hw/usb/hcd-ehci.h" | ||
44 | #include "hw/usb/hcd-ohci.h" | ||
45 | #include "target/arm/cpu.h" | ||
46 | @@ -XXX,XX +XXX,XX @@ struct NPCM7xxState { | ||
47 | NPCM7xxFIUState fiu[2]; | ||
48 | NPCM7xxEMCState emc[2]; | ||
49 | NPCM7xxSDHCIState mmc; | ||
50 | + NPCMPSPIState pspi[2]; | ||
51 | }; | ||
52 | |||
53 | #define TYPE_NPCM7XX "npcm7xx" | ||
54 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/hw/arm/npcm7xx.c | ||
57 | +++ b/hw/arm/npcm7xx.c | ||
58 | @@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt { | ||
59 | NPCM7XX_EMC1RX_IRQ = 15, | ||
60 | NPCM7XX_EMC1TX_IRQ, | ||
61 | NPCM7XX_MMC_IRQ = 26, | ||
62 | + NPCM7XX_PSPI2_IRQ = 28, | ||
63 | + NPCM7XX_PSPI1_IRQ = 31, | ||
64 | NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */ | ||
65 | NPCM7XX_TIMER1_IRQ, | ||
66 | NPCM7XX_TIMER2_IRQ, | ||
67 | @@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_emc_addr[] = { | ||
68 | 0xf0826000, | ||
69 | }; | ||
70 | |||
71 | +/* Register base address for each PSPI Module */ | ||
72 | +static const hwaddr npcm7xx_pspi_addr[] = { | ||
73 | + 0xf0200000, | ||
74 | + 0xf0201000, | ||
75 | +}; | ||
76 | + | ||
77 | static const struct { | ||
78 | hwaddr regs_addr; | ||
79 | uint32_t unconnected_pins; | ||
80 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj) | ||
81 | object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC); | ||
19 | } | 82 | } |
83 | |||
84 | + for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { | ||
85 | + object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI); | ||
86 | + } | ||
87 | + | ||
88 | object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); | ||
20 | } | 89 | } |
21 | 90 | ||
22 | -static inline void gen_exception(int excp, uint32_t syndrome, | 91 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) |
23 | - uint32_t target_el) | 92 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, |
24 | -{ | 93 | npcm7xx_irq(s, NPCM7XX_MMC_IRQ)); |
25 | - gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), | 94 | |
26 | - tcg_constant_i32(syndrome), | 95 | + /* PSPI */ |
27 | - tcg_constant_i32(target_el)); | 96 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi)); |
28 | -} | 97 | + for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { |
29 | - | 98 | + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]); |
30 | /* Generate an architectural singlestep exception */ | 99 | + int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ; |
31 | static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) | ||
32 | { | ||
33 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/translate.c | ||
36 | +++ b/target/arm/translate.c | ||
37 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) | ||
38 | s->base.is_jmp = DISAS_NORETURN; | ||
39 | } | ||
40 | |||
41 | +static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) | ||
42 | +{ | ||
43 | + gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), | ||
44 | + tcg_constant_i32(syndrome), | ||
45 | + tcg_constant_i32(target_el)); | ||
46 | +} | ||
47 | + | 100 | + |
48 | static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, | 101 | + sysbus_realize(sbd, &error_abort); |
49 | uint32_t syn, TCGv_i32 tcg_el) | 102 | + sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]); |
50 | { | 103 | + sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq)); |
104 | + } | ||
105 | + | ||
106 | create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); | ||
107 | create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); | ||
108 | create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); | ||
109 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
110 | create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); | ||
111 | create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); | ||
112 | create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); | ||
113 | - create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB); | ||
114 | - create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB); | ||
115 | create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB); | ||
116 | create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB); | ||
117 | create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB); | ||
51 | -- | 118 | -- |
52 | 2.25.1 | 119 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Move the computation from gen_swstep_exception into a helper. | 3 | Addresses targeting the second translation table (TTB1) in the SMMU have |
4 | all upper bits set. Ensure the IOMMU region covers all 64 bits. | ||
4 | 5 | ||
5 | This fixes a bug when: | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | - MDSCR_EL1.KDE == 1 to enable debug exceptions within EL_D itself | 7 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> |
7 | - we singlestep an ERET from EL_D to some lower EL | 8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
8 | 9 | Message-id: 20230214171921.1917916-2-jean-philippe@linaro.org | |
9 | Previously we were computing 'same el' based on the EL which | ||
10 | executed the ERET instruction, whereas it ought to be computed | ||
11 | based on the EL to which ERET returned. This happens naturally | ||
12 | with the new helper, which runs after EL has been changed. | ||
13 | |||
14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
16 | Message-id: 20220609202901.1177572-14-richard.henderson@linaro.org | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | --- | 11 | --- |
19 | target/arm/helper.h | 1 + | 12 | include/hw/arm/smmu-common.h | 2 -- |
20 | target/arm/translate.h | 12 +++--------- | 13 | hw/arm/smmu-common.c | 2 +- |
21 | target/arm/debug_helper.c | 16 ++++++++++++++++ | 14 | 2 files changed, 1 insertion(+), 3 deletions(-) |
22 | 3 files changed, 20 insertions(+), 9 deletions(-) | ||
23 | 15 | ||
24 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 16 | diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h |
25 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/target/arm/helper.h | 18 | --- a/include/hw/arm/smmu-common.h |
27 | +++ b/target/arm/helper.h | 19 | +++ b/include/hw/arm/smmu-common.h |
28 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, | 20 | @@ -XXX,XX +XXX,XX @@ |
29 | DEF_HELPER_2(exception_internal, noreturn, env, i32) | 21 | #define SMMU_PCI_DEVFN_MAX 256 |
30 | DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) | 22 | #define SMMU_PCI_DEVFN(sid) (sid & 0xFF) |
31 | DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) | 23 | |
32 | +DEF_HELPER_2(exception_swstep, noreturn, env, i32) | 24 | -#define SMMU_MAX_VA_BITS 48 |
33 | DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) | 25 | - |
34 | DEF_HELPER_1(setend, void, env) | 26 | /* |
35 | DEF_HELPER_2(wfi, void, env, i32) | 27 | * Page table walk error types |
36 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 28 | */ |
29 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/target/arm/translate.h | 31 | --- a/hw/arm/smmu-common.c |
39 | +++ b/target/arm/translate.h | 32 | +++ b/hw/arm/smmu-common.c |
40 | @@ -XXX,XX +XXX,XX @@ static inline void gen_exception(int excp, uint32_t syndrome, | 33 | @@ -XXX,XX +XXX,XX @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) |
41 | /* Generate an architectural singlestep exception */ | 34 | |
42 | static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) | 35 | memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), |
43 | { | 36 | s->mrtypename, |
44 | - bool same_el = (s->debug_target_el == s->current_el); | 37 | - OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS); |
45 | - | 38 | + OBJECT(s), name, UINT64_MAX); |
46 | - /* | 39 | address_space_init(&sdev->as, |
47 | - * If singlestep is targeting a lower EL than the current one, | 40 | MEMORY_REGION(&sdev->iommu), name); |
48 | - * then s->ss_active must be false and we can never get here. | 41 | trace_smmu_add_mr(name); |
49 | - */ | ||
50 | - assert(s->debug_target_el >= s->current_el); | ||
51 | - | ||
52 | - gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el); | ||
53 | + /* Fill in the same_el field of the syndrome in the helper. */ | ||
54 | + uint32_t syn = syn_swstep(false, isv, ex); | ||
55 | + gen_helper_exception_swstep(cpu_env, tcg_constant_i32(syn)); | ||
56 | } | ||
57 | |||
58 | /* | ||
59 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c | ||
60 | index XXXXXXX..XXXXXXX 100644 | ||
61 | --- a/target/arm/debug_helper.c | ||
62 | +++ b/target/arm/debug_helper.c | ||
63 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) | ||
64 | raise_exception(env, EXCP_BKPT, syndrome, debug_el); | ||
65 | } | ||
66 | |||
67 | +void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome) | ||
68 | +{ | ||
69 | + int debug_el = arm_debug_target_el(env); | ||
70 | + int cur_el = arm_current_el(env); | ||
71 | + | ||
72 | + /* | ||
73 | + * If singlestep is targeting a lower EL than the current one, then | ||
74 | + * DisasContext.ss_active must be false and we can never get here. | ||
75 | + */ | ||
76 | + assert(debug_el >= cur_el); | ||
77 | + if (debug_el == cur_el) { | ||
78 | + syndrome |= 1 << ARM_EL_EC_SHIFT; | ||
79 | + } | ||
80 | + raise_exception(env, EXCP_UDEF, syndrome, debug_el); | ||
81 | +} | ||
82 | + | ||
83 | #if !defined(CONFIG_USER_ONLY) | ||
84 | |||
85 | vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) | ||
86 | -- | 42 | -- |
87 | 2.25.1 | 43 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Use the accessor rather than the raw structure member. | 3 | Addresses targeting the second translation table (TTB1) in the SMMU have |
4 | all upper bits set (except for the top byte when TBI is enabled). Fix | ||
5 | the TTB1 check. | ||
4 | 6 | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reported-by: Ola Hugosson <ola.hugosson@arm.com> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
7 | Message-id: 20220609202901.1177572-7-richard.henderson@linaro.org | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
11 | Message-id: 20230214171921.1917916-3-jean-philippe@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 13 | --- |
10 | target/arm/debug_helper.c | 2 +- | 14 | hw/arm/smmu-common.c | 2 +- |
11 | 1 file changed, 1 insertion(+), 1 deletion(-) | 15 | 1 file changed, 1 insertion(+), 1 deletion(-) |
12 | 16 | ||
13 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c | 17 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c |
14 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/debug_helper.c | 19 | --- a/hw/arm/smmu-common.c |
16 | +++ b/target/arm/debug_helper.c | 20 | +++ b/hw/arm/smmu-common.c |
17 | @@ -XXX,XX +XXX,XX @@ static bool aa32_generate_debug_exceptions(CPUARMState *env) | 21 | @@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova) |
18 | */ | 22 | /* there is a ttbr0 region and we are in it (high bits all zero) */ |
19 | bool arm_generate_debug_exceptions(CPUARMState *env) | 23 | return &cfg->tt[0]; |
20 | { | 24 | } else if (cfg->tt[1].tsz && |
21 | - if (env->aarch64) { | 25 | - !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) { |
22 | + if (is_a64(env)) { | 26 | + sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) { |
23 | return aa64_generate_debug_exceptions(env); | 27 | /* there is a ttbr1 region and we are in it (high bits all one) */ |
24 | } else { | 28 | return &cfg->tt[1]; |
25 | return aa32_generate_debug_exceptions(env); | 29 | } else if (!cfg->tt[0].tsz) { |
26 | -- | 30 | -- |
27 | 2.25.1 | 31 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Claudio Fontana <cfontana@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | make it clearer from the name that this is a tcg-only function. |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | |
5 | Message-id: 20220609202901.1177572-12-richard.henderson@linaro.org | 5 | Signed-off-by: Claudio Fontana <cfontana@suse.de> |
6 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 11 | --- |
8 | target/arm/translate.h | 4 ++-- | 12 | target/arm/helper.c | 4 ++-- |
9 | target/arm/translate-a64.c | 36 ++++++++++++++++---------------- | 13 | 1 file changed, 2 insertions(+), 2 deletions(-) |
10 | target/arm/translate-m-nocp.c | 16 +++++++------- | ||
11 | target/arm/translate-mve.c | 4 ++-- | ||
12 | target/arm/translate-vfp.c | 6 +++--- | ||
13 | target/arm/translate.c | 39 ++++++++++++++++++----------------- | ||
14 | 6 files changed, 53 insertions(+), 52 deletions(-) | ||
15 | 14 | ||
16 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 15 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/translate.h | 17 | --- a/target/arm/helper.c |
19 | +++ b/target/arm/translate.h | 18 | +++ b/target/arm/helper.c |
20 | @@ -XXX,XX +XXX,XX @@ void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); | 19 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) |
21 | void arm_gen_test_cc(int cc, TCGLabel *label); | 20 | * trapped to the hypervisor in KVM. |
22 | MemOp pow2_align(unsigned i); | 21 | */ |
23 | void unallocated_encoding(DisasContext *s); | 22 | #ifdef CONFIG_TCG |
24 | -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, | 23 | -static void handle_semihosting(CPUState *cs) |
25 | - uint32_t syn, uint32_t target_el); | 24 | +static void tcg_handle_semihosting(CPUState *cs) |
26 | +void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, | 25 | { |
27 | + uint32_t syn, uint32_t target_el); | 26 | ARMCPU *cpu = ARM_CPU(cs); |
28 | 27 | CPUARMState *env = &cpu->env; | |
29 | /* Return state of Alternate Half-precision flag, caller frees result */ | 28 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) |
30 | static inline TCGv_i32 get_ahp_flag(void) | 29 | */ |
31 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 30 | #ifdef CONFIG_TCG |
32 | index XXXXXXX..XXXXXXX 100644 | 31 | if (cs->exception_index == EXCP_SEMIHOST) { |
33 | --- a/target/arm/translate-a64.c | 32 | - handle_semihosting(cs); |
34 | +++ b/target/arm/translate-a64.c | 33 | + tcg_handle_semihosting(cs); |
35 | @@ -XXX,XX +XXX,XX @@ static bool fp_access_check(DisasContext *s) | ||
36 | assert(!s->fp_access_checked); | ||
37 | s->fp_access_checked = true; | ||
38 | |||
39 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
40 | - syn_fp_access_trap(1, 0xe, false, 0), | ||
41 | - s->fp_excp_el); | ||
42 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | ||
43 | + syn_fp_access_trap(1, 0xe, false, 0), | ||
44 | + s->fp_excp_el); | ||
45 | return false; | ||
46 | } | ||
47 | s->fp_access_checked = true; | ||
48 | @@ -XXX,XX +XXX,XX @@ bool sve_access_check(DisasContext *s) | ||
49 | assert(!s->sve_access_checked); | ||
50 | s->sve_access_checked = true; | ||
51 | |||
52 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
53 | - syn_sve_access_trap(), s->sve_excp_el); | ||
54 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | ||
55 | + syn_sve_access_trap(), s->sve_excp_el); | ||
56 | return false; | ||
57 | } | ||
58 | s->sve_access_checked = true; | ||
59 | @@ -XXX,XX +XXX,XX @@ static void gen_sysreg_undef(DisasContext *s, bool isread, | ||
60 | } else { | ||
61 | syndrome = syn_uncategorized(); | ||
62 | } | ||
63 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome, | ||
64 | - default_exception_el(s)); | ||
65 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syndrome, | ||
66 | + default_exception_el(s)); | ||
67 | } | ||
68 | |||
69 | /* MRS - move from system register | ||
70 | @@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn) | ||
71 | switch (op2_ll) { | ||
72 | case 1: /* SVC */ | ||
73 | gen_ss_advance(s); | ||
74 | - gen_exception_insn(s, s->base.pc_next, EXCP_SWI, | ||
75 | - syn_aa64_svc(imm16), default_exception_el(s)); | ||
76 | + gen_exception_insn_el(s, s->base.pc_next, EXCP_SWI, | ||
77 | + syn_aa64_svc(imm16), default_exception_el(s)); | ||
78 | break; | ||
79 | case 2: /* HVC */ | ||
80 | if (s->current_el == 0) { | ||
81 | @@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn) | ||
82 | gen_a64_set_pc_im(s->pc_curr); | ||
83 | gen_helper_pre_hvc(cpu_env); | ||
84 | gen_ss_advance(s); | ||
85 | - gen_exception_insn(s, s->base.pc_next, EXCP_HVC, | ||
86 | - syn_aa64_hvc(imm16), 2); | ||
87 | + gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC, | ||
88 | + syn_aa64_hvc(imm16), 2); | ||
89 | break; | ||
90 | case 3: /* SMC */ | ||
91 | if (s->current_el == 0) { | ||
92 | @@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn) | ||
93 | gen_a64_set_pc_im(s->pc_curr); | ||
94 | gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16))); | ||
95 | gen_ss_advance(s); | ||
96 | - gen_exception_insn(s, s->base.pc_next, EXCP_SMC, | ||
97 | - syn_aa64_smc(imm16), 3); | ||
98 | + gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC, | ||
99 | + syn_aa64_smc(imm16), 3); | ||
100 | break; | ||
101 | default: | ||
102 | unallocated_encoding(s); | ||
103 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
104 | * Illegal execution state. This has priority over BTI | ||
105 | * exceptions, but comes after instruction abort exceptions. | ||
106 | */ | ||
107 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
108 | - syn_illegalstate(), default_exception_el(s)); | ||
109 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | ||
110 | + syn_illegalstate(), default_exception_el(s)); | ||
111 | return; | 34 | return; |
112 | } | 35 | } |
113 | 36 | #endif | |
114 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
115 | if (s->btype != 0 | ||
116 | && s->guarded_page | ||
117 | && !btype_destination_ok(insn, s->bt, s->btype)) { | ||
118 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
119 | - syn_btitrap(s->btype), | ||
120 | - default_exception_el(s)); | ||
121 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | ||
122 | + syn_btitrap(s->btype), | ||
123 | + default_exception_el(s)); | ||
124 | return; | ||
125 | } | ||
126 | } else { | ||
127 | diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c | ||
128 | index XXXXXXX..XXXXXXX 100644 | ||
129 | --- a/target/arm/translate-m-nocp.c | ||
130 | +++ b/target/arm/translate-m-nocp.c | ||
131 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) | ||
132 | tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); | ||
133 | |||
134 | if (s->fp_excp_el != 0) { | ||
135 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
136 | - syn_uncategorized(), s->fp_excp_el); | ||
137 | + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, | ||
138 | + syn_uncategorized(), s->fp_excp_el); | ||
139 | return true; | ||
140 | } | ||
141 | |||
142 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
143 | if (!vfp_access_check_m(s, true)) { | ||
144 | /* | ||
145 | * This was only a conditional exception, so override | ||
146 | - * gen_exception_insn()'s default to DISAS_NORETURN | ||
147 | + * gen_exception_insn_el()'s default to DISAS_NORETURN | ||
148 | */ | ||
149 | s->base.is_jmp = DISAS_NEXT; | ||
150 | break; | ||
151 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
152 | if (!vfp_access_check_m(s, true)) { | ||
153 | /* | ||
154 | * This was only a conditional exception, so override | ||
155 | - * gen_exception_insn()'s default to DISAS_NORETURN | ||
156 | + * gen_exception_insn_el()'s default to DISAS_NORETURN | ||
157 | */ | ||
158 | s->base.is_jmp = DISAS_NEXT; | ||
159 | break; | ||
160 | @@ -XXX,XX +XXX,XX @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a) | ||
161 | } | ||
162 | |||
163 | if (a->cp != 10) { | ||
164 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
165 | - syn_uncategorized(), default_exception_el(s)); | ||
166 | + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, | ||
167 | + syn_uncategorized(), default_exception_el(s)); | ||
168 | return true; | ||
169 | } | ||
170 | |||
171 | if (s->fp_excp_el != 0) { | ||
172 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
173 | - syn_uncategorized(), s->fp_excp_el); | ||
174 | + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, | ||
175 | + syn_uncategorized(), s->fp_excp_el); | ||
176 | return true; | ||
177 | } | ||
178 | |||
179 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
180 | index XXXXXXX..XXXXXXX 100644 | ||
181 | --- a/target/arm/translate-mve.c | ||
182 | +++ b/target/arm/translate-mve.c | ||
183 | @@ -XXX,XX +XXX,XX @@ bool mve_eci_check(DisasContext *s) | ||
184 | return true; | ||
185 | default: | ||
186 | /* Reserved value: INVSTATE UsageFault */ | ||
187 | - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
188 | - default_exception_el(s)); | ||
189 | + gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
190 | + default_exception_el(s)); | ||
191 | return false; | ||
192 | } | ||
193 | } | ||
194 | diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c | ||
195 | index XXXXXXX..XXXXXXX 100644 | ||
196 | --- a/target/arm/translate-vfp.c | ||
197 | +++ b/target/arm/translate-vfp.c | ||
198 | @@ -XXX,XX +XXX,XX @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled) | ||
199 | int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa; | ||
200 | uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc); | ||
201 | |||
202 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el); | ||
203 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el); | ||
204 | return false; | ||
205 | } | ||
206 | |||
207 | @@ -XXX,XX +XXX,XX @@ bool vfp_access_check_m(DisasContext *s, bool skip_context_update) | ||
208 | * the encoding space handled by the patterns in m-nocp.decode, | ||
209 | * and for them we may need to raise NOCP here. | ||
210 | */ | ||
211 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
212 | - syn_uncategorized(), s->fp_excp_el); | ||
213 | + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, | ||
214 | + syn_uncategorized(), s->fp_excp_el); | ||
215 | return false; | ||
216 | } | ||
217 | |||
218 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
219 | index XXXXXXX..XXXXXXX 100644 | ||
220 | --- a/target/arm/translate.c | ||
221 | +++ b/target/arm/translate.c | ||
222 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, | ||
223 | s->base.is_jmp = DISAS_NORETURN; | ||
224 | } | ||
225 | |||
226 | -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, | ||
227 | - uint32_t syn, uint32_t target_el) | ||
228 | +void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, | ||
229 | + uint32_t syn, uint32_t target_el) | ||
230 | { | ||
231 | gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el)); | ||
232 | } | ||
233 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) | ||
234 | void unallocated_encoding(DisasContext *s) | ||
235 | { | ||
236 | /* Unallocated and reserved encodings are uncategorized */ | ||
237 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), | ||
238 | - default_exception_el(s)); | ||
239 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), | ||
240 | + default_exception_el(s)); | ||
241 | } | ||
242 | |||
243 | /* Force a TB lookup after an instruction that changes the CPU state. */ | ||
244 | @@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, | ||
245 | |||
246 | undef: | ||
247 | /* If we get here then some access check did not pass */ | ||
248 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
249 | - syn_uncategorized(), exc_target); | ||
250 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | ||
251 | + syn_uncategorized(), exc_target); | ||
252 | return false; | ||
253 | } | ||
254 | |||
255 | @@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s, | ||
256 | * For the UNPREDICTABLE cases we choose to UNDEF. | ||
257 | */ | ||
258 | if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) { | ||
259 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), 3); | ||
260 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | ||
261 | + syn_uncategorized(), 3); | ||
262 | return; | ||
263 | } | ||
264 | |||
265 | @@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) | ||
266 | * Do the check-and-raise-exception by hand. | ||
267 | */ | ||
268 | if (s->fp_excp_el) { | ||
269 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
270 | - syn_uncategorized(), s->fp_excp_el); | ||
271 | + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, | ||
272 | + syn_uncategorized(), s->fp_excp_el); | ||
273 | return true; | ||
274 | } | ||
275 | } | ||
276 | @@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a) | ||
277 | tmp = load_cpu_field(v7m.ltpsize); | ||
278 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc); | ||
279 | tcg_temp_free_i32(tmp); | ||
280 | - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
281 | - default_exception_el(s)); | ||
282 | + gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
283 | + default_exception_el(s)); | ||
284 | gen_set_label(skipexc); | ||
285 | } | ||
286 | |||
287 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
288 | * UsageFault exception. | ||
289 | */ | ||
290 | if (arm_dc_feature(s, ARM_FEATURE_M)) { | ||
291 | - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
292 | - default_exception_el(s)); | ||
293 | + gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
294 | + default_exception_el(s)); | ||
295 | return; | ||
296 | } | ||
297 | |||
298 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
299 | * Illegal execution state. This has priority over BTI | ||
300 | * exceptions, but comes after instruction abort exceptions. | ||
301 | */ | ||
302 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
303 | - syn_illegalstate(), default_exception_el(s)); | ||
304 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | ||
305 | + syn_illegalstate(), default_exception_el(s)); | ||
306 | return; | ||
307 | } | ||
308 | |||
309 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
310 | * Illegal execution state. This has priority over BTI | ||
311 | * exceptions, but comes after instruction abort exceptions. | ||
312 | */ | ||
313 | - gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, | ||
314 | - syn_illegalstate(), default_exception_el(dc)); | ||
315 | + gen_exception_insn_el(dc, dc->pc_curr, EXCP_UDEF, | ||
316 | + syn_illegalstate(), default_exception_el(dc)); | ||
317 | return; | ||
318 | } | ||
319 | |||
320 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
321 | */ | ||
322 | tcg_remove_ops_after(dc->insn_eci_rewind); | ||
323 | dc->condjmp = 0; | ||
324 | - gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
325 | - default_exception_el(dc)); | ||
326 | + gen_exception_insn_el(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
327 | + default_exception_el(dc)); | ||
328 | } | ||
329 | |||
330 | arm_post_translate_insn(dc); | ||
331 | -- | 37 | -- |
332 | 2.25.1 | 38 | 2.34.1 |
39 | |||
40 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Claudio Fontana <cfontana@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | We were using arm_is_secure and is_a64, which are | 3 | for "all" builds (tcg + kvm), we want to avoid doing |
4 | tests against the current EL, as opposed to | 4 | the psci check if tcg is built-in, but not enabled. |
5 | arm_el_is_aa64 and arm_is_secure_below_el3, which | ||
6 | can be applied to a different EL than current. | ||
7 | Consolidate the two tests. | ||
8 | 5 | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Claudio Fontana <cfontana@suse.de> |
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Message-id: 20220609202901.1177572-24-richard.henderson@linaro.org | 8 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
9 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 11 | --- |
14 | target/arm/helper.c | 23 +++++++++-------------- | 12 | target/arm/helper.c | 3 ++- |
15 | 1 file changed, 9 insertions(+), 14 deletions(-) | 13 | 1 file changed, 2 insertions(+), 1 deletion(-) |
16 | 14 | ||
17 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 15 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
18 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/helper.c | 17 | --- a/target/arm/helper.c |
20 | +++ b/target/arm/helper.c | 18 | +++ b/target/arm/helper.c |
21 | @@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el) | 19 | @@ -XXX,XX +XXX,XX @@ |
22 | int fpen = FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN); | 20 | #include "hw/irq.h" |
23 | 21 | #include "sysemu/cpu-timers.h" | |
24 | switch (fpen) { | 22 | #include "sysemu/kvm.h" |
25 | + case 1: | 23 | +#include "sysemu/tcg.h" |
26 | + if (cur_el != 0) { | 24 | #include "qapi/qapi-commands-machine-target.h" |
27 | + break; | 25 | #include "qapi/error.h" |
28 | + } | 26 | #include "qemu/guest-random.h" |
29 | + /* fall through */ | 27 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) |
30 | case 0: | 28 | env->exception.syndrome); |
31 | case 2: | ||
32 | - if (cur_el == 0 || cur_el == 1) { | ||
33 | - /* Trap to PL1, which might be EL1 or EL3 */ | ||
34 | - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { | ||
35 | - return 3; | ||
36 | - } | ||
37 | - return 1; | ||
38 | - } | ||
39 | - if (cur_el == 3 && !is_a64(env)) { | ||
40 | - /* Secure PL1 running at EL3 */ | ||
41 | + /* Trap from Secure PL0 or PL1 to Secure PL1. */ | ||
42 | + if (!arm_el_is_aa64(env, 3) | ||
43 | + && (cur_el == 3 || arm_is_secure_below_el3(env))) { | ||
44 | return 3; | ||
45 | } | ||
46 | - break; | ||
47 | - case 1: | ||
48 | - if (cur_el == 0) { | ||
49 | + if (cur_el <= 1) { | ||
50 | return 1; | ||
51 | } | ||
52 | break; | ||
53 | - case 3: | ||
54 | - break; | ||
55 | } | ||
56 | } | 29 | } |
57 | 30 | ||
31 | - if (arm_is_psci_call(cpu, cs->exception_index)) { | ||
32 | + if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) { | ||
33 | arm_handle_psci_call(cpu); | ||
34 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | ||
35 | return; | ||
58 | -- | 36 | -- |
59 | 2.25.1 | 37 | 2.34.1 |
38 | |||
39 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Claudio Fontana <cfontana@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | Because reset always initializes the AA64 version, SCR_EL3, | 3 | Signed-off-by: Claudio Fontana <cfontana@suse.de> |
4 | test the mode of EL3 instead of the type of the cpreg. | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | 5 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | Message-id: 20220609214657.1217913-2-richard.henderson@linaro.org | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 8 | --- |
11 | target/arm/helper.c | 14 ++++++++------ | 9 | target/arm/helper.c | 12 +++++++----- |
12 | 1 file changed, 8 insertions(+), 6 deletions(-) | 10 | 1 file changed, 7 insertions(+), 5 deletions(-) |
13 | 11 | ||
14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 12 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
15 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper.c | 14 | --- a/target/arm/helper.c |
17 | +++ b/target/arm/helper.c | 15 | +++ b/target/arm/helper.c |
18 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | 16 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) |
19 | uint32_t valid_mask = 0x3fff; | 17 | unsigned int cur_el = arm_current_el(env); |
20 | ARMCPU *cpu = env_archcpu(env); | 18 | int rt; |
21 | 19 | ||
22 | - if (ri->state == ARM_CP_STATE_AA64) { | 20 | - /* |
23 | - if (arm_feature(env, ARM_FEATURE_AARCH64) && | 21 | - * Note that new_el can never be 0. If cur_el is 0, then |
24 | - !cpu_isar_feature(aa64_aa32_el1, cpu)) { | 22 | - * el0_a64 is is_a64(), else el0_a64 is ignored. |
25 | - value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ | 23 | - */ |
26 | - } | 24 | - aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); |
27 | - valid_mask &= ~SCR_NET; | 25 | + if (tcg_enabled()) { |
28 | + /* | 26 | + /* |
29 | + * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always | 27 | + * Note that new_el can never be 0. If cur_el is 0, then |
30 | + * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64. | 28 | + * el0_a64 is is_a64(), else el0_a64 is ignored. |
31 | + * Instead, choose the format based on the mode of EL3. | 29 | + */ |
32 | + */ | 30 | + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); |
33 | + if (arm_el_is_aa64(env, 3)) { | 31 | + } |
34 | + value |= SCR_FW | SCR_AW; /* RES1 */ | 32 | |
35 | + valid_mask &= ~SCR_NET; /* RES0 */ | 33 | if (cur_el < new_el) { |
36 | 34 | /* | |
37 | if (cpu_isar_feature(aa64_ras, cpu)) { | ||
38 | valid_mask |= SCR_TERR; | ||
39 | -- | 35 | -- |
40 | 2.25.1 | 36 | 2.34.1 |
37 | |||
38 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Move this earlier to make the next patch diff cleaner. While here |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | update the comment slightly to not give the impression that the |
5 | Message-id: 20220609202901.1177572-17-richard.henderson@linaro.org | 5 | misalignment affects only TCG. |
6 | |||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
10 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 12 | --- |
8 | target/arm/translate.c | 18 +++++++++--------- | 13 | target/arm/machine.c | 18 +++++++++--------- |
9 | 1 file changed, 9 insertions(+), 9 deletions(-) | 14 | 1 file changed, 9 insertions(+), 9 deletions(-) |
10 | 15 | ||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 16 | diff --git a/target/arm/machine.c b/target/arm/machine.c |
12 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate.c | 18 | --- a/target/arm/machine.c |
14 | +++ b/target/arm/translate.c | 19 | +++ b/target/arm/machine.c |
15 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) | 20 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) |
16 | s->base.is_jmp = DISAS_NORETURN; | ||
17 | } | ||
18 | |||
19 | -static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) | ||
20 | +static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) | ||
21 | { | ||
22 | gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), | ||
23 | tcg_constant_i32(syndrome), | ||
24 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
25 | switch (dc->base.is_jmp) { | ||
26 | case DISAS_SWI: | ||
27 | gen_ss_advance(dc); | ||
28 | - gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), | ||
29 | - default_exception_el(dc)); | ||
30 | + gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), | ||
31 | + default_exception_el(dc)); | ||
32 | break; | ||
33 | case DISAS_HVC: | ||
34 | gen_ss_advance(dc); | ||
35 | - gen_exception(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); | ||
36 | + gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); | ||
37 | break; | ||
38 | case DISAS_SMC: | ||
39 | gen_ss_advance(dc); | ||
40 | - gen_exception(EXCP_SMC, syn_aa32_smc(), 3); | ||
41 | + gen_exception_el(EXCP_SMC, syn_aa32_smc(), 3); | ||
42 | break; | ||
43 | case DISAS_NEXT: | ||
44 | case DISAS_TOO_MANY: | ||
45 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
46 | gen_helper_yield(cpu_env); | ||
47 | break; | ||
48 | case DISAS_SWI: | ||
49 | - gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), | ||
50 | - default_exception_el(dc)); | ||
51 | + gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), | ||
52 | + default_exception_el(dc)); | ||
53 | break; | ||
54 | case DISAS_HVC: | ||
55 | - gen_exception(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); | ||
56 | + gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); | ||
57 | break; | ||
58 | case DISAS_SMC: | ||
59 | - gen_exception(EXCP_SMC, syn_aa32_smc(), 3); | ||
60 | + gen_exception_el(EXCP_SMC, syn_aa32_smc(), 3); | ||
61 | break; | ||
62 | } | 21 | } |
63 | } | 22 | } |
23 | |||
24 | + /* | ||
25 | + * Misaligned thumb pc is architecturally impossible. Fail the | ||
26 | + * incoming migration. For TCG it would trigger the assert in | ||
27 | + * thumb_tr_translate_insn(). | ||
28 | + */ | ||
29 | + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { | ||
30 | + return -1; | ||
31 | + } | ||
32 | + | ||
33 | hw_breakpoint_update_all(cpu); | ||
34 | hw_watchpoint_update_all(cpu); | ||
35 | |||
36 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) | ||
37 | } | ||
38 | } | ||
39 | |||
40 | - /* | ||
41 | - * Misaligned thumb pc is architecturally impossible. | ||
42 | - * We have an assert in thumb_tr_translate_insn to verify this. | ||
43 | - * Fail an incoming migrate to avoid this assert. | ||
44 | - */ | ||
45 | - if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { | ||
46 | - return -1; | ||
47 | - } | ||
48 | - | ||
49 | if (!kvm_enabled()) { | ||
50 | pmu_op_finish(&cpu->env); | ||
51 | } | ||
64 | -- | 52 | -- |
65 | 2.25.1 | 53 | 2.34.1 |
54 | |||
55 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | Move arm_generate_debug_exceptions and its two subroutines, | 3 | Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have |
4 | {aa32,aa64}_generate_debug_exceptions into debug_helper.c, | 4 | a cpregs.h header which is more suitable for this code. |
5 | and the one interface declaration to internals.h. | 5 | |
6 | 6 | Code moved verbatim. | |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
9 | Message-id: 20220609202901.1177572-6-richard.henderson@linaro.org | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
11 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 13 | --- |
12 | target/arm/cpu.h | 91 ------------------------------------- | 14 | target/arm/cpregs.h | 98 +++++++++++++++++++++++++++++++++++++++++++++ |
13 | target/arm/internals.h | 1 + | 15 | target/arm/cpu.h | 91 ----------------------------------------- |
14 | target/arm/debug_helper.c | 94 +++++++++++++++++++++++++++++++++++++++ | 16 | 2 files changed, 98 insertions(+), 91 deletions(-) |
15 | 3 files changed, 95 insertions(+), 91 deletions(-) | 17 | |
16 | 18 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | |
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/cpregs.h | ||
21 | +++ b/target/arm/cpregs.h | ||
22 | @@ -XXX,XX +XXX,XX @@ enum { | ||
23 | ARM_CP_SME = 1 << 19, | ||
24 | }; | ||
25 | |||
26 | +/* | ||
27 | + * Interface for defining coprocessor registers. | ||
28 | + * Registers are defined in tables of arm_cp_reginfo structs | ||
29 | + * which are passed to define_arm_cp_regs(). | ||
30 | + */ | ||
31 | + | ||
32 | +/* | ||
33 | + * When looking up a coprocessor register we look for it | ||
34 | + * via an integer which encodes all of: | ||
35 | + * coprocessor number | ||
36 | + * Crn, Crm, opc1, opc2 fields | ||
37 | + * 32 or 64 bit register (ie is it accessed via MRC/MCR | ||
38 | + * or via MRRC/MCRR?) | ||
39 | + * non-secure/secure bank (AArch32 only) | ||
40 | + * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. | ||
41 | + * (In this case crn and opc2 should be zero.) | ||
42 | + * For AArch64, there is no 32/64 bit size distinction; | ||
43 | + * instead all registers have a 2 bit op0, 3 bit op1 and op2, | ||
44 | + * and 4 bit CRn and CRm. The encoding patterns are chosen | ||
45 | + * to be easy to convert to and from the KVM encodings, and also | ||
46 | + * so that the hashtable can contain both AArch32 and AArch64 | ||
47 | + * registers (to allow for interprocessing where we might run | ||
48 | + * 32 bit code on a 64 bit core). | ||
49 | + */ | ||
50 | +/* | ||
51 | + * This bit is private to our hashtable cpreg; in KVM register | ||
52 | + * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 | ||
53 | + * in the upper bits of the 64 bit ID. | ||
54 | + */ | ||
55 | +#define CP_REG_AA64_SHIFT 28 | ||
56 | +#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) | ||
57 | + | ||
58 | +/* | ||
59 | + * To enable banking of coprocessor registers depending on ns-bit we | ||
60 | + * add a bit to distinguish between secure and non-secure cpregs in the | ||
61 | + * hashtable. | ||
62 | + */ | ||
63 | +#define CP_REG_NS_SHIFT 29 | ||
64 | +#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) | ||
65 | + | ||
66 | +#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ | ||
67 | + ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ | ||
68 | + ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) | ||
69 | + | ||
70 | +#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ | ||
71 | + (CP_REG_AA64_MASK | \ | ||
72 | + ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ | ||
73 | + ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ | ||
74 | + ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ | ||
75 | + ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ | ||
76 | + ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ | ||
77 | + ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) | ||
78 | + | ||
79 | +/* | ||
80 | + * Convert a full 64 bit KVM register ID to the truncated 32 bit | ||
81 | + * version used as a key for the coprocessor register hashtable | ||
82 | + */ | ||
83 | +static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | ||
84 | +{ | ||
85 | + uint32_t cpregid = kvmid; | ||
86 | + if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { | ||
87 | + cpregid |= CP_REG_AA64_MASK; | ||
88 | + } else { | ||
89 | + if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { | ||
90 | + cpregid |= (1 << 15); | ||
91 | + } | ||
92 | + | ||
93 | + /* | ||
94 | + * KVM is always non-secure so add the NS flag on AArch32 register | ||
95 | + * entries. | ||
96 | + */ | ||
97 | + cpregid |= 1 << CP_REG_NS_SHIFT; | ||
98 | + } | ||
99 | + return cpregid; | ||
100 | +} | ||
101 | + | ||
102 | +/* | ||
103 | + * Convert a truncated 32 bit hashtable key into the full | ||
104 | + * 64 bit KVM register ID. | ||
105 | + */ | ||
106 | +static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | ||
107 | +{ | ||
108 | + uint64_t kvmid; | ||
109 | + | ||
110 | + if (cpregid & CP_REG_AA64_MASK) { | ||
111 | + kvmid = cpregid & ~CP_REG_AA64_MASK; | ||
112 | + kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; | ||
113 | + } else { | ||
114 | + kvmid = cpregid & ~(1 << 15); | ||
115 | + if (cpregid & (1 << 15)) { | ||
116 | + kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; | ||
117 | + } else { | ||
118 | + kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; | ||
119 | + } | ||
120 | + } | ||
121 | + return kvmid; | ||
122 | +} | ||
123 | + | ||
124 | /* | ||
125 | * Valid values for ARMCPRegInfo state field, indicating which of | ||
126 | * the AArch32 and AArch64 execution states this register is visible in. | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 127 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
18 | index XXXXXXX..XXXXXXX 100644 | 128 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 129 | --- a/target/arm/cpu.h |
20 | +++ b/target/arm/cpu.h | 130 | +++ b/target/arm/cpu.h |
21 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) | 131 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void); |
22 | return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; | 132 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
23 | } | 133 | uint32_t cur_el, bool secure); |
24 | 134 | ||
25 | -/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ | 135 | -/* Interface for defining coprocessor registers. |
26 | -static inline bool aa64_generate_debug_exceptions(CPUARMState *env) | 136 | - * Registers are defined in tables of arm_cp_reginfo structs |
137 | - * which are passed to define_arm_cp_regs(). | ||
138 | - */ | ||
139 | - | ||
140 | -/* When looking up a coprocessor register we look for it | ||
141 | - * via an integer which encodes all of: | ||
142 | - * coprocessor number | ||
143 | - * Crn, Crm, opc1, opc2 fields | ||
144 | - * 32 or 64 bit register (ie is it accessed via MRC/MCR | ||
145 | - * or via MRRC/MCRR?) | ||
146 | - * non-secure/secure bank (AArch32 only) | ||
147 | - * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. | ||
148 | - * (In this case crn and opc2 should be zero.) | ||
149 | - * For AArch64, there is no 32/64 bit size distinction; | ||
150 | - * instead all registers have a 2 bit op0, 3 bit op1 and op2, | ||
151 | - * and 4 bit CRn and CRm. The encoding patterns are chosen | ||
152 | - * to be easy to convert to and from the KVM encodings, and also | ||
153 | - * so that the hashtable can contain both AArch32 and AArch64 | ||
154 | - * registers (to allow for interprocessing where we might run | ||
155 | - * 32 bit code on a 64 bit core). | ||
156 | - */ | ||
157 | -/* This bit is private to our hashtable cpreg; in KVM register | ||
158 | - * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 | ||
159 | - * in the upper bits of the 64 bit ID. | ||
160 | - */ | ||
161 | -#define CP_REG_AA64_SHIFT 28 | ||
162 | -#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) | ||
163 | - | ||
164 | -/* To enable banking of coprocessor registers depending on ns-bit we | ||
165 | - * add a bit to distinguish between secure and non-secure cpregs in the | ||
166 | - * hashtable. | ||
167 | - */ | ||
168 | -#define CP_REG_NS_SHIFT 29 | ||
169 | -#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) | ||
170 | - | ||
171 | -#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ | ||
172 | - ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ | ||
173 | - ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) | ||
174 | - | ||
175 | -#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ | ||
176 | - (CP_REG_AA64_MASK | \ | ||
177 | - ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ | ||
178 | - ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ | ||
179 | - ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ | ||
180 | - ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ | ||
181 | - ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ | ||
182 | - ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) | ||
183 | - | ||
184 | -/* Convert a full 64 bit KVM register ID to the truncated 32 bit | ||
185 | - * version used as a key for the coprocessor register hashtable | ||
186 | - */ | ||
187 | -static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | ||
27 | -{ | 188 | -{ |
28 | - int cur_el = arm_current_el(env); | 189 | - uint32_t cpregid = kvmid; |
29 | - int debug_el; | 190 | - if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { |
30 | - | 191 | - cpregid |= CP_REG_AA64_MASK; |
31 | - if (cur_el == 3) { | 192 | - } else { |
32 | - return false; | 193 | - if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { |
194 | - cpregid |= (1 << 15); | ||
195 | - } | ||
196 | - | ||
197 | - /* KVM is always non-secure so add the NS flag on AArch32 register | ||
198 | - * entries. | ||
199 | - */ | ||
200 | - cpregid |= 1 << CP_REG_NS_SHIFT; | ||
33 | - } | 201 | - } |
34 | - | 202 | - return cpregid; |
35 | - /* MDCR_EL3.SDD disables debug events from Secure state */ | ||
36 | - if (arm_is_secure_below_el3(env) | ||
37 | - && extract32(env->cp15.mdcr_el3, 16, 1)) { | ||
38 | - return false; | ||
39 | - } | ||
40 | - | ||
41 | - /* | ||
42 | - * Same EL to same EL debug exceptions need MDSCR_KDE enabled | ||
43 | - * while not masking the (D)ebug bit in DAIF. | ||
44 | - */ | ||
45 | - debug_el = arm_debug_target_el(env); | ||
46 | - | ||
47 | - if (cur_el == debug_el) { | ||
48 | - return extract32(env->cp15.mdscr_el1, 13, 1) | ||
49 | - && !(env->daif & PSTATE_D); | ||
50 | - } | ||
51 | - | ||
52 | - /* Otherwise the debug target needs to be a higher EL */ | ||
53 | - return debug_el > cur_el; | ||
54 | -} | 203 | -} |
55 | - | 204 | - |
56 | -static inline bool aa32_generate_debug_exceptions(CPUARMState *env) | 205 | -/* Convert a truncated 32 bit hashtable key into the full |
206 | - * 64 bit KVM register ID. | ||
207 | - */ | ||
208 | -static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | ||
57 | -{ | 209 | -{ |
58 | - int el = arm_current_el(env); | 210 | - uint64_t kvmid; |
59 | - | 211 | - |
60 | - if (el == 0 && arm_el_is_aa64(env, 1)) { | 212 | - if (cpregid & CP_REG_AA64_MASK) { |
61 | - return aa64_generate_debug_exceptions(env); | 213 | - kvmid = cpregid & ~CP_REG_AA64_MASK; |
62 | - } | 214 | - kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; |
63 | - | 215 | - } else { |
64 | - if (arm_is_secure(env)) { | 216 | - kvmid = cpregid & ~(1 << 15); |
65 | - int spd; | 217 | - if (cpregid & (1 << 15)) { |
66 | - | 218 | - kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; |
67 | - if (el == 0 && (env->cp15.sder & 1)) { | 219 | - } else { |
68 | - /* SDER.SUIDEN means debug exceptions from Secure EL0 | 220 | - kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; |
69 | - * are always enabled. Otherwise they are controlled by | ||
70 | - * SDCR.SPD like those from other Secure ELs. | ||
71 | - */ | ||
72 | - return true; | ||
73 | - } | ||
74 | - | ||
75 | - spd = extract32(env->cp15.mdcr_el3, 14, 2); | ||
76 | - switch (spd) { | ||
77 | - case 1: | ||
78 | - /* SPD == 0b01 is reserved, but behaves as 0b00. */ | ||
79 | - case 0: | ||
80 | - /* For 0b00 we return true if external secure invasive debug | ||
81 | - * is enabled. On real hardware this is controlled by external | ||
82 | - * signals to the core. QEMU always permits debug, and behaves | ||
83 | - * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. | ||
84 | - */ | ||
85 | - return true; | ||
86 | - case 2: | ||
87 | - return false; | ||
88 | - case 3: | ||
89 | - return true; | ||
90 | - } | 221 | - } |
91 | - } | 222 | - } |
92 | - | 223 | - return kvmid; |
93 | - return el != 2; | ||
94 | -} | 224 | -} |
95 | - | 225 | - |
96 | -/* Return true if debugging exceptions are currently enabled. | 226 | /* Return the highest implemented Exception Level */ |
97 | - * This corresponds to what in ARM ARM pseudocode would be | 227 | static inline int arm_highest_el(CPUARMState *env) |
98 | - * if UsingAArch32() then | ||
99 | - * return AArch32.GenerateDebugExceptions() | ||
100 | - * else | ||
101 | - * return AArch64.GenerateDebugExceptions() | ||
102 | - * We choose to push the if() down into this function for clarity, | ||
103 | - * since the pseudocode has it at all callsites except for the one in | ||
104 | - * CheckSoftwareStep(), where it is elided because both branches would | ||
105 | - * always return the same value. | ||
106 | - */ | ||
107 | -static inline bool arm_generate_debug_exceptions(CPUARMState *env) | ||
108 | -{ | ||
109 | - if (env->aarch64) { | ||
110 | - return aa64_generate_debug_exceptions(env); | ||
111 | - } else { | ||
112 | - return aa32_generate_debug_exceptions(env); | ||
113 | - } | ||
114 | -} | ||
115 | - | ||
116 | static inline bool arm_sctlr_b(CPUARMState *env) | ||
117 | { | 228 | { |
118 | return | ||
119 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
120 | index XXXXXXX..XXXXXXX 100644 | ||
121 | --- a/target/arm/internals.h | ||
122 | +++ b/target/arm/internals.h | ||
123 | @@ -XXX,XX +XXX,XX @@ bool el_is_in_host(CPUARMState *env, int el); | ||
124 | void aa32_max_features(ARMCPU *cpu); | ||
125 | int exception_target_el(CPUARMState *env); | ||
126 | bool arm_singlestep_active(CPUARMState *env); | ||
127 | +bool arm_generate_debug_exceptions(CPUARMState *env); | ||
128 | |||
129 | /* Powers of 2 for sve_vq_map et al. */ | ||
130 | #define SVE_VQ_POW2_MAP \ | ||
131 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c | ||
132 | index XXXXXXX..XXXXXXX 100644 | ||
133 | --- a/target/arm/debug_helper.c | ||
134 | +++ b/target/arm/debug_helper.c | ||
135 | @@ -XXX,XX +XXX,XX @@ | ||
136 | #include "exec/helper-proto.h" | ||
137 | |||
138 | |||
139 | +/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ | ||
140 | +static bool aa64_generate_debug_exceptions(CPUARMState *env) | ||
141 | +{ | ||
142 | + int cur_el = arm_current_el(env); | ||
143 | + int debug_el; | ||
144 | + | ||
145 | + if (cur_el == 3) { | ||
146 | + return false; | ||
147 | + } | ||
148 | + | ||
149 | + /* MDCR_EL3.SDD disables debug events from Secure state */ | ||
150 | + if (arm_is_secure_below_el3(env) | ||
151 | + && extract32(env->cp15.mdcr_el3, 16, 1)) { | ||
152 | + return false; | ||
153 | + } | ||
154 | + | ||
155 | + /* | ||
156 | + * Same EL to same EL debug exceptions need MDSCR_KDE enabled | ||
157 | + * while not masking the (D)ebug bit in DAIF. | ||
158 | + */ | ||
159 | + debug_el = arm_debug_target_el(env); | ||
160 | + | ||
161 | + if (cur_el == debug_el) { | ||
162 | + return extract32(env->cp15.mdscr_el1, 13, 1) | ||
163 | + && !(env->daif & PSTATE_D); | ||
164 | + } | ||
165 | + | ||
166 | + /* Otherwise the debug target needs to be a higher EL */ | ||
167 | + return debug_el > cur_el; | ||
168 | +} | ||
169 | + | ||
170 | +static bool aa32_generate_debug_exceptions(CPUARMState *env) | ||
171 | +{ | ||
172 | + int el = arm_current_el(env); | ||
173 | + | ||
174 | + if (el == 0 && arm_el_is_aa64(env, 1)) { | ||
175 | + return aa64_generate_debug_exceptions(env); | ||
176 | + } | ||
177 | + | ||
178 | + if (arm_is_secure(env)) { | ||
179 | + int spd; | ||
180 | + | ||
181 | + if (el == 0 && (env->cp15.sder & 1)) { | ||
182 | + /* | ||
183 | + * SDER.SUIDEN means debug exceptions from Secure EL0 | ||
184 | + * are always enabled. Otherwise they are controlled by | ||
185 | + * SDCR.SPD like those from other Secure ELs. | ||
186 | + */ | ||
187 | + return true; | ||
188 | + } | ||
189 | + | ||
190 | + spd = extract32(env->cp15.mdcr_el3, 14, 2); | ||
191 | + switch (spd) { | ||
192 | + case 1: | ||
193 | + /* SPD == 0b01 is reserved, but behaves as 0b00. */ | ||
194 | + case 0: | ||
195 | + /* | ||
196 | + * For 0b00 we return true if external secure invasive debug | ||
197 | + * is enabled. On real hardware this is controlled by external | ||
198 | + * signals to the core. QEMU always permits debug, and behaves | ||
199 | + * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. | ||
200 | + */ | ||
201 | + return true; | ||
202 | + case 2: | ||
203 | + return false; | ||
204 | + case 3: | ||
205 | + return true; | ||
206 | + } | ||
207 | + } | ||
208 | + | ||
209 | + return el != 2; | ||
210 | +} | ||
211 | + | ||
212 | +/* | ||
213 | + * Return true if debugging exceptions are currently enabled. | ||
214 | + * This corresponds to what in ARM ARM pseudocode would be | ||
215 | + * if UsingAArch32() then | ||
216 | + * return AArch32.GenerateDebugExceptions() | ||
217 | + * else | ||
218 | + * return AArch64.GenerateDebugExceptions() | ||
219 | + * We choose to push the if() down into this function for clarity, | ||
220 | + * since the pseudocode has it at all callsites except for the one in | ||
221 | + * CheckSoftwareStep(), where it is elided because both branches would | ||
222 | + * always return the same value. | ||
223 | + */ | ||
224 | +bool arm_generate_debug_exceptions(CPUARMState *env) | ||
225 | +{ | ||
226 | + if (env->aarch64) { | ||
227 | + return aa64_generate_debug_exceptions(env); | ||
228 | + } else { | ||
229 | + return aa32_generate_debug_exceptions(env); | ||
230 | + } | ||
231 | +} | ||
232 | + | ||
233 | /* | ||
234 | * Is single-stepping active? (Note that the "is EL_D AArch64?" check | ||
235 | * implicitly means this always returns false in pre-v8 CPUs.) | ||
236 | -- | 229 | -- |
237 | 2.25.1 | 230 | 2.34.1 |
231 | |||
232 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | Rename to helper_exception_with_syndrome_el, to emphasize | 3 | If a test was tagged with the "accel" tag and the specified |
4 | that the target el is a parameter. | 4 | accelerator it not present in the qemu binary, cancel the test. |
5 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | We can now write tests without explicit calls to require_accelerator, |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | just the tag is enough. |
8 | Message-id: 20220609202901.1177572-10-richard.henderson@linaro.org | 8 | |
9 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 13 | --- |
11 | target/arm/helper.h | 2 +- | 14 | tests/avocado/avocado_qemu/__init__.py | 4 ++++ |
12 | target/arm/translate.h | 6 +++--- | 15 | 1 file changed, 4 insertions(+) |
13 | target/arm/op_helper.c | 6 +++--- | ||
14 | target/arm/translate.c | 6 +++--- | ||
15 | 4 files changed, 10 insertions(+), 10 deletions(-) | ||
16 | 16 | ||
17 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 17 | diff --git a/tests/avocado/avocado_qemu/__init__.py b/tests/avocado/avocado_qemu/__init__.py |
18 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/helper.h | 19 | --- a/tests/avocado/avocado_qemu/__init__.py |
20 | +++ b/target/arm/helper.h | 20 | +++ b/tests/avocado/avocado_qemu/__init__.py |
21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) | 21 | @@ -XXX,XX +XXX,XX @@ def setUp(self): |
22 | DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, | 22 | |
23 | i32, i32, i32, i32) | 23 | super().setUp('qemu-system-') |
24 | DEF_HELPER_2(exception_internal, noreturn, env, i32) | 24 | |
25 | -DEF_HELPER_4(exception_with_syndrome, noreturn, env, i32, i32, i32) | 25 | + accel_required = self._get_unique_tag_val('accel') |
26 | +DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) | 26 | + if accel_required: |
27 | DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) | 27 | + self.require_accelerator(accel_required) |
28 | DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) | 28 | + |
29 | DEF_HELPER_1(setend, void, env) | 29 | self.machine = self.params.get('machine', |
30 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 30 | default=self._get_unique_tag_val('machine')) |
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/translate.h | ||
33 | +++ b/target/arm/translate.h | ||
34 | @@ -XXX,XX +XXX,XX @@ static inline void gen_ss_advance(DisasContext *s) | ||
35 | static inline void gen_exception(int excp, uint32_t syndrome, | ||
36 | uint32_t target_el) | ||
37 | { | ||
38 | - gen_helper_exception_with_syndrome(cpu_env, tcg_constant_i32(excp), | ||
39 | - tcg_constant_i32(syndrome), | ||
40 | - tcg_constant_i32(target_el)); | ||
41 | + gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), | ||
42 | + tcg_constant_i32(syndrome), | ||
43 | + tcg_constant_i32(target_el)); | ||
44 | } | ||
45 | |||
46 | /* Generate an architectural singlestep exception */ | ||
47 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/target/arm/op_helper.c | ||
50 | +++ b/target/arm/op_helper.c | ||
51 | @@ -XXX,XX +XXX,XX @@ void HELPER(yield)(CPUARMState *env) | ||
52 | * those EXCP values which are special cases for QEMU to interrupt | ||
53 | * execution and not to be used for exceptions which are passed to | ||
54 | * the guest (those must all have syndrome information and thus should | ||
55 | - * use exception_with_syndrome). | ||
56 | + * use exception_with_syndrome*). | ||
57 | */ | ||
58 | void HELPER(exception_internal)(CPUARMState *env, uint32_t excp) | ||
59 | { | ||
60 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_internal)(CPUARMState *env, uint32_t excp) | ||
61 | } | ||
62 | |||
63 | /* Raise an exception with the specified syndrome register value */ | ||
64 | -void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, | ||
65 | - uint32_t syndrome, uint32_t target_el) | ||
66 | +void HELPER(exception_with_syndrome_el)(CPUARMState *env, uint32_t excp, | ||
67 | + uint32_t syndrome, uint32_t target_el) | ||
68 | { | ||
69 | raise_exception(env, excp, syndrome, target_el); | ||
70 | } | ||
71 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
72 | index XXXXXXX..XXXXXXX 100644 | ||
73 | --- a/target/arm/translate.c | ||
74 | +++ b/target/arm/translate.c | ||
75 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_el(DisasContext *s, int excp, uint32_t syn, | ||
76 | { | ||
77 | gen_set_condexec(s); | ||
78 | gen_set_pc_im(s, s->pc_curr); | ||
79 | - gen_helper_exception_with_syndrome(cpu_env, | ||
80 | - tcg_constant_i32(excp), | ||
81 | - tcg_constant_i32(syn), tcg_el); | ||
82 | + gen_helper_exception_with_syndrome_el(cpu_env, | ||
83 | + tcg_constant_i32(excp), | ||
84 | + tcg_constant_i32(syn), tcg_el); | ||
85 | s->base.is_jmp = DISAS_NORETURN; | ||
86 | } | ||
87 | 31 | ||
88 | -- | 32 | -- |
89 | 2.25.1 | 33 | 2.34.1 |
34 | |||
35 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | Create a function below gen_exception_insn that takes | 3 | This allows the test to be skipped when TCG is not present in the QEMU |
4 | the target_el as a TCGv_i32, replacing gen_exception_el. | 4 | binary. |
5 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220609202901.1177572-11-richard.henderson@linaro.org | 8 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | target/arm/translate.c | 27 ++++++++++++--------------- | 11 | tests/avocado/boot_linux_console.py | 1 + |
12 | 1 file changed, 12 insertions(+), 15 deletions(-) | 12 | tests/avocado/reverse_debugging.py | 8 ++++++++ |
13 | 2 files changed, 9 insertions(+) | ||
13 | 14 | ||
14 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 15 | diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py |
15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/translate.c | 17 | --- a/tests/avocado/boot_linux_console.py |
17 | +++ b/target/arm/translate.c | 18 | +++ b/tests/avocado/boot_linux_console.py |
18 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) | 19 | @@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_uboot_netbsd9(self): |
19 | s->base.is_jmp = DISAS_NORETURN; | 20 | |
20 | } | 21 | def test_aarch64_raspi3_atf(self): |
21 | 22 | """ | |
22 | -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, | 23 | + :avocado: tags=accel:tcg |
23 | - uint32_t syn, uint32_t target_el) | 24 | :avocado: tags=arch:aarch64 |
24 | +static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, | 25 | :avocado: tags=machine:raspi3b |
25 | + uint32_t syn, TCGv_i32 tcg_el) | 26 | :avocado: tags=cpu:cortex-a53 |
26 | { | 27 | diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py |
27 | if (s->aarch64) { | 28 | index XXXXXXX..XXXXXXX 100644 |
28 | gen_a64_set_pc_im(pc); | 29 | --- a/tests/avocado/reverse_debugging.py |
29 | @@ -XXX,XX +XXX,XX @@ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, | 30 | +++ b/tests/avocado/reverse_debugging.py |
30 | gen_set_condexec(s); | 31 | @@ -XXX,XX +XXX,XX @@ def reverse_debugging(self, shift=7, args=None): |
31 | gen_set_pc_im(s, pc); | 32 | vm.shutdown() |
32 | } | 33 | |
33 | - gen_exception(excp, syn, target_el); | 34 | class ReverseDebugging_X86_64(ReverseDebugging): |
34 | + gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), | 35 | + """ |
35 | + tcg_constant_i32(syn), tcg_el); | 36 | + :avocado: tags=accel:tcg |
36 | s->base.is_jmp = DISAS_NORETURN; | 37 | + """ |
37 | } | ||
38 | |||
39 | +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, | ||
40 | + uint32_t syn, uint32_t target_el) | ||
41 | +{ | ||
42 | + gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el)); | ||
43 | +} | ||
44 | + | 38 | + |
45 | static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) | 39 | REG_PC = 0x10 |
46 | { | 40 | REG_CS = 0x12 |
47 | gen_set_condexec(s); | 41 | def get_pc(self, g): |
48 | @@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s) | 42 | @@ -XXX,XX +XXX,XX @@ def test_x86_64_pc(self): |
49 | default_exception_el(s)); | 43 | self.reverse_debugging() |
50 | } | 44 | |
51 | 45 | class ReverseDebugging_AArch64(ReverseDebugging): | |
52 | -static void gen_exception_el(DisasContext *s, int excp, uint32_t syn, | 46 | + """ |
53 | - TCGv_i32 tcg_el) | 47 | + :avocado: tags=accel:tcg |
54 | -{ | 48 | + """ |
55 | - gen_set_condexec(s); | 49 | + |
56 | - gen_set_pc_im(s, s->pc_curr); | 50 | REG_PC = 32 |
57 | - gen_helper_exception_with_syndrome_el(cpu_env, | 51 | |
58 | - tcg_constant_i32(excp), | 52 | # unidentified gitlab timeout problem |
59 | - tcg_constant_i32(syn), tcg_el); | ||
60 | - s->base.is_jmp = DISAS_NORETURN; | ||
61 | -} | ||
62 | - | ||
63 | /* Force a TB lookup after an instruction that changes the CPU state. */ | ||
64 | void gen_lookup_tb(DisasContext *s) | ||
65 | { | ||
66 | @@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, | ||
67 | tcg_el = tcg_constant_i32(3); | ||
68 | } | ||
69 | |||
70 | - gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el); | ||
71 | + gen_exception_insn_el_v(s, s->pc_curr, EXCP_UDEF, | ||
72 | + syn_uncategorized(), tcg_el); | ||
73 | tcg_temp_free_i32(tcg_el); | ||
74 | return false; | ||
75 | } | ||
76 | -- | 53 | -- |
77 | 2.25.1 | 54 | 2.34.1 |
55 | |||
56 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | With ARMv8, this field is always RES0. | 3 | Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a |
4 | With ARMv7, targeting EL2 and TA=0, it is always 0xA. | 4 | KVM-only build the 'max' cpu. |
5 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Note that we cannot use 'host' here because the qtests can run without |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | any other accelerator (than qtest) and 'host' depends on KVM being |
8 | Message-id: 20220609202901.1177572-3-richard.henderson@linaro.org | 8 | enabled. |
9 | |||
10 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
11 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 14 | --- |
11 | target/arm/syndrome.h | 7 ++++--- | 15 | hw/arm/virt.c | 4 ++++ |
12 | target/arm/translate-a64.c | 3 ++- | 16 | 1 file changed, 4 insertions(+) |
13 | target/arm/translate-vfp.c | 14 ++++++++++++-- | ||
14 | 3 files changed, 18 insertions(+), 6 deletions(-) | ||
15 | 17 | ||
16 | diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h | 18 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
17 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/syndrome.h | 20 | --- a/hw/arm/virt.c |
19 | +++ b/target/arm/syndrome.h | 21 | +++ b/hw/arm/virt.c |
20 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, | 22 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data) |
21 | | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; | 23 | mc->minimum_page_bits = 12; |
22 | } | 24 | mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; |
23 | 25 | mc->cpu_index_to_instance_props = virt_cpu_index_to_props; | |
24 | -static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) | 26 | +#ifdef CONFIG_TCG |
25 | +static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit, | 27 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); |
26 | + int coproc) | 28 | +#else |
27 | { | 29 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); |
28 | - /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */ | 30 | +#endif |
29 | + /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */ | 31 | mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; |
30 | return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) | 32 | mc->kvm_type = virt_kvm_type; |
31 | | (is_16bit ? 0 : ARM_EL_IL) | 33 | assert(!mc->get_hotplug_handler); |
32 | - | (cv << 24) | (cond << 20) | 0xa; | ||
33 | + | (cv << 24) | (cond << 20) | coproc; | ||
34 | } | ||
35 | |||
36 | static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) | ||
37 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/translate-a64.c | ||
40 | +++ b/target/arm/translate-a64.c | ||
41 | @@ -XXX,XX +XXX,XX @@ static bool fp_access_check(DisasContext *s) | ||
42 | s->fp_access_checked = true; | ||
43 | |||
44 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
45 | - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | ||
46 | + syn_fp_access_trap(1, 0xe, false, 0), | ||
47 | + s->fp_excp_el); | ||
48 | return false; | ||
49 | } | ||
50 | s->fp_access_checked = true; | ||
51 | diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c | ||
52 | index XXXXXXX..XXXXXXX 100644 | ||
53 | --- a/target/arm/translate-vfp.c | ||
54 | +++ b/target/arm/translate-vfp.c | ||
55 | @@ -XXX,XX +XXX,XX @@ static void gen_update_fp_context(DisasContext *s) | ||
56 | static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled) | ||
57 | { | ||
58 | if (s->fp_excp_el) { | ||
59 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
60 | - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | ||
61 | + /* | ||
62 | + * The full syndrome is only used for HSR when HCPTR traps: | ||
63 | + * For v8, when TA==0, coproc is RES0. | ||
64 | + * For v7, any use of a Floating-point instruction or access | ||
65 | + * to a Floating-point Extension register that is trapped to | ||
66 | + * Hyp mode because of a trap configured in the HCPTR sets | ||
67 | + * this field to 0xA. | ||
68 | + */ | ||
69 | + int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa; | ||
70 | + uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc); | ||
71 | + | ||
72 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el); | ||
73 | return false; | ||
74 | } | ||
75 | |||
76 | -- | 34 | -- |
77 | 2.25.1 | 35 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | Move the function to op_helper.c, near raise_exception. | 3 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
4 | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | |
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Acked-by: Thomas Huth <thuth@redhat.com> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20220609202901.1177572-4-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 7 | --- |
10 | target/arm/internals.h | 16 +--------------- | 8 | tests/qtest/arm-cpu-features.c | 28 ++++++++++++++++++---------- |
11 | target/arm/op_helper.c | 15 +++++++++++++++ | 9 | 1 file changed, 18 insertions(+), 10 deletions(-) |
12 | 2 files changed, 16 insertions(+), 15 deletions(-) | ||
13 | 10 | ||
14 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 11 | diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c |
15 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/internals.h | 13 | --- a/tests/qtest/arm-cpu-features.c |
17 | +++ b/target/arm/internals.h | 14 | +++ b/tests/qtest/arm-cpu-features.c |
18 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
19 | int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); | ||
20 | int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx); | ||
21 | |||
22 | -static inline int exception_target_el(CPUARMState *env) | ||
23 | -{ | ||
24 | - int target_el = MAX(1, arm_current_el(env)); | ||
25 | - | ||
26 | - /* | ||
27 | - * No such thing as secure EL1 if EL3 is aarch32, | ||
28 | - * so update the target EL to EL3 in this case. | ||
29 | - */ | ||
30 | - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { | ||
31 | - target_el = 3; | ||
32 | - } | ||
33 | - | ||
34 | - return target_el; | ||
35 | -} | ||
36 | - | ||
37 | /* Determine if allocation tags are available. */ | ||
38 | static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, | ||
39 | uint64_t sctlr) | ||
40 | @@ -XXX,XX +XXX,XX @@ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); | ||
41 | bool el_is_in_host(CPUARMState *env, int el); | ||
42 | |||
43 | void aa32_max_features(ARMCPU *cpu); | ||
44 | +int exception_target_el(CPUARMState *env); | ||
45 | |||
46 | /* Powers of 2 for sve_vq_map et al. */ | ||
47 | #define SVE_VQ_POW2_MAP \ | ||
48 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/target/arm/op_helper.c | ||
51 | +++ b/target/arm/op_helper.c | ||
52 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ |
53 | #define SIGNBIT (uint32_t)0x80000000 | 16 | #define SVE_MAX_VQ 16 |
54 | #define SIGNBIT64 ((uint64_t)1 << 63) | 17 | |
55 | 18 | #define MACHINE "-machine virt,gic-version=max -accel tcg " | |
56 | +int exception_target_el(CPUARMState *env) | 19 | -#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg " |
57 | +{ | 20 | +#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm " |
58 | + int target_el = MAX(1, arm_current_el(env)); | 21 | #define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \ |
59 | + | 22 | " 'arguments': { 'type': 'full', " |
60 | + /* | 23 | #define QUERY_TAIL "}}" |
61 | + * No such thing as secure EL1 if EL3 is aarch32, | 24 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv) |
62 | + * so update the target EL to EL3 in this case. | 25 | { |
63 | + */ | 26 | g_test_init(&argc, &argv, NULL); |
64 | + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { | 27 | |
65 | + target_el = 3; | 28 | - qtest_add_data_func("/arm/query-cpu-model-expansion", |
29 | - NULL, test_query_cpu_model_expansion); | ||
30 | + if (qtest_has_accel("tcg")) { | ||
31 | + qtest_add_data_func("/arm/query-cpu-model-expansion", | ||
32 | + NULL, test_query_cpu_model_expansion); | ||
66 | + } | 33 | + } |
67 | + | 34 | + |
68 | + return target_el; | 35 | + if (!g_str_equal(qtest_get_arch(), "aarch64")) { |
69 | +} | 36 | + goto out; |
37 | + } | ||
38 | |||
39 | /* | ||
40 | * For now we only run KVM specific tests with AArch64 QEMU in | ||
41 | * order avoid attempting to run an AArch32 QEMU with KVM on | ||
42 | * AArch64 hosts. That won't work and isn't easy to detect. | ||
43 | */ | ||
44 | - if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) { | ||
45 | + if (qtest_has_accel("kvm")) { | ||
46 | /* | ||
47 | * This tests target the 'host' CPU type, so register it only if | ||
48 | * KVM is available. | ||
49 | */ | ||
50 | qtest_add_data_func("/arm/kvm/query-cpu-model-expansion", | ||
51 | NULL, test_query_cpu_model_expansion_kvm); | ||
52 | - } | ||
53 | |||
54 | - if (g_str_equal(qtest_get_arch(), "aarch64")) { | ||
55 | - qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8", | ||
56 | - NULL, sve_tests_sve_max_vq_8); | ||
57 | - qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off", | ||
58 | - NULL, sve_tests_sve_off); | ||
59 | qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off", | ||
60 | NULL, sve_tests_sve_off_kvm); | ||
61 | } | ||
62 | |||
63 | + if (qtest_has_accel("tcg")) { | ||
64 | + qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8", | ||
65 | + NULL, sve_tests_sve_max_vq_8); | ||
66 | + qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off", | ||
67 | + NULL, sve_tests_sve_off); | ||
68 | + } | ||
70 | + | 69 | + |
71 | void raise_exception(CPUARMState *env, uint32_t excp, | 70 | +out: |
72 | uint32_t syndrome, uint32_t target_el) | 71 | return g_test_run(); |
73 | { | 72 | } |
74 | -- | 73 | -- |
75 | 2.25.1 | 74 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | These tests set -accel tcg, so restrict them to when TCG is present. |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | |
5 | Message-id: 20220609202901.1177572-2-richard.henderson@linaro.org | 5 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
6 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 9 | --- |
8 | target/arm/helper.h | 6 +++--- | 10 | tests/qtest/meson.build | 4 ++-- |
9 | 1 file changed, 3 insertions(+), 3 deletions(-) | 11 | 1 file changed, 2 insertions(+), 2 deletions(-) |
10 | 12 | ||
11 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 13 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build |
12 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/helper.h | 15 | --- a/tests/qtest/meson.build |
14 | +++ b/target/arm/helper.h | 16 | +++ b/tests/qtest/meson.build |
15 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) | 17 | @@ -XXX,XX +XXX,XX @@ qtests_arm = \ |
16 | 18 | # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional | |
17 | DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, | 19 | qtests_aarch64 = \ |
18 | i32, i32, i32, i32) | 20 | (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) + \ |
19 | -DEF_HELPER_2(exception_internal, void, env, i32) | 21 | - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \ |
20 | -DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) | 22 | - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \ |
21 | -DEF_HELPER_2(exception_bkpt_insn, void, env, i32) | 23 | + (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? \ |
22 | +DEF_HELPER_2(exception_internal, noreturn, env, i32) | 24 | + ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \ |
23 | +DEF_HELPER_4(exception_with_syndrome, noreturn, env, i32, i32, i32) | 25 | (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \ |
24 | +DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) | 26 | (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \ |
25 | DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) | 27 | ['arm-cpu-features', |
26 | DEF_HELPER_1(setend, void, env) | ||
27 | DEF_HELPER_2(wfi, void, env, i32) | ||
28 | -- | 28 | -- |
29 | 2.25.1 | 29 | 2.34.1 | diff view generated by jsdifflib |