[v1] target/arm: SCR_EL3 RES0, RAO/WI tweaks

[PATCH 0/2] target/arm: SCR_EL3 RES0, RAO/WI tweaks

Richard Henderson posted 2 patches 1 year, 11 months ago

Diff against v2
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20220605161056.293920-1-richard.henderson@linaro.org

Maintainers: Peter Maydell <peter.maydell@linaro.org>

There is a newer version of this series

target/arm/cpu.h    |  5 +++++
target/arm/helper.c | 11 ++++++-----
2 files changed, 11 insertions(+), 5 deletions(-)

Expand all Fold all

[PATCH 0/2] target/arm: SCR_EL3 RES0, RAO/WI tweaks

Posted by Richard Henderson 1 year, 11 months ago

Adjust RW, fixing #1062, and adjusting bits [4:2].

r~

Richard Henderson (2):
  target/arm: SCR_EL3 bits 4,5 are always res0
  target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12]

 target/arm/cpu.h    |  5 +++++
 target/arm/helper.c | 11 ++++++-----
 2 files changed, 11 insertions(+), 5 deletions(-)

-- 
2.34.1

[PATCH 1/2] target/arm: SCR_EL3 bits 4,5 are always res0
[PATCH 2/2] target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12]